diff options
author | Ali Saidi <saidi@eecs.umich.edu> | 2004-10-25 18:14:13 -0400 |
---|---|---|
committer | Ali Saidi <saidi@eecs.umich.edu> | 2004-10-25 18:14:13 -0400 |
commit | 3402411661caff075890c20a6c59fa471d5e68ac (patch) | |
tree | 1fdff9005fd8e020217a21bdfac672ff0885b99f | |
parent | eaf66f46588cdfd8a91b93821406e1d797c6d1fb (diff) | |
download | gem5-3402411661caff075890c20a6c59fa471d5e68ac.tar.xz |
changes to make interrupts part of the platform rather than tsunami
specific
--HG--
extra : convert_revision : f51788dd41c23f13b253268bb2b286a5225ef087
-rw-r--r-- | dev/ide_ctrl.cc | 4 | ||||
-rw-r--r-- | dev/ide_disk.cc | 2 | ||||
-rw-r--r-- | dev/ns_gige.cc | 4 | ||||
-rw-r--r-- | dev/platform.hh | 2 | ||||
-rw-r--r-- | dev/tsunami.cc | 12 | ||||
-rw-r--r-- | dev/tsunami.hh | 10 |
6 files changed, 30 insertions, 4 deletions
diff --git a/dev/ide_ctrl.cc b/dev/ide_ctrl.cc index e40248461..ec881ed15 100644 --- a/dev/ide_ctrl.cc +++ b/dev/ide_ctrl.cc @@ -245,13 +245,13 @@ IdeController::setDmaComplete(IdeDisk *disk) void IdeController::intrPost() { - tsunami->cchip->postDRIR(configData->config.hdr.pci0.interruptLine); + tsunami->postPciInt(configData->config.hdr.pci0.interruptLine); } void IdeController::intrClear() { - tsunami->cchip->clearDRIR(configData->config.hdr.pci0.interruptLine); + tsunami->clearPciInt(configData->config.hdr.pci0.interruptLine); } //// diff --git a/dev/ide_disk.cc b/dev/ide_disk.cc index 99724f077..f4e7c1ef1 100644 --- a/dev/ide_disk.cc +++ b/dev/ide_disk.cc @@ -732,6 +732,7 @@ IdeDisk::startCommand() void IdeDisk::intrPost() { + DPRINTF(IdeDisk, "IDE Disk Posting Interrupt\n"); if (intrPending) panic("Attempt to post an interrupt with one pending\n"); @@ -745,6 +746,7 @@ IdeDisk::intrPost() void IdeDisk::intrClear() { + DPRINTF(IdeDisk, "IDE Disk Clearing Interrupt\n"); if (!intrPending) panic("Attempt to clear a non-pending interrupt\n"); diff --git a/dev/ns_gige.cc b/dev/ns_gige.cc index 9238a7c7e..7260ecde4 100644 --- a/dev/ns_gige.cc +++ b/dev/ns_gige.cc @@ -1038,7 +1038,7 @@ NSGigE::cpuInterrupt() cpuPendingIntr = true; DPRINTF(EthernetIntr, "posting cchip interrupt\n"); - tsunami->cchip->postDRIR(configData->config.hdr.pci0.interruptLine); + tsunami->postPciInt(configData->config.hdr.pci0.interruptLine); } } @@ -1058,7 +1058,7 @@ NSGigE::cpuIntrClear() cpuPendingIntr = false; DPRINTF(EthernetIntr, "clearing cchip interrupt\n"); - tsunami->cchip->clearDRIR(configData->config.hdr.pci0.interruptLine); + tsunami->clearPciInt(configData->config.hdr.pci0.interruptLine); } bool diff --git a/dev/platform.hh b/dev/platform.hh index 7920480bc..0c90e06ba 100644 --- a/dev/platform.hh +++ b/dev/platform.hh @@ -65,6 +65,8 @@ class Platform : public SimObject virtual void postConsoleInt() = 0; virtual void clearConsoleInt() = 0; virtual Tick intrFrequency() = 0; + virtual void postPciInt(int line) = 0; + virtual void clearPciInt(int line) = 0; }; #endif // __PLATFORM_HH_ diff --git a/dev/tsunami.cc b/dev/tsunami.cc index c44da69b7..ce2d473a9 100644 --- a/dev/tsunami.cc +++ b/dev/tsunami.cc @@ -75,6 +75,18 @@ Tsunami::clearConsoleInt() } void +Tsunami::postPciInt(int line) +{ + this->cchip->postDRIR(line); +} + +void +Tsunami::clearPciInt(int line) +{ + this->cchip->clearDRIR(line); +} + +void Tsunami::serialize(std::ostream &os) { SERIALIZE_ARRAY(intr_sum_type, Tsunami::Max_CPUs); diff --git a/dev/tsunami.hh b/dev/tsunami.hh index db266d62d..df804956a 100644 --- a/dev/tsunami.hh +++ b/dev/tsunami.hh @@ -112,6 +112,16 @@ class Tsunami : public Platform virtual void clearConsoleInt(); /** + * Cause the chipset to post a cpi interrupt to the CPU. + */ + virtual void postPciInt(int line); + + /** + * Clear a posted PCI->CPU interrupt + */ + virtual void clearPciInt(int line); + + /** * Serialize this object to the given output stream. * @param os The stream to serialize to. */ |