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author | Ali Saidi <saidi@eecs.umich.edu> | 2007-12-18 01:52:57 -0500 |
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committer | Ali Saidi <saidi@eecs.umich.edu> | 2007-12-18 01:52:57 -0500 |
commit | 45ea1549c9cec71b5119702056fad20a0db1ebdf (patch) | |
tree | b420d99a930c9209664884edd299c219e0136d05 | |
parent | 71909a50de2dd5154622c936179d97ec5220f872 (diff) | |
download | gem5-45ea1549c9cec71b5119702056fad20a0db1ebdf.tar.xz |
Checkpointing: Fix a bug in the simulation script when restoring without standard switch and change some ifs to work with the default port since every port is now connected to something.
--HG--
extra : convert_revision : 72507cf13e58465291b0dce6322e853bee5a2b89
-rw-r--r-- | configs/common/Simulation.py | 2 | ||||
-rw-r--r-- | src/cpu/base.cc | 4 |
2 files changed, 3 insertions, 3 deletions
diff --git a/configs/common/Simulation.py b/configs/common/Simulation.py index 84628b347..1ff36c5d0 100644 --- a/configs/common/Simulation.py +++ b/configs/common/Simulation.py @@ -91,7 +91,7 @@ def run(options, root, testsys, cpu_class): switch_cpus[i].workload = testsys.cpu[i].workload switch_cpus[i].clock = testsys.cpu[0].clock - root.switch_cpus = switch_cpus + testsys.switch_cpus = switch_cpus switch_cpu_list = [(testsys.cpu[i], switch_cpus[i]) for i in xrange(np)] if options.standard_switch: diff --git a/src/cpu/base.cc b/src/cpu/base.cc index 7b04f5a90..677152ce8 100644 --- a/src/cpu/base.cc +++ b/src/cpu/base.cc @@ -352,7 +352,7 @@ BaseCPU::takeOverFrom(BaseCPU *oldCPU, Port *ic, Port *dc) // connected to anything. Also connect old CPU's memory to new // CPU. Port *peer; - if (ic->getPeer() == NULL) { + if (ic->getPeer() == NULL || ic->getPeer()->isDefaultPort()) { peer = oldCPU->getPort("icache_port")->getPeer(); ic->setPeer(peer); } else { @@ -360,7 +360,7 @@ BaseCPU::takeOverFrom(BaseCPU *oldCPU, Port *ic, Port *dc) } peer->setPeer(ic); - if (dc->getPeer() == NULL) { + if (dc->getPeer() == NULL || dc->getPeer()->isDefaultPort()) { peer = oldCPU->getPort("dcache_port")->getPeer(); dc->setPeer(peer); } else { |