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authorLisa Hsu <hsul@eecs.umich.edu>2006-12-12 21:19:51 -0500
committerLisa Hsu <hsul@eecs.umich.edu>2006-12-12 21:19:51 -0500
commit5d42fd836b88c1a234a5d7ddd768422f9878e2df (patch)
treebf0c98492bfa25e3e128a19769e9562ea3897596
parent369e10d95adb45da7a791e6e8a6a4ced64892f14 (diff)
parent6c8c86f2f97913788237f763d4810ab12730ca60 (diff)
downloadgem5-5d42fd836b88c1a234a5d7ddd768422f9878e2df.tar.xz
Merge zizzer:/bk/newmem
into zed.eecs.umich.edu:/z/hsul/work/sparc/m5 --HG-- extra : convert_revision : 6e58629b1e51f1fc493a89f16c3f2e676dc5d191
-rw-r--r--SConstruct55
-rw-r--r--build_opts/SPARC_FS1
-rw-r--r--build_opts/SPARC_SE1
-rw-r--r--src/SConscript1
-rwxr-xr-xsrc/arch/isa_parser.py25
-rw-r--r--src/arch/mips/isa/formats/fp.isa6
-rw-r--r--src/base/compression/base.hh71
-rw-r--r--src/base/compression/lzss_compression.hh4
-rw-r--r--src/base/compression/null_compression.hh28
-rw-r--r--src/cpu/base_dyn_inst.hh12
-rw-r--r--src/cpu/checker/cpu.hh25
-rw-r--r--src/cpu/exec_context.hh25
-rw-r--r--src/cpu/o3/alpha/dyn_inst.hh35
-rw-r--r--src/cpu/o3/commit_impl.hh7
-rw-r--r--src/cpu/o3/fetch_impl.hh62
-rw-r--r--src/cpu/o3/lsq_unit_impl.hh3
-rwxr-xr-xsrc/cpu/o3/mips/dyn_inst.hh35
-rw-r--r--src/cpu/ozone/cpu.hh99
-rw-r--r--src/cpu/ozone/dyn_inst.hh25
-rw-r--r--src/cpu/ozone/inorder_back_end.hh74
-rw-r--r--src/cpu/simple/base.hh25
-rw-r--r--src/cpu/simple_thread.hh69
-rw-r--r--src/mem/cache/cache.cc66
-rw-r--r--src/mem/cache/cache.hh15
-rw-r--r--src/mem/cache/cache_builder.cc148
-rw-r--r--src/mem/cache/cache_impl.hh70
-rw-r--r--src/mem/cache/miss/blocking_buffer.cc41
-rw-r--r--src/mem/cache/miss/blocking_buffer.hh61
-rw-r--r--src/mem/cache/miss/miss_buffer.cc62
-rw-r--r--src/mem/cache/miss/miss_buffer.hh223
-rw-r--r--src/mem/cache/miss/miss_queue.cc36
-rw-r--r--src/mem/cache/miss/miss_queue.hh30
-rw-r--r--src/mem/cache/prefetch/ghb_prefetcher.cc8
-rw-r--r--src/mem/cache/prefetch/ghb_prefetcher.hh10
-rw-r--r--src/mem/cache/prefetch/stride_prefetcher.cc8
-rw-r--r--src/mem/cache/prefetch/stride_prefetcher.hh10
-rw-r--r--src/mem/cache/prefetch/tagged_prefetcher.hh8
-rw-r--r--src/mem/cache/prefetch/tagged_prefetcher_impl.hh10
-rw-r--r--src/python/m5/objects/Repl.py6
-rw-r--r--src/python/m5/params.py11
-rw-r--r--tests/SConscript6
-rw-r--r--tests/long/00.gzip/ref/alpha/linux/o3-timing/config.ini28
-rw-r--r--tests/long/00.gzip/ref/alpha/linux/o3-timing/config.out105
-rw-r--r--tests/long/00.gzip/ref/alpha/linux/o3-timing/m5stats.txt2157
-rw-r--r--tests/long/00.gzip/ref/alpha/linux/o3-timing/stderr2
-rw-r--r--tests/long/00.gzip/ref/alpha/linux/o3-timing/stdout44
-rw-r--r--tests/long/00.gzip/ref/alpha/linux/simple-atomic/config.ini352
-rw-r--r--tests/long/00.gzip/ref/alpha/linux/simple-atomic/config.out346
-rw-r--r--tests/long/00.gzip/ref/alpha/linux/simple-atomic/m5stats.txt1980
-rw-r--r--tests/long/00.gzip/ref/alpha/linux/simple-atomic/stderr2
-rw-r--r--tests/long/00.gzip/ref/alpha/linux/simple-atomic/stdout44
-rw-r--r--tests/long/00.gzip/ref/alpha/linux/simple-timing/config.ini225
-rw-r--r--tests/long/00.gzip/ref/alpha/linux/simple-timing/config.out265
-rw-r--r--tests/long/00.gzip/ref/alpha/linux/simple-timing/m5stats.txt2040
-rw-r--r--tests/long/00.gzip/ref/alpha/linux/simple-timing/stderr2
-rw-r--r--tests/long/00.gzip/ref/alpha/linux/simple-timing/stdout44
-rw-r--r--tests/long/20.parser/ref/alpha/linux/NOTE6
-rw-r--r--tests/long/30.eon/ref/alpha/linux/o3-timing/config.ini417
-rw-r--r--tests/long/30.eon/ref/alpha/linux/o3-timing/config.out403
-rw-r--r--tests/long/30.eon/ref/alpha/linux/o3-timing/m5stats.txt1974
-rw-r--r--tests/long/30.eon/ref/alpha/linux/o3-timing/stderr3
-rw-r--r--tests/long/30.eon/ref/alpha/linux/o3-timing/stdout13
-rw-r--r--tests/long/30.eon/ref/alpha/linux/simple-atomic/config.ini352
-rw-r--r--tests/long/30.eon/ref/alpha/linux/simple-atomic/config.out346
-rw-r--r--tests/long/30.eon/ref/alpha/linux/simple-atomic/m5stats.txt1982
-rw-r--r--tests/long/30.eon/ref/alpha/linux/simple-atomic/stderr48
-rw-r--r--tests/long/30.eon/ref/alpha/linux/simple-atomic/stdout15
-rw-r--r--tests/long/30.eon/ref/alpha/linux/simple-timing/config.ini225
-rw-r--r--tests/long/30.eon/ref/alpha/linux/simple-timing/config.out265
-rw-r--r--tests/long/30.eon/ref/alpha/linux/simple-timing/m5stats.txt2036
-rw-r--r--tests/long/30.eon/ref/alpha/linux/simple-timing/stderr48
-rw-r--r--tests/long/30.eon/ref/alpha/linux/simple-timing/stdout15
-rw-r--r--tests/long/40.perlbmk/ref/alpha/linux/simple-atomic/config.ini352
-rw-r--r--tests/long/40.perlbmk/ref/alpha/linux/simple-atomic/config.out346
-rw-r--r--tests/long/40.perlbmk/ref/alpha/linux/simple-atomic/m5stats.txt1982
-rw-r--r--tests/long/40.perlbmk/ref/alpha/linux/simple-atomic/stderr3
-rw-r--r--tests/long/40.perlbmk/ref/alpha/linux/simple-atomic/stdout1389
-rw-r--r--tests/long/40.perlbmk/ref/alpha/linux/simple-timing/config.ini225
-rw-r--r--tests/long/40.perlbmk/ref/alpha/linux/simple-timing/config.out265
-rw-r--r--tests/long/40.perlbmk/ref/alpha/linux/simple-timing/m5stats.txt2048
-rw-r--r--tests/long/40.perlbmk/ref/alpha/linux/simple-timing/stderr3
-rw-r--r--tests/long/40.perlbmk/ref/alpha/linux/simple-timing/stdout1389
-rw-r--r--tests/long/50.vortex/ref/alpha/linux/o3-timing/config.ini28
-rw-r--r--tests/long/50.vortex/ref/alpha/linux/o3-timing/config.out105
-rw-r--r--tests/long/50.vortex/ref/alpha/linux/o3-timing/m5stats.txt2167
-rw-r--r--tests/long/50.vortex/ref/alpha/linux/o3-timing/smred.msg158
-rw-r--r--tests/long/50.vortex/ref/alpha/linux/o3-timing/smred.out258
-rw-r--r--tests/long/50.vortex/ref/alpha/linux/o3-timing/stderr2
-rw-r--r--tests/long/50.vortex/ref/alpha/linux/o3-timing/stdout13
-rw-r--r--tests/long/50.vortex/ref/alpha/linux/simple-atomic/config.ini352
-rw-r--r--tests/long/50.vortex/ref/alpha/linux/simple-atomic/config.out346
-rw-r--r--tests/long/50.vortex/ref/alpha/linux/simple-atomic/m5stats.txt1982
-rw-r--r--tests/long/50.vortex/ref/alpha/linux/simple-atomic/smred.msg158
-rw-r--r--tests/long/50.vortex/ref/alpha/linux/simple-atomic/smred.out258
-rw-r--r--tests/long/50.vortex/ref/alpha/linux/simple-atomic/stderr2
-rw-r--r--tests/long/50.vortex/ref/alpha/linux/simple-atomic/stdout13
-rw-r--r--tests/long/50.vortex/ref/alpha/linux/simple-timing/config.ini225
-rw-r--r--tests/long/50.vortex/ref/alpha/linux/simple-timing/config.out265
-rw-r--r--tests/long/50.vortex/ref/alpha/linux/simple-timing/m5stats.txt2048
-rw-r--r--tests/long/50.vortex/ref/alpha/linux/simple-timing/smred.msg158
-rw-r--r--tests/long/50.vortex/ref/alpha/linux/simple-timing/smred.out258
-rw-r--r--tests/long/50.vortex/ref/alpha/linux/simple-timing/stderr2
-rw-r--r--tests/long/50.vortex/ref/alpha/linux/simple-timing/stdout13
-rw-r--r--tests/long/60.bzip2/ref/alpha/linux/o3-timing/config.ini28
-rw-r--r--tests/long/60.bzip2/ref/alpha/linux/o3-timing/config.out105
-rw-r--r--tests/long/60.bzip2/ref/alpha/linux/o3-timing/m5stats.txt2167
-rw-r--r--tests/long/60.bzip2/ref/alpha/linux/o3-timing/stderr2
-rw-r--r--tests/long/60.bzip2/ref/alpha/linux/o3-timing/stdout27
-rw-r--r--tests/long/60.bzip2/ref/alpha/linux/simple-atomic/config.ini352
-rw-r--r--tests/long/60.bzip2/ref/alpha/linux/simple-atomic/config.out346
-rw-r--r--tests/long/60.bzip2/ref/alpha/linux/simple-atomic/m5stats.txt1982
-rw-r--r--tests/long/60.bzip2/ref/alpha/linux/simple-atomic/stderr2
-rw-r--r--tests/long/60.bzip2/ref/alpha/linux/simple-atomic/stdout27
-rw-r--r--tests/long/60.bzip2/ref/alpha/linux/simple-timing/config.ini225
-rw-r--r--tests/long/60.bzip2/ref/alpha/linux/simple-timing/config.out265
-rw-r--r--tests/long/60.bzip2/ref/alpha/linux/simple-timing/m5stats.txt2048
-rw-r--r--tests/long/60.bzip2/ref/alpha/linux/simple-timing/stderr2
-rw-r--r--tests/long/60.bzip2/ref/alpha/linux/simple-timing/stdout27
-rw-r--r--tests/long/70.twolf/ref/alpha/linux/o3-timing/config.ini28
-rw-r--r--tests/long/70.twolf/ref/alpha/linux/o3-timing/config.out105
-rw-r--r--tests/long/70.twolf/ref/alpha/linux/o3-timing/m5stats.txt2167
-rw-r--r--tests/long/70.twolf/ref/alpha/linux/o3-timing/smred.out276
-rw-r--r--tests/long/70.twolf/ref/alpha/linux/o3-timing/smred.pin17
-rw-r--r--tests/long/70.twolf/ref/alpha/linux/o3-timing/smred.pl111
-rw-r--r--tests/long/70.twolf/ref/alpha/linux/o3-timing/smred.pl22
-rw-r--r--tests/long/70.twolf/ref/alpha/linux/o3-timing/smred.sav18
-rw-r--r--tests/long/70.twolf/ref/alpha/linux/o3-timing/smred.sv219
-rw-r--r--tests/long/70.twolf/ref/alpha/linux/o3-timing/smred.twf29
-rw-r--r--tests/long/70.twolf/ref/alpha/linux/o3-timing/stderr2
-rw-r--r--tests/long/70.twolf/ref/alpha/linux/o3-timing/stdout25
-rw-r--r--tests/long/70.twolf/ref/alpha/linux/simple-atomic/config.ini352
-rw-r--r--tests/long/70.twolf/ref/alpha/linux/simple-atomic/config.out346
-rw-r--r--tests/long/70.twolf/ref/alpha/linux/simple-atomic/m5stats.txt1982
-rw-r--r--tests/long/70.twolf/ref/alpha/linux/simple-atomic/smred.out276
-rw-r--r--tests/long/70.twolf/ref/alpha/linux/simple-atomic/smred.pin17
-rw-r--r--tests/long/70.twolf/ref/alpha/linux/simple-atomic/smred.pl111
-rw-r--r--tests/long/70.twolf/ref/alpha/linux/simple-atomic/smred.pl22
-rw-r--r--tests/long/70.twolf/ref/alpha/linux/simple-atomic/smred.sav18
-rw-r--r--tests/long/70.twolf/ref/alpha/linux/simple-atomic/smred.sv219
-rw-r--r--tests/long/70.twolf/ref/alpha/linux/simple-atomic/smred.twf29
-rw-r--r--tests/long/70.twolf/ref/alpha/linux/simple-atomic/stderr2
-rw-r--r--tests/long/70.twolf/ref/alpha/linux/simple-atomic/stdout25
-rw-r--r--tests/long/70.twolf/ref/alpha/linux/simple-timing/config.ini225
-rw-r--r--tests/long/70.twolf/ref/alpha/linux/simple-timing/config.out265
-rw-r--r--tests/long/70.twolf/ref/alpha/linux/simple-timing/m5stats.txt2036
-rw-r--r--tests/long/70.twolf/ref/alpha/linux/simple-timing/smred.out276
-rw-r--r--tests/long/70.twolf/ref/alpha/linux/simple-timing/smred.pin17
-rw-r--r--tests/long/70.twolf/ref/alpha/linux/simple-timing/smred.pl111
-rw-r--r--tests/long/70.twolf/ref/alpha/linux/simple-timing/smred.pl22
-rw-r--r--tests/long/70.twolf/ref/alpha/linux/simple-timing/smred.sav18
-rw-r--r--tests/long/70.twolf/ref/alpha/linux/simple-timing/smred.sv219
-rw-r--r--tests/long/70.twolf/ref/alpha/linux/simple-timing/smred.twf29
-rw-r--r--tests/long/70.twolf/ref/alpha/linux/simple-timing/stderr2
-rw-r--r--tests/long/70.twolf/ref/alpha/linux/simple-timing/stdout25
-rw-r--r--tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini8
-rw-r--r--tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.out8
-rw-r--r--tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/console.drivesys.sim_console4
-rw-r--r--tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/console.testsys.sim_console4
-rw-r--r--tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/m5stats.txt38
-rw-r--r--tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stdout13
-rwxr-xr-xutil/cscope-find.py38
-rwxr-xr-xutil/cscope-index.py71
-rwxr-xr-xutil/make_release.py30
-rwxr-xr-xutil/regress19
164 files changed, 9433 insertions, 41222 deletions
diff --git a/SConstruct b/SConstruct
index 50ca2d6e4..7e8c6c2f0 100644
--- a/SConstruct
+++ b/SConstruct
@@ -66,6 +66,7 @@
# Python library imports
import sys
import os
+from os.path import join as joinpath
# Check for recent-enough Python and SCons versions. If your system's
# default installation of Python is not recent enough, you can use a
@@ -89,11 +90,11 @@ except:
# The absolute path to the current directory (where this file lives).
ROOT = Dir('.').abspath
-# Paths to the M5 and external source trees.
-SRCDIR = os.path.join(ROOT, 'src')
+# Path to the M5 source tree.
+SRCDIR = joinpath(ROOT, 'src')
# tell python where to find m5 python code
-sys.path.append(os.path.join(ROOT, 'src/python'))
+sys.path.append(joinpath(ROOT, 'src/python'))
###################################################
#
@@ -105,13 +106,6 @@ sys.path.append(os.path.join(ROOT, 'src/python'))
# Find default configuration & binary.
Default(os.environ.get('M5_DEFAULT_BINARY', 'build/ALPHA_SE/m5.debug'))
-# Ask SCons which directory it was invoked from.
-launch_dir = GetLaunchDir()
-
-# Make targets relative to invocation directory
-abs_targets = map(lambda x: os.path.normpath(os.path.join(launch_dir, str(x))),
- BUILD_TARGETS)
-
# helper function: find last occurrence of element in list
def rfind(l, elt, offs = -1):
for i in range(len(l)+offs, 0, -1):
@@ -141,6 +135,19 @@ def compare_versions(v1, v2):
# recognize that ALPHA_SE specifies the configuration because it
# follow 'build' in the bulid path.
+# Generate absolute paths to targets so we can see where the build dir is
+if COMMAND_LINE_TARGETS:
+ # Ask SCons which directory it was invoked from
+ launch_dir = GetLaunchDir()
+ # Make targets relative to invocation directory
+ abs_targets = map(lambda x: os.path.normpath(joinpath(launch_dir, str(x))),
+ COMMAND_LINE_TARGETS)
+else:
+ # Default targets are relative to root of tree
+ abs_targets = map(lambda x: os.path.normpath(joinpath(ROOT, str(x))),
+ DEFAULT_TARGETS)
+
+
# Generate a list of the unique build roots and configs that the
# collected targets reference.
build_paths = []
@@ -152,7 +159,7 @@ for t in abs_targets:
except:
print "Error: no non-leaf 'build' dir found on target path", t
Exit(1)
- this_build_root = os.path.join('/',*path_dirs[:build_top+1])
+ this_build_root = joinpath('/',*path_dirs[:build_top+1])
if not build_root:
build_root = this_build_root
else:
@@ -160,7 +167,7 @@ for t in abs_targets:
print "Error: build targets not under same build root\n"\
" %s\n %s" % (build_root, this_build_root)
Exit(1)
- build_path = os.path.join('/',*path_dirs[:build_top+2])
+ build_path = joinpath('/',*path_dirs[:build_top+2])
if build_path not in build_paths:
build_paths.append(build_path)
@@ -183,7 +190,7 @@ if ARGUMENTS.get('CC', None):
if ARGUMENTS.get('CXX', None):
env['CXX'] = ARGUMENTS.get('CXX')
-env.SConsignFile(os.path.join(build_root,"sconsign"))
+env.SConsignFile(joinpath(build_root,"sconsign"))
# Default duplicate option is to use hard links, but this messes up
# when you use emacs to edit a file in the target dir, as emacs moves
@@ -243,8 +250,8 @@ env.Append(SCANNERS = swig_scanner)
# Platform-specific configuration. Note again that we assume that all
# builds under a given build root run on the same host platform.
conf = Configure(env,
- conf_dir = os.path.join(build_root, '.scons_config'),
- log_file = os.path.join(build_root, 'scons_config.log'))
+ conf_dir = joinpath(build_root, '.scons_config'),
+ log_file = joinpath(build_root, 'scons_config.log'))
# Find Python include and library directories for embedding the
# interpreter. For consistency, we will use the same Python
@@ -257,7 +264,7 @@ conf = Configure(env,
py_version_name = 'python' + sys.version[:3]
# include path, e.g. /usr/local/include/python2.4
-py_header_path = os.path.join(sys.exec_prefix, 'include', py_version_name)
+py_header_path = joinpath(sys.exec_prefix, 'include', py_version_name)
env.Append(CPPPATH = py_header_path)
# verify that it works
if not conf.CheckHeader('Python.h', '<>'):
@@ -267,7 +274,7 @@ if not conf.CheckHeader('Python.h', '<>'):
# add library path too if it's not in the default place
py_lib_path = None
if sys.exec_prefix != '/usr':
- py_lib_path = os.path.join(sys.exec_prefix, 'lib')
+ py_lib_path = joinpath(sys.exec_prefix, 'lib')
elif sys.platform == 'cygwin':
# cygwin puts the .dll in /bin for some reason
py_lib_path = '/bin'
@@ -330,7 +337,7 @@ env['ALL_ISA_LIST'] = ['alpha', 'sparc', 'mips']
env['ALL_CPU_LIST'] = ['AtomicSimpleCPU', 'TimingSimpleCPU',
'O3CPU', 'OzoneCPU']
-if os.path.isdir(os.path.join(SRCDIR, 'src/encumbered/cpu/full')):
+if os.path.isdir(joinpath(SRCDIR, 'encumbered/cpu/full')):
env['ALL_CPU_LIST'] += ['FullCPU']
# Sticky options get saved in the options file so they persist from
@@ -417,7 +424,7 @@ def config_emitter(target, source, env):
# extract option name from Builder arg
option = str(target[0])
# True target is config header file
- target = os.path.join('config', option.lower() + '.hh')
+ target = joinpath('config', option.lower() + '.hh')
val = env[option]
if isinstance(val, bool):
# Force value to 0/1
@@ -466,7 +473,7 @@ Usage: scons [scons options] [build options] [target(s)]
# libelf build is shared across all configs in the build root.
env.SConscript('ext/libelf/SConscript',
- build_dir = os.path.join(build_root, 'libelf'),
+ build_dir = joinpath(build_root, 'libelf'),
exports = 'env')
###################################################
@@ -531,7 +538,7 @@ for build_path in build_paths:
# Options for $BUILD_ROOT/$BUILD_DIR are stored in
# $BUILD_ROOT/options/$BUILD_DIR so you can nuke
# $BUILD_ROOT/$BUILD_DIR without losing your options settings.
- current_opts_file = os.path.join(build_root, 'options', build_dir)
+ current_opts_file = joinpath(build_root, 'options', build_dir)
if os.path.isfile(current_opts_file):
sticky_opts.files.append(current_opts_file)
print "Using saved options file %s" % current_opts_file
@@ -546,8 +553,8 @@ for build_path in build_paths:
# Get default build options from source tree. Options are
# normally determined by name of $BUILD_DIR, but can be
# overriden by 'default=' arg on command line.
- default_opts_file = os.path.join('build_opts',
- ARGUMENTS.get('default', build_dir))
+ default_opts_file = joinpath('build_opts',
+ ARGUMENTS.get('default', build_dir))
if os.path.isfile(default_opts_file):
sticky_opts.files.append(default_opts_file)
print "Options file %s not found,\n using defaults in %s" \
@@ -611,7 +618,7 @@ for build_path in build_paths:
# Set up the regression tests for each build.
for e in envList:
SConscript('tests/SConscript',
- build_dir = os.path.join(build_path, 'tests', e.Label),
+ build_dir = joinpath(build_path, 'tests', e.Label),
exports = { 'env' : e }, duplicate = False)
Help(help_text)
diff --git a/build_opts/SPARC_FS b/build_opts/SPARC_FS
index 59d17eee9..7c8bda0ce 100644
--- a/build_opts/SPARC_FS
+++ b/build_opts/SPARC_FS
@@ -1,2 +1,3 @@
TARGET_ISA = 'sparc'
+CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU'
FULL_SYSTEM = 1
diff --git a/build_opts/SPARC_SE b/build_opts/SPARC_SE
index 3b256fc34..62b6841ad 100644
--- a/build_opts/SPARC_SE
+++ b/build_opts/SPARC_SE
@@ -1,2 +1,3 @@
TARGET_ISA = 'sparc'
+CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU'
FULL_SYSTEM = 0
diff --git a/src/SConscript b/src/SConscript
index 429e1bee1..f54e1de0d 100644
--- a/src/SConscript
+++ b/src/SConscript
@@ -108,6 +108,7 @@ base_sources = Split('''
mem/cache/coherence/coherence_protocol.cc
mem/cache/coherence/uni_coherence.cc
mem/cache/miss/blocking_buffer.cc
+ mem/cache/miss/miss_buffer.cc
mem/cache/miss/miss_queue.cc
mem/cache/miss/mshr.cc
mem/cache/miss/mshr_queue.cc
diff --git a/src/arch/isa_parser.py b/src/arch/isa_parser.py
index 2086473d6..59eb18c9c 100755
--- a/src/arch/isa_parser.py
+++ b/src/arch/isa_parser.py
@@ -1180,15 +1180,16 @@ class IntRegOperand(Operand):
if (self.ctype == 'float' or self.ctype == 'double'):
error(0, 'Attempt to read integer register as FP')
if (self.size == self.dflt_size):
- return '%s = xc->readIntReg(this, %d);\n' % \
+ return '%s = xc->readIntRegOperand(this, %d);\n' % \
(self.base_name, self.src_reg_idx)
elif (self.size > self.dflt_size):
- int_reg_val = 'xc->readIntReg(this, %d)' % (self.src_reg_idx)
+ int_reg_val = 'xc->readIntRegOperand(this, %d)' % \
+ (self.src_reg_idx)
if (self.is_signed):
int_reg_val = 'sext<%d>(%s)' % (self.dflt_size, int_reg_val)
return '%s = %s;\n' % (self.base_name, int_reg_val)
else:
- return '%s = bits(xc->readIntReg(this, %d), %d, 0);\n' % \
+ return '%s = bits(xc->readIntRegOperand(this, %d), %d, 0);\n' % \
(self.base_name, self.src_reg_idx, self.size-1)
def makeWrite(self):
@@ -1201,7 +1202,7 @@ class IntRegOperand(Operand):
wb = '''
{
%s final_val = %s;
- xc->setIntReg(this, %d, final_val);\n
+ xc->setIntRegOperand(this, %d, final_val);\n
if (traceData) { traceData->setData(final_val); }
}''' % (self.dflt_ctype, final_val, self.dest_reg_idx)
return wb
@@ -1227,13 +1228,13 @@ class FloatRegOperand(Operand):
bit_select = 0
width = 0;
if (self.ctype == 'float'):
- func = 'readFloatReg'
+ func = 'readFloatRegOperand'
width = 32;
elif (self.ctype == 'double'):
- func = 'readFloatReg'
+ func = 'readFloatRegOperand'
width = 64;
else:
- func = 'readFloatRegBits'
+ func = 'readFloatRegOperandBits'
if (self.ctype == 'uint32_t'):
width = 32;
elif (self.ctype == 'uint64_t'):
@@ -1259,18 +1260,18 @@ class FloatRegOperand(Operand):
width = 0
if (self.ctype == 'float'):
width = 32
- func = 'setFloatReg'
+ func = 'setFloatRegOperand'
elif (self.ctype == 'double'):
width = 64
- func = 'setFloatReg'
+ func = 'setFloatRegOperand'
elif (self.ctype == 'uint32_t'):
- func = 'setFloatRegBits'
+ func = 'setFloatRegOperandBits'
width = 32
elif (self.ctype == 'uint64_t'):
- func = 'setFloatRegBits'
+ func = 'setFloatRegOperandBits'
width = 64
else:
- func = 'setFloatRegBits'
+ func = 'setFloatRegOperandBits'
final_ctype = 'uint%d_t' % self.dflt_size
if (self.size != self.dflt_size and self.is_signed):
final_val = 'sext<%d>(%s)' % (self.size, self.base_name)
diff --git a/src/arch/mips/isa/formats/fp.isa b/src/arch/mips/isa/formats/fp.isa
index cdb892b3f..153f3f949 100644
--- a/src/arch/mips/isa/formats/fp.isa
+++ b/src/arch/mips/isa/formats/fp.isa
@@ -99,7 +99,7 @@ output exec {{
int size = sizeof(src_op) * 8;
for (int i = 0; i < inst->numSrcRegs(); i++) {
- uint64_t src_bits = xc->readFloatRegBits(inst, 0, size);
+ uint64_t src_bits = xc->readFloatRegOperandBits(inst, 0, size);
if (isNan(&src_bits, size) ) {
if (isSnan(&src_bits, size)) {
@@ -113,7 +113,7 @@ output exec {{
mips_nan = src_bits;
}
- xc->setFloatRegBits(inst, 0, mips_nan, size);
+ xc->setFloatRegOperandBits(inst, 0, mips_nan, size);
if (traceData) { traceData->setData(mips_nan); }
return true;
}
@@ -139,7 +139,7 @@ output exec {{
}
//Set value to QNAN
- cpu->setFloatRegBits(inst, 0, mips_nan, size);
+ cpu->setFloatRegOperandBits(inst, 0, mips_nan, size);
//Read FCSR from FloatRegFile
uint32_t fcsr_bits = cpu->tcBase()->readFloatRegBits(FCSR);
diff --git a/src/base/compression/base.hh b/src/base/compression/base.hh
new file mode 100644
index 000000000..8d1f8d6b5
--- /dev/null
+++ b/src/base/compression/base.hh
@@ -0,0 +1,71 @@
+/*
+ * Copyright (c) 2003-2005 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Erik Hallnor
+ * Nathan Binkert
+ */
+
+#ifndef __BASE_COMPRESSION_BASE_HH__
+#define __BASE_COMPRESSION_BASE_HH__
+
+/**
+ * @file
+ * This file defines a base (abstract virtual) compression algorithm object.
+ */
+
+#include <inttypes.h>
+
+/**
+ * Abstract virtual compression algorithm object.
+ */
+class CompressionAlgorithm
+{
+ public:
+ virtual ~CompressionAlgorithm() {}
+
+ /**
+ * Uncompress the data, causes a fatal since no data should be compressed.
+ * @param dest The output buffer.
+ * @param src The compressed data.
+ * @param size The number of bytes in src.
+ *
+ * @retval The size of the uncompressed data.
+ */
+ virtual int uncompress(uint8_t * dest, uint8_t *src, int size) = 0;
+
+ /**
+ * Compress the data, just returns the source data.
+ * @param dest The output buffer.
+ * @param src The data to be compressed.
+ * @param size The number of bytes in src.
+ *
+ * @retval The size of the compressed data.
+ */
+ virtual int compress(uint8_t *dest, uint8_t *src, int size) = 0;
+};
+
+#endif //__BASE_COMPRESSION_BASE_HH__
diff --git a/src/base/compression/lzss_compression.hh b/src/base/compression/lzss_compression.hh
index 35e4dcb3f..a23d07ffd 100644
--- a/src/base/compression/lzss_compression.hh
+++ b/src/base/compression/lzss_compression.hh
@@ -35,12 +35,12 @@
* LZSSCompression declarations.
*/
-#include "sim/host.hh" // for uint8_t
+#include "base/compression/base.hh"
/**
* Simple LZSS compression scheme.
*/
-class LZSSCompression
+class LZSSCompression : public CompressionAlgorithm
{
/**
* Finds the longest substring for the given offset.
diff --git a/src/base/compression/null_compression.hh b/src/base/compression/null_compression.hh
index 5a582d828..ff110807a 100644
--- a/src/base/compression/null_compression.hh
+++ b/src/base/compression/null_compression.hh
@@ -38,41 +38,23 @@
*/
#include "base/misc.hh" // for fatal()
-#include "sim/host.hh"
+#include "base/compression/base.hh"
/**
* A dummy compression class to use when no data compression is desired.
*/
-class NullCompression
+class NullCompression : public CompressionAlgorithm
{
public:
- /**
- * Uncompress the data, causes a fatal since no data should be compressed.
- * @param dest The output buffer.
- * @param src The compressed data.
- * @param size The number of bytes in src.
- *
- * @retval The size of the uncompressed data.
- */
- static int uncompress(uint8_t * dest, uint8_t *src, int size)
+ int uncompress(uint8_t * dest, uint8_t *src, int size)
{
fatal("Can't uncompress data");
}
- /**
- * Compress the data, just returns the source data.
- * @param dest The output buffer.
- * @param src The data to be compressed.
- * @param size The number of bytes in src.
- *
- * @retval The size of the compressed data.
- */
-
- static int compress(uint8_t *dest, uint8_t *src, int size)
+ int compress(uint8_t *dest, uint8_t *src, int size)
{
- memcpy(dest,src,size);
- return size;
+ fatal("Can't compress data");
}
};
diff --git a/src/cpu/base_dyn_inst.hh b/src/cpu/base_dyn_inst.hh
index 4a4555566..9037c96df 100644
--- a/src/cpu/base_dyn_inst.hh
+++ b/src/cpu/base_dyn_inst.hh
@@ -406,14 +406,15 @@ class BaseDynInst : public FastAlloc, public RefCounted
double readDoubleResult() { return instResult.dbl; }
/** Records an integer register being set to a value. */
- void setIntReg(const StaticInst *si, int idx, uint64_t val)
+ void setIntRegOperand(const StaticInst *si, int idx, uint64_t val)
{
if (recordResult)
instResult.integer = val;
}
/** Records an fp register being set to a value. */
- void setFloatReg(const StaticInst *si, int idx, FloatReg val, int width)
+ void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val,
+ int width)
{
if (recordResult) {
if (width == 32)
@@ -426,21 +427,22 @@ class BaseDynInst : public FastAlloc, public RefCounted
}
/** Records an fp register being set to a value. */
- void setFloatReg(const StaticInst *si, int idx, FloatReg val)
+ void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val)
{
if (recordResult)
instResult.dbl = (double)val;
}
/** Records an fp register being set to an integer value. */
- void setFloatRegBits(const StaticInst *si, int idx, uint64_t val, int width)
+ void setFloatRegOperandBits(const StaticInst *si, int idx, uint64_t val,
+ int width)
{
if (recordResult)
instResult.integer = val;
}
/** Records an fp register being set to an integer value. */
- void setFloatRegBits(const StaticInst *si, int idx, uint64_t val)
+ void setFloatRegOperandBits(const StaticInst *si, int idx, uint64_t val)
{
if (recordResult)
instResult.integer = val;
diff --git a/src/cpu/checker/cpu.hh b/src/cpu/checker/cpu.hh
index 9be54529f..3e08193ee 100644
--- a/src/cpu/checker/cpu.hh
+++ b/src/cpu/checker/cpu.hh
@@ -216,42 +216,44 @@ class CheckerCPU : public BaseCPU
// storage (which is pretty hard to imagine they would have reason
// to do).
- uint64_t readIntReg(const StaticInst *si, int idx)
+ uint64_t readIntRegOperand(const StaticInst *si, int idx)
{
return thread->readIntReg(si->srcRegIdx(idx));
}
- FloatReg readFloatReg(const StaticInst *si, int idx, int width)
+ FloatReg readFloatRegOperand(const StaticInst *si, int idx, int width)
{
int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
return thread->readFloatReg(reg_idx, width);
}
- FloatReg readFloatReg(const StaticInst *si, int idx)
+ FloatReg readFloatRegOperand(const StaticInst *si, int idx)
{
int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
return thread->readFloatReg(reg_idx);
}
- FloatRegBits readFloatRegBits(const StaticInst *si, int idx, int width)
+ FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx,
+ int width)
{
int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
return thread->readFloatRegBits(reg_idx, width);
}
- FloatRegBits readFloatRegBits(const StaticInst *si, int idx)
+ FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx)
{
int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
return thread->readFloatRegBits(reg_idx);
}
- void setIntReg(const StaticInst *si, int idx, uint64_t val)
+ void setIntRegOperand(const StaticInst *si, int idx, uint64_t val)
{
thread->setIntReg(si->destRegIdx(idx), val);
result.integer = val;
}
- void setFloatReg(const StaticInst *si, int idx, FloatReg val, int width)
+ void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val,
+ int width)
{
int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
thread->setFloatReg(reg_idx, val, width);
@@ -265,22 +267,23 @@ class CheckerCPU : public BaseCPU
};
}
- void setFloatReg(const StaticInst *si, int idx, FloatReg val)
+ void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val)
{
int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
thread->setFloatReg(reg_idx, val);
result.dbl = (double)val;
}
- void setFloatRegBits(const StaticInst *si, int idx, FloatRegBits val,
- int width)
+ void setFloatRegOperandBits(const StaticInst *si, int idx,
+ FloatRegBits val, int width)
{
int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
thread->setFloatRegBits(reg_idx, val, width);
result.integer = val;
}
- void setFloatRegBits(const StaticInst *si, int idx, FloatRegBits val)
+ void setFloatRegOperandBits(const StaticInst *si, int idx,
+ FloatRegBits val)
{
int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
thread->setFloatRegBits(reg_idx, val);
diff --git a/src/cpu/exec_context.hh b/src/cpu/exec_context.hh
index 13f70fa79..edccd747f 100644
--- a/src/cpu/exec_context.hh
+++ b/src/cpu/exec_context.hh
@@ -48,39 +48,42 @@ class ExecContext {
// to do).
/** Reads an integer register. */
- uint64_t readIntReg(const StaticInst *si, int idx);
+ uint64_t readIntRegOperand(const StaticInst *si, int idx);
/** Reads a floating point register of a specific width. */
- FloatReg readFloatReg(const StaticInst *si, int idx, int width);
+ FloatReg readFloatRegOperand(const StaticInst *si, int idx, int width);
/** Reads a floating point register of single register width. */
- FloatReg readFloatReg(const StaticInst *si, int idx);
+ FloatReg readFloatRegOperand(const StaticInst *si, int idx);
/** Reads a floating point register of a specific width in its
* binary format, instead of by value. */
- FloatRegBits readFloatRegBits(const StaticInst *si, int idx, int width);
+ FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx,
+ int width);
/** Reads a floating point register in its binary format, instead
* of by value. */
- FloatRegBits readFloatRegBits(const StaticInst *si, int idx);
+ FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx);
/** Sets an integer register to a value. */
- void setIntReg(const StaticInst *si, int idx, uint64_t val);
+ void setIntRegOperand(const StaticInst *si, int idx, uint64_t val);
/** Sets a floating point register of a specific width to a value. */
- void setFloatReg(const StaticInst *si, int idx, FloatReg val, int width);
+ void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val,
+ int width);
/** Sets a floating point register of single width to a value. */
- void setFloatReg(const StaticInst *si, int idx, FloatReg val);
+ void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val);
/** Sets the bits of a floating point register of a specific width
* to a binary value. */
- void setFloatRegBits(const StaticInst *si, int idx,
- FloatRegBits val, int width);
+ void setFloatRegOperandBits(const StaticInst *si, int idx,
+ FloatRegBits val, int width);
/** Sets the bits of a floating point register of single width
* to a binary value. */
- void setFloatRegBits(const StaticInst *si, int idx, FloatRegBits val);
+ void setFloatRegOperandBits(const StaticInst *si, int idx,
+ FloatRegBits val);
/** Reads the PC. */
uint64_t readPC();
diff --git a/src/cpu/o3/alpha/dyn_inst.hh b/src/cpu/o3/alpha/dyn_inst.hh
index 31df8ff78..49cc5a201 100644
--- a/src/cpu/o3/alpha/dyn_inst.hh
+++ b/src/cpu/o3/alpha/dyn_inst.hh
@@ -163,27 +163,28 @@ class AlphaDynInst : public BaseDynInst<Impl>
// storage (which is pretty hard to imagine they would have reason
// to do).
- uint64_t readIntReg(const StaticInst *si, int idx)
+ uint64_t readIntRegOperand(const StaticInst *si, int idx)
{
return this->cpu->readIntReg(_srcRegIdx[idx]);
}
- FloatReg readFloatReg(const StaticInst *si, int idx, int width)
+ FloatReg readFloatRegOperand(const StaticInst *si, int idx, int width)
{
return this->cpu->readFloatReg(_srcRegIdx[idx], width);
}
- FloatReg readFloatReg(const StaticInst *si, int idx)
+ FloatReg readFloatRegOperand(const StaticInst *si, int idx)
{
return this->cpu->readFloatReg(_srcRegIdx[idx]);
}
- FloatRegBits readFloatRegBits(const StaticInst *si, int idx, int width)
+ FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx,
+ int width)
{
return this->cpu->readFloatRegBits(_srcRegIdx[idx], width);
}
- FloatRegBits readFloatRegBits(const StaticInst *si, int idx)
+ FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx)
{
return this->cpu->readFloatRegBits(_srcRegIdx[idx]);
}
@@ -191,35 +192,37 @@ class AlphaDynInst : public BaseDynInst<Impl>
/** @todo: Make results into arrays so they can handle multiple dest
* registers.
*/
- void setIntReg(const StaticInst *si, int idx, uint64_t val)
+ void setIntRegOperand(const StaticInst *si, int idx, uint64_t val)
{
this->cpu->setIntReg(_destRegIdx[idx], val);
- BaseDynInst<Impl>::setIntReg(si, idx, val);
+ BaseDynInst<Impl>::setIntRegOperand(si, idx, val);
}
- void setFloatReg(const StaticInst *si, int idx, FloatReg val, int width)
+ void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val,
+ int width)
{
this->cpu->setFloatReg(_destRegIdx[idx], val, width);
- BaseDynInst<Impl>::setFloatReg(si, idx, val, width);
+ BaseDynInst<Impl>::setFloatRegOperand(si, idx, val, width);
}
- void setFloatReg(const StaticInst *si, int idx, FloatReg val)
+ void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val)
{
this->cpu->setFloatReg(_destRegIdx[idx], val);
- BaseDynInst<Impl>::setFloatReg(si, idx, val);
+ BaseDynInst<Impl>::setFloatRegOperand(si, idx, val);
}
- void setFloatRegBits(const StaticInst *si, int idx,
- FloatRegBits val, int width)
+ void setFloatRegOperandBits(const StaticInst *si, int idx,
+ FloatRegBits val, int width)
{
this->cpu->setFloatRegBits(_destRegIdx[idx], val, width);
- BaseDynInst<Impl>::setFloatRegBits(si, idx, val);
+ BaseDynInst<Impl>::setFloatRegOperandBits(si, idx, val);
}
- void setFloatRegBits(const StaticInst *si, int idx, FloatRegBits val)
+ void setFloatRegOperandBits(const StaticInst *si, int idx,
+ FloatRegBits val)
{
this->cpu->setFloatRegBits(_destRegIdx[idx], val);
- BaseDynInst<Impl>::setFloatRegBits(si, idx, val);
+ BaseDynInst<Impl>::setFloatRegOperandBits(si, idx, val);
}
/** Returns the physical register index of the i'th destination
diff --git a/src/cpu/o3/commit_impl.hh b/src/cpu/o3/commit_impl.hh
index e72679710..f400d757b 100644
--- a/src/cpu/o3/commit_impl.hh
+++ b/src/cpu/o3/commit_impl.hh
@@ -748,6 +748,7 @@ DefaultCommit<Impl>::commit()
}
} else {
bdelay_done_seq_num = squashed_inst;
+ squash_bdelay_slot = true;
}
#endif
@@ -1196,16 +1197,16 @@ DefaultCommit<Impl>::getInsts()
rename_idx < fromRename->size;
rename_idx++) {
DynInstPtr inst = fromRename->insts[rename_idx];
- int tid = inst->threadNumber;
if (!inst->isSquashed()) {
DPRINTF(Commit, "Inserting PC %#x [sn:%i] [tid:%i] into ",
- "skidBuffer.\n", inst->readPC(), inst->seqNum, tid);
+ "skidBuffer.\n", inst->readPC(), inst->seqNum,
+ inst->threadNumber);
skidBuffer.push(inst);
} else {
DPRINTF(Commit, "Instruction PC %#x [sn:%i] [tid:%i] was "
"squashed, skipping.\n",
- inst->readPC(), inst->seqNum, tid);
+ inst->readPC(), inst->seqNum, inst->threadNumber);
}
}
}
diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh
index 63d22b293..622259495 100644
--- a/src/cpu/o3/fetch_impl.hh
+++ b/src/cpu/o3/fetch_impl.hh
@@ -151,36 +151,6 @@ DefaultFetch<Impl>::DefaultFetch(Params *params)
" RoundRobin,LSQcount,IQcount}\n");
}
- // Size of cache block.
- cacheBlkSize = 64;
-
- // Create mask to get rid of offset bits.
- cacheBlkMask = (cacheBlkSize - 1);
-
- for (int tid=0; tid < numThreads; tid++) {
-
- fetchStatus[tid] = Running;
-
- priorityList.push_back(tid);
-
- memReq[tid] = NULL;
-
- // Create space to store a cache line.
- cacheData[tid] = new uint8_t[cacheBlkSize];
- cacheDataPC[tid] = 0;
- cacheDataValid[tid] = false;
-
- delaySlotInfo[tid].branchSeqNum = -1;
- delaySlotInfo[tid].numInsts = 0;
- delaySlotInfo[tid].targetAddr = 0;
- delaySlotInfo[tid].targetReady = false;
-
- stalls[tid].decode = false;
- stalls[tid].rename = false;
- stalls[tid].iew = false;
- stalls[tid].commit = false;
- }
-
// Get the size of an instruction.
instSize = sizeof(TheISA::MachInst);
}
@@ -353,6 +323,36 @@ DefaultFetch<Impl>::initStage()
nextNPC[tid] = cpu->readNextNPC(tid);
#endif
}
+
+ // Size of cache block.
+ cacheBlkSize = icachePort->peerBlockSize();
+
+ // Create mask to get rid of offset bits.
+ cacheBlkMask = (cacheBlkSize - 1);
+
+ for (int tid=0; tid < numThreads; tid++) {
+
+ fetchStatus[tid] = Running;
+
+ priorityList.push_back(tid);
+
+ memReq[tid] = NULL;
+
+ // Create space to store a cache line.
+ cacheData[tid] = new uint8_t[cacheBlkSize];
+ cacheDataPC[tid] = 0;
+ cacheDataValid[tid] = false;
+
+ delaySlotInfo[tid].branchSeqNum = -1;
+ delaySlotInfo[tid].numInsts = 0;
+ delaySlotInfo[tid].targetAddr = 0;
+ delaySlotInfo[tid].targetReady = false;
+
+ stalls[tid].decode = false;
+ stalls[tid].rename = false;
+ stalls[tid].iew = false;
+ stalls[tid].commit = false;
+ }
}
template<class Impl>
@@ -1139,6 +1139,8 @@ DefaultFetch<Impl>::fetch(bool &status_change)
ext_inst = TheISA::makeExtMI(inst, fetch_PC);
#elif THE_ISA == SPARC_ISA
ext_inst = TheISA::makeExtMI(inst, cpu->thread[tid]->getTC());
+#elif THE_ISA == MIPS_ISA
+ ext_inst = TheISA::makeExtMI(inst, cpu->thread[tid]->getTC());
#endif
// Create a new DynInst from the instruction fetched.
diff --git a/src/cpu/o3/lsq_unit_impl.hh b/src/cpu/o3/lsq_unit_impl.hh
index 4facea9f9..3b84d3411 100644
--- a/src/cpu/o3/lsq_unit_impl.hh
+++ b/src/cpu/o3/lsq_unit_impl.hh
@@ -418,7 +418,8 @@ LSQUnit<Impl>::executeLoad(DynInstPtr &inst)
// realizes there is activity.
// Mark it as executed unless it is an uncached load that
// needs to hit the head of commit.
- if (!(inst->req->isUncacheable()) || inst->isAtCommit()) {
+ if (!(inst->req && inst->req->isUncacheable()) ||
+ inst->isAtCommit()) {
inst->setExecuted();
}
iewStage->instToCommit(inst);
diff --git a/src/cpu/o3/mips/dyn_inst.hh b/src/cpu/o3/mips/dyn_inst.hh
index 9e95b2bfb..833371e00 100755
--- a/src/cpu/o3/mips/dyn_inst.hh
+++ b/src/cpu/o3/mips/dyn_inst.hh
@@ -156,27 +156,28 @@ class MipsDynInst : public BaseDynInst<Impl>
// storage (which is pretty hard to imagine they would have reason
// to do).
- uint64_t readIntReg(const StaticInst *si, int idx)
+ uint64_t readIntRegOperand(const StaticInst *si, int idx)
{
return this->cpu->readIntReg(_srcRegIdx[idx]);
}
- FloatReg readFloatReg(const StaticInst *si, int idx, int width)
+ FloatReg readFloatRegOperand(const StaticInst *si, int idx, int width)
{
return this->cpu->readFloatReg(_srcRegIdx[idx], width);
}
- FloatReg readFloatReg(const StaticInst *si, int idx)
+ FloatReg readFloatRegOperand(const StaticInst *si, int idx)
{
return this->cpu->readFloatReg(_srcRegIdx[idx]);
}
- FloatRegBits readFloatRegBits(const StaticInst *si, int idx, int width)
+ FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx,
+ int width)
{
return this->cpu->readFloatRegBits(_srcRegIdx[idx], width);
}
- FloatRegBits readFloatRegBits(const StaticInst *si, int idx)
+ FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx)
{
return this->cpu->readFloatRegBits(_srcRegIdx[idx]);
}
@@ -184,35 +185,37 @@ class MipsDynInst : public BaseDynInst<Impl>
/** @todo: Make results into arrays so they can handle multiple dest
* registers.
*/
- void setIntReg(const StaticInst *si, int idx, uint64_t val)
+ void setIntRegOperand(const StaticInst *si, int idx, uint64_t val)
{
this->cpu->setIntReg(_destRegIdx[idx], val);
- BaseDynInst<Impl>::setIntReg(si, idx, val);
+ BaseDynInst<Impl>::setIntRegOperand(si, idx, val);
}
- void setFloatReg(const StaticInst *si, int idx, FloatReg val, int width)
+ void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val,
+ int width)
{
this->cpu->setFloatReg(_destRegIdx[idx], val, width);
- BaseDynInst<Impl>::setFloatReg(si, idx, val, width);
+ BaseDynInst<Impl>::setFloatRegOperand(si, idx, val, width);
}
- void setFloatReg(const StaticInst *si, int idx, FloatReg val)
+ void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val)
{
this->cpu->setFloatReg(_destRegIdx[idx], val);
- BaseDynInst<Impl>::setFloatReg(si, idx, val);
+ BaseDynInst<Impl>::setFloatRegOperand(si, idx, val);
}
- void setFloatRegBits(const StaticInst *si, int idx,
- FloatRegBits val, int width)
+ void setFloatRegOperandBits(const StaticInst *si, int idx,
+ FloatRegBits val, int width)
{
this->cpu->setFloatRegBits(_destRegIdx[idx], val, width);
- BaseDynInst<Impl>::setFloatRegBits(si, idx, val);
+ BaseDynInst<Impl>::setFloatRegOperandBits(si, idx, val);
}
- void setFloatRegBits(const StaticInst *si, int idx, FloatRegBits val)
+ void setFloatRegOperandBits(const StaticInst *si, int idx,
+ FloatRegBits val)
{
this->cpu->setFloatRegBits(_destRegIdx[idx], val);
- BaseDynInst<Impl>::setFloatRegBits(si, idx, val);
+ BaseDynInst<Impl>::setFloatRegOperandBits(si, idx, val);
}
/** Returns the physical register index of the i'th destination
diff --git a/src/cpu/ozone/cpu.hh b/src/cpu/ozone/cpu.hh
index c1373944d..0da446c9c 100644
--- a/src/cpu/ozone/cpu.hh
+++ b/src/cpu/ozone/cpu.hh
@@ -448,30 +448,6 @@ class OzoneCPU : public BaseCPU
}
#endif
- /** Old CPU read from memory function. No longer used. */
- template <class T>
- Fault read(Request *req, T &data)
- {
-#if 0
-#if FULL_SYSTEM && defined(TARGET_ALPHA)
- if (req->isLocked()) {
- req->xc->setMiscReg(TheISA::Lock_Addr_DepTag, req->paddr);
- req->xc->setMiscReg(TheISA::Lock_Flag_DepTag, true);
- }
-#endif
- if (req->isLocked()) {
- lockAddrList.insert(req->paddr);
- lockFlag = true;
- }
-#endif
- Fault error;
-
- error = this->mem->read(req, data);
- data = gtoh(data);
- return error;
- }
-
-
/** CPU read function, forwards read to LSQ. */
template <class T>
Fault read(Request *req, T &data, int load_idx)
@@ -479,81 +455,6 @@ class OzoneCPU : public BaseCPU
return backEnd->read(req, data, load_idx);
}
- /** Old CPU write to memory function. No longer used. */
- template <class T>
- Fault write(Request *req, T &data)
- {
-#if 0
-#if FULL_SYSTEM && defined(TARGET_ALPHA)
- ExecContext *xc;
-
- // If this is a store conditional, act appropriately
- if (req->isLocked()) {
- xc = req->xc;
-
- if (req->isUncacheable()) {
- // Don't update result register (see stq_c in isa_desc)
- req->result = 2;
- xc->setStCondFailures(0);//Needed? [RGD]
- } else {
- bool lock_flag = xc->readMiscReg(TheISA::Lock_Flag_DepTag);
- Addr lock_addr = xc->readMiscReg(TheISA::Lock_Addr_DepTag);
- req->result = lock_flag;
- if (!lock_flag ||
- ((lock_addr & ~0xf) != (req->paddr & ~0xf))) {
- xc->setMiscReg(TheISA::Lock_Flag_DepTag, false);
- xc->setStCondFailures(xc->readStCondFailures() + 1);
- if (((xc->readStCondFailures()) % 100000) == 0) {
- std::cerr << "Warning: "
- << xc->readStCondFailures()
- << " consecutive store conditional failures "
- << "on cpu " << req->xc->readCpuId()
- << std::endl;
- }
- return NoFault;
- }
- else xc->setStCondFailures(0);
- }
- }
-
- // Need to clear any locked flags on other proccessors for
- // this address. Only do this for succsful Store Conditionals
- // and all other stores (WH64?). Unsuccessful Store
- // Conditionals would have returned above, and wouldn't fall
- // through.
- for (int i = 0; i < this->system->threadContexts.size(); i++){
- xc = this->system->threadContexts[i];
- if ((xc->readMiscReg(TheISA::Lock_Addr_DepTag) & ~0xf) ==
- (req->paddr & ~0xf)) {
- xc->setMiscReg(TheISA::Lock_Flag_DepTag, false);
- }
- }
-
-#endif
-
- if (req->isLocked()) {
- if (req->isUncacheable()) {
- req->result = 2;
- } else {
- if (this->lockFlag) {
- if (lockAddrList.find(req->paddr) !=
- lockAddrList.end()) {
- req->result = 1;
- } else {
- req->result = 0;
- return NoFault;
- }
- } else {
- req->result = 0;
- return NoFault;
- }
- }
- }
-#endif
-
- return this->mem->write(req, (T)htog(data));
- }
-
/** CPU write function, forwards write to LSQ. */
template <class T>
Fault write(Request *req, T &data, int store_idx)
diff --git a/src/cpu/ozone/dyn_inst.hh b/src/cpu/ozone/dyn_inst.hh
index 9445a5309..88f96b14b 100644
--- a/src/cpu/ozone/dyn_inst.hh
+++ b/src/cpu/ozone/dyn_inst.hh
@@ -146,12 +146,12 @@ class OzoneDynInst : public BaseDynInst<Impl>
// storage (which is pretty hard to imagine they would have reason
// to do).
- uint64_t readIntReg(const StaticInst *si, int idx)
+ uint64_t readIntRegOperand(const StaticInst *si, int idx)
{
return srcInsts[idx]->readIntResult();
}
- FloatReg readFloatReg(const StaticInst *si, int idx, int width)
+ FloatReg readFloatRegOperand(const StaticInst *si, int idx, int width)
{
switch(width) {
case 32:
@@ -164,17 +164,18 @@ class OzoneDynInst : public BaseDynInst<Impl>
}
}
- FloatReg readFloatReg(const StaticInst *si, int idx)
+ FloatReg readFloatRegOperand(const StaticInst *si, int idx)
{
return srcInsts[idx]->readFloatResult();
}
- FloatRegBits readFloatRegBits(const StaticInst *si, int idx, int width)
+ FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx,
+ int width)
{
return srcInsts[idx]->readIntResult();
}
- FloatRegBits readFloatRegBits(const StaticInst *si, int idx)
+ FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx)
{
return srcInsts[idx]->readIntResult();
}
@@ -182,28 +183,30 @@ class OzoneDynInst : public BaseDynInst<Impl>
/** @todo: Make results into arrays so they can handle multiple dest
* registers.
*/
- void setIntReg(const StaticInst *si, int idx, uint64_t val)
+ void setIntRegOperand(const StaticInst *si, int idx, uint64_t val)
{
BaseDynInst<Impl>::setIntReg(si, idx, val);
}
- void setFloatReg(const StaticInst *si, int idx, FloatReg val, int width)
+ void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val,
+ int width)
{
BaseDynInst<Impl>::setFloatReg(si, idx, val, width);
}
- void setFloatReg(const StaticInst *si, int idx, FloatReg val)
+ void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val)
{
BaseDynInst<Impl>::setFloatReg(si, idx, val);
}
- void setFloatRegBits(const StaticInst *si, int idx,
- FloatRegBits val, int width)
+ void setFloatRegOperandBits(const StaticInst *si, int idx,
+ FloatRegBits val, int width)
{
BaseDynInst<Impl>::setFloatRegBits(si, idx, val);
}
- void setFloatRegBits(const StaticInst *si, int idx, FloatRegBits val)
+ void setFloatRegOperandBits(const StaticInst *si, int idx,
+ FloatRegBits val)
{
BaseDynInst<Impl>::setFloatRegBits(si, idx, val);
}
diff --git a/src/cpu/ozone/inorder_back_end.hh b/src/cpu/ozone/inorder_back_end.hh
index b2522bdc8..4fd8e02f8 100644
--- a/src/cpu/ozone/inorder_back_end.hh
+++ b/src/cpu/ozone/inorder_back_end.hh
@@ -236,25 +236,6 @@ InorderBackEnd<Impl>::read(Addr addr, T &data, unsigned flags)
*/
return fault;
}
-#if 0
-template <class Impl>
-template <class T>
-Fault
-InorderBackEnd<Impl>::read(MemReqPtr &req, T &data)
-{
-#if FULL_SYSTEM && defined(TARGET_ALPHA)
- if (req->isLocked()) {
- req->xc->setMiscReg(TheISA::Lock_Addr_DepTag, req->paddr);
- req->xc->setMiscReg(TheISA::Lock_Flag_DepTag, true);
- }
-#endif
-
- Fault error;
- error = thread->mem->read(req, data);
- data = LittleEndianGuest::gtoh(data);
- return error;
-}
-#endif
template <class Impl>
template <class T>
@@ -296,61 +277,6 @@ InorderBackEnd<Impl>::write(T data, Addr addr, unsigned flags, uint64_t *res)
*/
return fault;
}
-#if 0
-template <class Impl>
-template <class T>
-Fault
-InorderBackEnd<Impl>::write(MemReqPtr &req, T &data)
-{
-#if FULL_SYSTEM && defined(TARGET_ALPHA)
- ExecContext *xc;
-
- // If this is a store conditional, act appropriately
- if (req->isLocked()) {
- xc = req->xc;
-
- if (req->isUncacheable()) {
- // Don't update result register (see stq_c in isa_desc)
- req->result = 2;
- xc->setStCondFailures(0);//Needed? [RGD]
- } else {
- bool lock_flag = xc->readMiscReg(TheISA::Lock_Flag_DepTag);
- Addr lock_addr = xc->readMiscReg(TheISA::Lock_Addr_DepTag);
- req->result = lock_flag;
- if (!lock_flag ||
- ((lock_addr & ~0xf) != (req->paddr & ~0xf))) {
- xc->setMiscReg(TheISA::Lock_Flag_DepTag, false);
- xc->setStCondFailures(xc->readStCondFailures() + 1);
- if (((xc->readStCondFailures()) % 100000) == 0) {
- std::cerr << "Warning: "
- << xc->readStCondFailures()
- << " consecutive store conditional failures "
- << "on cpu " << req->xc->readCpuId()
- << std::endl;
- }
- return NoFault;
- }
- else xc->setStCondFailures(0);
- }
- }
-
- // Need to clear any locked flags on other proccessors for
- // this address. Only do this for succsful Store Conditionals
- // and all other stores (WH64?). Unsuccessful Store
- // Conditionals would have returned above, and wouldn't fall
- // through.
- for (int i = 0; i < cpu->system->execContexts.size(); i++){
- xc = cpu->system->execContexts[i];
- if ((xc->readMiscReg(TheISA::Lock_Addr_DepTag) & ~0xf) ==
- (req->paddr & ~0xf)) {
- xc->setMiscReg(TheISA::Lock_Flag_DepTag, false);
- }
- }
-
-#endif
- return thread->mem->write(req, (T)LittleEndianGuest::htog(data));
-}
-#endif
template <class Impl>
template <class T>
diff --git a/src/cpu/simple/base.hh b/src/cpu/simple/base.hh
index efb884325..c39bfa9cd 100644
--- a/src/cpu/simple/base.hh
+++ b/src/cpu/simple/base.hh
@@ -213,60 +213,63 @@ class BaseSimpleCPU : public BaseCPU
// storage (which is pretty hard to imagine they would have reason
// to do).
- uint64_t readIntReg(const StaticInst *si, int idx)
+ uint64_t readIntRegOperand(const StaticInst *si, int idx)
{
return thread->readIntReg(si->srcRegIdx(idx));
}
- FloatReg readFloatReg(const StaticInst *si, int idx, int width)
+ FloatReg readFloatRegOperand(const StaticInst *si, int idx, int width)
{
int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
return thread->readFloatReg(reg_idx, width);
}
- FloatReg readFloatReg(const StaticInst *si, int idx)
+ FloatReg readFloatRegOperand(const StaticInst *si, int idx)
{
int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
return thread->readFloatReg(reg_idx);
}
- FloatRegBits readFloatRegBits(const StaticInst *si, int idx, int width)
+ FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx,
+ int width)
{
int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
return thread->readFloatRegBits(reg_idx, width);
}
- FloatRegBits readFloatRegBits(const StaticInst *si, int idx)
+ FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx)
{
int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
return thread->readFloatRegBits(reg_idx);
}
- void setIntReg(const StaticInst *si, int idx, uint64_t val)
+ void setIntRegOperand(const StaticInst *si, int idx, uint64_t val)
{
thread->setIntReg(si->destRegIdx(idx), val);
}
- void setFloatReg(const StaticInst *si, int idx, FloatReg val, int width)
+ void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val,
+ int width)
{
int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
thread->setFloatReg(reg_idx, val, width);
}
- void setFloatReg(const StaticInst *si, int idx, FloatReg val)
+ void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val)
{
int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
thread->setFloatReg(reg_idx, val);
}
- void setFloatRegBits(const StaticInst *si, int idx,
- FloatRegBits val, int width)
+ void setFloatRegOperandBits(const StaticInst *si, int idx,
+ FloatRegBits val, int width)
{
int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
thread->setFloatRegBits(reg_idx, val, width);
}
- void setFloatRegBits(const StaticInst *si, int idx, FloatRegBits val)
+ void setFloatRegOperandBits(const StaticInst *si, int idx,
+ FloatRegBits val)
{
int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
thread->setFloatRegBits(reg_idx, val);
diff --git a/src/cpu/simple_thread.hh b/src/cpu/simple_thread.hh
index e8757c8c2..10bbe292c 100644
--- a/src/cpu/simple_thread.hh
+++ b/src/cpu/simple_thread.hh
@@ -232,75 +232,6 @@ class SimpleThread : public ThreadState
/// Set the status to Halted.
void halt();
-/*
- template <class T>
- Fault read(RequestPtr &req, T &data)
- {
-#if FULL_SYSTEM && THE_ISA == ALPHA_ISA
- if (req->isLocked()) {
- req->xc->setMiscReg(TheISA::Lock_Addr_DepTag, req->paddr);
- req->xc->setMiscReg(TheISA::Lock_Flag_DepTag, true);
- }
-#endif
-
- Fault error;
- error = mem->prot_read(req->paddr, data, req->size);
- data = LittleEndianGuest::gtoh(data);
- return error;
- }
-
- template <class T>
- Fault write(RequestPtr &req, T &data)
- {
-#if FULL_SYSTEM && THE_ISA == ALPHA_ISA
- ExecContext *xc;
-
- // If this is a store conditional, act appropriately
- if (req->isLocked()) {
- xc = req->xc;
-
- if (req->isUncacheable()) {
- // Don't update result register (see stq_c in isa_desc)
- req->result = 2;
- xc->setStCondFailures(0);//Needed? [RGD]
- } else {
- bool lock_flag = xc->readMiscReg(TheISA::Lock_Flag_DepTag);
- Addr lock_addr = xc->readMiscReg(TheISA::Lock_Addr_DepTag);
- req->result = lock_flag;
- if (!lock_flag ||
- ((lock_addr & ~0xf) != (req->paddr & ~0xf))) {
- xc->setMiscReg(TheISA::Lock_Flag_DepTag, false);
- xc->setStCondFailures(xc->readStCondFailures() + 1);
- if (((xc->readStCondFailures()) % 100000) == 0) {
- std::cerr << "Warning: "
- << xc->readStCondFailures()
- << " consecutive store conditional failures "
- << "on cpu " << req->xc->readCpuId()
- << std::endl;
- }
- return NoFault;
- }
- else xc->setStCondFailures(0);
- }
- }
-
- // Need to clear any locked flags on other proccessors for
- // this address. Only do this for succsful Store Conditionals
- // and all other stores (WH64?). Unsuccessful Store
- // Conditionals would have returned above, and wouldn't fall
- // through.
- for (int i = 0; i < system->execContexts.size(); i++){
- xc = system->execContexts[i];
- if ((xc->readMiscReg(TheISA::Lock_Addr_DepTag) & ~0xf) ==
- (req->paddr & ~0xf)) {
- xc->setMiscReg(TheISA::Lock_Flag_DepTag, false);
- }
- }
-
-#endif
- return mem->prot_write(req->paddr, (T)htog(data), req->size);
- }
-*/
virtual bool misspeculating();
Fault instRead(RequestPtr &req)
diff --git a/src/mem/cache/cache.cc b/src/mem/cache/cache.cc
index db66c096e..29ca09060 100644
--- a/src/mem/cache/cache.cc
+++ b/src/mem/cache/cache.cc
@@ -37,7 +37,6 @@
*/
#include "mem/config/cache.hh"
-#include "mem/config/compression.hh"
#include "mem/cache/tags/cache_tags.hh"
@@ -61,11 +60,6 @@
#include "mem/cache/tags/split_lifo.hh"
#endif
-#include "base/compression/null_compression.hh"
-#if defined(USE_LZSS_COMPRESSION)
-#include "base/compression/lzss_compression.hh"
-#endif
-
#include "mem/cache/miss/miss_queue.hh"
#include "mem/cache/miss/blocking_buffer.hh"
@@ -79,68 +73,28 @@
#if defined(USE_CACHE_FALRU)
-template class Cache<CacheTags<FALRU,NullCompression>, BlockingBuffer, SimpleCoherence>;
-template class Cache<CacheTags<FALRU,NullCompression>, BlockingBuffer, UniCoherence>;
-template class Cache<CacheTags<FALRU,NullCompression>, MissQueue, SimpleCoherence>;
-template class Cache<CacheTags<FALRU,NullCompression>, MissQueue, UniCoherence>;
-#if defined(USE_LZSS_COMPRESSION)
-template class Cache<CacheTags<FALRU,LZSSCompression>, BlockingBuffer, SimpleCoherence>;
-template class Cache<CacheTags<FALRU,LZSSCompression>, BlockingBuffer, UniCoherence>;
-template class Cache<CacheTags<FALRU,LZSSCompression>, MissQueue, SimpleCoherence>;
-template class Cache<CacheTags<FALRU,LZSSCompression>, MissQueue, UniCoherence>;
-#endif
+template class Cache<CacheTags<FALRU>, SimpleCoherence>;
+template class Cache<CacheTags<FALRU>, UniCoherence>;
#endif
#if defined(USE_CACHE_IIC)
-template class Cache<CacheTags<IIC,NullCompression>, BlockingBuffer, SimpleCoherence>;
-template class Cache<CacheTags<IIC,NullCompression>, BlockingBuffer, UniCoherence>;
-template class Cache<CacheTags<IIC,NullCompression>, MissQueue, SimpleCoherence>;
-template class Cache<CacheTags<IIC,NullCompression>, MissQueue, UniCoherence>;
-#if defined(USE_LZSS_COMPRESSION)
-template class Cache<CacheTags<IIC,LZSSCompression>, BlockingBuffer, SimpleCoherence>;
-template class Cache<CacheTags<IIC,LZSSCompression>, BlockingBuffer, UniCoherence>;
-template class Cache<CacheTags<IIC,LZSSCompression>, MissQueue, SimpleCoherence>;
-template class Cache<CacheTags<IIC,LZSSCompression>, MissQueue, UniCoherence>;
-#endif
+template class Cache<CacheTags<IIC>, SimpleCoherence>;
+template class Cache<CacheTags<IIC>, UniCoherence>;
#endif
#if defined(USE_CACHE_LRU)
-template class Cache<CacheTags<LRU,NullCompression>, BlockingBuffer, SimpleCoherence>;
-template class Cache<CacheTags<LRU,NullCompression>, BlockingBuffer, UniCoherence>;
-template class Cache<CacheTags<LRU,NullCompression>, MissQueue, SimpleCoherence>;
-template class Cache<CacheTags<LRU,NullCompression>, MissQueue, UniCoherence>;
-#if defined(USE_LZSS_COMPRESSION)
-template class Cache<CacheTags<LRU,LZSSCompression>, BlockingBuffer, SimpleCoherence>;
-template class Cache<CacheTags<LRU,LZSSCompression>, BlockingBuffer, UniCoherence>;
-template class Cache<CacheTags<LRU,LZSSCompression>, MissQueue, SimpleCoherence>;
-template class Cache<CacheTags<LRU,LZSSCompression>, MissQueue, UniCoherence>;
-#endif
+template class Cache<CacheTags<LRU>, SimpleCoherence>;
+template class Cache<CacheTags<LRU>, UniCoherence>;
#endif
#if defined(USE_CACHE_SPLIT)
-template class Cache<CacheTags<Split,NullCompression>, BlockingBuffer, SimpleCoherence>;
-template class Cache<CacheTags<Split,NullCompression>, BlockingBuffer, UniCoherence>;
-template class Cache<CacheTags<Split,NullCompression>, MissQueue, SimpleCoherence>;
-template class Cache<CacheTags<Split,NullCompression>, MissQueue, UniCoherence>;
-#if defined(USE_LZSS_COMPRESSION)
-template class Cache<CacheTags<Split,LZSSCompression>, BlockingBuffer, SimpleCoherence>;
-template class Cache<CacheTags<Split,LZSSCompression>, BlockingBuffer, UniCoherence>;
-template class Cache<CacheTags<Split,LZSSCompression>, MissQueue, SimpleCoherence>;
-template class Cache<CacheTags<Split,LZSSCompression>, MissQueue, UniCoherence>;
-#endif
+template class Cache<CacheTags<Split>, SimpleCoherence>;
+template class Cache<CacheTags<Split>, UniCoherence>;
#endif
#if defined(USE_CACHE_SPLIT_LIFO)
-template class Cache<CacheTags<SplitLIFO,NullCompression>, BlockingBuffer, SimpleCoherence>;
-template class Cache<CacheTags<SplitLIFO,NullCompression>, BlockingBuffer, UniCoherence>;
-template class Cache<CacheTags<SplitLIFO,NullCompression>, MissQueue, SimpleCoherence>;
-template class Cache<CacheTags<SplitLIFO,NullCompression>, MissQueue, UniCoherence>;
-#if defined(USE_LZSS_COMPRESSION)
-template class Cache<CacheTags<SplitLIFO,LZSSCompression>, BlockingBuffer, SimpleCoherence>;
-template class Cache<CacheTags<SplitLIFO,LZSSCompression>, BlockingBuffer, UniCoherence>;
-template class Cache<CacheTags<SplitLIFO,LZSSCompression>, MissQueue, SimpleCoherence>;
-template class Cache<CacheTags<SplitLIFO,LZSSCompression>, MissQueue, UniCoherence>;
-#endif
+template class Cache<CacheTags<SplitLIFO>, SimpleCoherence>;
+template class Cache<CacheTags<SplitLIFO>, UniCoherence>;
#endif
#endif //DOXYGEN_SHOULD_SKIP_THIS
diff --git a/src/mem/cache/cache.hh b/src/mem/cache/cache.hh
index 1f3b087bb..29502042c 100644
--- a/src/mem/cache/cache.hh
+++ b/src/mem/cache/cache.hh
@@ -42,6 +42,7 @@
#include "cpu/smt.hh" // SMT_MAX_THREADS
#include "mem/cache/base_cache.hh"
+#include "mem/cache/miss/miss_buffer.hh"
#include "mem/cache/prefetch/prefetcher.hh"
//Forward decleration
@@ -55,7 +56,7 @@ class MSHR;
* @sa MissQueue. Coherence handles all coherence policy details @sa
* UniCoherence, SimpleMultiCoherence.
*/
-template <class TagStore, class Buffering, class Coherence>
+template <class TagStore, class Coherence>
class Cache : public BaseCache
{
public:
@@ -68,12 +69,12 @@ class Cache : public BaseCache
/** Tag and data Storage */
TagStore *tags;
/** Miss and Writeback handler */
- Buffering *missQueue;
+ MissBuffer *missQueue;
/** Coherence protocol. */
Coherence *coherence;
/** Prefetcher */
- Prefetcher<TagStore, Buffering> *prefetcher;
+ Prefetcher<TagStore> *prefetcher;
/**
* The clock ratio of the outgoing bus.
@@ -105,16 +106,16 @@ class Cache : public BaseCache
{
public:
TagStore *tags;
- Buffering *missQueue;
+ MissBuffer *missQueue;
Coherence *coherence;
BaseCache::Params baseParams;
- Prefetcher<TagStore, Buffering> *prefetcher;
+ Prefetcher<TagStore> *prefetcher;
bool prefetchAccess;
int hitLatency;
- Params(TagStore *_tags, Buffering *mq, Coherence *coh,
+ Params(TagStore *_tags, MissBuffer *mq, Coherence *coh,
BaseCache::Params params,
- Prefetcher<TagStore, Buffering> *_prefetcher,
+ Prefetcher<TagStore> *_prefetcher,
bool prefetch_access, int hit_latency)
: tags(_tags), missQueue(mq), coherence(coh),
baseParams(params),
diff --git a/src/mem/cache/cache_builder.cc b/src/mem/cache/cache_builder.cc
index 03646ec2a..4b1b19718 100644
--- a/src/mem/cache/cache_builder.cc
+++ b/src/mem/cache/cache_builder.cc
@@ -37,7 +37,6 @@
// Must be included first to determine which caches we want
#include "mem/config/cache.hh"
-#include "mem/config/compression.hh"
#include "mem/config/prefetch.hh"
#include "mem/cache/base_cache.hh"
@@ -69,9 +68,7 @@
// Compression Templates
#include "base/compression/null_compression.hh"
-#if defined(USE_LZSS_COMPRESSION)
#include "base/compression/lzss_compression.hh"
-#endif
// CacheTags Templates
#include "mem/cache/tags/cache_tags.hh"
@@ -211,156 +208,127 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(BaseCache)
END_INIT_SIM_OBJECT_PARAMS(BaseCache)
-#define BUILD_CACHE(t, comp, b, c) do { \
- Prefetcher<CacheTags<t, comp>, b> *pf; \
+#define BUILD_CACHE(t, c) do { \
+ Prefetcher<CacheTags<t> > *pf; \
if (pf_policy == "tagged") { \
- BUILD_TAGGED_PREFETCHER(t, comp, b); \
+ BUILD_TAGGED_PREFETCHER(t); \
} \
else if (pf_policy == "stride") { \
- BUILD_STRIDED_PREFETCHER(t, comp, b); \
+ BUILD_STRIDED_PREFETCHER(t); \
} \
else if (pf_policy == "ghb") { \
- BUILD_GHB_PREFETCHER(t, comp, b); \
+ BUILD_GHB_PREFETCHER(t); \
} \
else { \
- BUILD_NULL_PREFETCHER(t, comp, b); \
+ BUILD_NULL_PREFETCHER(t); \
} \
- Cache<CacheTags<t, comp>, b, c>::Params params(tagStore, mq, coh, \
+ Cache<CacheTags<t>, c>::Params params(tagStore, mq, coh, \
base_params, \
- /*in_bus, out_bus,*/ pf, \
+ pf, \
prefetch_access, hit_latency); \
- Cache<CacheTags<t, comp>, b, c> *retval = \
- new Cache<CacheTags<t, comp>, b, c>(getInstanceName(), /*hier,*/ \
- params); \
-/* if (in_bus == NULL) { \
- retval->setSlaveInterface(new MemoryInterface<Cache<CacheTags<t, comp>, b, c> >(getInstanceName(), hier, retval, mem_trace)); \
- } else { \
- retval->setSlaveInterface(new SlaveInterface<Cache<CacheTags<t, comp>, b, c>, Bus>(getInstanceName(), hier, retval, in_bus, mem_trace)); \
- } \
- retval->setMasterInterface(new MasterInterface<Cache<CacheTags<t, comp>, b, c>, Bus>(getInstanceName(), hier, retval, out_bus)); \
- out_bus->rangeChange(); \
- return retval; \
-*/return retval; \
+ Cache<CacheTags<t>, c> *retval = \
+ new Cache<CacheTags<t>, c>(getInstanceName(), params); \
+return retval; \
} while (0)
#define BUILD_CACHE_PANIC(x) do { \
panic("%s not compiled into M5", x); \
} while (0)
-#if defined(USE_LZSS_COMPRESSION)
-#define BUILD_COMPRESSED_CACHE(TAGS, tags, b, c) do { \
- if (compressed_bus || store_compressed){ \
- CacheTags<TAGS, LZSSCompression> *tagStore = \
- new CacheTags<TAGS, LZSSCompression>(tags, \
- compression_latency, \
- true, store_compressed, \
- adaptive_compression, \
- prefetch_miss); \
- BUILD_CACHE(TAGS, LZSSCompression, b, c); \
- } else { \
- CacheTags<TAGS, NullCompression> *tagStore = \
- new CacheTags<TAGS, NullCompression>(tags, \
- compression_latency, \
- true, store_compressed, \
- adaptive_compression, \
- prefetch_miss); \
- BUILD_CACHE(TAGS, NullCompression, b, c); \
- } \
- } while (0)
-#else
-#define BUILD_COMPRESSED_CACHE(TAGS, tags, b, c) do { \
- if (compressed_bus || store_compressed){ \
- BUILD_CACHE_PANIC("compressed caches"); \
+#define BUILD_COMPRESSED_CACHE(TAGS, tags, c) \
+ do { \
+ CompressionAlgorithm *compAlg; \
+ if (compressed_bus || store_compressed) { \
+ compAlg = new LZSSCompression(); \
} else { \
- CacheTags<TAGS, NullCompression> *tagStore = \
- new CacheTags<TAGS, NullCompression>(tags, \
- compression_latency, \
- true, store_compressed, \
- adaptive_compression \
- prefetch_miss); \
- BUILD_CACHE(TAGS, NullCompression, b, c); \
+ compAlg = new NullCompression(); \
} \
+ CacheTags<TAGS> *tagStore = \
+ new CacheTags<TAGS>(tags, compression_latency, true, \
+ store_compressed, adaptive_compression, \
+ compressed_bus, \
+ compAlg, prefetch_miss); \
+ BUILD_CACHE(TAGS, c); \
} while (0)
-#endif
#if defined(USE_CACHE_FALRU)
-#define BUILD_FALRU_CACHE(b,c) do { \
+#define BUILD_FALRU_CACHE(c) do { \
FALRU *tags = new FALRU(block_size, size, latency); \
- BUILD_COMPRESSED_CACHE(FALRU, tags, b, c); \
+ BUILD_COMPRESSED_CACHE(FALRU, tags, c); \
} while (0)
#else
-#define BUILD_FALRU_CACHE(b, c) BUILD_CACHE_PANIC("falru cache")
+#define BUILD_FALRU_CACHE(c) BUILD_CACHE_PANIC("falru cache")
#endif
#if defined(USE_CACHE_LRU)
-#define BUILD_LRU_CACHE(b, c) do { \
+#define BUILD_LRU_CACHE(c) do { \
LRU *tags = new LRU(numSets, block_size, assoc, latency); \
- BUILD_COMPRESSED_CACHE(LRU, tags, b, c); \
+ BUILD_COMPRESSED_CACHE(LRU, tags, c); \
} while (0)
#else
-#define BUILD_LRU_CACHE(b, c) BUILD_CACHE_PANIC("lru cache")
+#define BUILD_LRU_CACHE(c) BUILD_CACHE_PANIC("lru cache")
#endif
#if defined(USE_CACHE_SPLIT)
-#define BUILD_SPLIT_CACHE(b, c) do { \
+#define BUILD_SPLIT_CACHE(c) do { \
Split *tags = new Split(numSets, block_size, assoc, split_size, lifo, \
two_queue, latency); \
- BUILD_COMPRESSED_CACHE(Split, tags, b, c); \
+ BUILD_COMPRESSED_CACHE(Split, tags, c); \
} while (0)
#else
-#define BUILD_SPLIT_CACHE(b, c) BUILD_CACHE_PANIC("split cache")
+#define BUILD_SPLIT_CACHE(c) BUILD_CACHE_PANIC("split cache")
#endif
#if defined(USE_CACHE_SPLIT_LIFO)
-#define BUILD_SPLIT_LIFO_CACHE(b, c) do { \
+#define BUILD_SPLIT_LIFO_CACHE(c) do { \
SplitLIFO *tags = new SplitLIFO(block_size, size, assoc, \
latency, two_queue, -1); \
- BUILD_COMPRESSED_CACHE(SplitLIFO, tags, b, c); \
+ BUILD_COMPRESSED_CACHE(SplitLIFO, tags, c); \
} while (0)
#else
-#define BUILD_SPLIT_LIFO_CACHE(b, c) BUILD_CACHE_PANIC("lifo cache")
+#define BUILD_SPLIT_LIFO_CACHE(c) BUILD_CACHE_PANIC("lifo cache")
#endif
#if defined(USE_CACHE_IIC)
-#define BUILD_IIC_CACHE(b ,c) do { \
+#define BUILD_IIC_CACHE(c) do { \
IIC *tags = new IIC(iic_params); \
- BUILD_COMPRESSED_CACHE(IIC, tags, b, c); \
+ BUILD_COMPRESSED_CACHE(IIC, tags, c); \
} while (0)
#else
-#define BUILD_IIC_CACHE(b, c) BUILD_CACHE_PANIC("iic")
+#define BUILD_IIC_CACHE(c) BUILD_CACHE_PANIC("iic")
#endif
-#define BUILD_CACHES(b, c) do { \
+#define BUILD_CACHES(c) do { \
if (repl == NULL) { \
if (numSets == 1) { \
- BUILD_FALRU_CACHE(b, c); \
+ BUILD_FALRU_CACHE(c); \
} else { \
if (split == true) { \
- BUILD_SPLIT_CACHE(b, c); \
+ BUILD_SPLIT_CACHE(c); \
} else if (lifo == true) { \
- BUILD_SPLIT_LIFO_CACHE(b, c); \
+ BUILD_SPLIT_LIFO_CACHE(c); \
} else { \
- BUILD_LRU_CACHE(b, c); \
+ BUILD_LRU_CACHE(c); \
} \
} \
} else { \
- BUILD_IIC_CACHE(b, c); \
+ BUILD_IIC_CACHE(c); \
} \
} while (0)
#define BUILD_COHERENCE(b) do { \
if (protocol == NULL) { \
UniCoherence *coh = new UniCoherence(); \
- BUILD_CACHES(b, UniCoherence); \
+ BUILD_CACHES(UniCoherence); \
} else { \
SimpleCoherence *coh = new SimpleCoherence(protocol); \
- BUILD_CACHES(b, SimpleCoherence); \
+ BUILD_CACHES(SimpleCoherence); \
} \
} while (0)
#if defined(USE_TAGGED)
-#define BUILD_TAGGED_PREFETCHER(t, comp, b) pf = new \
- TaggedPrefetcher<CacheTags<t, comp>, b>(prefetcher_size, \
+#define BUILD_TAGGED_PREFETCHER(t) pf = new \
+ TaggedPrefetcher<CacheTags<t> >(prefetcher_size, \
!prefetch_past_page, \
prefetch_serial_squash, \
prefetch_cache_check_push, \
@@ -368,12 +336,12 @@ END_INIT_SIM_OBJECT_PARAMS(BaseCache)
prefetch_latency, \
prefetch_degree)
#else
-#define BUILD_TAGGED_PREFETCHER(t, comp, b) BUILD_CACHE_PANIC("Tagged Prefetcher")
+#define BUILD_TAGGED_PREFETCHER(t) BUILD_CACHE_PANIC("Tagged Prefetcher")
#endif
#if defined(USE_STRIDED)
-#define BUILD_STRIDED_PREFETCHER(t, comp, b) pf = new \
- StridePrefetcher<CacheTags<t, comp>, b>(prefetcher_size, \
+#define BUILD_STRIDED_PREFETCHER(t) pf = new \
+ StridePrefetcher<CacheTags<t> >(prefetcher_size, \
!prefetch_past_page, \
prefetch_serial_squash, \
prefetch_cache_check_push, \
@@ -382,12 +350,12 @@ END_INIT_SIM_OBJECT_PARAMS(BaseCache)
prefetch_degree, \
prefetch_use_cpu_id)
#else
-#define BUILD_STRIDED_PREFETCHER(t, comp, b) BUILD_CACHE_PANIC("Stride Prefetcher")
+#define BUILD_STRIDED_PREFETCHER(t) BUILD_CACHE_PANIC("Stride Prefetcher")
#endif
#if defined(USE_GHB)
-#define BUILD_GHB_PREFETCHER(t, comp, b) pf = new \
- GHBPrefetcher<CacheTags<t, comp>, b>(prefetcher_size, \
+#define BUILD_GHB_PREFETCHER(t) pf = new \
+ GHBPrefetcher<CacheTags<t> >(prefetcher_size, \
!prefetch_past_page, \
prefetch_serial_squash, \
prefetch_cache_check_push, \
@@ -396,12 +364,12 @@ END_INIT_SIM_OBJECT_PARAMS(BaseCache)
prefetch_degree, \
prefetch_use_cpu_id)
#else
-#define BUILD_GHB_PREFETCHER(t, comp, b) BUILD_CACHE_PANIC("GHB Prefetcher")
+#define BUILD_GHB_PREFETCHER(t) BUILD_CACHE_PANIC("GHB Prefetcher")
#endif
#if defined(USE_TAGGED)
-#define BUILD_NULL_PREFETCHER(t, comp, b) pf = new \
- TaggedPrefetcher<CacheTags<t, comp>, b>(prefetcher_size, \
+#define BUILD_NULL_PREFETCHER(t) pf = new \
+ TaggedPrefetcher<CacheTags<t> >(prefetcher_size, \
!prefetch_past_page, \
prefetch_serial_squash, \
prefetch_cache_check_push, \
@@ -409,7 +377,7 @@ END_INIT_SIM_OBJECT_PARAMS(BaseCache)
prefetch_latency, \
prefetch_degree)
#else
-#define BUILD_NULL_PREFETCHER(t, comp, b) BUILD_CACHE_PANIC("NULL Prefetcher (uses Tagged)")
+#define BUILD_NULL_PREFETCHER(t) BUILD_CACHE_PANIC("NULL Prefetcher (uses Tagged)")
#endif
CREATE_SIM_OBJECT(BaseCache)
diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh
index 3a681bc52..6742d5892 100644
--- a/src/mem/cache/cache_impl.hh
+++ b/src/mem/cache/cache_impl.hh
@@ -55,9 +55,9 @@
bool SIGNAL_NACK_HACK;
-template<class TagStore, class Buffering, class Coherence>
+template<class TagStore, class Coherence>
bool
-Cache<TagStore,Buffering,Coherence>::
+Cache<TagStore,Coherence>::
doTimingAccess(PacketPtr pkt, CachePort *cachePort, bool isCpuSide)
{
if (isCpuSide)
@@ -81,9 +81,9 @@ doTimingAccess(PacketPtr pkt, CachePort *cachePort, bool isCpuSide)
return true;
}
-template<class TagStore, class Buffering, class Coherence>
+template<class TagStore, class Coherence>
Tick
-Cache<TagStore,Buffering,Coherence>::
+Cache<TagStore,Coherence>::
doAtomicAccess(PacketPtr pkt, bool isCpuSide)
{
if (isCpuSide)
@@ -103,9 +103,9 @@ doAtomicAccess(PacketPtr pkt, bool isCpuSide)
return hitLatency;
}
-template<class TagStore, class Buffering, class Coherence>
+template<class TagStore, class Coherence>
void
-Cache<TagStore,Buffering,Coherence>::
+Cache<TagStore,Coherence>::
doFunctionalAccess(PacketPtr pkt, bool isCpuSide)
{
if (isCpuSide)
@@ -123,19 +123,19 @@ doFunctionalAccess(PacketPtr pkt, bool isCpuSide)
}
}
-template<class TagStore, class Buffering, class Coherence>
+template<class TagStore, class Coherence>
void
-Cache<TagStore,Buffering,Coherence>::
+Cache<TagStore,Coherence>::
recvStatusChange(Port::Status status, bool isCpuSide)
{
}
-template<class TagStore, class Buffering, class Coherence>
-Cache<TagStore,Buffering,Coherence>::
+template<class TagStore, class Coherence>
+Cache<TagStore,Coherence>::
Cache(const std::string &_name,
- Cache<TagStore,Buffering,Coherence>::Params &params)
+ Cache<TagStore,Coherence>::Params &params)
: BaseCache(_name, params.baseParams),
prefetchAccess(params.prefetchAccess),
tags(params.tags), missQueue(params.missQueue),
@@ -154,9 +154,9 @@ Cache(const std::string &_name,
invalidatePkt = new Packet(invalidateReq, Packet::InvalidateReq, 0);
}
-template<class TagStore, class Buffering, class Coherence>
+template<class TagStore, class Coherence>
void
-Cache<TagStore,Buffering,Coherence>::regStats()
+Cache<TagStore,Coherence>::regStats()
{
BaseCache::regStats();
tags->regStats(name());
@@ -165,9 +165,9 @@ Cache<TagStore,Buffering,Coherence>::regStats()
prefetcher->regStats(name());
}
-template<class TagStore, class Buffering, class Coherence>
+template<class TagStore, class Coherence>
bool
-Cache<TagStore,Buffering,Coherence>::access(PacketPtr &pkt)
+Cache<TagStore,Coherence>::access(PacketPtr &pkt)
{
//@todo Add back in MemDebug Calls
// MemDebug::cacheAccess(pkt);
@@ -253,9 +253,9 @@ Cache<TagStore,Buffering,Coherence>::access(PacketPtr &pkt)
}
-template<class TagStore, class Buffering, class Coherence>
+template<class TagStore, class Coherence>
PacketPtr
-Cache<TagStore,Buffering,Coherence>::getPacket()
+Cache<TagStore,Coherence>::getPacket()
{
assert(missQueue->havePending());
PacketPtr pkt = missQueue->getPacket();
@@ -276,9 +276,9 @@ Cache<TagStore,Buffering,Coherence>::getPacket()
return pkt;
}
-template<class TagStore, class Buffering, class Coherence>
+template<class TagStore, class Coherence>
void
-Cache<TagStore,Buffering,Coherence>::sendResult(PacketPtr &pkt, MSHR* mshr,
+Cache<TagStore,Coherence>::sendResult(PacketPtr &pkt, MSHR* mshr,
bool success)
{
if (success && !(SIGNAL_NACK_HACK)) {
@@ -319,9 +319,9 @@ Cache<TagStore,Buffering,Coherence>::sendResult(PacketPtr &pkt, MSHR* mshr,
}
}
-template<class TagStore, class Buffering, class Coherence>
+template<class TagStore, class Coherence>
void
-Cache<TagStore,Buffering,Coherence>::handleResponse(PacketPtr &pkt)
+Cache<TagStore,Coherence>::handleResponse(PacketPtr &pkt)
{
BlkType *blk = NULL;
if (pkt->senderState) {
@@ -363,16 +363,16 @@ Cache<TagStore,Buffering,Coherence>::handleResponse(PacketPtr &pkt)
}
}
-template<class TagStore, class Buffering, class Coherence>
+template<class TagStore, class Coherence>
PacketPtr
-Cache<TagStore,Buffering,Coherence>::getCoherencePacket()
+Cache<TagStore,Coherence>::getCoherencePacket()
{
return coherence->getPacket();
}
-template<class TagStore, class Buffering, class Coherence>
+template<class TagStore, class Coherence>
void
-Cache<TagStore,Buffering,Coherence>::sendCoherenceResult(PacketPtr &pkt,
+Cache<TagStore,Coherence>::sendCoherenceResult(PacketPtr &pkt,
MSHR *cshr,
bool success)
{
@@ -380,9 +380,9 @@ Cache<TagStore,Buffering,Coherence>::sendCoherenceResult(PacketPtr &pkt,
}
-template<class TagStore, class Buffering, class Coherence>
+template<class TagStore, class Coherence>
void
-Cache<TagStore,Buffering,Coherence>::snoop(PacketPtr &pkt)
+Cache<TagStore,Coherence>::snoop(PacketPtr &pkt)
{
if (pkt->req->isUncacheable()) {
//Can't get a hit on an uncacheable address
@@ -514,9 +514,9 @@ Cache<TagStore,Buffering,Coherence>::snoop(PacketPtr &pkt)
tags->handleSnoop(blk, new_state);
}
-template<class TagStore, class Buffering, class Coherence>
+template<class TagStore, class Coherence>
void
-Cache<TagStore,Buffering,Coherence>::snoopResponse(PacketPtr &pkt)
+Cache<TagStore,Coherence>::snoopResponse(PacketPtr &pkt)
{
//Need to handle the response, if NACKED
if (pkt->flags & NACKED_LINE) {
@@ -533,9 +533,9 @@ Cache<TagStore,Buffering,Coherence>::snoopResponse(PacketPtr &pkt)
}
}
-template<class TagStore, class Buffering, class Coherence>
+template<class TagStore, class Coherence>
void
-Cache<TagStore,Buffering,Coherence>::invalidateBlk(Addr addr)
+Cache<TagStore,Coherence>::invalidateBlk(Addr addr)
{
tags->invalidateBlk(addr);
}
@@ -544,9 +544,9 @@ Cache<TagStore,Buffering,Coherence>::invalidateBlk(Addr addr)
/**
* @todo Fix to not assume write allocate
*/
-template<class TagStore, class Buffering, class Coherence>
+template<class TagStore, class Coherence>
Tick
-Cache<TagStore,Buffering,Coherence>::probe(PacketPtr &pkt, bool update,
+Cache<TagStore,Coherence>::probe(PacketPtr &pkt, bool update,
CachePort* otherSidePort)
{
// MemDebug::cacheProbe(pkt);
@@ -694,9 +694,9 @@ return 0;
return 0;
}
-template<class TagStore, class Buffering, class Coherence>
+template<class TagStore, class Coherence>
Tick
-Cache<TagStore,Buffering,Coherence>::snoopProbe(PacketPtr &pkt)
+Cache<TagStore,Coherence>::snoopProbe(PacketPtr &pkt)
{
//Send a atomic (false) invalidate up if the protocol calls for it
if (coherence->propogateInvalidate(pkt, false)) {
diff --git a/src/mem/cache/miss/blocking_buffer.cc b/src/mem/cache/miss/blocking_buffer.cc
index bf741e547..4a431d82d 100644
--- a/src/mem/cache/miss/blocking_buffer.cc
+++ b/src/mem/cache/miss/blocking_buffer.cc
@@ -33,11 +33,9 @@
* Definitions of a simple buffer for a blocking cache.
*/
-#include "cpu/smt.hh" //for maxThreadsPerCPU
#include "mem/cache/base_cache.hh"
#include "mem/cache/miss/blocking_buffer.hh"
#include "mem/cache/prefetch/base_prefetcher.hh"
-#include "sim/eventq.hh" // for Event declaration.
#include "mem/request.hh"
/**
@@ -46,28 +44,11 @@
void
BlockingBuffer::regStats(const std::string &name)
{
- using namespace Stats;
- writebacks
- .init(maxThreadsPerCPU)
- .name(name + ".writebacks")
- .desc("number of writebacks")
- .flags(total)
- ;
+ MissBuffer::regStats(name);
}
-void
-BlockingBuffer::setCache(BaseCache *_cache)
-{
- cache = _cache;
- blkSize = cache->getBlockSize();
-}
void
-BlockingBuffer::setPrefetcher(BasePrefetcher *_prefetcher)
-{
- prefetcher = _prefetcher;
-}
-void
BlockingBuffer::handleMiss(PacketPtr &pkt, int blk_size, Tick time)
{
Addr blk_addr = pkt->getAddr() & ~(Addr)(blk_size - 1);
@@ -241,3 +222,23 @@ BlockingBuffer::doWriteback(PacketPtr &pkt)
cache->setBlocked(Blocked_NoWBBuffers);
cache->setMasterRequest(Request_WB, curTick);
}
+
+
+MSHR *
+BlockingBuffer::findMSHR(Addr addr)
+{
+ if (miss.addr == addr && miss.pkt)
+ return &miss;
+ return NULL;
+}
+
+
+bool
+BlockingBuffer::findWrites(Addr addr, std::vector<MSHR*>& writes)
+{
+ if (wb.addr == addr && wb.pkt) {
+ writes.push_back(&wb);
+ return true;
+ }
+ return false;
+}
diff --git a/src/mem/cache/miss/blocking_buffer.hh b/src/mem/cache/miss/blocking_buffer.hh
index 934a843a6..205068a8c 100644
--- a/src/mem/cache/miss/blocking_buffer.hh
+++ b/src/mem/cache/miss/blocking_buffer.hh
@@ -38,16 +38,14 @@
#include <vector>
+#include "base/misc.hh" // for fatal()
+#include "mem/cache/miss/miss_buffer.hh"
#include "mem/cache/miss/mshr.hh"
-#include "base/statistics.hh"
-
-class BaseCache;
-class BasePrefetcher;
/**
* Miss and writeback storage for a blocking cache.
*/
-class BlockingBuffer
+class BlockingBuffer : public MissBuffer
{
protected:
/** Miss storage. */
@@ -55,38 +53,13 @@ protected:
/** WB storage. */
MSHR wb;
- //Params
-
- /** Allocate on write misses. */
- const bool writeAllocate;
-
- /** Pointer to the parent cache. */
- BaseCache* cache;
-
- BasePrefetcher* prefetcher;
-
- /** Block size of the parent cache. */
- int blkSize;
-
- // Statistics
- /**
- * @addtogroup CacheStatistics
- * @{
- */
- /** Number of blocks written back per thread. */
- Stats::Vector<> writebacks;
-
- /**
- * @}
- */
-
public:
/**
* Builds and initializes this buffer.
* @param write_allocate If true, treat write misses the same as reads.
*/
BlockingBuffer(bool write_allocate)
- : writeAllocate(write_allocate)
+ : MissBuffer(write_allocate)
{
}
@@ -97,14 +70,6 @@ public:
void regStats(const std::string &name);
/**
- * Called by the parent cache to set the back pointer.
- * @param _cache A pointer to the parent cache.
- */
- void setCache(BaseCache *_cache);
-
- void setPrefetcher(BasePrefetcher *_prefetcher);
-
- /**
* Handle a cache miss properly. Requests the bus and marks the cache as
* blocked.
* @param pkt The request that missed in the cache.
@@ -183,12 +148,7 @@ public:
* @param asid The address space id.
* @return A pointer to miss if it matches.
*/
- MSHR* findMSHR(Addr addr)
- {
- if (miss.addr == addr && miss.pkt)
- return &miss;
- return NULL;
- }
+ MSHR* findMSHR(Addr addr);
/**
* Searches for the supplied address in the write buffer.
@@ -197,16 +157,7 @@ public:
* @param writes List of pointers to the matching writes.
* @return True if there is a matching write.
*/
- bool findWrites(Addr addr, std::vector<MSHR*>& writes)
- {
- if (wb.addr == addr && wb.pkt) {
- writes.push_back(&wb);
- return true;
- }
- return false;
- }
-
-
+ bool findWrites(Addr addr, std::vector<MSHR*>& writes);
/**
* Perform a writeback of dirty data to the given address.
diff --git a/src/mem/cache/miss/miss_buffer.cc b/src/mem/cache/miss/miss_buffer.cc
new file mode 100644
index 000000000..4d9cd0958
--- /dev/null
+++ b/src/mem/cache/miss/miss_buffer.cc
@@ -0,0 +1,62 @@
+/*
+ * Copyright (c) 2003-2006 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Erik Hallnor
+ */
+
+#include "cpu/smt.hh" //for maxThreadsPerCPU
+#include "mem/cache/base_cache.hh"
+#include "mem/cache/miss/miss_buffer.hh"
+#include "mem/cache/prefetch/base_prefetcher.hh"
+
+/**
+ * @todo Move writebacks into shared BaseBuffer class.
+ */
+void
+MissBuffer::regStats(const std::string &name)
+{
+ using namespace Stats;
+ writebacks
+ .init(maxThreadsPerCPU)
+ .name(name + ".writebacks")
+ .desc("number of writebacks")
+ .flags(total)
+ ;
+}
+
+void
+MissBuffer::setCache(BaseCache *_cache)
+{
+ cache = _cache;
+ blkSize = cache->getBlockSize();
+}
+
+void
+MissBuffer::setPrefetcher(BasePrefetcher *_prefetcher)
+{
+ prefetcher = _prefetcher;
+}
diff --git a/src/mem/cache/miss/miss_buffer.hh b/src/mem/cache/miss/miss_buffer.hh
new file mode 100644
index 000000000..3e3080578
--- /dev/null
+++ b/src/mem/cache/miss/miss_buffer.hh
@@ -0,0 +1,223 @@
+/*
+ * Copyright (c) 2003-2006 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Steve Reinhardt
+ */
+
+/**
+ * @file
+ * MissBuffer declaration.
+ */
+
+#ifndef __MISS_BUFFER_HH__
+#define __MISS_BUFFER_HH__
+
+class BaseCache;
+class BasePrefetcher;
+class MSHR;
+
+/**
+ * Abstract base class for cache miss buffering.
+ */
+class MissBuffer
+{
+ protected:
+ /** True if the cache should allocate on a write miss. */
+ const bool writeAllocate;
+
+ /** Pointer to the parent cache. */
+ BaseCache *cache;
+
+ /** The Prefetcher */
+ BasePrefetcher *prefetcher;
+
+ /** Block size of the parent cache. */
+ int blkSize;
+
+ // Statistics
+ /**
+ * @addtogroup CacheStatistics
+ * @{
+ */
+ /** Number of blocks written back per thread. */
+ Stats::Vector<> writebacks;
+
+ /**
+ * @}
+ */
+
+ public:
+ MissBuffer(bool write_allocate)
+ : writeAllocate(write_allocate)
+ {
+ }
+
+ virtual ~MissBuffer() {}
+
+ /**
+ * Called by the parent cache to set the back pointer.
+ * @param _cache A pointer to the parent cache.
+ */
+ void setCache(BaseCache *_cache);
+
+ void setPrefetcher(BasePrefetcher *_prefetcher);
+
+ /**
+ * Register statistics for this object.
+ * @param name The name of the parent cache.
+ */
+ virtual void regStats(const std::string &name);
+
+ /**
+ * Handle a cache miss properly. Either allocate an MSHR for the request,
+ * or forward it through the write buffer.
+ * @param pkt The request that missed in the cache.
+ * @param blk_size The block size of the cache.
+ * @param time The time the miss is detected.
+ */
+ virtual void handleMiss(PacketPtr &pkt, int blk_size, Tick time) = 0;
+
+ /**
+ * Fetch the block for the given address and buffer the given target.
+ * @param addr The address to fetch.
+ * @param asid The address space of the address.
+ * @param blk_size The block size of the cache.
+ * @param time The time the miss is detected.
+ * @param target The target for the fetch.
+ */
+ virtual MSHR *fetchBlock(Addr addr, int blk_size, Tick time,
+ PacketPtr &target) = 0;
+
+ /**
+ * Selects a outstanding request to service.
+ * @return The request to service, NULL if none found.
+ */
+ virtual PacketPtr getPacket() = 0;
+
+ /**
+ * Set the command to the given bus command.
+ * @param pkt The request to update.
+ * @param cmd The bus command to use.
+ */
+ virtual void setBusCmd(PacketPtr &pkt, Packet::Command cmd) = 0;
+
+ /**
+ * Restore the original command in case of a bus transmission error.
+ * @param pkt The request to reset.
+ */
+ virtual void restoreOrigCmd(PacketPtr &pkt) = 0;
+
+ /**
+ * Marks a request as in service (sent on the bus). This can have side
+ * effect since storage for no response commands is deallocated once they
+ * are successfully sent.
+ * @param pkt The request that was sent on the bus.
+ */
+ virtual void markInService(PacketPtr &pkt, MSHR* mshr) = 0;
+
+ /**
+ * Collect statistics and free resources of a satisfied request.
+ * @param pkt The request that has been satisfied.
+ * @param time The time when the request is satisfied.
+ */
+ virtual void handleResponse(PacketPtr &pkt, Tick time) = 0;
+
+ /**
+ * Removes all outstanding requests for a given thread number. If a request
+ * has been sent to the bus, this function removes all of its targets.
+ * @param threadNum The thread number of the requests to squash.
+ */
+ virtual void squash(int threadNum) = 0;
+
+ /**
+ * Return the current number of outstanding misses.
+ * @return the number of outstanding misses.
+ */
+ virtual int getMisses() = 0;
+
+ /**
+ * Searches for the supplied address in the miss queue.
+ * @param addr The address to look for.
+ * @param asid The address space id.
+ * @return The MSHR that contains the address, NULL if not found.
+ * @warning Currently only searches the miss queue. If non write allocate
+ * might need to search the write buffer for coherence.
+ */
+ virtual MSHR* findMSHR(Addr addr) = 0;
+
+ /**
+ * Searches for the supplied address in the write buffer.
+ * @param addr The address to look for.
+ * @param asid The address space id.
+ * @param writes The list of writes that match the address.
+ * @return True if any writes are found
+ */
+ virtual bool findWrites(Addr addr, std::vector<MSHR*>& writes) = 0;
+
+ /**
+ * Perform a writeback of dirty data to the given address.
+ * @param addr The address to write to.
+ * @param asid The address space id.
+ * @param xc The execution context of the address space.
+ * @param size The number of bytes to write.
+ * @param data The data to write, can be NULL.
+ * @param compressed True if the data is compressed.
+ */
+ virtual void doWriteback(Addr addr, int size, uint8_t *data,
+ bool compressed) = 0;
+
+ /**
+ * Perform the given writeback request.
+ * @param pkt The writeback request.
+ */
+ virtual void doWriteback(PacketPtr &pkt) = 0;
+
+ /**
+ * Returns true if there are outstanding requests.
+ * @return True if there are outstanding requests.
+ */
+ virtual bool havePending() = 0;
+
+ /**
+ * Add a target to the given MSHR. This assumes it is in the miss queue.
+ * @param mshr The mshr to add a target to.
+ * @param pkt The target to add.
+ */
+ virtual void addTarget(MSHR *mshr, PacketPtr &pkt) = 0;
+
+ /**
+ * Allocate a MSHR to hold a list of targets to a block involved in a copy.
+ * If the block is marked done then the MSHR already holds the data to
+ * fill the block. Otherwise the block needs to be fetched.
+ * @param addr The address to buffer.
+ * @param asid The address space ID.
+ * @return A pointer to the allocated MSHR.
+ */
+ virtual MSHR* allocateTargetList(Addr addr) = 0;
+};
+
+#endif //__MISS_BUFFER_HH__
diff --git a/src/mem/cache/miss/miss_queue.cc b/src/mem/cache/miss/miss_queue.cc
index 3c4586272..1d3e22326 100644
--- a/src/mem/cache/miss/miss_queue.cc
+++ b/src/mem/cache/miss/miss_queue.cc
@@ -48,16 +48,25 @@ using namespace std;
*/
MissQueue::MissQueue(int numMSHRs, int numTargets, int write_buffers,
bool write_allocate, bool prefetch_miss)
- : mq(numMSHRs, 4), wb(write_buffers,numMSHRs+1000), numMSHR(numMSHRs),
+ : MissBuffer(write_allocate),
+ mq(numMSHRs, 4), wb(write_buffers,numMSHRs+1000), numMSHR(numMSHRs),
numTarget(numTargets), writeBuffers(write_buffers),
- writeAllocate(write_allocate), order(0), prefetchMiss(prefetch_miss)
+ order(0), prefetchMiss(prefetch_miss)
{
noTargetMSHR = NULL;
}
+
+MissQueue::~MissQueue()
+{
+}
+
+
void
MissQueue::regStats(const string &name)
{
+ MissBuffer::regStats(name);
+
Request temp_req((Addr) NULL, 4, 0);
Packet::Command temp_cmd = Packet::ReadReq;
Packet temp_pkt(&temp_req, temp_cmd, 0); //@todo FIx command strings so this isn't neccessary
@@ -65,13 +74,6 @@ MissQueue::regStats(const string &name)
using namespace Stats;
- writebacks
- .init(maxThreadsPerCPU)
- .name(name + ".writebacks")
- .desc("number of writebacks")
- .flags(total)
- ;
-
// MSHR hit statistics
for (int access_idx = 0; access_idx < NUM_MEM_CMDS; ++access_idx) {
Packet::Command cmd = (Packet::Command)access_idx;
@@ -336,18 +338,6 @@ MissQueue::regStats(const string &name)
}
-void
-MissQueue::setCache(BaseCache *_cache)
-{
- cache = _cache;
- blkSize = cache->getBlockSize();
-}
-
-void
-MissQueue::setPrefetcher(BasePrefetcher *_prefetcher)
-{
- prefetcher = _prefetcher;
-}
MSHR*
MissQueue::allocateMiss(PacketPtr &pkt, int size, Tick time)
@@ -706,13 +696,13 @@ MissQueue::squash(int threadNum)
}
MSHR*
-MissQueue::findMSHR(Addr addr) const
+MissQueue::findMSHR(Addr addr)
{
return mq.findMatch(addr);
}
bool
-MissQueue::findWrites(Addr addr, vector<MSHR*> &writes) const
+MissQueue::findWrites(Addr addr, vector<MSHR*> &writes)
{
return wb.findMatches(addr,writes);
}
diff --git a/src/mem/cache/miss/miss_queue.hh b/src/mem/cache/miss/miss_queue.hh
index b67a896f4..1f9bb1e0c 100644
--- a/src/mem/cache/miss/miss_queue.hh
+++ b/src/mem/cache/miss/miss_queue.hh
@@ -38,19 +38,18 @@
#include <vector>
+#include "mem/cache/miss/miss_buffer.hh"
#include "mem/cache/miss/mshr.hh"
#include "mem/cache/miss/mshr_queue.hh"
#include "base/statistics.hh"
-class BaseCache;
-class BasePrefetcher;
/**
* Manages cache misses and writebacks. Contains MSHRs to store miss data
* and the writebuffer for writes/writebacks.
* @todo need to handle data on writes better (encapsulate).
* @todo need to make replacements/writebacks happen in Cache::access
*/
-class MissQueue
+class MissQueue : public MissBuffer
{
protected:
/** The MSHRs. */
@@ -66,16 +65,6 @@ class MissQueue
const int numTarget;
/** The number of write buffers. */
const int writeBuffers;
- /** True if the cache should allocate on a write miss. */
- const bool writeAllocate;
- /** Pointer to the parent cache. */
- BaseCache* cache;
-
- /** The Prefetcher */
- BasePrefetcher *prefetcher;
-
- /** The block size of the parent cache. */
- int blkSize;
/** Increasing order number assigned to each incoming request. */
uint64_t order;
@@ -87,9 +76,6 @@ class MissQueue
* @addtogroup CacheStatistics
* @{
*/
- /** Number of blocks written back per thread. */
- Stats::Vector<> writebacks;
-
/** Number of misses that hit in the MSHRs per command and thread. */
Stats::Vector<> mshr_hits[NUM_MEM_CMDS];
/** Demand misses that hit in the MSHRs. */
@@ -204,14 +190,6 @@ class MissQueue
void regStats(const std::string &name);
/**
- * Called by the parent cache to set the back pointer.
- * @param _cache A pointer to the parent cache.
- */
- void setCache(BaseCache *_cache);
-
- void setPrefetcher(BasePrefetcher *_prefetcher);
-
- /**
* Handle a cache miss properly. Either allocate an MSHR for the request,
* or forward it through the write buffer.
* @param pkt The request that missed in the cache.
@@ -289,7 +267,7 @@ class MissQueue
* @warning Currently only searches the miss queue. If non write allocate
* might need to search the write buffer for coherence.
*/
- MSHR* findMSHR(Addr addr) const;
+ MSHR* findMSHR(Addr addr);
/**
* Searches for the supplied address in the write buffer.
@@ -298,7 +276,7 @@ class MissQueue
* @param writes The list of writes that match the address.
* @return True if any writes are found
*/
- bool findWrites(Addr addr, std::vector<MSHR*>& writes) const;
+ bool findWrites(Addr addr, std::vector<MSHR*>& writes);
/**
* Perform a writeback of dirty data to the given address.
diff --git a/src/mem/cache/prefetch/ghb_prefetcher.cc b/src/mem/cache/prefetch/ghb_prefetcher.cc
index 247ec6e8b..a6c419113 100644
--- a/src/mem/cache/prefetch/ghb_prefetcher.cc
+++ b/src/mem/cache/prefetch/ghb_prefetcher.cc
@@ -38,17 +38,11 @@
#include "mem/cache/tags/lru.hh"
-#include "base/compression/null_compression.hh"
-
-#include "mem/cache/miss/miss_queue.hh"
-#include "mem/cache/miss/blocking_buffer.hh"
-
#include "mem/cache/prefetch/ghb_prefetcher.hh"
// Template Instantiations
#ifndef DOXYGEN_SHOULD_SKIP_THIS
-template class GHBPrefetcher<CacheTags<LRU,NullCompression>, MissQueue>;
-template class GHBPrefetcher<CacheTags<LRU,NullCompression>, BlockingBuffer>;
+template class GHBPrefetcher<CacheTags<LRU> >;
#endif //DOXYGEN_SHOULD_SKIP_THIS
diff --git a/src/mem/cache/prefetch/ghb_prefetcher.hh b/src/mem/cache/prefetch/ghb_prefetcher.hh
index 14f5747df..c558a3e64 100644
--- a/src/mem/cache/prefetch/ghb_prefetcher.hh
+++ b/src/mem/cache/prefetch/ghb_prefetcher.hh
@@ -43,16 +43,16 @@
/**
* A template-policy based cache. The behavior of the cache can be altered by
* supplying different template policies. TagStore handles all tag and data
- * storage @sa TagStore. Buffering handles all misses and writes/writebacks
+ * storage @sa TagStore. MissBuffer handles all misses and writes/writebacks
* @sa MissQueue. Coherence handles all coherence policy details @sa
* UniCoherence, SimpleMultiCoherence.
*/
-template <class TagStore, class Buffering>
-class GHBPrefetcher : public Prefetcher<TagStore, Buffering>
+template <class TagStore>
+class GHBPrefetcher : public Prefetcher<TagStore>
{
protected:
- Buffering* mq;
+ MissBuffer* mq;
TagStore* tags;
Addr second_last_miss_addr[64/*MAX_CPUS*/];
@@ -67,7 +67,7 @@ class GHBPrefetcher : public Prefetcher<TagStore, Buffering>
GHBPrefetcher(int size, bool pageStop, bool serialSquash,
bool cacheCheckPush, bool onlyData,
Tick latency, int degree, bool useCPUId)
- :Prefetcher<TagStore, Buffering>(size, pageStop, serialSquash,
+ :Prefetcher<TagStore>(size, pageStop, serialSquash,
cacheCheckPush, onlyData),
latency(latency), degree(degree), useCPUId(useCPUId)
{
diff --git a/src/mem/cache/prefetch/stride_prefetcher.cc b/src/mem/cache/prefetch/stride_prefetcher.cc
index 93a096468..2204871cc 100644
--- a/src/mem/cache/prefetch/stride_prefetcher.cc
+++ b/src/mem/cache/prefetch/stride_prefetcher.cc
@@ -38,17 +38,11 @@
#include "mem/cache/tags/lru.hh"
-#include "base/compression/null_compression.hh"
-
-#include "mem/cache/miss/miss_queue.hh"
-#include "mem/cache/miss/blocking_buffer.hh"
-
#include "mem/cache/prefetch/stride_prefetcher.hh"
// Template Instantiations
#ifndef DOXYGEN_SHOULD_SKIP_THIS
-template class StridePrefetcher<CacheTags<LRU,NullCompression>, MissQueue>;
-template class StridePrefetcher<CacheTags<LRU,NullCompression>, BlockingBuffer>;
+template class StridePrefetcher<CacheTags<LRU> >;
#endif //DOXYGEN_SHOULD_SKIP_THIS
diff --git a/src/mem/cache/prefetch/stride_prefetcher.hh b/src/mem/cache/prefetch/stride_prefetcher.hh
index d6fb8ab66..57e430400 100644
--- a/src/mem/cache/prefetch/stride_prefetcher.hh
+++ b/src/mem/cache/prefetch/stride_prefetcher.hh
@@ -43,16 +43,16 @@
/**
* A template-policy based cache. The behavior of the cache can be altered by
* supplying different template policies. TagStore handles all tag and data
- * storage @sa TagStore. Buffering handles all misses and writes/writebacks
+ * storage @sa TagStore. MissBuffer handles all misses and writes/writebacks
* @sa MissQueue. Coherence handles all coherence policy details @sa
* UniCoherence, SimpleMultiCoherence.
*/
-template <class TagStore, class Buffering>
-class StridePrefetcher : public Prefetcher<TagStore, Buffering>
+template <class TagStore>
+class StridePrefetcher : public Prefetcher<TagStore>
{
protected:
- Buffering* mq;
+ MissBuffer* mq;
TagStore* tags;
class strideEntry
@@ -84,7 +84,7 @@ class StridePrefetcher : public Prefetcher<TagStore, Buffering>
StridePrefetcher(int size, bool pageStop, bool serialSquash,
bool cacheCheckPush, bool onlyData,
Tick latency, int degree, bool useCPUId)
- :Prefetcher<TagStore, Buffering>(size, pageStop, serialSquash,
+ :Prefetcher<TagStore>(size, pageStop, serialSquash,
cacheCheckPush, onlyData),
latency(latency), degree(degree), useCPUId(useCPUId)
{
diff --git a/src/mem/cache/prefetch/tagged_prefetcher.hh b/src/mem/cache/prefetch/tagged_prefetcher.hh
index b61e57dcc..dc2aaec50 100644
--- a/src/mem/cache/prefetch/tagged_prefetcher.hh
+++ b/src/mem/cache/prefetch/tagged_prefetcher.hh
@@ -41,16 +41,16 @@
/**
* A template-policy based cache. The behavior of the cache can be altered by
* supplying different template policies. TagStore handles all tag and data
- * storage @sa TagStore. Buffering handles all misses and writes/writebacks
+ * storage @sa TagStore. MissBuffer handles all misses and writes/writebacks
* @sa MissQueue. Coherence handles all coherence policy details @sa
* UniCoherence, SimpleMultiCoherence.
*/
-template <class TagStore, class Buffering>
-class TaggedPrefetcher : public Prefetcher<TagStore, Buffering>
+template <class TagStore>
+class TaggedPrefetcher : public Prefetcher<TagStore>
{
protected:
- Buffering* mq;
+ MissBuffer* mq;
TagStore* tags;
Tick latency;
diff --git a/src/mem/cache/prefetch/tagged_prefetcher_impl.hh b/src/mem/cache/prefetch/tagged_prefetcher_impl.hh
index a18de4571..b3d4284c7 100644
--- a/src/mem/cache/prefetch/tagged_prefetcher_impl.hh
+++ b/src/mem/cache/prefetch/tagged_prefetcher_impl.hh
@@ -36,20 +36,20 @@
#include "arch/isa_traits.hh"
#include "mem/cache/prefetch/tagged_prefetcher.hh"
-template <class TagStore, class Buffering>
-TaggedPrefetcher<TagStore, Buffering>::
+template <class TagStore>
+TaggedPrefetcher<TagStore>::
TaggedPrefetcher(int size, bool pageStop, bool serialSquash,
bool cacheCheckPush, bool onlyData,
Tick latency, int degree)
- :Prefetcher<TagStore, Buffering>(size, pageStop, serialSquash,
+ :Prefetcher<TagStore>(size, pageStop, serialSquash,
cacheCheckPush, onlyData),
latency(latency), degree(degree)
{
}
-template <class TagStore, class Buffering>
+template <class TagStore>
void
-TaggedPrefetcher<TagStore, Buffering>::
+TaggedPrefetcher<TagStore>::
calculatePrefetch(PacketPtr &pkt, std::list<Addr> &addresses,
std::list<Tick> &delays)
{
diff --git a/src/python/m5/objects/Repl.py b/src/python/m5/objects/Repl.py
index 10892cf6f..b76aa1d6e 100644
--- a/src/python/m5/objects/Repl.py
+++ b/src/python/m5/objects/Repl.py
@@ -6,6 +6,6 @@ class Repl(SimObject):
class GenRepl(Repl):
type = 'GenRepl'
- fresh_res = Param.Int("associativity")
- num_pools = Param.Int("capacity in bytes")
- pool_res = Param.Int("block size in bytes")
+ fresh_res = Param.Int("Fresh pool residency time")
+ num_pools = Param.Int("Number of priority pools")
+ pool_res = Param.Int("Pool residency time")
diff --git a/src/python/m5/params.py b/src/python/m5/params.py
index 9e5f985c3..d83d5f73f 100644
--- a/src/python/m5/params.py
+++ b/src/python/m5/params.py
@@ -237,6 +237,12 @@ class NumericParamValue(ParamValue):
def __float__(self):
return float(self.value)
+ def __long__(self):
+ return long(self.value)
+
+ def __int__(self):
+ return int(self.value)
+
# hook for bounds checking
def _check(self):
return
@@ -308,8 +314,11 @@ class CheckedInt(NumericParamValue):
def __init__(self, value):
if isinstance(value, str):
self.value = convert.toInteger(value)
- elif isinstance(value, (int, long, float)):
+ elif isinstance(value, (int, long, float, NumericParamValue)):
self.value = long(value)
+ else:
+ raise TypeError, "Can't convert object of type %s to CheckedInt" \
+ % type(value).__name__
self._check()
class Int(CheckedInt): cxx_type = 'int'; size = 32; unsigned = False
diff --git a/tests/SConscript b/tests/SConscript
index 8560363f9..8c9029be6 100644
--- a/tests/SConscript
+++ b/tests/SConscript
@@ -114,11 +114,7 @@ def update_test(target, source, env):
src_dir = str(source[1].get_dir())
dest_files = os.listdir(dest_dir)
src_files = os.listdir(src_dir)
- # Exclude status & diff outputs
- for f in ('outdiff', 'statsdiff', 'status'):
- if f in src_files:
- src_files.remove(f)
- for f in src_files:
+ for f in ('stdout', 'stderr', 'm5stats.txt', 'config.ini', 'config.out'):
if f in dest_files:
print " Replacing file", f
dest_files.remove(f)
diff --git a/tests/long/00.gzip/ref/alpha/linux/o3-timing/config.ini b/tests/long/00.gzip/ref/alpha/linux/o3-timing/config.ini
index c3a59fbce..b221360e2 100644
--- a/tests/long/00.gzip/ref/alpha/linux/o3-timing/config.ini
+++ b/tests/long/00.gzip/ref/alpha/linux/o3-timing/config.ini
@@ -7,11 +7,9 @@ max_tick=0
output_file=cout
progress_interval=0
-[debug]
-break_cycles=
-
[exetrace]
intel_format=false
+legion_lockstep=false
pc_symbol=true
print_cpseq=false
print_cycle=true
@@ -102,14 +100,15 @@ max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
-mem=system.cpu.dcache
numIQEntries=64
numPhysFloatRegs=256
numPhysIntRegs=256
numROBEntries=192
numRobs=1
numThreads=1
+phase=0
predType=tournament
+progress_interval=0
renameToDecodeDelay=1
renameToFetchDelay=1
renameToIEWDelay=2
@@ -131,7 +130,6 @@ assoc=2
block_size=64
compressed_bus=false
compression_latency=0
-do_copy=false
hash_delay=1
hit_latency=1
latency=1
@@ -308,7 +306,6 @@ assoc=2
block_size=64
compressed_bus=false
compression_latency=0
-do_copy=false
hash_delay=1
hit_latency=1
latency=1
@@ -348,7 +345,6 @@ assoc=2
block_size=64
compressed_bus=false
compression_latency=0
-do_copy=false
hash_delay=1
hit_latency=1
latency=1
@@ -384,20 +380,33 @@ mem_side=system.membus.port[1]
[system.cpu.toL2Bus]
type=Bus
bus_id=0
+clock=1000
+responder_set=false
+width=64
port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
[system.cpu.workload]
type=LiveProcess
-cmd=hello
+cmd=gzip input.log 1
+cwd=build/ALPHA_SE/tests/opt/long/00.gzip/alpha/linux/o3-timing
+egid=100
env=
-executable=tests/test-progs/hello/bin/alpha/linux/hello
+euid=100
+executable=/dist/m5/cpu2000/binaries/alpha/tru64/gzip
+gid=100
input=cin
output=cout
+pid=100
+ppid=99
system=system
+uid=100
[system.membus]
type=Bus
bus_id=0
+clock=1000
+responder_set=false
+width=64
port=system.physmem.port system.cpu.l2cache.mem_side
[system.physmem]
@@ -409,6 +418,7 @@ port=system.membus.port[0]
[trace]
bufsize=0
+cycle=0
dump_on_exit=false
file=cout
flags=
diff --git a/tests/long/00.gzip/ref/alpha/linux/o3-timing/config.out b/tests/long/00.gzip/ref/alpha/linux/o3-timing/config.out
index f491a3081..704fa2535 100644
--- a/tests/long/00.gzip/ref/alpha/linux/o3-timing/config.out
+++ b/tests/long/00.gzip/ref/alpha/linux/o3-timing/config.out
@@ -19,54 +19,25 @@ mem_mode=atomic
[system.membus]
type=Bus
bus_id=0
+clock=1000
+width=64
+responder_set=false
[system.cpu.workload]
type=LiveProcess
-cmd=hello
-executable=tests/test-progs/hello/bin/alpha/linux/hello
+cmd=gzip input.log 1
+executable=/dist/m5/cpu2000/binaries/alpha/tru64/gzip
input=cin
output=cout
env=
+cwd=build/ALPHA_SE/tests/opt/long/00.gzip/alpha/linux/o3-timing
system=system
-
-[system.cpu.dcache]
-type=BaseCache
-size=262144
-assoc=2
-block_size=64
-latency=1
-mshrs=10
-tgts_per_mshr=5
-write_buffers=8
-prioritizeRequests=false
-do_copy=false
-protocol=null
-trace_addr=0
-hash_delay=1
-repl=null
-compressed_bus=false
-store_compressed=false
-adaptive_compression=false
-compression_latency=0
-block_size=64
-max_miss_count=0
-addr_range=[0,18446744073709551615]
-split=false
-split_size=0
-lifo=false
-two_queue=false
-prefetch_miss=false
-prefetch_access=false
-prefetcher_size=100
-prefetch_past_page=false
-prefetch_serial_squash=false
-prefetch_latency=10
-prefetch_degree=1
-prefetch_policy=none
-prefetch_cache_check_push=true
-prefetch_use_cpu_id=true
-prefetch_data_accesses_only=false
-hit_latency=1
+uid=100
+euid=100
+gid=100
+egid=100
+pid=100
+ppid=99
[system.cpu.fuPool.FUList0.opList0]
type=OpDesc
@@ -199,15 +170,16 @@ FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUL
[system.cpu]
type=DerivO3CPU
clock=1
+phase=0
numThreads=1
activity=0
workload=system.cpu.workload
-mem=system.cpu.dcache
checker=null
max_insts_any_thread=0
max_insts_all_threads=0
max_loads_any_thread=0
max_loads_all_threads=0
+progress_interval=0
cachePorts=200
decodeToFetchDelay=1
renameToFetchDelay=1
@@ -283,7 +255,44 @@ mshrs=10
tgts_per_mshr=5
write_buffers=8
prioritizeRequests=false
-do_copy=false
+protocol=null
+trace_addr=0
+hash_delay=1
+repl=null
+compressed_bus=false
+store_compressed=false
+adaptive_compression=false
+compression_latency=0
+block_size=64
+max_miss_count=0
+addr_range=[0,18446744073709551615]
+split=false
+split_size=0
+lifo=false
+two_queue=false
+prefetch_miss=false
+prefetch_access=false
+prefetcher_size=100
+prefetch_past_page=false
+prefetch_serial_squash=false
+prefetch_latency=10
+prefetch_degree=1
+prefetch_policy=none
+prefetch_cache_check_push=true
+prefetch_use_cpu_id=true
+prefetch_data_accesses_only=false
+hit_latency=1
+
+[system.cpu.dcache]
+type=BaseCache
+size=262144
+assoc=2
+block_size=64
+latency=1
+mshrs=10
+tgts_per_mshr=5
+write_buffers=8
+prioritizeRequests=false
protocol=null
trace_addr=0
hash_delay=1
@@ -322,7 +331,6 @@ mshrs=10
tgts_per_mshr=5
write_buffers=8
prioritizeRequests=false
-do_copy=false
protocol=null
trace_addr=0
hash_delay=1
@@ -354,10 +362,14 @@ hit_latency=1
[system.cpu.toL2Bus]
type=Bus
bus_id=0
+clock=1000
+width=64
+responder_set=false
[trace]
flags=
start=0
+cycle=0
bufsize=0
file=cout
dump_on_exit=false
@@ -396,8 +408,9 @@ print_cpseq=false
print_reg_delta=false
pc_symbol=true
intel_format=false
+legion_lockstep=false
trace_system=client
-[debug]
-break_cycles=
+[statsreset]
+reset_cycle=0
diff --git a/tests/long/00.gzip/ref/alpha/linux/o3-timing/m5stats.txt b/tests/long/00.gzip/ref/alpha/linux/o3-timing/m5stats.txt
index 5d4f9235a..bd4e6c524 100644
--- a/tests/long/00.gzip/ref/alpha/linux/o3-timing/m5stats.txt
+++ b/tests/long/00.gzip/ref/alpha/linux/o3-timing/m5stats.txt
@@ -1,112 +1,112 @@
---------- Begin Simulation Statistics ----------
global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-global.BPredUnit.BTBHits 542 # Number of BTB hits
-global.BPredUnit.BTBLookups 1938 # Number of BTB lookups
-global.BPredUnit.RASInCorrect 48 # Number of incorrect RAS predictions.
-global.BPredUnit.condIncorrect 420 # Number of conditional branches incorrect
-global.BPredUnit.condPredicted 1304 # Number of conditional branches predicted
-global.BPredUnit.lookups 2256 # Number of BP lookups
-global.BPredUnit.usedRAS 291 # Number of times the RAS was used to get a target.
-host_inst_rate 41797 # Simulator instruction rate (inst/s)
-host_mem_usage 160344 # Number of bytes of host memory used
-host_seconds 0.13 # Real time elapsed on the host
-host_tick_rate 50948 # Simulator tick rate (ticks/s)
-memdepunit.memDep.conflictingLoads 12 # Number of conflicting loads.
-memdepunit.memDep.conflictingStores 259 # Number of conflicting stores.
-memdepunit.memDep.insertedLoads 2050 # Number of loads inserted to the mem dependence unit.
-memdepunit.memDep.insertedStores 1221 # Number of stores inserted to the mem dependence unit.
+global.BPredUnit.BTBHits 97621780 # Number of BTB hits
+global.BPredUnit.BTBLookups 104888901 # Number of BTB lookups
+global.BPredUnit.RASInCorrect 203 # Number of incorrect RAS predictions.
+global.BPredUnit.condIncorrect 4270829 # Number of conditional branches incorrect
+global.BPredUnit.condPredicted 101462576 # Number of conditional branches predicted
+global.BPredUnit.lookups 108029652 # Number of BP lookups
+global.BPredUnit.usedRAS 1765818 # Number of times the RAS was used to get a target.
+host_inst_rate 49266 # Simulator instruction rate (inst/s)
+host_mem_usage 315608 # Number of bytes of host memory used
+host_seconds 11479.54 # Real time elapsed on the host
+host_tick_rate 147031 # Simulator tick rate (ticks/s)
+memdepunit.memDep.conflictingLoads 20975706 # Number of conflicting loads.
+memdepunit.memDep.conflictingStores 18042230 # Number of conflicting stores.
+memdepunit.memDep.insertedLoads 207074480 # Number of loads inserted to the mem dependence unit.
+memdepunit.memDep.insertedStores 57063120 # Number of stores inserted to the mem dependence unit.
sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 5623 # Number of instructions simulated
-sim_seconds 0.000000 # Number of seconds simulated
-sim_ticks 6870 # Number of ticks simulated
-system.cpu.commit.COM:branches 862 # Number of branches committed
-system.cpu.commit.COM:bw_lim_events 74 # number cycles where commit BW limit reached
+sim_insts 565552443 # Number of instructions simulated
+sim_seconds 0.001688 # Number of seconds simulated
+sim_ticks 1687849017 # Number of ticks simulated
+system.cpu.commit.COM:branches 62547159 # Number of branches committed
+system.cpu.commit.COM:bw_lim_events 17132854 # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle.samples 6116
+system.cpu.commit.COM:committed_per_cycle.samples 701581491
system.cpu.commit.COM:committed_per_cycle.min_value 0
- 0 3908 6389.80%
- 1 1064 1739.70%
- 2 389 636.04%
- 3 210 343.36%
- 4 153 250.16%
- 5 93 152.06%
- 6 76 124.26%
- 7 149 243.62%
- 8 74 120.99%
+ 0 480309675 6846.10%
+ 1 104094392 1483.71%
+ 2 40244499 573.63%
+ 3 11990473 170.91%
+ 4 15113210 215.42%
+ 5 17360338 247.45%
+ 6 10367558 147.77%
+ 7 4968492 70.82%
+ 8 17132854 244.20%
system.cpu.commit.COM:committed_per_cycle.max_value 8
system.cpu.commit.COM:committed_per_cycle.end_dist
-system.cpu.commit.COM:count 5640 # Number of instructions committed
-system.cpu.commit.COM:loads 979 # Number of loads committed
+system.cpu.commit.COM:count 601856963 # Number of instructions committed
+system.cpu.commit.COM:loads 115049510 # Number of loads committed
system.cpu.commit.COM:membars 0 # Number of memory barriers committed
-system.cpu.commit.COM:refs 1791 # Number of memory references committed
+system.cpu.commit.COM:refs 154862033 # Number of memory references committed
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.branchMispredicts 337 # The number of times a branch was mispredicted
-system.cpu.commit.commitCommittedInsts 5640 # The number of committed instructions
+system.cpu.commit.branchMispredicts 4270194 # The number of times a branch was mispredicted
+system.cpu.commit.commitCommittedInsts 601856963 # The number of committed instructions
system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.commitSquashedInsts 4350 # The number of squashed insts skipped by commit
-system.cpu.committedInsts 5623 # Number of Instructions Simulated
-system.cpu.committedInsts_total 5623 # Number of Instructions Simulated
-system.cpu.cpi 1.221768 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 1.221768 # CPI: Total CPI of All Threads
-system.cpu.dcache.ReadReq_accesses 1538 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 3.072000 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2.240000 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits 1413 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 384 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate 0.081274 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses 125 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_hits 25 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_miss_latency 224 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate 0.065020 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses 100 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_accesses 821 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 2.467742 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2.140845 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 635 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 459 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.226553 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 186 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_hits 108 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_miss_latency 152 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.086480 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 71 # number of WriteReq MSHR misses
-system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles_no_targets 0.800000 # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 11.505618 # Average number of references to valid blocks.
-system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_no_targets 5 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles_no_targets 4 # number of cycles access was blocked
+system.cpu.commit.commitSquashedInsts 331156834 # The number of squashed insts skipped by commit
+system.cpu.committedInsts 565552443 # Number of Instructions Simulated
+system.cpu.committedInsts_total 565552443 # Number of Instructions Simulated
+system.cpu.cpi 2.984425 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 2.984425 # CPI: Total CPI of All Threads
+system.cpu.dcache.ReadReq_accesses 114919015 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 3573.284961 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 3259.194046 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits 114199728 # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency 2570217420 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate 0.006259 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses 719287 # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_hits 495902 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_miss_latency 728055062 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate 0.001944 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_misses 223385 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_accesses 39451321 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_avg_miss_latency 3753.412851 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 3080.837357 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits 38221364 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 4616536410 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate 0.031177 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses 1229957 # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_hits 972712 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_miss_latency 792530006 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.006521 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses 257245 # number of WriteReq MSHR misses
+system.cpu.dcache.avg_blocked_cycles_no_mshrs 329.539233 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles_no_targets 2285.588257 # average number of cycles each access was blocked
+system.cpu.dcache.avg_refs 317.127712 # Average number of references to valid blocks.
+system.cpu.dcache.blocked_no_mshrs 3492 # number of cycles access was blocked
+system.cpu.dcache.blocked_no_targets 327032 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles_no_mshrs 1150751 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles_no_targets 747460499 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.demand_accesses 2359 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 2.710611 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 2.198830 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 2048 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 843 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.131836 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 311 # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits 133 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 376 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate 0.072488 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 171 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_accesses 154370336 # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency 3686.944185 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 3163.733159 # average overall mshr miss latency
+system.cpu.dcache.demand_hits 152421092 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 7186753830 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate 0.012627 # miss rate for demand accesses
+system.cpu.dcache.demand_misses 1949244 # number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits 1468614 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency 1520585068 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate 0.003113 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses 480630 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.overall_accesses 2359 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 2.710611 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 2.198830 # average overall mshr miss latency
+system.cpu.dcache.overall_accesses 154370336 # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency 3686.944185 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 3163.733159 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 2048 # number of overall hits
-system.cpu.dcache.overall_miss_latency 843 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.131836 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 311 # number of overall misses
-system.cpu.dcache.overall_mshr_hits 133 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 376 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate 0.072488 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 171 # number of overall MSHR misses
+system.cpu.dcache.overall_hits 152421092 # number of overall hits
+system.cpu.dcache.overall_miss_latency 7186753830 # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate 0.012627 # miss rate for overall accesses
+system.cpu.dcache.overall_misses 1949244 # number of overall misses
+system.cpu.dcache.overall_mshr_hits 1468614 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_miss_latency 1520585068 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate 0.003113 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses 480630 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@@ -118,92 +118,92 @@ system.cpu.dcache.prefetcher.num_hwpf_issued 0
system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.dcache.replacements 0 # number of replacements
-system.cpu.dcache.sampled_refs 178 # Sample count of references to valid blocks.
+system.cpu.dcache.replacements 476534 # number of replacements
+system.cpu.dcache.sampled_refs 480630 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 119.831029 # Cycle average of tags in use
-system.cpu.dcache.total_refs 2048 # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks 0 # number of writebacks
-system.cpu.decode.DECODE:BlockedCycles 387 # Number of cycles decode is blocked
-system.cpu.decode.DECODE:BranchMispred 93 # Number of times decode detected a branch misprediction
-system.cpu.decode.DECODE:BranchResolved 185 # Number of times decode resolved a branch
-system.cpu.decode.DECODE:DecodedInsts 12349 # Number of instructions handled by decode
-system.cpu.decode.DECODE:IdleCycles 3542 # Number of cycles decode is idle
-system.cpu.decode.DECODE:RunCycles 2158 # Number of cycles decode is running
-system.cpu.decode.DECODE:SquashCycles 754 # Number of cycles decode is squashing
-system.cpu.decode.DECODE:SquashedInsts 286 # Number of squashed instructions handled by decode
-system.cpu.decode.DECODE:UnblockCycles 30 # Number of cycles decode is unblocking
-system.cpu.fetch.Branches 2256 # Number of branches that fetch encountered
-system.cpu.fetch.CacheLines 1582 # Number of cache lines fetched
-system.cpu.fetch.Cycles 3905 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.IcacheSquashes 148 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.Insts 13707 # Number of instructions fetch has processed
-system.cpu.fetch.SquashCycles 456 # Number of cycles fetch has spent squashing
-system.cpu.fetch.branchRate 0.328336 # Number of branch fetches per cycle
-system.cpu.fetch.icacheStallCycles 1582 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.predictedBranches 833 # Number of branches that fetch has predicted taken
-system.cpu.fetch.rate 1.994906 # Number of inst fetches per cycle
+system.cpu.dcache.tagsinuse 4061.534340 # Cycle average of tags in use
+system.cpu.dcache.total_refs 152421092 # Total number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 22778000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.writebacks 337990 # number of writebacks
+system.cpu.decode.DECODE:BlockedCycles 113629190 # Number of cycles decode is blocked
+system.cpu.decode.DECODE:BranchMispred 667 # Number of times decode detected a branch misprediction
+system.cpu.decode.DECODE:BranchResolved 4610173 # Number of times decode resolved a branch
+system.cpu.decode.DECODE:DecodedInsts 1474333999 # Number of instructions handled by decode
+system.cpu.decode.DECODE:IdleCycles 347767079 # Number of cycles decode is idle
+system.cpu.decode.DECODE:RunCycles 231043933 # Number of cycles decode is running
+system.cpu.decode.DECODE:SquashCycles 53597030 # Number of cycles decode is squashing
+system.cpu.decode.DECODE:SquashedInsts 1980 # Number of squashed instructions handled by decode
+system.cpu.decode.DECODE:UnblockCycles 9141290 # Number of cycles decode is unblocking
+system.cpu.fetch.Branches 108029652 # Number of branches that fetch encountered
+system.cpu.fetch.CacheLines 167528188 # Number of cache lines fetched
+system.cpu.fetch.Cycles 410392582 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.IcacheSquashes 7840605 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.Insts 1486495774 # Number of instructions fetch has processed
+system.cpu.fetch.SquashCycles 39151172 # Number of cycles fetch has spent squashing
+system.cpu.fetch.branchRate 0.143052 # Number of branch fetches per cycle
+system.cpu.fetch.icacheStallCycles 167528188 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.predictedBranches 99387598 # Number of branches that fetch has predicted taken
+system.cpu.fetch.rate 1.968403 # Number of inst fetches per cycle
system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist.samples 6871
+system.cpu.fetch.rateDist.samples 755178522
system.cpu.fetch.rateDist.min_value 0
- 0 4549 6620.58%
- 1 174 253.24%
- 2 186 270.70%
- 3 157 228.50%
- 4 211 307.09%
- 5 153 222.68%
- 6 171 248.87%
- 7 105 152.82%
- 8 1165 1695.53%
+ 0 512314112 6784.01%
+ 1 11453310 151.66%
+ 2 16801464 222.48%
+ 3 16318450 216.09%
+ 4 18767749 248.52%
+ 5 15201778 201.30%
+ 6 32935567 436.13%
+ 7 7297838 96.64%
+ 8 124088254 1643.16%
system.cpu.fetch.rateDist.max_value 8
system.cpu.fetch.rateDist.end_dist
-system.cpu.icache.ReadReq_accesses 1582 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 2.960245 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 1.996885 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits 1255 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 968 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate 0.206700 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses 327 # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_hits 6 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_miss_latency 641 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.202908 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses 321 # number of ReadReq MSHR misses
-system.cpu.icache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles_no_targets no value # average number of cycles each access was blocked
-system.cpu.icache.avg_refs 3.909657 # Average number of references to valid blocks.
+system.cpu.icache.ReadReq_accesses 167528184 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency 5600.855285 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 4703.251892 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits 167526954 # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency 6889052 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_rate 0.000007 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_misses 1230 # number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_hits 305 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_miss_latency 4350508 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate 0.000006 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_misses 925 # number of ReadReq MSHR misses
+system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles_no_targets 5880.941176 # average number of cycles each access was blocked
+system.cpu.icache.avg_refs 181110.220541 # Average number of references to valid blocks.
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu.icache.blocked_no_targets 17 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles_no_targets 99976 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.demand_accesses 1582 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 2.960245 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 1.996885 # average overall mshr miss latency
-system.cpu.icache.demand_hits 1255 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 968 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate 0.206700 # miss rate for demand accesses
-system.cpu.icache.demand_misses 327 # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_hits 6 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 641 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate 0.202908 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses 321 # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_accesses 167528184 # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency 5600.855285 # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 4703.251892 # average overall mshr miss latency
+system.cpu.icache.demand_hits 167526954 # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency 6889052 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_rate 0.000007 # miss rate for demand accesses
+system.cpu.icache.demand_misses 1230 # number of demand (read+write) misses
+system.cpu.icache.demand_mshr_hits 305 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_miss_latency 4350508 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_rate 0.000006 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_misses 925 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.overall_accesses 1582 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 2.960245 # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 1.996885 # average overall mshr miss latency
+system.cpu.icache.overall_accesses 167528184 # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency 5600.855285 # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 4703.251892 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits 1255 # number of overall hits
-system.cpu.icache.overall_miss_latency 968 # number of overall miss cycles
-system.cpu.icache.overall_miss_rate 0.206700 # miss rate for overall accesses
-system.cpu.icache.overall_misses 327 # number of overall misses
-system.cpu.icache.overall_mshr_hits 6 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 641 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate 0.202908 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses 321 # number of overall MSHR misses
+system.cpu.icache.overall_hits 167526954 # number of overall hits
+system.cpu.icache.overall_miss_latency 6889052 # number of overall miss cycles
+system.cpu.icache.overall_miss_rate 0.000007 # miss rate for overall accesses
+system.cpu.icache.overall_misses 1230 # number of overall misses
+system.cpu.icache.overall_mshr_hits 305 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_miss_latency 4350508 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_rate 0.000006 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_misses 925 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@@ -215,1646 +215,80 @@ system.cpu.icache.prefetcher.num_hwpf_issued 0
system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.icache.replacements 0 # number of replacements
-system.cpu.icache.sampled_refs 321 # Sample count of references to valid blocks.
+system.cpu.icache.replacements 47 # number of replacements
+system.cpu.icache.sampled_refs 925 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 176.393247 # Cycle average of tags in use
-system.cpu.icache.total_refs 1255 # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse 739.927243 # Cycle average of tags in use
+system.cpu.icache.total_refs 167526954 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.iew.EXEC:branches 1206 # Number of branches executed
-system.cpu.iew.EXEC:insts 7969 # Number of executed instructions
-system.cpu.iew.EXEC:loads 1610 # Number of load instructions executed
-system.cpu.iew.EXEC:nop 37 # number of nop insts executed
-system.cpu.iew.EXEC:rate 1.159802 # Inst execution rate
-system.cpu.iew.EXEC:refs 2599 # number of memory reference insts executed
-system.cpu.iew.EXEC:squashedInsts 419 # Number of squashed instructions skipped in execute
-system.cpu.iew.EXEC:stores 989 # Number of stores executed
+system.cpu.idleCycles 932670496 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.iew.EXEC:branches 92484798 # Number of branches executed
+system.cpu.iew.EXEC:nop 154927960 # number of nop insts executed
+system.cpu.iew.EXEC:rate 0.987080 # Inst execution rate
+system.cpu.iew.EXEC:refs 253735466 # number of memory reference insts executed
+system.cpu.iew.EXEC:stores 51400640 # Number of stores executed
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
-system.cpu.iew.WB:consumers 5438 # num instructions consuming a value
-system.cpu.iew.WB:count 7722 # cumulative count of insts written-back
-system.cpu.iew.WB:fanout 0.744575 # average fanout of values written-back
+system.cpu.iew.WB:consumers 486804101 # num instructions consuming a value
+system.cpu.iew.WB:count 671280122 # cumulative count of insts written-back
+system.cpu.iew.WB:fanout 0.809385 # average fanout of values written-back
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.iew.WB:producers 4049 # num instructions producing a value
-system.cpu.iew.WB:rate 1.123854 # insts written-back per cycle
-system.cpu.iew.WB:sent 7762 # cumulative count of insts sent to commit
-system.cpu.iew.branchMispredicts 393 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewBlockCycles 4 # Number of cycles IEW is blocking
-system.cpu.iew.iewDispLoadInsts 2050 # Number of dispatched load instructions
-system.cpu.iew.iewDispNonSpecInsts 21 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewDispSquashedInsts 272 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispStoreInsts 1221 # Number of dispatched store instructions
-system.cpu.iew.iewDispatchedInsts 9990 # Number of instructions dispatched to IQ
-system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.WB:producers 394011709 # num instructions producing a value
+system.cpu.iew.WB:rate 0.888903 # insts written-back per cycle
+system.cpu.iew.WB:sent 673021204 # cumulative count of insts sent to commit
+system.cpu.iew.branchMispredicts 4738518 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewBlockCycles 26824121 # Number of cycles IEW is blocking
+system.cpu.iew.iewDispLoadInsts 207074480 # Number of dispatched load instructions
+system.cpu.iew.iewDispNonSpecInsts 25 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewDispSquashedInsts 169524029 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispStoreInsts 57063120 # Number of dispatched store instructions
+system.cpu.iew.iewDispatchedInsts 933012139 # Number of instructions dispatched to IQ
+system.cpu.iew.iewExecLoadInsts 202334826 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 7294318 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewExecutedInsts 745421559 # Number of executed instructions
+system.cpu.iew.iewIQFullEvents 36474 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.iewSquashCycles 754 # Number of cycles IEW is squashing
-system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking
-system.cpu.iew.lsq.thread.0.blockedLoads 1 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread.0.cacheBlocked 5 # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.lsq.thread.0.forwLoads 55 # Number of loads that had data forwarded from stores
-system.cpu.iew.lsq.thread.0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.iewLSQFullEvents 1439 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.iewSquashCycles 53597030 # Number of cycles IEW is squashing
+system.cpu.iew.iewUnblockCycles 214253 # Number of cycles IEW is unblocking
+system.cpu.iew.lsq.thread.0.blockedLoads 5548 # Number of blocked loads due to partial load-store forwarding
+system.cpu.iew.lsq.thread.0.cacheBlocked 70837719 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread.0.forwLoads 7377596 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread.0.ignoredResponses 20150 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
-system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread.0.squashedLoads 1071 # Number of loads squashed
-system.cpu.iew.lsq.thread.0.squashedStores 409 # Number of stores squashed
-system.cpu.iew.memOrderViolationEvents 41 # Number of memory order violations
-system.cpu.iew.predictedNotTakenIncorrect 296 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.predictedTakenIncorrect 97 # Number of branches that were predicted taken incorrectly
-system.cpu.ipc 0.818486 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.818486 # IPC: Total IPC of All Threads
-system.cpu.iq.IQ:residence:(null).start_dist # cycles from dispatch to issue
-system.cpu.iq.IQ:residence:(null).samples 0
-system.cpu.iq.IQ:residence:(null).min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
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- 98 0
-system.cpu.iq.IQ:residence:(null).max_value 0
-system.cpu.iq.IQ:residence:(null).end_dist
-
-system.cpu.iq.IQ:residence:IntAlu.start_dist # cycles from dispatch to issue
-system.cpu.iq.IQ:residence:IntAlu.samples 0
-system.cpu.iq.IQ:residence:IntAlu.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
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- 96 0
- 98 0
-system.cpu.iq.IQ:residence:IntAlu.max_value 0
-system.cpu.iq.IQ:residence:IntAlu.end_dist
-
-system.cpu.iq.IQ:residence:IntMult.start_dist # cycles from dispatch to issue
-system.cpu.iq.IQ:residence:IntMult.samples 0
-system.cpu.iq.IQ:residence:IntMult.min_value 0
- 0 0
- 2 0
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- 96 0
- 98 0
-system.cpu.iq.IQ:residence:IntMult.max_value 0
-system.cpu.iq.IQ:residence:IntMult.end_dist
-
-system.cpu.iq.IQ:residence:IntDiv.start_dist # cycles from dispatch to issue
-system.cpu.iq.IQ:residence:IntDiv.samples 0
-system.cpu.iq.IQ:residence:IntDiv.min_value 0
- 0 0
- 2 0
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- 92 0
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- 96 0
- 98 0
-system.cpu.iq.IQ:residence:IntDiv.max_value 0
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-
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-
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-
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-
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-
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-
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-
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-
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-
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-
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-
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-
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- 40 0
- 42 0
- 44 0
- 46 0
- 48 0
- 50 0
- 52 0
- 54 0
- 56 0
- 58 0
- 60 0
- 62 0
- 64 0
- 66 0
- 68 0
- 70 0
- 72 0
- 74 0
- 76 0
- 78 0
- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.ISSUE:IprAccess_delay.max_value 0
-system.cpu.iq.ISSUE:IprAccess_delay.end_dist
-
-system.cpu.iq.ISSUE:InstPrefetch_delay.start_dist # cycles from operands ready to issue
-system.cpu.iq.ISSUE:InstPrefetch_delay.samples 0
-system.cpu.iq.ISSUE:InstPrefetch_delay.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
- 20 0
- 22 0
- 24 0
- 26 0
- 28 0
- 30 0
- 32 0
- 34 0
- 36 0
- 38 0
- 40 0
- 42 0
- 44 0
- 46 0
- 48 0
- 50 0
- 52 0
- 54 0
- 56 0
- 58 0
- 60 0
- 62 0
- 64 0
- 66 0
- 68 0
- 70 0
- 72 0
- 74 0
- 76 0
- 78 0
- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.ISSUE:InstPrefetch_delay.max_value 0
-system.cpu.iq.ISSUE:InstPrefetch_delay.end_dist
-
-system.cpu.iq.ISSUE:FU_type_0 8388 # Type of FU issued
+system.cpu.iew.lsq.thread.0.memOrderViolation 1892 # Number of memory ordering violations
+system.cpu.iew.lsq.thread.0.rescheduledLoads 5548 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread.0.squashedLoads 92024970 # Number of loads squashed
+system.cpu.iew.lsq.thread.0.squashedStores 17250597 # Number of stores squashed
+system.cpu.iew.memOrderViolationEvents 1892 # Number of memory order violations
+system.cpu.iew.predictedNotTakenIncorrect 2705247 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.predictedTakenIncorrect 2033271 # Number of branches that were predicted taken incorrectly
+system.cpu.ipc 0.335073 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.335073 # IPC: Total IPC of All Threads
+system.cpu.iq.ISSUE:FU_type_0 752715877 # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0.start_dist
- (null) 2 0.02% # Type of FU issued
- IntAlu 5594 66.69% # Type of FU issued
- IntMult 1 0.01% # Type of FU issued
+ (null) 0 0.00% # Type of FU issued
+ IntAlu 496182294 65.92% # Type of FU issued
+ IntMult 8208 0.00% # Type of FU issued
IntDiv 0 0.00% # Type of FU issued
- FloatAdd 2 0.02% # Type of FU issued
- FloatCmp 0 0.00% # Type of FU issued
- FloatCvt 0 0.00% # Type of FU issued
- FloatMult 0 0.00% # Type of FU issued
+ FloatAdd 33 0.00% # Type of FU issued
+ FloatCmp 6 0.00% # Type of FU issued
+ FloatCvt 5 0.00% # Type of FU issued
+ FloatMult 5 0.00% # Type of FU issued
FloatDiv 0 0.00% # Type of FU issued
FloatSqrt 0 0.00% # Type of FU issued
- MemRead 1757 20.95% # Type of FU issued
- MemWrite 1032 12.30% # Type of FU issued
+ MemRead 204178453 27.13% # Type of FU issued
+ MemWrite 52346873 6.95% # Type of FU issued
IprAccess 0 0.00% # Type of FU issued
InstPrefetch 0 0.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0.end_dist
-system.cpu.iq.ISSUE:fu_busy_cnt 115 # FU busy when requested
-system.cpu.iq.ISSUE:fu_busy_rate 0.013710 # FU busy rate (busy events/executed inst)
+system.cpu.iq.ISSUE:fu_busy_cnt 3466320 # FU busy when requested
+system.cpu.iq.ISSUE:fu_busy_rate 0.004605 # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:fu_full.start_dist
(null) 0 0.00% # attempts to use FU when none available
- IntAlu 1 0.87% # attempts to use FU when none available
+ IntAlu 2723724 78.58% # attempts to use FU when none available
IntMult 0 0.00% # attempts to use FU when none available
IntDiv 0 0.00% # attempts to use FU when none available
FloatAdd 0 0.00% # attempts to use FU when none available
@@ -1863,78 +297,80 @@ system.cpu.iq.ISSUE:fu_full.start_dist
FloatMult 0 0.00% # attempts to use FU when none available
FloatDiv 0 0.00% # attempts to use FU when none available
FloatSqrt 0 0.00% # attempts to use FU when none available
- MemRead 76 66.09% # attempts to use FU when none available
- MemWrite 38 33.04% # attempts to use FU when none available
+ MemRead 683243 19.71% # attempts to use FU when none available
+ MemWrite 59353 1.71% # attempts to use FU when none available
IprAccess 0 0.00% # attempts to use FU when none available
InstPrefetch 0 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full.end_dist
system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle.samples 6871
+system.cpu.iq.ISSUE:issued_per_cycle.samples 755178522
system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
- 0 3753 5462.09%
- 1 894 1301.12%
- 2 723 1052.25%
- 3 614 893.61%
- 4 451 656.38%
- 5 279 406.05%
- 6 104 151.36%
- 7 41 59.67%
- 8 12 17.46%
+ 0 450030250 5959.26%
+ 1 91846319 1216.22%
+ 2 83470092 1105.30%
+ 3 53962116 714.56%
+ 4 57175468 757.11%
+ 5 10089384 133.60%
+ 6 7448894 98.64%
+ 7 1047122 13.87%
+ 8 108877 1.44%
system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
system.cpu.iq.ISSUE:issued_per_cycle.end_dist
-system.cpu.iq.ISSUE:rate 1.220783 # Inst issue rate
-system.cpu.iq.iqInstsAdded 9932 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqInstsIssued 8388 # Number of instructions issued
-system.cpu.iq.iqNonSpecInstsAdded 21 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqSquashedInstsExamined 3990 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedInstsIssued 21 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedNonSpecRemoved 4 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.iqSquashedOperandsExamined 2486 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.l2cache.ReadReq_accesses 499 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 2.042254 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency 1015 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate 0.995992 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses 497 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 490 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.981964 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses 490 # number of ReadReq MSHR misses
+system.cpu.iq.ISSUE:rate 0.996739 # Inst issue rate
+system.cpu.iq.iqInstsAdded 778084154 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqInstsIssued 752715877 # Number of instructions issued
+system.cpu.iq.iqNonSpecInstsAdded 25 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqSquashedInstsExamined 210836257 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedInstsIssued 250496 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedNonSpecRemoved 8 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.iqSquashedOperandsExamined 119170992 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.l2cache.ReadReq_accesses 481555 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_avg_miss_latency 6806.870170 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2221.284395 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_hits 455236 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_miss_latency 179150016 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate 0.054654 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses 26319 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency 58461984 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.054654 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses 26319 # number of ReadReq MSHR misses
+system.cpu.l2cache.WriteReqNoAck|Writeback_accesses 337990 # number of WriteReqNoAck|Writeback accesses(hits+misses)
+system.cpu.l2cache.WriteReqNoAck|Writeback_hits 337990 # number of WriteReqNoAck|Writeback hits
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs 0.004024 # Average number of references to valid blocks.
+system.cpu.l2cache.avg_refs 30.138911 # Average number of references to valid blocks.
system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.demand_accesses 499 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 2.042254 # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 1 # average overall mshr miss latency
-system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 1015 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate 0.995992 # miss rate for demand accesses
-system.cpu.l2cache.demand_misses 497 # number of demand (read+write) misses
+system.cpu.l2cache.demand_accesses 481555 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_avg_miss_latency 6806.870170 # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 2221.284395 # average overall mshr miss latency
+system.cpu.l2cache.demand_hits 455236 # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency 179150016 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate 0.054654 # miss rate for demand accesses
+system.cpu.l2cache.demand_misses 26319 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency 490 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate 0.981964 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses 490 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_miss_latency 58461984 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate 0.054654 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses 26319 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.overall_accesses 499 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 2.042254 # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 1 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits 2 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 1015 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate 0.995992 # miss rate for overall accesses
-system.cpu.l2cache.overall_misses 497 # number of overall misses
+system.cpu.l2cache.overall_accesses 819545 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_avg_miss_latency 6806.870170 # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 2221.284395 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_hits 793226 # number of overall hits
+system.cpu.l2cache.overall_miss_latency 179150016 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate 0.032114 # miss rate for overall accesses
+system.cpu.l2cache.overall_misses 26319 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 490 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate 0.981964 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses 490 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_miss_latency 58461984 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate 0.032114 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses 26319 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@@ -1946,29 +382,32 @@ system.cpu.l2cache.prefetcher.num_hwpf_issued 0
system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.l2cache.replacements 0 # number of replacements
-system.cpu.l2cache.sampled_refs 497 # Sample count of references to valid blocks.
+system.cpu.l2cache.replacements 934 # number of replacements
+system.cpu.l2cache.sampled_refs 26319 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 295.773395 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks.
+system.cpu.l2cache.tagsinuse 24352.046438 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 793226 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks 0 # number of writebacks
-system.cpu.numCycles 6871 # number of cpu cycles simulated
-system.cpu.rename.RENAME:BlockCycles 4 # Number of cycles rename is blocking
-system.cpu.rename.RENAME:CommittedMaps 4051 # Number of HB maps that are committed
-system.cpu.rename.RENAME:IdleCycles 3758 # Number of cycles rename is idle
-system.cpu.rename.RENAME:LSQFullEvents 62 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RENAME:RenameLookups 14786 # Number of register rename lookups that rename has made
-system.cpu.rename.RENAME:RenamedInsts 11555 # Number of instructions processed by rename
-system.cpu.rename.RENAME:RenamedOperands 8634 # Number of destination operands rename has renamed
-system.cpu.rename.RENAME:RunCycles 1975 # Number of cycles rename is running
-system.cpu.rename.RENAME:SquashCycles 754 # Number of cycles rename is squashing
-system.cpu.rename.RENAME:UnblockCycles 111 # Number of cycles rename is unblocking
-system.cpu.rename.RENAME:UndoneMaps 4583 # Number of HB maps that are undone due to squashing
-system.cpu.rename.RENAME:serializeStallCycles 269 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RENAME:serializingInsts 26 # count of serializing insts renamed
-system.cpu.rename.RENAME:skidInsts 408 # count of insts added to the skid buffer
-system.cpu.rename.RENAME:tempSerializingInsts 21 # count of temporary serializing insts renamed
+system.cpu.l2cache.writebacks 907 # number of writebacks
+system.cpu.numCycles 755178522 # number of cpu cycles simulated
+system.cpu.rename.RENAME:BlockCycles 71954881 # Number of cycles rename is blocking
+system.cpu.rename.RENAME:CommittedMaps 463854889 # Number of HB maps that are committed
+system.cpu.rename.RENAME:IQFullEvents 32102756 # Number of times rename has blocked due to IQ full
+system.cpu.rename.RENAME:IdleCycles 363513131 # Number of cycles rename is idle
+system.cpu.rename.RENAME:LSQFullEvents 18414484 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RENAME:ROBFullEvents 164520 # Number of times rename has blocked due to ROB full
+system.cpu.rename.RENAME:RenameLookups 1301215151 # Number of register rename lookups that rename has made
+system.cpu.rename.RENAME:RenamedInsts 1374424300 # Number of instructions processed by rename
+system.cpu.rename.RENAME:RenamedOperands 698904999 # Number of destination operands rename has renamed
+system.cpu.rename.RENAME:RunCycles 224329578 # Number of cycles rename is running
+system.cpu.rename.RENAME:SquashCycles 53597030 # Number of cycles rename is squashing
+system.cpu.rename.RENAME:UnblockCycles 41747264 # Number of cycles rename is unblocking
+system.cpu.rename.RENAME:UndoneMaps 235050110 # Number of HB maps that are undone due to squashing
+system.cpu.rename.RENAME:serializeStallCycles 36638 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RENAME:serializingInsts 30 # count of serializing insts renamed
+system.cpu.rename.RENAME:skidInsts 105666858 # count of insts added to the skid buffer
+system.cpu.rename.RENAME:tempSerializingInsts 28 # count of temporary serializing insts renamed
+system.cpu.timesIdled 349047 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload.PROG:num_syscalls 17 # Number of system calls
---------- End Simulation Statistics ----------
diff --git a/tests/long/00.gzip/ref/alpha/linux/o3-timing/stderr b/tests/long/00.gzip/ref/alpha/linux/o3-timing/stderr
index 8893caac8..87866a2a5 100644
--- a/tests/long/00.gzip/ref/alpha/linux/o3-timing/stderr
+++ b/tests/long/00.gzip/ref/alpha/linux/o3-timing/stderr
@@ -1,3 +1 @@
warn: Entering event queue @ 0. Starting simulation...
-warn: cycle 0: fault (page_table_fault) detected @ PC 0x000000
-warn: Increasing stack 0x11ff92000:0x11ff9b000 to 0x11ff90000:0x11ff9b000 because of access to 0x11ff91ff0
diff --git a/tests/long/00.gzip/ref/alpha/linux/o3-timing/stdout b/tests/long/00.gzip/ref/alpha/linux/o3-timing/stdout
index fbb329a2f..9aaca3eeb 100644
--- a/tests/long/00.gzip/ref/alpha/linux/o3-timing/stdout
+++ b/tests/long/00.gzip/ref/alpha/linux/o3-timing/stdout
@@ -1,13 +1,31 @@
-Hello world!
-M5 Simulator System
-
-Copyright (c) 2001-2006
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Sep 5 2006 15:28:48
-M5 started Tue Sep 5 15:42:12 2006
-M5 executing on zizzer.eecs.umich.edu
-command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/o3-timing tests/run.py quick/00.hello/alpha/linux/o3-timing
-Exiting @ tick 6870 because target called exit()
+spec_init
+Loading Input Data
+Duplicating 262144 bytes
+Duplicating 524288 bytes
+Input data 1048576 bytes in length
+Compressing Input Data, level 1
+Compressed data 108074 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Compressing Input Data, level 3
+Compressed data 97831 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Compressing Input Data, level 5
+Compressed data 83382 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Compressing Input Data, level 7
+Compressed data 76606 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Compressing Input Data, level 9
+Compressed data 73189 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Tested 1MB buffer: OK!
diff --git a/tests/long/00.gzip/ref/alpha/linux/simple-atomic/config.ini b/tests/long/00.gzip/ref/alpha/linux/simple-atomic/config.ini
index c3a59fbce..841e8766f 100644
--- a/tests/long/00.gzip/ref/alpha/linux/simple-atomic/config.ini
+++ b/tests/long/00.gzip/ref/alpha/linux/simple-atomic/config.ini
@@ -7,11 +7,9 @@ max_tick=0
output_file=cout
progress_interval=0
-[debug]
-break_cycles=
-
[exetrace]
intel_format=false
+legion_lockstep=false
pc_symbol=true
print_cpseq=false
print_cycle=true
@@ -53,352 +51,49 @@ mem_mode=atomic
physmem=system.physmem
[system.cpu]
-type=DerivO3CPU
-children=dcache fuPool icache l2cache toL2Bus workload
-BTBEntries=4096
-BTBTagSize=16
-LFSTSize=1024
-LQEntries=32
-RASSize=16
-SQEntries=32
-SSITSize=1024
-activity=0
-backComSize=5
-choiceCtrBits=2
-choicePredictorSize=8192
+type=AtomicSimpleCPU
+children=workload
clock=1
-commitToDecodeDelay=1
-commitToFetchDelay=1
-commitToIEWDelay=1
-commitToRenameDelay=1
-commitWidth=8
-decodeToFetchDelay=1
-decodeToRenameDelay=1
-decodeWidth=8
+cpu_id=0
defer_registration=false
-dispatchWidth=8
-fetchToDecodeDelay=1
-fetchTrapLatency=1
-fetchWidth=8
-forwardComSize=5
-fuPool=system.cpu.fuPool
function_trace=false
function_trace_start=0
-globalCtrBits=2
-globalHistoryBits=13
-globalPredictorSize=8192
-iewToCommitDelay=1
-iewToDecodeDelay=1
-iewToFetchDelay=1
-iewToRenameDelay=1
-instShiftAmt=2
-issueToExecuteDelay=1
-issueWidth=8
-localCtrBits=2
-localHistoryBits=11
-localHistoryTableSize=2048
-localPredictorSize=2048
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
-mem=system.cpu.dcache
-numIQEntries=64
-numPhysFloatRegs=256
-numPhysIntRegs=256
-numROBEntries=192
-numRobs=1
-numThreads=1
-predType=tournament
-renameToDecodeDelay=1
-renameToFetchDelay=1
-renameToIEWDelay=2
-renameToROBDelay=1
-renameWidth=8
-squashWidth=8
+phase=0
+progress_interval=0
+simulate_stalls=false
system=system
-trapLatency=13
-wbDepth=1
-wbWidth=8
+width=1
workload=system.cpu.workload
-dcache_port=system.cpu.dcache.cpu_side
-icache_port=system.cpu.icache.cpu_side
-
-[system.cpu.dcache]
-type=BaseCache
-adaptive_compression=false
-assoc=2
-block_size=64
-compressed_bus=false
-compression_latency=0
-do_copy=false
-hash_delay=1
-hit_latency=1
-latency=1
-lifo=false
-max_miss_count=0
-mshrs=10
-prefetch_access=false
-prefetch_cache_check_push=true
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10
-prefetch_miss=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
-prioritizeRequests=false
-protocol=Null
-repl=Null
-size=262144
-split=false
-split_size=0
-store_compressed=false
-subblock_size=0
-tgts_per_mshr=5
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu.dcache_port
-mem_side=system.cpu.toL2Bus.port[1]
-
-[system.cpu.fuPool]
-type=FUPool
-children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7
-FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7
-
-[system.cpu.fuPool.FUList0]
-type=FUDesc
-children=opList0
-count=6
-opList=system.cpu.fuPool.FUList0.opList0
-
-[system.cpu.fuPool.FUList0.opList0]
-type=OpDesc
-issueLat=1
-opClass=IntAlu
-opLat=1
-
-[system.cpu.fuPool.FUList1]
-type=FUDesc
-children=opList0 opList1
-count=2
-opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
-
-[system.cpu.fuPool.FUList1.opList0]
-type=OpDesc
-issueLat=1
-opClass=IntMult
-opLat=3
-
-[system.cpu.fuPool.FUList1.opList1]
-type=OpDesc
-issueLat=19
-opClass=IntDiv
-opLat=20
-
-[system.cpu.fuPool.FUList2]
-type=FUDesc
-children=opList0 opList1 opList2
-count=4
-opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
-
-[system.cpu.fuPool.FUList2.opList0]
-type=OpDesc
-issueLat=1
-opClass=FloatAdd
-opLat=2
-
-[system.cpu.fuPool.FUList2.opList1]
-type=OpDesc
-issueLat=1
-opClass=FloatCmp
-opLat=2
-
-[system.cpu.fuPool.FUList2.opList2]
-type=OpDesc
-issueLat=1
-opClass=FloatCvt
-opLat=2
-
-[system.cpu.fuPool.FUList3]
-type=FUDesc
-children=opList0 opList1 opList2
-count=2
-opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
-
-[system.cpu.fuPool.FUList3.opList0]
-type=OpDesc
-issueLat=1
-opClass=FloatMult
-opLat=4
-
-[system.cpu.fuPool.FUList3.opList1]
-type=OpDesc
-issueLat=12
-opClass=FloatDiv
-opLat=12
-
-[system.cpu.fuPool.FUList3.opList2]
-type=OpDesc
-issueLat=24
-opClass=FloatSqrt
-opLat=24
-
-[system.cpu.fuPool.FUList4]
-type=FUDesc
-children=opList0
-count=0
-opList=system.cpu.fuPool.FUList4.opList0
-
-[system.cpu.fuPool.FUList4.opList0]
-type=OpDesc
-issueLat=1
-opClass=MemRead
-opLat=1
-
-[system.cpu.fuPool.FUList5]
-type=FUDesc
-children=opList0
-count=0
-opList=system.cpu.fuPool.FUList5.opList0
-
-[system.cpu.fuPool.FUList5.opList0]
-type=OpDesc
-issueLat=1
-opClass=MemWrite
-opLat=1
-
-[system.cpu.fuPool.FUList6]
-type=FUDesc
-children=opList0 opList1
-count=4
-opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1
-
-[system.cpu.fuPool.FUList6.opList0]
-type=OpDesc
-issueLat=1
-opClass=MemRead
-opLat=1
-
-[system.cpu.fuPool.FUList6.opList1]
-type=OpDesc
-issueLat=1
-opClass=MemWrite
-opLat=1
-
-[system.cpu.fuPool.FUList7]
-type=FUDesc
-children=opList0
-count=1
-opList=system.cpu.fuPool.FUList7.opList0
-
-[system.cpu.fuPool.FUList7.opList0]
-type=OpDesc
-issueLat=3
-opClass=IprAccess
-opLat=3
-
-[system.cpu.icache]
-type=BaseCache
-adaptive_compression=false
-assoc=2
-block_size=64
-compressed_bus=false
-compression_latency=0
-do_copy=false
-hash_delay=1
-hit_latency=1
-latency=1
-lifo=false
-max_miss_count=0
-mshrs=10
-prefetch_access=false
-prefetch_cache_check_push=true
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10
-prefetch_miss=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
-prioritizeRequests=false
-protocol=Null
-repl=Null
-size=131072
-split=false
-split_size=0
-store_compressed=false
-subblock_size=0
-tgts_per_mshr=5
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu.icache_port
-mem_side=system.cpu.toL2Bus.port[0]
-
-[system.cpu.l2cache]
-type=BaseCache
-adaptive_compression=false
-assoc=2
-block_size=64
-compressed_bus=false
-compression_latency=0
-do_copy=false
-hash_delay=1
-hit_latency=1
-latency=1
-lifo=false
-max_miss_count=0
-mshrs=10
-prefetch_access=false
-prefetch_cache_check_push=true
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10
-prefetch_miss=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
-prioritizeRequests=false
-protocol=Null
-repl=Null
-size=2097152
-split=false
-split_size=0
-store_compressed=false
-subblock_size=0
-tgts_per_mshr=5
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[1]
-
-[system.cpu.toL2Bus]
-type=Bus
-bus_id=0
-port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+dcache_port=system.membus.port[2]
+icache_port=system.membus.port[1]
[system.cpu.workload]
type=LiveProcess
-cmd=hello
+cmd=gzip input.log 1
+cwd=build/ALPHA_SE/tests/opt/long/00.gzip/alpha/linux/simple-atomic
+egid=100
env=
-executable=tests/test-progs/hello/bin/alpha/linux/hello
+euid=100
+executable=/dist/m5/cpu2000/binaries/alpha/tru64/gzip
+gid=100
input=cin
output=cout
+pid=100
+ppid=99
system=system
+uid=100
[system.membus]
type=Bus
bus_id=0
-port=system.physmem.port system.cpu.l2cache.mem_side
+clock=1000
+responder_set=false
+width=64
+port=system.physmem.port system.cpu.icache_port system.cpu.dcache_port
[system.physmem]
type=PhysicalMemory
@@ -409,6 +104,7 @@ port=system.membus.port[0]
[trace]
bufsize=0
+cycle=0
dump_on_exit=false
file=cout
flags=
diff --git a/tests/long/00.gzip/ref/alpha/linux/simple-atomic/config.out b/tests/long/00.gzip/ref/alpha/linux/simple-atomic/config.out
index f491a3081..b5a24e5fb 100644
--- a/tests/long/00.gzip/ref/alpha/linux/simple-atomic/config.out
+++ b/tests/long/00.gzip/ref/alpha/linux/simple-atomic/config.out
@@ -19,345 +19,48 @@ mem_mode=atomic
[system.membus]
type=Bus
bus_id=0
+clock=1000
+width=64
+responder_set=false
[system.cpu.workload]
type=LiveProcess
-cmd=hello
-executable=tests/test-progs/hello/bin/alpha/linux/hello
+cmd=gzip input.log 1
+executable=/dist/m5/cpu2000/binaries/alpha/tru64/gzip
input=cin
output=cout
env=
+cwd=build/ALPHA_SE/tests/opt/long/00.gzip/alpha/linux/simple-atomic
system=system
-
-[system.cpu.dcache]
-type=BaseCache
-size=262144
-assoc=2
-block_size=64
-latency=1
-mshrs=10
-tgts_per_mshr=5
-write_buffers=8
-prioritizeRequests=false
-do_copy=false
-protocol=null
-trace_addr=0
-hash_delay=1
-repl=null
-compressed_bus=false
-store_compressed=false
-adaptive_compression=false
-compression_latency=0
-block_size=64
-max_miss_count=0
-addr_range=[0,18446744073709551615]
-split=false
-split_size=0
-lifo=false
-two_queue=false
-prefetch_miss=false
-prefetch_access=false
-prefetcher_size=100
-prefetch_past_page=false
-prefetch_serial_squash=false
-prefetch_latency=10
-prefetch_degree=1
-prefetch_policy=none
-prefetch_cache_check_push=true
-prefetch_use_cpu_id=true
-prefetch_data_accesses_only=false
-hit_latency=1
-
-[system.cpu.fuPool.FUList0.opList0]
-type=OpDesc
-opClass=IntAlu
-opLat=1
-issueLat=1
-
-[system.cpu.fuPool.FUList0]
-type=FUDesc
-opList=system.cpu.fuPool.FUList0.opList0
-count=6
-
-[system.cpu.fuPool.FUList1.opList0]
-type=OpDesc
-opClass=IntMult
-opLat=3
-issueLat=1
-
-[system.cpu.fuPool.FUList1.opList1]
-type=OpDesc
-opClass=IntDiv
-opLat=20
-issueLat=19
-
-[system.cpu.fuPool.FUList1]
-type=FUDesc
-opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
-count=2
-
-[system.cpu.fuPool.FUList2.opList0]
-type=OpDesc
-opClass=FloatAdd
-opLat=2
-issueLat=1
-
-[system.cpu.fuPool.FUList2.opList1]
-type=OpDesc
-opClass=FloatCmp
-opLat=2
-issueLat=1
-
-[system.cpu.fuPool.FUList2.opList2]
-type=OpDesc
-opClass=FloatCvt
-opLat=2
-issueLat=1
-
-[system.cpu.fuPool.FUList2]
-type=FUDesc
-opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
-count=4
-
-[system.cpu.fuPool.FUList3.opList0]
-type=OpDesc
-opClass=FloatMult
-opLat=4
-issueLat=1
-
-[system.cpu.fuPool.FUList3.opList1]
-type=OpDesc
-opClass=FloatDiv
-opLat=12
-issueLat=12
-
-[system.cpu.fuPool.FUList3.opList2]
-type=OpDesc
-opClass=FloatSqrt
-opLat=24
-issueLat=24
-
-[system.cpu.fuPool.FUList3]
-type=FUDesc
-opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
-count=2
-
-[system.cpu.fuPool.FUList4.opList0]
-type=OpDesc
-opClass=MemRead
-opLat=1
-issueLat=1
-
-[system.cpu.fuPool.FUList4]
-type=FUDesc
-opList=system.cpu.fuPool.FUList4.opList0
-count=0
-
-[system.cpu.fuPool.FUList5.opList0]
-type=OpDesc
-opClass=MemWrite
-opLat=1
-issueLat=1
-
-[system.cpu.fuPool.FUList5]
-type=FUDesc
-opList=system.cpu.fuPool.FUList5.opList0
-count=0
-
-[system.cpu.fuPool.FUList6.opList0]
-type=OpDesc
-opClass=MemRead
-opLat=1
-issueLat=1
-
-[system.cpu.fuPool.FUList6.opList1]
-type=OpDesc
-opClass=MemWrite
-opLat=1
-issueLat=1
-
-[system.cpu.fuPool.FUList6]
-type=FUDesc
-opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1
-count=4
-
-[system.cpu.fuPool.FUList7.opList0]
-type=OpDesc
-opClass=IprAccess
-opLat=3
-issueLat=3
-
-[system.cpu.fuPool.FUList7]
-type=FUDesc
-opList=system.cpu.fuPool.FUList7.opList0
-count=1
-
-[system.cpu.fuPool]
-type=FUPool
-FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7
+uid=100
+euid=100
+gid=100
+egid=100
+pid=100
+ppid=99
[system.cpu]
-type=DerivO3CPU
-clock=1
-numThreads=1
-activity=0
-workload=system.cpu.workload
-mem=system.cpu.dcache
-checker=null
+type=AtomicSimpleCPU
max_insts_any_thread=0
max_insts_all_threads=0
max_loads_any_thread=0
max_loads_all_threads=0
-cachePorts=200
-decodeToFetchDelay=1
-renameToFetchDelay=1
-iewToFetchDelay=1
-commitToFetchDelay=1
-fetchWidth=8
-renameToDecodeDelay=1
-iewToDecodeDelay=1
-commitToDecodeDelay=1
-fetchToDecodeDelay=1
-decodeWidth=8
-iewToRenameDelay=1
-commitToRenameDelay=1
-decodeToRenameDelay=1
-renameWidth=8
-commitToIEWDelay=1
-renameToIEWDelay=2
-issueToExecuteDelay=1
-dispatchWidth=8
-issueWidth=8
-wbWidth=8
-wbDepth=1
-fuPool=system.cpu.fuPool
-iewToCommitDelay=1
-renameToROBDelay=1
-commitWidth=8
-squashWidth=8
-trapLatency=13
-backComSize=5
-forwardComSize=5
-predType=tournament
-localPredictorSize=2048
-localCtrBits=2
-localHistoryTableSize=2048
-localHistoryBits=11
-globalPredictorSize=8192
-globalCtrBits=2
-globalHistoryBits=13
-choicePredictorSize=8192
-choiceCtrBits=2
-BTBEntries=4096
-BTBTagSize=16
-RASSize=16
-LQEntries=32
-SQEntries=32
-LFSTSize=1024
-SSITSize=1024
-numPhysIntRegs=256
-numPhysFloatRegs=256
-numIQEntries=64
-numROBEntries=192
-smtNumFetchingThreads=1
-smtFetchPolicy=SingleThread
-smtLSQPolicy=Partitioned
-smtLSQThreshold=100
-smtIQPolicy=Partitioned
-smtIQThreshold=100
-smtROBPolicy=Partitioned
-smtROBThreshold=100
-smtCommitPolicy=RoundRobin
-instShiftAmt=2
+progress_interval=0
+system=system
+cpu_id=0
+workload=system.cpu.workload
+clock=1
+phase=0
defer_registration=false
+width=1
function_trace=false
function_trace_start=0
-
-[system.cpu.icache]
-type=BaseCache
-size=131072
-assoc=2
-block_size=64
-latency=1
-mshrs=10
-tgts_per_mshr=5
-write_buffers=8
-prioritizeRequests=false
-do_copy=false
-protocol=null
-trace_addr=0
-hash_delay=1
-repl=null
-compressed_bus=false
-store_compressed=false
-adaptive_compression=false
-compression_latency=0
-block_size=64
-max_miss_count=0
-addr_range=[0,18446744073709551615]
-split=false
-split_size=0
-lifo=false
-two_queue=false
-prefetch_miss=false
-prefetch_access=false
-prefetcher_size=100
-prefetch_past_page=false
-prefetch_serial_squash=false
-prefetch_latency=10
-prefetch_degree=1
-prefetch_policy=none
-prefetch_cache_check_push=true
-prefetch_use_cpu_id=true
-prefetch_data_accesses_only=false
-hit_latency=1
-
-[system.cpu.l2cache]
-type=BaseCache
-size=2097152
-assoc=2
-block_size=64
-latency=1
-mshrs=10
-tgts_per_mshr=5
-write_buffers=8
-prioritizeRequests=false
-do_copy=false
-protocol=null
-trace_addr=0
-hash_delay=1
-repl=null
-compressed_bus=false
-store_compressed=false
-adaptive_compression=false
-compression_latency=0
-block_size=64
-max_miss_count=0
-addr_range=[0,18446744073709551615]
-split=false
-split_size=0
-lifo=false
-two_queue=false
-prefetch_miss=false
-prefetch_access=false
-prefetcher_size=100
-prefetch_past_page=false
-prefetch_serial_squash=false
-prefetch_latency=10
-prefetch_degree=1
-prefetch_policy=none
-prefetch_cache_check_push=true
-prefetch_use_cpu_id=true
-prefetch_data_accesses_only=false
-hit_latency=1
-
-[system.cpu.toL2Bus]
-type=Bus
-bus_id=0
+simulate_stalls=false
[trace]
flags=
start=0
+cycle=0
bufsize=0
file=cout
dump_on_exit=false
@@ -396,8 +99,9 @@ print_cpseq=false
print_reg_delta=false
pc_symbol=true
intel_format=false
+legion_lockstep=false
trace_system=client
-[debug]
-break_cycles=
+[statsreset]
+reset_cycle=0
diff --git a/tests/long/00.gzip/ref/alpha/linux/simple-atomic/m5stats.txt b/tests/long/00.gzip/ref/alpha/linux/simple-atomic/m5stats.txt
index 5d4f9235a..b8593d3a3 100644
--- a/tests/long/00.gzip/ref/alpha/linux/simple-atomic/m5stats.txt
+++ b/tests/long/00.gzip/ref/alpha/linux/simple-atomic/m5stats.txt
@@ -1,1974 +1,18 @@
---------- Begin Simulation Statistics ----------
-global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-global.BPredUnit.BTBHits 542 # Number of BTB hits
-global.BPredUnit.BTBLookups 1938 # Number of BTB lookups
-global.BPredUnit.RASInCorrect 48 # Number of incorrect RAS predictions.
-global.BPredUnit.condIncorrect 420 # Number of conditional branches incorrect
-global.BPredUnit.condPredicted 1304 # Number of conditional branches predicted
-global.BPredUnit.lookups 2256 # Number of BP lookups
-global.BPredUnit.usedRAS 291 # Number of times the RAS was used to get a target.
-host_inst_rate 41797 # Simulator instruction rate (inst/s)
-host_mem_usage 160344 # Number of bytes of host memory used
-host_seconds 0.13 # Real time elapsed on the host
-host_tick_rate 50948 # Simulator tick rate (ticks/s)
-memdepunit.memDep.conflictingLoads 12 # Number of conflicting loads.
-memdepunit.memDep.conflictingStores 259 # Number of conflicting stores.
-memdepunit.memDep.insertedLoads 2050 # Number of loads inserted to the mem dependence unit.
-memdepunit.memDep.insertedStores 1221 # Number of stores inserted to the mem dependence unit.
+host_inst_rate 970342 # Simulator instruction rate (inst/s)
+host_mem_usage 144620 # Number of bytes of host memory used
+host_seconds 620.25 # Real time elapsed on the host
+host_tick_rate 970342 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 5623 # Number of instructions simulated
-sim_seconds 0.000000 # Number of seconds simulated
-sim_ticks 6870 # Number of ticks simulated
-system.cpu.commit.COM:branches 862 # Number of branches committed
-system.cpu.commit.COM:bw_lim_events 74 # number cycles where commit BW limit reached
-system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle.samples 6116
-system.cpu.commit.COM:committed_per_cycle.min_value 0
- 0 3908 6389.80%
- 1 1064 1739.70%
- 2 389 636.04%
- 3 210 343.36%
- 4 153 250.16%
- 5 93 152.06%
- 6 76 124.26%
- 7 149 243.62%
- 8 74 120.99%
-system.cpu.commit.COM:committed_per_cycle.max_value 8
-system.cpu.commit.COM:committed_per_cycle.end_dist
-
-system.cpu.commit.COM:count 5640 # Number of instructions committed
-system.cpu.commit.COM:loads 979 # Number of loads committed
-system.cpu.commit.COM:membars 0 # Number of memory barriers committed
-system.cpu.commit.COM:refs 1791 # Number of memory references committed
-system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.branchMispredicts 337 # The number of times a branch was mispredicted
-system.cpu.commit.commitCommittedInsts 5640 # The number of committed instructions
-system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.commitSquashedInsts 4350 # The number of squashed insts skipped by commit
-system.cpu.committedInsts 5623 # Number of Instructions Simulated
-system.cpu.committedInsts_total 5623 # Number of Instructions Simulated
-system.cpu.cpi 1.221768 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 1.221768 # CPI: Total CPI of All Threads
-system.cpu.dcache.ReadReq_accesses 1538 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 3.072000 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2.240000 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits 1413 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 384 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate 0.081274 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses 125 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_hits 25 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_miss_latency 224 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate 0.065020 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses 100 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_accesses 821 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 2.467742 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2.140845 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 635 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 459 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.226553 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 186 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_hits 108 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_miss_latency 152 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.086480 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 71 # number of WriteReq MSHR misses
-system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles_no_targets 0.800000 # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 11.505618 # Average number of references to valid blocks.
-system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_no_targets 5 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles_no_targets 4 # number of cycles access was blocked
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.demand_accesses 2359 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 2.710611 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 2.198830 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 2048 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 843 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.131836 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 311 # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits 133 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 376 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate 0.072488 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 171 # number of demand (read+write) MSHR misses
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.overall_accesses 2359 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 2.710611 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 2.198830 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 2048 # number of overall hits
-system.cpu.dcache.overall_miss_latency 843 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.131836 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 311 # number of overall misses
-system.cpu.dcache.overall_mshr_hits 133 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 376 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate 0.072488 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 171 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.dcache.replacements 0 # number of replacements
-system.cpu.dcache.sampled_refs 178 # Sample count of references to valid blocks.
-system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 119.831029 # Cycle average of tags in use
-system.cpu.dcache.total_refs 2048 # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks 0 # number of writebacks
-system.cpu.decode.DECODE:BlockedCycles 387 # Number of cycles decode is blocked
-system.cpu.decode.DECODE:BranchMispred 93 # Number of times decode detected a branch misprediction
-system.cpu.decode.DECODE:BranchResolved 185 # Number of times decode resolved a branch
-system.cpu.decode.DECODE:DecodedInsts 12349 # Number of instructions handled by decode
-system.cpu.decode.DECODE:IdleCycles 3542 # Number of cycles decode is idle
-system.cpu.decode.DECODE:RunCycles 2158 # Number of cycles decode is running
-system.cpu.decode.DECODE:SquashCycles 754 # Number of cycles decode is squashing
-system.cpu.decode.DECODE:SquashedInsts 286 # Number of squashed instructions handled by decode
-system.cpu.decode.DECODE:UnblockCycles 30 # Number of cycles decode is unblocking
-system.cpu.fetch.Branches 2256 # Number of branches that fetch encountered
-system.cpu.fetch.CacheLines 1582 # Number of cache lines fetched
-system.cpu.fetch.Cycles 3905 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.IcacheSquashes 148 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.Insts 13707 # Number of instructions fetch has processed
-system.cpu.fetch.SquashCycles 456 # Number of cycles fetch has spent squashing
-system.cpu.fetch.branchRate 0.328336 # Number of branch fetches per cycle
-system.cpu.fetch.icacheStallCycles 1582 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.predictedBranches 833 # Number of branches that fetch has predicted taken
-system.cpu.fetch.rate 1.994906 # Number of inst fetches per cycle
-system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist.samples 6871
-system.cpu.fetch.rateDist.min_value 0
- 0 4549 6620.58%
- 1 174 253.24%
- 2 186 270.70%
- 3 157 228.50%
- 4 211 307.09%
- 5 153 222.68%
- 6 171 248.87%
- 7 105 152.82%
- 8 1165 1695.53%
-system.cpu.fetch.rateDist.max_value 8
-system.cpu.fetch.rateDist.end_dist
-
-system.cpu.icache.ReadReq_accesses 1582 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 2.960245 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 1.996885 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits 1255 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 968 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate 0.206700 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses 327 # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_hits 6 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_miss_latency 641 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.202908 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses 321 # number of ReadReq MSHR misses
-system.cpu.icache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles_no_targets no value # average number of cycles each access was blocked
-system.cpu.icache.avg_refs 3.909657 # Average number of references to valid blocks.
-system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.demand_accesses 1582 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 2.960245 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 1.996885 # average overall mshr miss latency
-system.cpu.icache.demand_hits 1255 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 968 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate 0.206700 # miss rate for demand accesses
-system.cpu.icache.demand_misses 327 # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_hits 6 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 641 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate 0.202908 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses 321 # number of demand (read+write) MSHR misses
-system.cpu.icache.fast_writes 0 # number of fast writes performed
-system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.overall_accesses 1582 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 2.960245 # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 1.996885 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits 1255 # number of overall hits
-system.cpu.icache.overall_miss_latency 968 # number of overall miss cycles
-system.cpu.icache.overall_miss_rate 0.206700 # miss rate for overall accesses
-system.cpu.icache.overall_misses 327 # number of overall misses
-system.cpu.icache.overall_mshr_hits 6 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 641 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate 0.202908 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses 321 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.icache.replacements 0 # number of replacements
-system.cpu.icache.sampled_refs 321 # Sample count of references to valid blocks.
-system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 176.393247 # Cycle average of tags in use
-system.cpu.icache.total_refs 1255 # Total number of references to valid blocks.
-system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.iew.EXEC:branches 1206 # Number of branches executed
-system.cpu.iew.EXEC:insts 7969 # Number of executed instructions
-system.cpu.iew.EXEC:loads 1610 # Number of load instructions executed
-system.cpu.iew.EXEC:nop 37 # number of nop insts executed
-system.cpu.iew.EXEC:rate 1.159802 # Inst execution rate
-system.cpu.iew.EXEC:refs 2599 # number of memory reference insts executed
-system.cpu.iew.EXEC:squashedInsts 419 # Number of squashed instructions skipped in execute
-system.cpu.iew.EXEC:stores 989 # Number of stores executed
-system.cpu.iew.EXEC:swp 0 # number of swp insts executed
-system.cpu.iew.WB:consumers 5438 # num instructions consuming a value
-system.cpu.iew.WB:count 7722 # cumulative count of insts written-back
-system.cpu.iew.WB:fanout 0.744575 # average fanout of values written-back
-system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.iew.WB:producers 4049 # num instructions producing a value
-system.cpu.iew.WB:rate 1.123854 # insts written-back per cycle
-system.cpu.iew.WB:sent 7762 # cumulative count of insts sent to commit
-system.cpu.iew.branchMispredicts 393 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewBlockCycles 4 # Number of cycles IEW is blocking
-system.cpu.iew.iewDispLoadInsts 2050 # Number of dispatched load instructions
-system.cpu.iew.iewDispNonSpecInsts 21 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewDispSquashedInsts 272 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispStoreInsts 1221 # Number of dispatched store instructions
-system.cpu.iew.iewDispatchedInsts 9990 # Number of instructions dispatched to IQ
-system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.iewSquashCycles 754 # Number of cycles IEW is squashing
-system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking
-system.cpu.iew.lsq.thread.0.blockedLoads 1 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread.0.cacheBlocked 5 # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.lsq.thread.0.forwLoads 55 # Number of loads that had data forwarded from stores
-system.cpu.iew.lsq.thread.0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
-system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread.0.squashedLoads 1071 # Number of loads squashed
-system.cpu.iew.lsq.thread.0.squashedStores 409 # Number of stores squashed
-system.cpu.iew.memOrderViolationEvents 41 # Number of memory order violations
-system.cpu.iew.predictedNotTakenIncorrect 296 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.predictedTakenIncorrect 97 # Number of branches that were predicted taken incorrectly
-system.cpu.ipc 0.818486 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.818486 # IPC: Total IPC of All Threads
-system.cpu.iq.IQ:residence:(null).start_dist # cycles from dispatch to issue
-system.cpu.iq.IQ:residence:(null).samples 0
-system.cpu.iq.IQ:residence:(null).min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
- 20 0
- 22 0
- 24 0
- 26 0
- 28 0
- 30 0
- 32 0
- 34 0
- 36 0
- 38 0
- 40 0
- 42 0
- 44 0
- 46 0
- 48 0
- 50 0
- 52 0
- 54 0
- 56 0
- 58 0
- 60 0
- 62 0
- 64 0
- 66 0
- 68 0
- 70 0
- 72 0
- 74 0
- 76 0
- 78 0
- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.IQ:residence:(null).max_value 0
-system.cpu.iq.IQ:residence:(null).end_dist
-
-system.cpu.iq.IQ:residence:IntAlu.start_dist # cycles from dispatch to issue
-system.cpu.iq.IQ:residence:IntAlu.samples 0
-system.cpu.iq.IQ:residence:IntAlu.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
- 20 0
- 22 0
- 24 0
- 26 0
- 28 0
- 30 0
- 32 0
- 34 0
- 36 0
- 38 0
- 40 0
- 42 0
- 44 0
- 46 0
- 48 0
- 50 0
- 52 0
- 54 0
- 56 0
- 58 0
- 60 0
- 62 0
- 64 0
- 66 0
- 68 0
- 70 0
- 72 0
- 74 0
- 76 0
- 78 0
- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.IQ:residence:IntAlu.max_value 0
-system.cpu.iq.IQ:residence:IntAlu.end_dist
-
-system.cpu.iq.IQ:residence:IntMult.start_dist # cycles from dispatch to issue
-system.cpu.iq.IQ:residence:IntMult.samples 0
-system.cpu.iq.IQ:residence:IntMult.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
- 20 0
- 22 0
- 24 0
- 26 0
- 28 0
- 30 0
- 32 0
- 34 0
- 36 0
- 38 0
- 40 0
- 42 0
- 44 0
- 46 0
- 48 0
- 50 0
- 52 0
- 54 0
- 56 0
- 58 0
- 60 0
- 62 0
- 64 0
- 66 0
- 68 0
- 70 0
- 72 0
- 74 0
- 76 0
- 78 0
- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.IQ:residence:IntMult.max_value 0
-system.cpu.iq.IQ:residence:IntMult.end_dist
-
-system.cpu.iq.IQ:residence:IntDiv.start_dist # cycles from dispatch to issue
-system.cpu.iq.IQ:residence:IntDiv.samples 0
-system.cpu.iq.IQ:residence:IntDiv.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
- 20 0
- 22 0
- 24 0
- 26 0
- 28 0
- 30 0
- 32 0
- 34 0
- 36 0
- 38 0
- 40 0
- 42 0
- 44 0
- 46 0
- 48 0
- 50 0
- 52 0
- 54 0
- 56 0
- 58 0
- 60 0
- 62 0
- 64 0
- 66 0
- 68 0
- 70 0
- 72 0
- 74 0
- 76 0
- 78 0
- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.IQ:residence:IntDiv.max_value 0
-system.cpu.iq.IQ:residence:IntDiv.end_dist
-
-system.cpu.iq.IQ:residence:FloatAdd.start_dist # cycles from dispatch to issue
-system.cpu.iq.IQ:residence:FloatAdd.samples 0
-system.cpu.iq.IQ:residence:FloatAdd.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
- 20 0
- 22 0
- 24 0
- 26 0
- 28 0
- 30 0
- 32 0
- 34 0
- 36 0
- 38 0
- 40 0
- 42 0
- 44 0
- 46 0
- 48 0
- 50 0
- 52 0
- 54 0
- 56 0
- 58 0
- 60 0
- 62 0
- 64 0
- 66 0
- 68 0
- 70 0
- 72 0
- 74 0
- 76 0
- 78 0
- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.IQ:residence:FloatAdd.max_value 0
-system.cpu.iq.IQ:residence:FloatAdd.end_dist
-
-system.cpu.iq.IQ:residence:FloatCmp.start_dist # cycles from dispatch to issue
-system.cpu.iq.IQ:residence:FloatCmp.samples 0
-system.cpu.iq.IQ:residence:FloatCmp.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
- 20 0
- 22 0
- 24 0
- 26 0
- 28 0
- 30 0
- 32 0
- 34 0
- 36 0
- 38 0
- 40 0
- 42 0
- 44 0
- 46 0
- 48 0
- 50 0
- 52 0
- 54 0
- 56 0
- 58 0
- 60 0
- 62 0
- 64 0
- 66 0
- 68 0
- 70 0
- 72 0
- 74 0
- 76 0
- 78 0
- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.IQ:residence:FloatCmp.max_value 0
-system.cpu.iq.IQ:residence:FloatCmp.end_dist
-
-system.cpu.iq.IQ:residence:FloatCvt.start_dist # cycles from dispatch to issue
-system.cpu.iq.IQ:residence:FloatCvt.samples 0
-system.cpu.iq.IQ:residence:FloatCvt.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
- 20 0
- 22 0
- 24 0
- 26 0
- 28 0
- 30 0
- 32 0
- 34 0
- 36 0
- 38 0
- 40 0
- 42 0
- 44 0
- 46 0
- 48 0
- 50 0
- 52 0
- 54 0
- 56 0
- 58 0
- 60 0
- 62 0
- 64 0
- 66 0
- 68 0
- 70 0
- 72 0
- 74 0
- 76 0
- 78 0
- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.IQ:residence:FloatCvt.max_value 0
-system.cpu.iq.IQ:residence:FloatCvt.end_dist
-
-system.cpu.iq.IQ:residence:FloatMult.start_dist # cycles from dispatch to issue
-system.cpu.iq.IQ:residence:FloatMult.samples 0
-system.cpu.iq.IQ:residence:FloatMult.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
- 20 0
- 22 0
- 24 0
- 26 0
- 28 0
- 30 0
- 32 0
- 34 0
- 36 0
- 38 0
- 40 0
- 42 0
- 44 0
- 46 0
- 48 0
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-
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-
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-
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-
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-
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-
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-
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-
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-
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-
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-
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-
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-
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-
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-
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-
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-system.cpu.iq.ISSUE:issued_per_cycle.samples 6871
-system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
- 0 3753 5462.09%
- 1 894 1301.12%
- 2 723 1052.25%
- 3 614 893.61%
- 4 451 656.38%
- 5 279 406.05%
- 6 104 151.36%
- 7 41 59.67%
- 8 12 17.46%
-system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
-system.cpu.iq.ISSUE:issued_per_cycle.end_dist
-
-system.cpu.iq.ISSUE:rate 1.220783 # Inst issue rate
-system.cpu.iq.iqInstsAdded 9932 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqInstsIssued 8388 # Number of instructions issued
-system.cpu.iq.iqNonSpecInstsAdded 21 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqSquashedInstsExamined 3990 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedInstsIssued 21 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedNonSpecRemoved 4 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.iqSquashedOperandsExamined 2486 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.l2cache.ReadReq_accesses 499 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 2.042254 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency 1015 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate 0.995992 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses 497 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 490 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.981964 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses 490 # number of ReadReq MSHR misses
-system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs 0.004024 # Average number of references to valid blocks.
-system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.demand_accesses 499 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 2.042254 # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 1 # average overall mshr miss latency
-system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 1015 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate 0.995992 # miss rate for demand accesses
-system.cpu.l2cache.demand_misses 497 # number of demand (read+write) misses
-system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency 490 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate 0.981964 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses 490 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.fast_writes 0 # number of fast writes performed
-system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.overall_accesses 499 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 2.042254 # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 1 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits 2 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 1015 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate 0.995992 # miss rate for overall accesses
-system.cpu.l2cache.overall_misses 497 # number of overall misses
-system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 490 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate 0.981964 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses 490 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.l2cache.replacements 0 # number of replacements
-system.cpu.l2cache.sampled_refs 497 # Sample count of references to valid blocks.
-system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 295.773395 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks 0 # number of writebacks
-system.cpu.numCycles 6871 # number of cpu cycles simulated
-system.cpu.rename.RENAME:BlockCycles 4 # Number of cycles rename is blocking
-system.cpu.rename.RENAME:CommittedMaps 4051 # Number of HB maps that are committed
-system.cpu.rename.RENAME:IdleCycles 3758 # Number of cycles rename is idle
-system.cpu.rename.RENAME:LSQFullEvents 62 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RENAME:RenameLookups 14786 # Number of register rename lookups that rename has made
-system.cpu.rename.RENAME:RenamedInsts 11555 # Number of instructions processed by rename
-system.cpu.rename.RENAME:RenamedOperands 8634 # Number of destination operands rename has renamed
-system.cpu.rename.RENAME:RunCycles 1975 # Number of cycles rename is running
-system.cpu.rename.RENAME:SquashCycles 754 # Number of cycles rename is squashing
-system.cpu.rename.RENAME:UnblockCycles 111 # Number of cycles rename is unblocking
-system.cpu.rename.RENAME:UndoneMaps 4583 # Number of HB maps that are undone due to squashing
-system.cpu.rename.RENAME:serializeStallCycles 269 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RENAME:serializingInsts 26 # count of serializing insts renamed
-system.cpu.rename.RENAME:skidInsts 408 # count of insts added to the skid buffer
-system.cpu.rename.RENAME:tempSerializingInsts 21 # count of temporary serializing insts renamed
+sim_insts 601856965 # Number of instructions simulated
+sim_seconds 0.000602 # Number of seconds simulated
+sim_ticks 601856964 # Number of ticks simulated
+system.cpu.idle_fraction 0 # Percentage of idle cycles
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.numCycles 601856965 # number of cpu cycles simulated
+system.cpu.num_insts 601856965 # Number of instructions executed
+system.cpu.num_refs 154862034 # Number of memory references
system.cpu.workload.PROG:num_syscalls 17 # Number of system calls
---------- End Simulation Statistics ----------
diff --git a/tests/long/00.gzip/ref/alpha/linux/simple-atomic/stderr b/tests/long/00.gzip/ref/alpha/linux/simple-atomic/stderr
index 8893caac8..87866a2a5 100644
--- a/tests/long/00.gzip/ref/alpha/linux/simple-atomic/stderr
+++ b/tests/long/00.gzip/ref/alpha/linux/simple-atomic/stderr
@@ -1,3 +1 @@
warn: Entering event queue @ 0. Starting simulation...
-warn: cycle 0: fault (page_table_fault) detected @ PC 0x000000
-warn: Increasing stack 0x11ff92000:0x11ff9b000 to 0x11ff90000:0x11ff9b000 because of access to 0x11ff91ff0
diff --git a/tests/long/00.gzip/ref/alpha/linux/simple-atomic/stdout b/tests/long/00.gzip/ref/alpha/linux/simple-atomic/stdout
index fbb329a2f..9aaca3eeb 100644
--- a/tests/long/00.gzip/ref/alpha/linux/simple-atomic/stdout
+++ b/tests/long/00.gzip/ref/alpha/linux/simple-atomic/stdout
@@ -1,13 +1,31 @@
-Hello world!
-M5 Simulator System
-
-Copyright (c) 2001-2006
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Sep 5 2006 15:28:48
-M5 started Tue Sep 5 15:42:12 2006
-M5 executing on zizzer.eecs.umich.edu
-command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/o3-timing tests/run.py quick/00.hello/alpha/linux/o3-timing
-Exiting @ tick 6870 because target called exit()
+spec_init
+Loading Input Data
+Duplicating 262144 bytes
+Duplicating 524288 bytes
+Input data 1048576 bytes in length
+Compressing Input Data, level 1
+Compressed data 108074 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Compressing Input Data, level 3
+Compressed data 97831 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Compressing Input Data, level 5
+Compressed data 83382 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Compressing Input Data, level 7
+Compressed data 76606 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Compressing Input Data, level 9
+Compressed data 73189 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Tested 1MB buffer: OK!
diff --git a/tests/long/00.gzip/ref/alpha/linux/simple-timing/config.ini b/tests/long/00.gzip/ref/alpha/linux/simple-timing/config.ini
index c3a59fbce..48a760b08 100644
--- a/tests/long/00.gzip/ref/alpha/linux/simple-timing/config.ini
+++ b/tests/long/00.gzip/ref/alpha/linux/simple-timing/config.ini
@@ -7,11 +7,9 @@ max_tick=0
output_file=cout
progress_interval=0
-[debug]
-break_cycles=
-
[exetrace]
intel_format=false
+legion_lockstep=false
pc_symbol=true
print_cpseq=false
print_cycle=true
@@ -53,73 +51,20 @@ mem_mode=atomic
physmem=system.physmem
[system.cpu]
-type=DerivO3CPU
-children=dcache fuPool icache l2cache toL2Bus workload
-BTBEntries=4096
-BTBTagSize=16
-LFSTSize=1024
-LQEntries=32
-RASSize=16
-SQEntries=32
-SSITSize=1024
-activity=0
-backComSize=5
-choiceCtrBits=2
-choicePredictorSize=8192
+type=TimingSimpleCPU
+children=dcache icache l2cache toL2Bus workload
clock=1
-commitToDecodeDelay=1
-commitToFetchDelay=1
-commitToIEWDelay=1
-commitToRenameDelay=1
-commitWidth=8
-decodeToFetchDelay=1
-decodeToRenameDelay=1
-decodeWidth=8
+cpu_id=0
defer_registration=false
-dispatchWidth=8
-fetchToDecodeDelay=1
-fetchTrapLatency=1
-fetchWidth=8
-forwardComSize=5
-fuPool=system.cpu.fuPool
function_trace=false
function_trace_start=0
-globalCtrBits=2
-globalHistoryBits=13
-globalPredictorSize=8192
-iewToCommitDelay=1
-iewToDecodeDelay=1
-iewToFetchDelay=1
-iewToRenameDelay=1
-instShiftAmt=2
-issueToExecuteDelay=1
-issueWidth=8
-localCtrBits=2
-localHistoryBits=11
-localHistoryTableSize=2048
-localPredictorSize=2048
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
-mem=system.cpu.dcache
-numIQEntries=64
-numPhysFloatRegs=256
-numPhysIntRegs=256
-numROBEntries=192
-numRobs=1
-numThreads=1
-predType=tournament
-renameToDecodeDelay=1
-renameToFetchDelay=1
-renameToIEWDelay=2
-renameToROBDelay=1
-renameWidth=8
-squashWidth=8
+phase=0
+progress_interval=0
system=system
-trapLatency=13
-wbDepth=1
-wbWidth=8
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
@@ -131,7 +76,6 @@ assoc=2
block_size=64
compressed_bus=false
compression_latency=0
-do_copy=false
hash_delay=1
hit_latency=1
latency=1
@@ -164,143 +108,6 @@ write_buffers=8
cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.port[1]
-[system.cpu.fuPool]
-type=FUPool
-children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7
-FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7
-
-[system.cpu.fuPool.FUList0]
-type=FUDesc
-children=opList0
-count=6
-opList=system.cpu.fuPool.FUList0.opList0
-
-[system.cpu.fuPool.FUList0.opList0]
-type=OpDesc
-issueLat=1
-opClass=IntAlu
-opLat=1
-
-[system.cpu.fuPool.FUList1]
-type=FUDesc
-children=opList0 opList1
-count=2
-opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
-
-[system.cpu.fuPool.FUList1.opList0]
-type=OpDesc
-issueLat=1
-opClass=IntMult
-opLat=3
-
-[system.cpu.fuPool.FUList1.opList1]
-type=OpDesc
-issueLat=19
-opClass=IntDiv
-opLat=20
-
-[system.cpu.fuPool.FUList2]
-type=FUDesc
-children=opList0 opList1 opList2
-count=4
-opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
-
-[system.cpu.fuPool.FUList2.opList0]
-type=OpDesc
-issueLat=1
-opClass=FloatAdd
-opLat=2
-
-[system.cpu.fuPool.FUList2.opList1]
-type=OpDesc
-issueLat=1
-opClass=FloatCmp
-opLat=2
-
-[system.cpu.fuPool.FUList2.opList2]
-type=OpDesc
-issueLat=1
-opClass=FloatCvt
-opLat=2
-
-[system.cpu.fuPool.FUList3]
-type=FUDesc
-children=opList0 opList1 opList2
-count=2
-opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
-
-[system.cpu.fuPool.FUList3.opList0]
-type=OpDesc
-issueLat=1
-opClass=FloatMult
-opLat=4
-
-[system.cpu.fuPool.FUList3.opList1]
-type=OpDesc
-issueLat=12
-opClass=FloatDiv
-opLat=12
-
-[system.cpu.fuPool.FUList3.opList2]
-type=OpDesc
-issueLat=24
-opClass=FloatSqrt
-opLat=24
-
-[system.cpu.fuPool.FUList4]
-type=FUDesc
-children=opList0
-count=0
-opList=system.cpu.fuPool.FUList4.opList0
-
-[system.cpu.fuPool.FUList4.opList0]
-type=OpDesc
-issueLat=1
-opClass=MemRead
-opLat=1
-
-[system.cpu.fuPool.FUList5]
-type=FUDesc
-children=opList0
-count=0
-opList=system.cpu.fuPool.FUList5.opList0
-
-[system.cpu.fuPool.FUList5.opList0]
-type=OpDesc
-issueLat=1
-opClass=MemWrite
-opLat=1
-
-[system.cpu.fuPool.FUList6]
-type=FUDesc
-children=opList0 opList1
-count=4
-opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1
-
-[system.cpu.fuPool.FUList6.opList0]
-type=OpDesc
-issueLat=1
-opClass=MemRead
-opLat=1
-
-[system.cpu.fuPool.FUList6.opList1]
-type=OpDesc
-issueLat=1
-opClass=MemWrite
-opLat=1
-
-[system.cpu.fuPool.FUList7]
-type=FUDesc
-children=opList0
-count=1
-opList=system.cpu.fuPool.FUList7.opList0
-
-[system.cpu.fuPool.FUList7.opList0]
-type=OpDesc
-issueLat=3
-opClass=IprAccess
-opLat=3
-
[system.cpu.icache]
type=BaseCache
adaptive_compression=false
@@ -308,7 +115,6 @@ assoc=2
block_size=64
compressed_bus=false
compression_latency=0
-do_copy=false
hash_delay=1
hit_latency=1
latency=1
@@ -348,7 +154,6 @@ assoc=2
block_size=64
compressed_bus=false
compression_latency=0
-do_copy=false
hash_delay=1
hit_latency=1
latency=1
@@ -384,20 +189,33 @@ mem_side=system.membus.port[1]
[system.cpu.toL2Bus]
type=Bus
bus_id=0
+clock=1000
+responder_set=false
+width=64
port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
[system.cpu.workload]
type=LiveProcess
-cmd=hello
+cmd=gzip input.log 1
+cwd=build/ALPHA_SE/tests/opt/long/00.gzip/alpha/linux/simple-timing
+egid=100
env=
-executable=tests/test-progs/hello/bin/alpha/linux/hello
+euid=100
+executable=/dist/m5/cpu2000/binaries/alpha/tru64/gzip
+gid=100
input=cin
output=cout
+pid=100
+ppid=99
system=system
+uid=100
[system.membus]
type=Bus
bus_id=0
+clock=1000
+responder_set=false
+width=64
port=system.physmem.port system.cpu.l2cache.mem_side
[system.physmem]
@@ -409,6 +227,7 @@ port=system.membus.port[0]
[trace]
bufsize=0
+cycle=0
dump_on_exit=false
file=cout
flags=
diff --git a/tests/long/00.gzip/ref/alpha/linux/simple-timing/config.out b/tests/long/00.gzip/ref/alpha/linux/simple-timing/config.out
index f491a3081..eddb9ff53 100644
--- a/tests/long/00.gzip/ref/alpha/linux/simple-timing/config.out
+++ b/tests/long/00.gzip/ref/alpha/linux/simple-timing/config.out
@@ -19,19 +19,54 @@ mem_mode=atomic
[system.membus]
type=Bus
bus_id=0
+clock=1000
+width=64
+responder_set=false
[system.cpu.workload]
type=LiveProcess
-cmd=hello
-executable=tests/test-progs/hello/bin/alpha/linux/hello
+cmd=gzip input.log 1
+executable=/dist/m5/cpu2000/binaries/alpha/tru64/gzip
input=cin
output=cout
env=
+cwd=build/ALPHA_SE/tests/opt/long/00.gzip/alpha/linux/simple-timing
system=system
+uid=100
+euid=100
+gid=100
+egid=100
+pid=100
+ppid=99
-[system.cpu.dcache]
+[system.cpu]
+type=TimingSimpleCPU
+max_insts_any_thread=0
+max_insts_all_threads=0
+max_loads_any_thread=0
+max_loads_all_threads=0
+progress_interval=0
+system=system
+cpu_id=0
+workload=system.cpu.workload
+clock=1
+phase=0
+defer_registration=false
+// width not specified
+function_trace=false
+function_trace_start=0
+// simulate_stalls not specified
+
+[system.cpu.toL2Bus]
+type=Bus
+bus_id=0
+clock=1000
+width=64
+responder_set=false
+
+[system.cpu.icache]
type=BaseCache
-size=262144
+size=131072
assoc=2
block_size=64
latency=1
@@ -39,7 +74,6 @@ mshrs=10
tgts_per_mshr=5
write_buffers=8
prioritizeRequests=false
-do_copy=false
protocol=null
trace_addr=0
hash_delay=1
@@ -68,214 +102,9 @@ prefetch_use_cpu_id=true
prefetch_data_accesses_only=false
hit_latency=1
-[system.cpu.fuPool.FUList0.opList0]
-type=OpDesc
-opClass=IntAlu
-opLat=1
-issueLat=1
-
-[system.cpu.fuPool.FUList0]
-type=FUDesc
-opList=system.cpu.fuPool.FUList0.opList0
-count=6
-
-[system.cpu.fuPool.FUList1.opList0]
-type=OpDesc
-opClass=IntMult
-opLat=3
-issueLat=1
-
-[system.cpu.fuPool.FUList1.opList1]
-type=OpDesc
-opClass=IntDiv
-opLat=20
-issueLat=19
-
-[system.cpu.fuPool.FUList1]
-type=FUDesc
-opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
-count=2
-
-[system.cpu.fuPool.FUList2.opList0]
-type=OpDesc
-opClass=FloatAdd
-opLat=2
-issueLat=1
-
-[system.cpu.fuPool.FUList2.opList1]
-type=OpDesc
-opClass=FloatCmp
-opLat=2
-issueLat=1
-
-[system.cpu.fuPool.FUList2.opList2]
-type=OpDesc
-opClass=FloatCvt
-opLat=2
-issueLat=1
-
-[system.cpu.fuPool.FUList2]
-type=FUDesc
-opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
-count=4
-
-[system.cpu.fuPool.FUList3.opList0]
-type=OpDesc
-opClass=FloatMult
-opLat=4
-issueLat=1
-
-[system.cpu.fuPool.FUList3.opList1]
-type=OpDesc
-opClass=FloatDiv
-opLat=12
-issueLat=12
-
-[system.cpu.fuPool.FUList3.opList2]
-type=OpDesc
-opClass=FloatSqrt
-opLat=24
-issueLat=24
-
-[system.cpu.fuPool.FUList3]
-type=FUDesc
-opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
-count=2
-
-[system.cpu.fuPool.FUList4.opList0]
-type=OpDesc
-opClass=MemRead
-opLat=1
-issueLat=1
-
-[system.cpu.fuPool.FUList4]
-type=FUDesc
-opList=system.cpu.fuPool.FUList4.opList0
-count=0
-
-[system.cpu.fuPool.FUList5.opList0]
-type=OpDesc
-opClass=MemWrite
-opLat=1
-issueLat=1
-
-[system.cpu.fuPool.FUList5]
-type=FUDesc
-opList=system.cpu.fuPool.FUList5.opList0
-count=0
-
-[system.cpu.fuPool.FUList6.opList0]
-type=OpDesc
-opClass=MemRead
-opLat=1
-issueLat=1
-
-[system.cpu.fuPool.FUList6.opList1]
-type=OpDesc
-opClass=MemWrite
-opLat=1
-issueLat=1
-
-[system.cpu.fuPool.FUList6]
-type=FUDesc
-opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1
-count=4
-
-[system.cpu.fuPool.FUList7.opList0]
-type=OpDesc
-opClass=IprAccess
-opLat=3
-issueLat=3
-
-[system.cpu.fuPool.FUList7]
-type=FUDesc
-opList=system.cpu.fuPool.FUList7.opList0
-count=1
-
-[system.cpu.fuPool]
-type=FUPool
-FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7
-
-[system.cpu]
-type=DerivO3CPU
-clock=1
-numThreads=1
-activity=0
-workload=system.cpu.workload
-mem=system.cpu.dcache
-checker=null
-max_insts_any_thread=0
-max_insts_all_threads=0
-max_loads_any_thread=0
-max_loads_all_threads=0
-cachePorts=200
-decodeToFetchDelay=1
-renameToFetchDelay=1
-iewToFetchDelay=1
-commitToFetchDelay=1
-fetchWidth=8
-renameToDecodeDelay=1
-iewToDecodeDelay=1
-commitToDecodeDelay=1
-fetchToDecodeDelay=1
-decodeWidth=8
-iewToRenameDelay=1
-commitToRenameDelay=1
-decodeToRenameDelay=1
-renameWidth=8
-commitToIEWDelay=1
-renameToIEWDelay=2
-issueToExecuteDelay=1
-dispatchWidth=8
-issueWidth=8
-wbWidth=8
-wbDepth=1
-fuPool=system.cpu.fuPool
-iewToCommitDelay=1
-renameToROBDelay=1
-commitWidth=8
-squashWidth=8
-trapLatency=13
-backComSize=5
-forwardComSize=5
-predType=tournament
-localPredictorSize=2048
-localCtrBits=2
-localHistoryTableSize=2048
-localHistoryBits=11
-globalPredictorSize=8192
-globalCtrBits=2
-globalHistoryBits=13
-choicePredictorSize=8192
-choiceCtrBits=2
-BTBEntries=4096
-BTBTagSize=16
-RASSize=16
-LQEntries=32
-SQEntries=32
-LFSTSize=1024
-SSITSize=1024
-numPhysIntRegs=256
-numPhysFloatRegs=256
-numIQEntries=64
-numROBEntries=192
-smtNumFetchingThreads=1
-smtFetchPolicy=SingleThread
-smtLSQPolicy=Partitioned
-smtLSQThreshold=100
-smtIQPolicy=Partitioned
-smtIQThreshold=100
-smtROBPolicy=Partitioned
-smtROBThreshold=100
-smtCommitPolicy=RoundRobin
-instShiftAmt=2
-defer_registration=false
-function_trace=false
-function_trace_start=0
-
-[system.cpu.icache]
+[system.cpu.dcache]
type=BaseCache
-size=131072
+size=262144
assoc=2
block_size=64
latency=1
@@ -283,7 +112,6 @@ mshrs=10
tgts_per_mshr=5
write_buffers=8
prioritizeRequests=false
-do_copy=false
protocol=null
trace_addr=0
hash_delay=1
@@ -322,7 +150,6 @@ mshrs=10
tgts_per_mshr=5
write_buffers=8
prioritizeRequests=false
-do_copy=false
protocol=null
trace_addr=0
hash_delay=1
@@ -351,13 +178,10 @@ prefetch_use_cpu_id=true
prefetch_data_accesses_only=false
hit_latency=1
-[system.cpu.toL2Bus]
-type=Bus
-bus_id=0
-
[trace]
flags=
start=0
+cycle=0
bufsize=0
file=cout
dump_on_exit=false
@@ -396,8 +220,9 @@ print_cpseq=false
print_reg_delta=false
pc_symbol=true
intel_format=false
+legion_lockstep=false
trace_system=client
-[debug]
-break_cycles=
+[statsreset]
+reset_cycle=0
diff --git a/tests/long/00.gzip/ref/alpha/linux/simple-timing/m5stats.txt b/tests/long/00.gzip/ref/alpha/linux/simple-timing/m5stats.txt
index 5d4f9235a..5e7441c54 100644
--- a/tests/long/00.gzip/ref/alpha/linux/simple-timing/m5stats.txt
+++ b/tests/long/00.gzip/ref/alpha/linux/simple-timing/m5stats.txt
@@ -1,112 +1,67 @@
---------- Begin Simulation Statistics ----------
-global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-global.BPredUnit.BTBHits 542 # Number of BTB hits
-global.BPredUnit.BTBLookups 1938 # Number of BTB lookups
-global.BPredUnit.RASInCorrect 48 # Number of incorrect RAS predictions.
-global.BPredUnit.condIncorrect 420 # Number of conditional branches incorrect
-global.BPredUnit.condPredicted 1304 # Number of conditional branches predicted
-global.BPredUnit.lookups 2256 # Number of BP lookups
-global.BPredUnit.usedRAS 291 # Number of times the RAS was used to get a target.
-host_inst_rate 41797 # Simulator instruction rate (inst/s)
-host_mem_usage 160344 # Number of bytes of host memory used
-host_seconds 0.13 # Real time elapsed on the host
-host_tick_rate 50948 # Simulator tick rate (ticks/s)
-memdepunit.memDep.conflictingLoads 12 # Number of conflicting loads.
-memdepunit.memDep.conflictingStores 259 # Number of conflicting stores.
-memdepunit.memDep.insertedLoads 2050 # Number of loads inserted to the mem dependence unit.
-memdepunit.memDep.insertedStores 1221 # Number of stores inserted to the mem dependence unit.
+host_inst_rate 549029 # Simulator instruction rate (inst/s)
+host_mem_usage 300652 # Number of bytes of host memory used
+host_seconds 1096.22 # Real time elapsed on the host
+host_tick_rate 1916109 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 5623 # Number of instructions simulated
-sim_seconds 0.000000 # Number of seconds simulated
-sim_ticks 6870 # Number of ticks simulated
-system.cpu.commit.COM:branches 862 # Number of branches committed
-system.cpu.commit.COM:bw_lim_events 74 # number cycles where commit BW limit reached
-system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle.samples 6116
-system.cpu.commit.COM:committed_per_cycle.min_value 0
- 0 3908 6389.80%
- 1 1064 1739.70%
- 2 389 636.04%
- 3 210 343.36%
- 4 153 250.16%
- 5 93 152.06%
- 6 76 124.26%
- 7 149 243.62%
- 8 74 120.99%
-system.cpu.commit.COM:committed_per_cycle.max_value 8
-system.cpu.commit.COM:committed_per_cycle.end_dist
-
-system.cpu.commit.COM:count 5640 # Number of instructions committed
-system.cpu.commit.COM:loads 979 # Number of loads committed
-system.cpu.commit.COM:membars 0 # Number of memory barriers committed
-system.cpu.commit.COM:refs 1791 # Number of memory references committed
-system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.branchMispredicts 337 # The number of times a branch was mispredicted
-system.cpu.commit.commitCommittedInsts 5640 # The number of committed instructions
-system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.commitSquashedInsts 4350 # The number of squashed insts skipped by commit
-system.cpu.committedInsts 5623 # Number of Instructions Simulated
-system.cpu.committedInsts_total 5623 # Number of Instructions Simulated
-system.cpu.cpi 1.221768 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 1.221768 # CPI: Total CPI of All Threads
-system.cpu.dcache.ReadReq_accesses 1538 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 3.072000 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2.240000 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits 1413 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 384 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate 0.081274 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses 125 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_hits 25 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_miss_latency 224 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate 0.065020 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses 100 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_accesses 821 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 2.467742 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2.140845 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 635 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 459 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.226553 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 186 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_hits 108 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_miss_latency 152 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.086480 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 71 # number of WriteReq MSHR misses
+sim_insts 601856965 # Number of instructions simulated
+sim_seconds 0.002100 # Number of seconds simulated
+sim_ticks 2100480012 # Number of ticks simulated
+system.cpu.dcache.ReadReq_accesses 114514042 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 2845.396229 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 1845.396229 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits 114312810 # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency 572584774 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate 0.001757 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses 201232 # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_miss_latency 371352774 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate 0.001757 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_misses 201232 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_accesses 39451321 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_avg_miss_latency 3026.723012 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2026.723012 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits 39197158 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 769281001 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate 0.006442 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses 254163 # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_miss_latency 515118001 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.006442 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses 254163 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles_no_targets 0.800000 # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 11.505618 # Average number of references to valid blocks.
+system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu.dcache.avg_refs 337.091905 # Average number of references to valid blocks.
system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_no_targets 5 # number of cycles access was blocked
+system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles_no_targets 4 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.demand_accesses 2359 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 2.710611 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 2.198830 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 2048 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 843 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.131836 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 311 # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits 133 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 376 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate 0.072488 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 171 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_accesses 153965363 # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency 2946.597514 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 1946.597514 # average overall mshr miss latency
+system.cpu.dcache.demand_hits 153509968 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 1341865775 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate 0.002958 # miss rate for demand accesses
+system.cpu.dcache.demand_misses 455395 # number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency 886470775 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate 0.002958 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses 455395 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.overall_accesses 2359 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 2.710611 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 2.198830 # average overall mshr miss latency
+system.cpu.dcache.overall_accesses 153965363 # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency 2946.597514 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 1946.597514 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 2048 # number of overall hits
-system.cpu.dcache.overall_miss_latency 843 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.131836 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 311 # number of overall misses
-system.cpu.dcache.overall_mshr_hits 133 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 376 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate 0.072488 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 171 # number of overall MSHR misses
+system.cpu.dcache.overall_hits 153509968 # number of overall hits
+system.cpu.dcache.overall_miss_latency 1341865775 # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate 0.002958 # miss rate for overall accesses
+system.cpu.dcache.overall_misses 455395 # number of overall misses
+system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_miss_latency 886470775 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate 0.002958 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses 455395 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@@ -118,92 +73,57 @@ system.cpu.dcache.prefetcher.num_hwpf_issued 0
system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.dcache.replacements 0 # number of replacements
-system.cpu.dcache.sampled_refs 178 # Sample count of references to valid blocks.
+system.cpu.dcache.replacements 451299 # number of replacements
+system.cpu.dcache.sampled_refs 455395 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 119.831029 # Cycle average of tags in use
-system.cpu.dcache.total_refs 2048 # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks 0 # number of writebacks
-system.cpu.decode.DECODE:BlockedCycles 387 # Number of cycles decode is blocked
-system.cpu.decode.DECODE:BranchMispred 93 # Number of times decode detected a branch misprediction
-system.cpu.decode.DECODE:BranchResolved 185 # Number of times decode resolved a branch
-system.cpu.decode.DECODE:DecodedInsts 12349 # Number of instructions handled by decode
-system.cpu.decode.DECODE:IdleCycles 3542 # Number of cycles decode is idle
-system.cpu.decode.DECODE:RunCycles 2158 # Number of cycles decode is running
-system.cpu.decode.DECODE:SquashCycles 754 # Number of cycles decode is squashing
-system.cpu.decode.DECODE:SquashedInsts 286 # Number of squashed instructions handled by decode
-system.cpu.decode.DECODE:UnblockCycles 30 # Number of cycles decode is unblocking
-system.cpu.fetch.Branches 2256 # Number of branches that fetch encountered
-system.cpu.fetch.CacheLines 1582 # Number of cache lines fetched
-system.cpu.fetch.Cycles 3905 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.IcacheSquashes 148 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.Insts 13707 # Number of instructions fetch has processed
-system.cpu.fetch.SquashCycles 456 # Number of cycles fetch has spent squashing
-system.cpu.fetch.branchRate 0.328336 # Number of branch fetches per cycle
-system.cpu.fetch.icacheStallCycles 1582 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.predictedBranches 833 # Number of branches that fetch has predicted taken
-system.cpu.fetch.rate 1.994906 # Number of inst fetches per cycle
-system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist.samples 6871
-system.cpu.fetch.rateDist.min_value 0
- 0 4549 6620.58%
- 1 174 253.24%
- 2 186 270.70%
- 3 157 228.50%
- 4 211 307.09%
- 5 153 222.68%
- 6 171 248.87%
- 7 105 152.82%
- 8 1165 1695.53%
-system.cpu.fetch.rateDist.max_value 8
-system.cpu.fetch.rateDist.end_dist
-
-system.cpu.icache.ReadReq_accesses 1582 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 2.960245 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 1.996885 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits 1255 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 968 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate 0.206700 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses 327 # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_hits 6 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_miss_latency 641 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.202908 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses 321 # number of ReadReq MSHR misses
-system.cpu.icache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles_no_targets no value # average number of cycles each access was blocked
-system.cpu.icache.avg_refs 3.909657 # Average number of references to valid blocks.
+system.cpu.dcache.tagsinuse 4053.427393 # Cycle average of tags in use
+system.cpu.dcache.total_refs 153509968 # Total number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 33693000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.writebacks 325723 # number of writebacks
+system.cpu.icache.ReadReq_accesses 601856966 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency 4085.659119 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 3085.659119 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits 601856171 # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency 3248099 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_rate 0.000001 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_misses 795 # number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_miss_latency 2453099 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate 0.000001 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_misses 795 # number of ReadReq MSHR misses
+system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu.icache.avg_refs 757051.787421 # Average number of references to valid blocks.
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.demand_accesses 1582 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 2.960245 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 1.996885 # average overall mshr miss latency
-system.cpu.icache.demand_hits 1255 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 968 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate 0.206700 # miss rate for demand accesses
-system.cpu.icache.demand_misses 327 # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_hits 6 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 641 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate 0.202908 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses 321 # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_accesses 601856966 # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency 4085.659119 # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 3085.659119 # average overall mshr miss latency
+system.cpu.icache.demand_hits 601856171 # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency 3248099 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_rate 0.000001 # miss rate for demand accesses
+system.cpu.icache.demand_misses 795 # number of demand (read+write) misses
+system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_miss_latency 2453099 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_rate 0.000001 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_misses 795 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.overall_accesses 1582 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 2.960245 # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 1.996885 # average overall mshr miss latency
+system.cpu.icache.overall_accesses 601856966 # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency 4085.659119 # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 3085.659119 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits 1255 # number of overall hits
-system.cpu.icache.overall_miss_latency 968 # number of overall miss cycles
-system.cpu.icache.overall_miss_rate 0.206700 # miss rate for overall accesses
-system.cpu.icache.overall_misses 327 # number of overall misses
-system.cpu.icache.overall_mshr_hits 6 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 641 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate 0.202908 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses 321 # number of overall MSHR misses
+system.cpu.icache.overall_hits 601856171 # number of overall hits
+system.cpu.icache.overall_miss_latency 3248099 # number of overall miss cycles
+system.cpu.icache.overall_miss_rate 0.000001 # miss rate for overall accesses
+system.cpu.icache.overall_misses 795 # number of overall misses
+system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_miss_latency 2453099 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_rate 0.000001 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_misses 795 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@@ -215,1726 +135,60 @@ system.cpu.icache.prefetcher.num_hwpf_issued 0
system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.icache.replacements 0 # number of replacements
-system.cpu.icache.sampled_refs 321 # Sample count of references to valid blocks.
+system.cpu.icache.replacements 24 # number of replacements
+system.cpu.icache.sampled_refs 795 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 176.393247 # Cycle average of tags in use
-system.cpu.icache.total_refs 1255 # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse 642.094524 # Cycle average of tags in use
+system.cpu.icache.total_refs 601856171 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.iew.EXEC:branches 1206 # Number of branches executed
-system.cpu.iew.EXEC:insts 7969 # Number of executed instructions
-system.cpu.iew.EXEC:loads 1610 # Number of load instructions executed
-system.cpu.iew.EXEC:nop 37 # number of nop insts executed
-system.cpu.iew.EXEC:rate 1.159802 # Inst execution rate
-system.cpu.iew.EXEC:refs 2599 # number of memory reference insts executed
-system.cpu.iew.EXEC:squashedInsts 419 # Number of squashed instructions skipped in execute
-system.cpu.iew.EXEC:stores 989 # Number of stores executed
-system.cpu.iew.EXEC:swp 0 # number of swp insts executed
-system.cpu.iew.WB:consumers 5438 # num instructions consuming a value
-system.cpu.iew.WB:count 7722 # cumulative count of insts written-back
-system.cpu.iew.WB:fanout 0.744575 # average fanout of values written-back
-system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.iew.WB:producers 4049 # num instructions producing a value
-system.cpu.iew.WB:rate 1.123854 # insts written-back per cycle
-system.cpu.iew.WB:sent 7762 # cumulative count of insts sent to commit
-system.cpu.iew.branchMispredicts 393 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewBlockCycles 4 # Number of cycles IEW is blocking
-system.cpu.iew.iewDispLoadInsts 2050 # Number of dispatched load instructions
-system.cpu.iew.iewDispNonSpecInsts 21 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewDispSquashedInsts 272 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispStoreInsts 1221 # Number of dispatched store instructions
-system.cpu.iew.iewDispatchedInsts 9990 # Number of instructions dispatched to IQ
-system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.iewSquashCycles 754 # Number of cycles IEW is squashing
-system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking
-system.cpu.iew.lsq.thread.0.blockedLoads 1 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread.0.cacheBlocked 5 # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.lsq.thread.0.forwLoads 55 # Number of loads that had data forwarded from stores
-system.cpu.iew.lsq.thread.0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
-system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread.0.squashedLoads 1071 # Number of loads squashed
-system.cpu.iew.lsq.thread.0.squashedStores 409 # Number of stores squashed
-system.cpu.iew.memOrderViolationEvents 41 # Number of memory order violations
-system.cpu.iew.predictedNotTakenIncorrect 296 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.predictedTakenIncorrect 97 # Number of branches that were predicted taken incorrectly
-system.cpu.ipc 0.818486 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.818486 # IPC: Total IPC of All Threads
-system.cpu.iq.IQ:residence:(null).start_dist # cycles from dispatch to issue
-system.cpu.iq.IQ:residence:(null).samples 0
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-
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-
-system.cpu.iq.IQ:residence:IntMult.start_dist # cycles from dispatch to issue
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-
-system.cpu.iq.IQ:residence:IntDiv.start_dist # cycles from dispatch to issue
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-
-system.cpu.iq.IQ:residence:FloatAdd.start_dist # cycles from dispatch to issue
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-system.cpu.iq.IQ:residence:FloatCmp.start_dist # cycles from dispatch to issue
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-system.cpu.iq.IQ:residence:FloatCvt.start_dist # cycles from dispatch to issue
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-system.cpu.iq.IQ:residence:FloatMult.start_dist # cycles from dispatch to issue
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- 78 0
- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.ISSUE:(null)_delay.max_value 0
-system.cpu.iq.ISSUE:(null)_delay.end_dist
-
-system.cpu.iq.ISSUE:IntAlu_delay.start_dist # cycles from operands ready to issue
-system.cpu.iq.ISSUE:IntAlu_delay.samples 0
-system.cpu.iq.ISSUE:IntAlu_delay.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
- 20 0
- 22 0
- 24 0
- 26 0
- 28 0
- 30 0
- 32 0
- 34 0
- 36 0
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- 78 0
- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.ISSUE:IntAlu_delay.max_value 0
-system.cpu.iq.ISSUE:IntAlu_delay.end_dist
-
-system.cpu.iq.ISSUE:IntMult_delay.start_dist # cycles from operands ready to issue
-system.cpu.iq.ISSUE:IntMult_delay.samples 0
-system.cpu.iq.ISSUE:IntMult_delay.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
- 20 0
- 22 0
- 24 0
- 26 0
- 28 0
- 30 0
- 32 0
- 34 0
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- 78 0
- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.ISSUE:IntMult_delay.max_value 0
-system.cpu.iq.ISSUE:IntMult_delay.end_dist
-
-system.cpu.iq.ISSUE:IntDiv_delay.start_dist # cycles from operands ready to issue
-system.cpu.iq.ISSUE:IntDiv_delay.samples 0
-system.cpu.iq.ISSUE:IntDiv_delay.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
- 20 0
- 22 0
- 24 0
- 26 0
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- 30 0
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- 78 0
- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.ISSUE:IntDiv_delay.max_value 0
-system.cpu.iq.ISSUE:IntDiv_delay.end_dist
-
-system.cpu.iq.ISSUE:FloatAdd_delay.start_dist # cycles from operands ready to issue
-system.cpu.iq.ISSUE:FloatAdd_delay.samples 0
-system.cpu.iq.ISSUE:FloatAdd_delay.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
- 20 0
- 22 0
- 24 0
- 26 0
- 28 0
- 30 0
- 32 0
- 34 0
- 36 0
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- 42 0
- 44 0
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- 74 0
- 76 0
- 78 0
- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.ISSUE:FloatAdd_delay.max_value 0
-system.cpu.iq.ISSUE:FloatAdd_delay.end_dist
-
-system.cpu.iq.ISSUE:FloatCmp_delay.start_dist # cycles from operands ready to issue
-system.cpu.iq.ISSUE:FloatCmp_delay.samples 0
-system.cpu.iq.ISSUE:FloatCmp_delay.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
- 20 0
- 22 0
- 24 0
- 26 0
- 28 0
- 30 0
- 32 0
- 34 0
- 36 0
- 38 0
- 40 0
- 42 0
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- 72 0
- 74 0
- 76 0
- 78 0
- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.ISSUE:FloatCmp_delay.max_value 0
-system.cpu.iq.ISSUE:FloatCmp_delay.end_dist
-
-system.cpu.iq.ISSUE:FloatCvt_delay.start_dist # cycles from operands ready to issue
-system.cpu.iq.ISSUE:FloatCvt_delay.samples 0
-system.cpu.iq.ISSUE:FloatCvt_delay.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
- 20 0
- 22 0
- 24 0
- 26 0
- 28 0
- 30 0
- 32 0
- 34 0
- 36 0
- 38 0
- 40 0
- 42 0
- 44 0
- 46 0
- 48 0
- 50 0
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- 54 0
- 56 0
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- 62 0
- 64 0
- 66 0
- 68 0
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- 72 0
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- 76 0
- 78 0
- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.ISSUE:FloatCvt_delay.max_value 0
-system.cpu.iq.ISSUE:FloatCvt_delay.end_dist
-
-system.cpu.iq.ISSUE:FloatMult_delay.start_dist # cycles from operands ready to issue
-system.cpu.iq.ISSUE:FloatMult_delay.samples 0
-system.cpu.iq.ISSUE:FloatMult_delay.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
- 20 0
- 22 0
- 24 0
- 26 0
- 28 0
- 30 0
- 32 0
- 34 0
- 36 0
- 38 0
- 40 0
- 42 0
- 44 0
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- 48 0
- 50 0
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- 66 0
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- 70 0
- 72 0
- 74 0
- 76 0
- 78 0
- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.ISSUE:FloatMult_delay.max_value 0
-system.cpu.iq.ISSUE:FloatMult_delay.end_dist
-
-system.cpu.iq.ISSUE:FloatDiv_delay.start_dist # cycles from operands ready to issue
-system.cpu.iq.ISSUE:FloatDiv_delay.samples 0
-system.cpu.iq.ISSUE:FloatDiv_delay.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
- 20 0
- 22 0
- 24 0
- 26 0
- 28 0
- 30 0
- 32 0
- 34 0
- 36 0
- 38 0
- 40 0
- 42 0
- 44 0
- 46 0
- 48 0
- 50 0
- 52 0
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- 62 0
- 64 0
- 66 0
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- 70 0
- 72 0
- 74 0
- 76 0
- 78 0
- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.ISSUE:FloatDiv_delay.max_value 0
-system.cpu.iq.ISSUE:FloatDiv_delay.end_dist
-
-system.cpu.iq.ISSUE:FloatSqrt_delay.start_dist # cycles from operands ready to issue
-system.cpu.iq.ISSUE:FloatSqrt_delay.samples 0
-system.cpu.iq.ISSUE:FloatSqrt_delay.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
- 20 0
- 22 0
- 24 0
- 26 0
- 28 0
- 30 0
- 32 0
- 34 0
- 36 0
- 38 0
- 40 0
- 42 0
- 44 0
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- 48 0
- 50 0
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- 54 0
- 56 0
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- 60 0
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- 64 0
- 66 0
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- 70 0
- 72 0
- 74 0
- 76 0
- 78 0
- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.ISSUE:FloatSqrt_delay.max_value 0
-system.cpu.iq.ISSUE:FloatSqrt_delay.end_dist
-
-system.cpu.iq.ISSUE:MemRead_delay.start_dist # cycles from operands ready to issue
-system.cpu.iq.ISSUE:MemRead_delay.samples 0
-system.cpu.iq.ISSUE:MemRead_delay.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
- 20 0
- 22 0
- 24 0
- 26 0
- 28 0
- 30 0
- 32 0
- 34 0
- 36 0
- 38 0
- 40 0
- 42 0
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- 50 0
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- 64 0
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- 70 0
- 72 0
- 74 0
- 76 0
- 78 0
- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.ISSUE:MemRead_delay.max_value 0
-system.cpu.iq.ISSUE:MemRead_delay.end_dist
-
-system.cpu.iq.ISSUE:MemWrite_delay.start_dist # cycles from operands ready to issue
-system.cpu.iq.ISSUE:MemWrite_delay.samples 0
-system.cpu.iq.ISSUE:MemWrite_delay.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
- 20 0
- 22 0
- 24 0
- 26 0
- 28 0
- 30 0
- 32 0
- 34 0
- 36 0
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- 40 0
- 42 0
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- 50 0
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- 72 0
- 74 0
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- 78 0
- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.ISSUE:MemWrite_delay.max_value 0
-system.cpu.iq.ISSUE:MemWrite_delay.end_dist
-
-system.cpu.iq.ISSUE:IprAccess_delay.start_dist # cycles from operands ready to issue
-system.cpu.iq.ISSUE:IprAccess_delay.samples 0
-system.cpu.iq.ISSUE:IprAccess_delay.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
- 20 0
- 22 0
- 24 0
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- 32 0
- 34 0
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- 42 0
- 44 0
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- 50 0
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- 70 0
- 72 0
- 74 0
- 76 0
- 78 0
- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.ISSUE:IprAccess_delay.max_value 0
-system.cpu.iq.ISSUE:IprAccess_delay.end_dist
-
-system.cpu.iq.ISSUE:InstPrefetch_delay.start_dist # cycles from operands ready to issue
-system.cpu.iq.ISSUE:InstPrefetch_delay.samples 0
-system.cpu.iq.ISSUE:InstPrefetch_delay.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
- 20 0
- 22 0
- 24 0
- 26 0
- 28 0
- 30 0
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- 36 0
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- 40 0
- 42 0
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- 46 0
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- 50 0
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- 70 0
- 72 0
- 74 0
- 76 0
- 78 0
- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.ISSUE:InstPrefetch_delay.max_value 0
-system.cpu.iq.ISSUE:InstPrefetch_delay.end_dist
-
-system.cpu.iq.ISSUE:FU_type_0 8388 # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0.start_dist
- (null) 2 0.02% # Type of FU issued
- IntAlu 5594 66.69% # Type of FU issued
- IntMult 1 0.01% # Type of FU issued
- IntDiv 0 0.00% # Type of FU issued
- FloatAdd 2 0.02% # Type of FU issued
- FloatCmp 0 0.00% # Type of FU issued
- FloatCvt 0 0.00% # Type of FU issued
- FloatMult 0 0.00% # Type of FU issued
- FloatDiv 0 0.00% # Type of FU issued
- FloatSqrt 0 0.00% # Type of FU issued
- MemRead 1757 20.95% # Type of FU issued
- MemWrite 1032 12.30% # Type of FU issued
- IprAccess 0 0.00% # Type of FU issued
- InstPrefetch 0 0.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0.end_dist
-system.cpu.iq.ISSUE:fu_busy_cnt 115 # FU busy when requested
-system.cpu.iq.ISSUE:fu_busy_rate 0.013710 # FU busy rate (busy events/executed inst)
-system.cpu.iq.ISSUE:fu_full.start_dist
- (null) 0 0.00% # attempts to use FU when none available
- IntAlu 1 0.87% # attempts to use FU when none available
- IntMult 0 0.00% # attempts to use FU when none available
- IntDiv 0 0.00% # attempts to use FU when none available
- FloatAdd 0 0.00% # attempts to use FU when none available
- FloatCmp 0 0.00% # attempts to use FU when none available
- FloatCvt 0 0.00% # attempts to use FU when none available
- FloatMult 0 0.00% # attempts to use FU when none available
- FloatDiv 0 0.00% # attempts to use FU when none available
- FloatSqrt 0 0.00% # attempts to use FU when none available
- MemRead 76 66.09% # attempts to use FU when none available
- MemWrite 38 33.04% # attempts to use FU when none available
- IprAccess 0 0.00% # attempts to use FU when none available
- InstPrefetch 0 0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full.end_dist
-system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle.samples 6871
-system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
- 0 3753 5462.09%
- 1 894 1301.12%
- 2 723 1052.25%
- 3 614 893.61%
- 4 451 656.38%
- 5 279 406.05%
- 6 104 151.36%
- 7 41 59.67%
- 8 12 17.46%
-system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
-system.cpu.iq.ISSUE:issued_per_cycle.end_dist
-
-system.cpu.iq.ISSUE:rate 1.220783 # Inst issue rate
-system.cpu.iq.iqInstsAdded 9932 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqInstsIssued 8388 # Number of instructions issued
-system.cpu.iq.iqNonSpecInstsAdded 21 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqSquashedInstsExamined 3990 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedInstsIssued 21 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedNonSpecRemoved 4 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.iqSquashedOperandsExamined 2486 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.l2cache.ReadReq_accesses 499 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 2.042254 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency 1015 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate 0.995992 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses 497 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 490 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.981964 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses 490 # number of ReadReq MSHR misses
+system.cpu.idle_fraction 0 # Percentage of idle cycles
+system.cpu.l2cache.ReadReq_accesses 456190 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_avg_miss_latency 3251.348149 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1946.946471 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_hits 430092 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_miss_latency 84853684 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate 0.057209 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses 26098 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency 50811409 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.057209 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses 26098 # number of ReadReq MSHR misses
+system.cpu.l2cache.WriteReqNoAck|Writeback_accesses 325723 # number of WriteReqNoAck|Writeback accesses(hits+misses)
+system.cpu.l2cache.WriteReqNoAck|Writeback_hits 325723 # number of WriteReqNoAck|Writeback hits
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs 0.004024 # Average number of references to valid blocks.
+system.cpu.l2cache.avg_refs 28.960648 # Average number of references to valid blocks.
system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.demand_accesses 499 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 2.042254 # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 1 # average overall mshr miss latency
-system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 1015 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate 0.995992 # miss rate for demand accesses
-system.cpu.l2cache.demand_misses 497 # number of demand (read+write) misses
+system.cpu.l2cache.demand_accesses 456190 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_avg_miss_latency 3251.348149 # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 1946.946471 # average overall mshr miss latency
+system.cpu.l2cache.demand_hits 430092 # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency 84853684 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate 0.057209 # miss rate for demand accesses
+system.cpu.l2cache.demand_misses 26098 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency 490 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate 0.981964 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses 490 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_miss_latency 50811409 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate 0.057209 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses 26098 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.overall_accesses 499 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 2.042254 # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 1 # average overall mshr miss latency
+system.cpu.l2cache.overall_accesses 781913 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_avg_miss_latency 3251.348149 # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 1946.946471 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits 2 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 1015 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate 0.995992 # miss rate for overall accesses
-system.cpu.l2cache.overall_misses 497 # number of overall misses
+system.cpu.l2cache.overall_hits 755815 # number of overall hits
+system.cpu.l2cache.overall_miss_latency 84853684 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate 0.033377 # miss rate for overall accesses
+system.cpu.l2cache.overall_misses 26098 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 490 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate 0.981964 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses 490 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_miss_latency 50811409 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate 0.033377 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses 26098 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@@ -1946,29 +200,17 @@ system.cpu.l2cache.prefetcher.num_hwpf_issued 0
system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.l2cache.replacements 0 # number of replacements
-system.cpu.l2cache.sampled_refs 497 # Sample count of references to valid blocks.
+system.cpu.l2cache.replacements 903 # number of replacements
+system.cpu.l2cache.sampled_refs 26098 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 295.773395 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks.
+system.cpu.l2cache.tagsinuse 24085.007455 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 755815 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks 0 # number of writebacks
-system.cpu.numCycles 6871 # number of cpu cycles simulated
-system.cpu.rename.RENAME:BlockCycles 4 # Number of cycles rename is blocking
-system.cpu.rename.RENAME:CommittedMaps 4051 # Number of HB maps that are committed
-system.cpu.rename.RENAME:IdleCycles 3758 # Number of cycles rename is idle
-system.cpu.rename.RENAME:LSQFullEvents 62 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RENAME:RenameLookups 14786 # Number of register rename lookups that rename has made
-system.cpu.rename.RENAME:RenamedInsts 11555 # Number of instructions processed by rename
-system.cpu.rename.RENAME:RenamedOperands 8634 # Number of destination operands rename has renamed
-system.cpu.rename.RENAME:RunCycles 1975 # Number of cycles rename is running
-system.cpu.rename.RENAME:SquashCycles 754 # Number of cycles rename is squashing
-system.cpu.rename.RENAME:UnblockCycles 111 # Number of cycles rename is unblocking
-system.cpu.rename.RENAME:UndoneMaps 4583 # Number of HB maps that are undone due to squashing
-system.cpu.rename.RENAME:serializeStallCycles 269 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RENAME:serializingInsts 26 # count of serializing insts renamed
-system.cpu.rename.RENAME:skidInsts 408 # count of insts added to the skid buffer
-system.cpu.rename.RENAME:tempSerializingInsts 21 # count of temporary serializing insts renamed
+system.cpu.l2cache.writebacks 883 # number of writebacks
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.numCycles 2100480012 # number of cpu cycles simulated
+system.cpu.num_insts 601856965 # Number of instructions executed
+system.cpu.num_refs 154862034 # Number of memory references
system.cpu.workload.PROG:num_syscalls 17 # Number of system calls
---------- End Simulation Statistics ----------
diff --git a/tests/long/00.gzip/ref/alpha/linux/simple-timing/stderr b/tests/long/00.gzip/ref/alpha/linux/simple-timing/stderr
index 8893caac8..87866a2a5 100644
--- a/tests/long/00.gzip/ref/alpha/linux/simple-timing/stderr
+++ b/tests/long/00.gzip/ref/alpha/linux/simple-timing/stderr
@@ -1,3 +1 @@
warn: Entering event queue @ 0. Starting simulation...
-warn: cycle 0: fault (page_table_fault) detected @ PC 0x000000
-warn: Increasing stack 0x11ff92000:0x11ff9b000 to 0x11ff90000:0x11ff9b000 because of access to 0x11ff91ff0
diff --git a/tests/long/00.gzip/ref/alpha/linux/simple-timing/stdout b/tests/long/00.gzip/ref/alpha/linux/simple-timing/stdout
index fbb329a2f..9aaca3eeb 100644
--- a/tests/long/00.gzip/ref/alpha/linux/simple-timing/stdout
+++ b/tests/long/00.gzip/ref/alpha/linux/simple-timing/stdout
@@ -1,13 +1,31 @@
-Hello world!
-M5 Simulator System
-
-Copyright (c) 2001-2006
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Sep 5 2006 15:28:48
-M5 started Tue Sep 5 15:42:12 2006
-M5 executing on zizzer.eecs.umich.edu
-command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/o3-timing tests/run.py quick/00.hello/alpha/linux/o3-timing
-Exiting @ tick 6870 because target called exit()
+spec_init
+Loading Input Data
+Duplicating 262144 bytes
+Duplicating 524288 bytes
+Input data 1048576 bytes in length
+Compressing Input Data, level 1
+Compressed data 108074 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Compressing Input Data, level 3
+Compressed data 97831 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Compressing Input Data, level 5
+Compressed data 83382 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Compressing Input Data, level 7
+Compressed data 76606 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Compressing Input Data, level 9
+Compressed data 73189 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Tested 1MB buffer: OK!
diff --git a/tests/long/20.parser/ref/alpha/linux/NOTE b/tests/long/20.parser/ref/alpha/linux/NOTE
new file mode 100644
index 000000000..5e7d8c358
--- /dev/null
+++ b/tests/long/20.parser/ref/alpha/linux/NOTE
@@ -0,0 +1,6 @@
+I removed the reference outputs for this program because it's taking
+way too long... over an hour for simple-atomic and over 19 hrs for
+o3-timing. We need to find a shorter input if we want to keep this
+in the regressions.
+
+Steve
diff --git a/tests/long/30.eon/ref/alpha/linux/o3-timing/config.ini b/tests/long/30.eon/ref/alpha/linux/o3-timing/config.ini
index c3a59fbce..e69de29bb 100644
--- a/tests/long/30.eon/ref/alpha/linux/o3-timing/config.ini
+++ b/tests/long/30.eon/ref/alpha/linux/o3-timing/config.ini
@@ -1,417 +0,0 @@
-[root]
-type=Root
-children=system
-checkpoint=
-clock=1000000000000
-max_tick=0
-output_file=cout
-progress_interval=0
-
-[debug]
-break_cycles=
-
-[exetrace]
-intel_format=false
-pc_symbol=true
-print_cpseq=false
-print_cycle=true
-print_data=true
-print_effaddr=true
-print_fetchseq=false
-print_iregs=false
-print_opclass=true
-print_thread=true
-speculative=true
-trace_system=client
-
-[serialize]
-count=10
-cycle=0
-dir=cpt.%012d
-period=0
-
-[stats]
-descriptions=true
-dump_cycle=0
-dump_period=0
-dump_reset=false
-ignore_events=
-mysql_db=
-mysql_host=
-mysql_password=
-mysql_user=
-project_name=test
-simulation_name=test
-simulation_sample=0
-text_compat=true
-text_file=m5stats.txt
-
-[system]
-type=System
-children=cpu membus physmem
-mem_mode=atomic
-physmem=system.physmem
-
-[system.cpu]
-type=DerivO3CPU
-children=dcache fuPool icache l2cache toL2Bus workload
-BTBEntries=4096
-BTBTagSize=16
-LFSTSize=1024
-LQEntries=32
-RASSize=16
-SQEntries=32
-SSITSize=1024
-activity=0
-backComSize=5
-choiceCtrBits=2
-choicePredictorSize=8192
-clock=1
-commitToDecodeDelay=1
-commitToFetchDelay=1
-commitToIEWDelay=1
-commitToRenameDelay=1
-commitWidth=8
-decodeToFetchDelay=1
-decodeToRenameDelay=1
-decodeWidth=8
-defer_registration=false
-dispatchWidth=8
-fetchToDecodeDelay=1
-fetchTrapLatency=1
-fetchWidth=8
-forwardComSize=5
-fuPool=system.cpu.fuPool
-function_trace=false
-function_trace_start=0
-globalCtrBits=2
-globalHistoryBits=13
-globalPredictorSize=8192
-iewToCommitDelay=1
-iewToDecodeDelay=1
-iewToFetchDelay=1
-iewToRenameDelay=1
-instShiftAmt=2
-issueToExecuteDelay=1
-issueWidth=8
-localCtrBits=2
-localHistoryBits=11
-localHistoryTableSize=2048
-localPredictorSize=2048
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-mem=system.cpu.dcache
-numIQEntries=64
-numPhysFloatRegs=256
-numPhysIntRegs=256
-numROBEntries=192
-numRobs=1
-numThreads=1
-predType=tournament
-renameToDecodeDelay=1
-renameToFetchDelay=1
-renameToIEWDelay=2
-renameToROBDelay=1
-renameWidth=8
-squashWidth=8
-system=system
-trapLatency=13
-wbDepth=1
-wbWidth=8
-workload=system.cpu.workload
-dcache_port=system.cpu.dcache.cpu_side
-icache_port=system.cpu.icache.cpu_side
-
-[system.cpu.dcache]
-type=BaseCache
-adaptive_compression=false
-assoc=2
-block_size=64
-compressed_bus=false
-compression_latency=0
-do_copy=false
-hash_delay=1
-hit_latency=1
-latency=1
-lifo=false
-max_miss_count=0
-mshrs=10
-prefetch_access=false
-prefetch_cache_check_push=true
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10
-prefetch_miss=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
-prioritizeRequests=false
-protocol=Null
-repl=Null
-size=262144
-split=false
-split_size=0
-store_compressed=false
-subblock_size=0
-tgts_per_mshr=5
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu.dcache_port
-mem_side=system.cpu.toL2Bus.port[1]
-
-[system.cpu.fuPool]
-type=FUPool
-children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7
-FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7
-
-[system.cpu.fuPool.FUList0]
-type=FUDesc
-children=opList0
-count=6
-opList=system.cpu.fuPool.FUList0.opList0
-
-[system.cpu.fuPool.FUList0.opList0]
-type=OpDesc
-issueLat=1
-opClass=IntAlu
-opLat=1
-
-[system.cpu.fuPool.FUList1]
-type=FUDesc
-children=opList0 opList1
-count=2
-opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
-
-[system.cpu.fuPool.FUList1.opList0]
-type=OpDesc
-issueLat=1
-opClass=IntMult
-opLat=3
-
-[system.cpu.fuPool.FUList1.opList1]
-type=OpDesc
-issueLat=19
-opClass=IntDiv
-opLat=20
-
-[system.cpu.fuPool.FUList2]
-type=FUDesc
-children=opList0 opList1 opList2
-count=4
-opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
-
-[system.cpu.fuPool.FUList2.opList0]
-type=OpDesc
-issueLat=1
-opClass=FloatAdd
-opLat=2
-
-[system.cpu.fuPool.FUList2.opList1]
-type=OpDesc
-issueLat=1
-opClass=FloatCmp
-opLat=2
-
-[system.cpu.fuPool.FUList2.opList2]
-type=OpDesc
-issueLat=1
-opClass=FloatCvt
-opLat=2
-
-[system.cpu.fuPool.FUList3]
-type=FUDesc
-children=opList0 opList1 opList2
-count=2
-opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
-
-[system.cpu.fuPool.FUList3.opList0]
-type=OpDesc
-issueLat=1
-opClass=FloatMult
-opLat=4
-
-[system.cpu.fuPool.FUList3.opList1]
-type=OpDesc
-issueLat=12
-opClass=FloatDiv
-opLat=12
-
-[system.cpu.fuPool.FUList3.opList2]
-type=OpDesc
-issueLat=24
-opClass=FloatSqrt
-opLat=24
-
-[system.cpu.fuPool.FUList4]
-type=FUDesc
-children=opList0
-count=0
-opList=system.cpu.fuPool.FUList4.opList0
-
-[system.cpu.fuPool.FUList4.opList0]
-type=OpDesc
-issueLat=1
-opClass=MemRead
-opLat=1
-
-[system.cpu.fuPool.FUList5]
-type=FUDesc
-children=opList0
-count=0
-opList=system.cpu.fuPool.FUList5.opList0
-
-[system.cpu.fuPool.FUList5.opList0]
-type=OpDesc
-issueLat=1
-opClass=MemWrite
-opLat=1
-
-[system.cpu.fuPool.FUList6]
-type=FUDesc
-children=opList0 opList1
-count=4
-opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1
-
-[system.cpu.fuPool.FUList6.opList0]
-type=OpDesc
-issueLat=1
-opClass=MemRead
-opLat=1
-
-[system.cpu.fuPool.FUList6.opList1]
-type=OpDesc
-issueLat=1
-opClass=MemWrite
-opLat=1
-
-[system.cpu.fuPool.FUList7]
-type=FUDesc
-children=opList0
-count=1
-opList=system.cpu.fuPool.FUList7.opList0
-
-[system.cpu.fuPool.FUList7.opList0]
-type=OpDesc
-issueLat=3
-opClass=IprAccess
-opLat=3
-
-[system.cpu.icache]
-type=BaseCache
-adaptive_compression=false
-assoc=2
-block_size=64
-compressed_bus=false
-compression_latency=0
-do_copy=false
-hash_delay=1
-hit_latency=1
-latency=1
-lifo=false
-max_miss_count=0
-mshrs=10
-prefetch_access=false
-prefetch_cache_check_push=true
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10
-prefetch_miss=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
-prioritizeRequests=false
-protocol=Null
-repl=Null
-size=131072
-split=false
-split_size=0
-store_compressed=false
-subblock_size=0
-tgts_per_mshr=5
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu.icache_port
-mem_side=system.cpu.toL2Bus.port[0]
-
-[system.cpu.l2cache]
-type=BaseCache
-adaptive_compression=false
-assoc=2
-block_size=64
-compressed_bus=false
-compression_latency=0
-do_copy=false
-hash_delay=1
-hit_latency=1
-latency=1
-lifo=false
-max_miss_count=0
-mshrs=10
-prefetch_access=false
-prefetch_cache_check_push=true
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10
-prefetch_miss=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
-prioritizeRequests=false
-protocol=Null
-repl=Null
-size=2097152
-split=false
-split_size=0
-store_compressed=false
-subblock_size=0
-tgts_per_mshr=5
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[1]
-
-[system.cpu.toL2Bus]
-type=Bus
-bus_id=0
-port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
-
-[system.cpu.workload]
-type=LiveProcess
-cmd=hello
-env=
-executable=tests/test-progs/hello/bin/alpha/linux/hello
-input=cin
-output=cout
-system=system
-
-[system.membus]
-type=Bus
-bus_id=0
-port=system.physmem.port system.cpu.l2cache.mem_side
-
-[system.physmem]
-type=PhysicalMemory
-file=
-latency=1
-range=0:134217727
-port=system.membus.port[0]
-
-[trace]
-bufsize=0
-dump_on_exit=false
-file=cout
-flags=
-ignore=
-start=0
-
diff --git a/tests/long/30.eon/ref/alpha/linux/o3-timing/config.out b/tests/long/30.eon/ref/alpha/linux/o3-timing/config.out
index f491a3081..e69de29bb 100644
--- a/tests/long/30.eon/ref/alpha/linux/o3-timing/config.out
+++ b/tests/long/30.eon/ref/alpha/linux/o3-timing/config.out
@@ -1,403 +0,0 @@
-[root]
-type=Root
-clock=1000000000000
-max_tick=0
-progress_interval=0
-output_file=cout
-
-[system.physmem]
-type=PhysicalMemory
-file=
-range=[0,134217727]
-latency=1
-
-[system]
-type=System
-physmem=system.physmem
-mem_mode=atomic
-
-[system.membus]
-type=Bus
-bus_id=0
-
-[system.cpu.workload]
-type=LiveProcess
-cmd=hello
-executable=tests/test-progs/hello/bin/alpha/linux/hello
-input=cin
-output=cout
-env=
-system=system
-
-[system.cpu.dcache]
-type=BaseCache
-size=262144
-assoc=2
-block_size=64
-latency=1
-mshrs=10
-tgts_per_mshr=5
-write_buffers=8
-prioritizeRequests=false
-do_copy=false
-protocol=null
-trace_addr=0
-hash_delay=1
-repl=null
-compressed_bus=false
-store_compressed=false
-adaptive_compression=false
-compression_latency=0
-block_size=64
-max_miss_count=0
-addr_range=[0,18446744073709551615]
-split=false
-split_size=0
-lifo=false
-two_queue=false
-prefetch_miss=false
-prefetch_access=false
-prefetcher_size=100
-prefetch_past_page=false
-prefetch_serial_squash=false
-prefetch_latency=10
-prefetch_degree=1
-prefetch_policy=none
-prefetch_cache_check_push=true
-prefetch_use_cpu_id=true
-prefetch_data_accesses_only=false
-hit_latency=1
-
-[system.cpu.fuPool.FUList0.opList0]
-type=OpDesc
-opClass=IntAlu
-opLat=1
-issueLat=1
-
-[system.cpu.fuPool.FUList0]
-type=FUDesc
-opList=system.cpu.fuPool.FUList0.opList0
-count=6
-
-[system.cpu.fuPool.FUList1.opList0]
-type=OpDesc
-opClass=IntMult
-opLat=3
-issueLat=1
-
-[system.cpu.fuPool.FUList1.opList1]
-type=OpDesc
-opClass=IntDiv
-opLat=20
-issueLat=19
-
-[system.cpu.fuPool.FUList1]
-type=FUDesc
-opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
-count=2
-
-[system.cpu.fuPool.FUList2.opList0]
-type=OpDesc
-opClass=FloatAdd
-opLat=2
-issueLat=1
-
-[system.cpu.fuPool.FUList2.opList1]
-type=OpDesc
-opClass=FloatCmp
-opLat=2
-issueLat=1
-
-[system.cpu.fuPool.FUList2.opList2]
-type=OpDesc
-opClass=FloatCvt
-opLat=2
-issueLat=1
-
-[system.cpu.fuPool.FUList2]
-type=FUDesc
-opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
-count=4
-
-[system.cpu.fuPool.FUList3.opList0]
-type=OpDesc
-opClass=FloatMult
-opLat=4
-issueLat=1
-
-[system.cpu.fuPool.FUList3.opList1]
-type=OpDesc
-opClass=FloatDiv
-opLat=12
-issueLat=12
-
-[system.cpu.fuPool.FUList3.opList2]
-type=OpDesc
-opClass=FloatSqrt
-opLat=24
-issueLat=24
-
-[system.cpu.fuPool.FUList3]
-type=FUDesc
-opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
-count=2
-
-[system.cpu.fuPool.FUList4.opList0]
-type=OpDesc
-opClass=MemRead
-opLat=1
-issueLat=1
-
-[system.cpu.fuPool.FUList4]
-type=FUDesc
-opList=system.cpu.fuPool.FUList4.opList0
-count=0
-
-[system.cpu.fuPool.FUList5.opList0]
-type=OpDesc
-opClass=MemWrite
-opLat=1
-issueLat=1
-
-[system.cpu.fuPool.FUList5]
-type=FUDesc
-opList=system.cpu.fuPool.FUList5.opList0
-count=0
-
-[system.cpu.fuPool.FUList6.opList0]
-type=OpDesc
-opClass=MemRead
-opLat=1
-issueLat=1
-
-[system.cpu.fuPool.FUList6.opList1]
-type=OpDesc
-opClass=MemWrite
-opLat=1
-issueLat=1
-
-[system.cpu.fuPool.FUList6]
-type=FUDesc
-opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1
-count=4
-
-[system.cpu.fuPool.FUList7.opList0]
-type=OpDesc
-opClass=IprAccess
-opLat=3
-issueLat=3
-
-[system.cpu.fuPool.FUList7]
-type=FUDesc
-opList=system.cpu.fuPool.FUList7.opList0
-count=1
-
-[system.cpu.fuPool]
-type=FUPool
-FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7
-
-[system.cpu]
-type=DerivO3CPU
-clock=1
-numThreads=1
-activity=0
-workload=system.cpu.workload
-mem=system.cpu.dcache
-checker=null
-max_insts_any_thread=0
-max_insts_all_threads=0
-max_loads_any_thread=0
-max_loads_all_threads=0
-cachePorts=200
-decodeToFetchDelay=1
-renameToFetchDelay=1
-iewToFetchDelay=1
-commitToFetchDelay=1
-fetchWidth=8
-renameToDecodeDelay=1
-iewToDecodeDelay=1
-commitToDecodeDelay=1
-fetchToDecodeDelay=1
-decodeWidth=8
-iewToRenameDelay=1
-commitToRenameDelay=1
-decodeToRenameDelay=1
-renameWidth=8
-commitToIEWDelay=1
-renameToIEWDelay=2
-issueToExecuteDelay=1
-dispatchWidth=8
-issueWidth=8
-wbWidth=8
-wbDepth=1
-fuPool=system.cpu.fuPool
-iewToCommitDelay=1
-renameToROBDelay=1
-commitWidth=8
-squashWidth=8
-trapLatency=13
-backComSize=5
-forwardComSize=5
-predType=tournament
-localPredictorSize=2048
-localCtrBits=2
-localHistoryTableSize=2048
-localHistoryBits=11
-globalPredictorSize=8192
-globalCtrBits=2
-globalHistoryBits=13
-choicePredictorSize=8192
-choiceCtrBits=2
-BTBEntries=4096
-BTBTagSize=16
-RASSize=16
-LQEntries=32
-SQEntries=32
-LFSTSize=1024
-SSITSize=1024
-numPhysIntRegs=256
-numPhysFloatRegs=256
-numIQEntries=64
-numROBEntries=192
-smtNumFetchingThreads=1
-smtFetchPolicy=SingleThread
-smtLSQPolicy=Partitioned
-smtLSQThreshold=100
-smtIQPolicy=Partitioned
-smtIQThreshold=100
-smtROBPolicy=Partitioned
-smtROBThreshold=100
-smtCommitPolicy=RoundRobin
-instShiftAmt=2
-defer_registration=false
-function_trace=false
-function_trace_start=0
-
-[system.cpu.icache]
-type=BaseCache
-size=131072
-assoc=2
-block_size=64
-latency=1
-mshrs=10
-tgts_per_mshr=5
-write_buffers=8
-prioritizeRequests=false
-do_copy=false
-protocol=null
-trace_addr=0
-hash_delay=1
-repl=null
-compressed_bus=false
-store_compressed=false
-adaptive_compression=false
-compression_latency=0
-block_size=64
-max_miss_count=0
-addr_range=[0,18446744073709551615]
-split=false
-split_size=0
-lifo=false
-two_queue=false
-prefetch_miss=false
-prefetch_access=false
-prefetcher_size=100
-prefetch_past_page=false
-prefetch_serial_squash=false
-prefetch_latency=10
-prefetch_degree=1
-prefetch_policy=none
-prefetch_cache_check_push=true
-prefetch_use_cpu_id=true
-prefetch_data_accesses_only=false
-hit_latency=1
-
-[system.cpu.l2cache]
-type=BaseCache
-size=2097152
-assoc=2
-block_size=64
-latency=1
-mshrs=10
-tgts_per_mshr=5
-write_buffers=8
-prioritizeRequests=false
-do_copy=false
-protocol=null
-trace_addr=0
-hash_delay=1
-repl=null
-compressed_bus=false
-store_compressed=false
-adaptive_compression=false
-compression_latency=0
-block_size=64
-max_miss_count=0
-addr_range=[0,18446744073709551615]
-split=false
-split_size=0
-lifo=false
-two_queue=false
-prefetch_miss=false
-prefetch_access=false
-prefetcher_size=100
-prefetch_past_page=false
-prefetch_serial_squash=false
-prefetch_latency=10
-prefetch_degree=1
-prefetch_policy=none
-prefetch_cache_check_push=true
-prefetch_use_cpu_id=true
-prefetch_data_accesses_only=false
-hit_latency=1
-
-[system.cpu.toL2Bus]
-type=Bus
-bus_id=0
-
-[trace]
-flags=
-start=0
-bufsize=0
-file=cout
-dump_on_exit=false
-ignore=
-
-[stats]
-descriptions=true
-project_name=test
-simulation_name=test
-simulation_sample=0
-text_file=m5stats.txt
-text_compat=true
-mysql_db=
-mysql_user=
-mysql_password=
-mysql_host=
-events_start=-1
-dump_reset=false
-dump_cycle=0
-dump_period=0
-ignore_events=
-
-[random]
-seed=1
-
-[exetrace]
-speculative=true
-print_cycle=true
-print_opclass=true
-print_thread=true
-print_effaddr=true
-print_data=true
-print_iregs=false
-print_fetchseq=false
-print_cpseq=false
-print_reg_delta=false
-pc_symbol=true
-intel_format=false
-trace_system=client
-
-[debug]
-break_cycles=
-
diff --git a/tests/long/30.eon/ref/alpha/linux/o3-timing/m5stats.txt b/tests/long/30.eon/ref/alpha/linux/o3-timing/m5stats.txt
index 5d4f9235a..e69de29bb 100644
--- a/tests/long/30.eon/ref/alpha/linux/o3-timing/m5stats.txt
+++ b/tests/long/30.eon/ref/alpha/linux/o3-timing/m5stats.txt
@@ -1,1974 +0,0 @@
-
----------- Begin Simulation Statistics ----------
-global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-global.BPredUnit.BTBHits 542 # Number of BTB hits
-global.BPredUnit.BTBLookups 1938 # Number of BTB lookups
-global.BPredUnit.RASInCorrect 48 # Number of incorrect RAS predictions.
-global.BPredUnit.condIncorrect 420 # Number of conditional branches incorrect
-global.BPredUnit.condPredicted 1304 # Number of conditional branches predicted
-global.BPredUnit.lookups 2256 # Number of BP lookups
-global.BPredUnit.usedRAS 291 # Number of times the RAS was used to get a target.
-host_inst_rate 41797 # Simulator instruction rate (inst/s)
-host_mem_usage 160344 # Number of bytes of host memory used
-host_seconds 0.13 # Real time elapsed on the host
-host_tick_rate 50948 # Simulator tick rate (ticks/s)
-memdepunit.memDep.conflictingLoads 12 # Number of conflicting loads.
-memdepunit.memDep.conflictingStores 259 # Number of conflicting stores.
-memdepunit.memDep.insertedLoads 2050 # Number of loads inserted to the mem dependence unit.
-memdepunit.memDep.insertedStores 1221 # Number of stores inserted to the mem dependence unit.
-sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 5623 # Number of instructions simulated
-sim_seconds 0.000000 # Number of seconds simulated
-sim_ticks 6870 # Number of ticks simulated
-system.cpu.commit.COM:branches 862 # Number of branches committed
-system.cpu.commit.COM:bw_lim_events 74 # number cycles where commit BW limit reached
-system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle.samples 6116
-system.cpu.commit.COM:committed_per_cycle.min_value 0
- 0 3908 6389.80%
- 1 1064 1739.70%
- 2 389 636.04%
- 3 210 343.36%
- 4 153 250.16%
- 5 93 152.06%
- 6 76 124.26%
- 7 149 243.62%
- 8 74 120.99%
-system.cpu.commit.COM:committed_per_cycle.max_value 8
-system.cpu.commit.COM:committed_per_cycle.end_dist
-
-system.cpu.commit.COM:count 5640 # Number of instructions committed
-system.cpu.commit.COM:loads 979 # Number of loads committed
-system.cpu.commit.COM:membars 0 # Number of memory barriers committed
-system.cpu.commit.COM:refs 1791 # Number of memory references committed
-system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.branchMispredicts 337 # The number of times a branch was mispredicted
-system.cpu.commit.commitCommittedInsts 5640 # The number of committed instructions
-system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.commitSquashedInsts 4350 # The number of squashed insts skipped by commit
-system.cpu.committedInsts 5623 # Number of Instructions Simulated
-system.cpu.committedInsts_total 5623 # Number of Instructions Simulated
-system.cpu.cpi 1.221768 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 1.221768 # CPI: Total CPI of All Threads
-system.cpu.dcache.ReadReq_accesses 1538 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 3.072000 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2.240000 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits 1413 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 384 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate 0.081274 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses 125 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_hits 25 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_miss_latency 224 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate 0.065020 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses 100 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_accesses 821 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 2.467742 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2.140845 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 635 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 459 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.226553 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 186 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_hits 108 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_miss_latency 152 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.086480 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 71 # number of WriteReq MSHR misses
-system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles_no_targets 0.800000 # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 11.505618 # Average number of references to valid blocks.
-system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_no_targets 5 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles_no_targets 4 # number of cycles access was blocked
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.demand_accesses 2359 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 2.710611 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 2.198830 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 2048 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 843 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.131836 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 311 # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits 133 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 376 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate 0.072488 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 171 # number of demand (read+write) MSHR misses
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.overall_accesses 2359 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 2.710611 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 2.198830 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 2048 # number of overall hits
-system.cpu.dcache.overall_miss_latency 843 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.131836 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 311 # number of overall misses
-system.cpu.dcache.overall_mshr_hits 133 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 376 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate 0.072488 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 171 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.dcache.replacements 0 # number of replacements
-system.cpu.dcache.sampled_refs 178 # Sample count of references to valid blocks.
-system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 119.831029 # Cycle average of tags in use
-system.cpu.dcache.total_refs 2048 # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks 0 # number of writebacks
-system.cpu.decode.DECODE:BlockedCycles 387 # Number of cycles decode is blocked
-system.cpu.decode.DECODE:BranchMispred 93 # Number of times decode detected a branch misprediction
-system.cpu.decode.DECODE:BranchResolved 185 # Number of times decode resolved a branch
-system.cpu.decode.DECODE:DecodedInsts 12349 # Number of instructions handled by decode
-system.cpu.decode.DECODE:IdleCycles 3542 # Number of cycles decode is idle
-system.cpu.decode.DECODE:RunCycles 2158 # Number of cycles decode is running
-system.cpu.decode.DECODE:SquashCycles 754 # Number of cycles decode is squashing
-system.cpu.decode.DECODE:SquashedInsts 286 # Number of squashed instructions handled by decode
-system.cpu.decode.DECODE:UnblockCycles 30 # Number of cycles decode is unblocking
-system.cpu.fetch.Branches 2256 # Number of branches that fetch encountered
-system.cpu.fetch.CacheLines 1582 # Number of cache lines fetched
-system.cpu.fetch.Cycles 3905 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.IcacheSquashes 148 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.Insts 13707 # Number of instructions fetch has processed
-system.cpu.fetch.SquashCycles 456 # Number of cycles fetch has spent squashing
-system.cpu.fetch.branchRate 0.328336 # Number of branch fetches per cycle
-system.cpu.fetch.icacheStallCycles 1582 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.predictedBranches 833 # Number of branches that fetch has predicted taken
-system.cpu.fetch.rate 1.994906 # Number of inst fetches per cycle
-system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist.samples 6871
-system.cpu.fetch.rateDist.min_value 0
- 0 4549 6620.58%
- 1 174 253.24%
- 2 186 270.70%
- 3 157 228.50%
- 4 211 307.09%
- 5 153 222.68%
- 6 171 248.87%
- 7 105 152.82%
- 8 1165 1695.53%
-system.cpu.fetch.rateDist.max_value 8
-system.cpu.fetch.rateDist.end_dist
-
-system.cpu.icache.ReadReq_accesses 1582 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 2.960245 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 1.996885 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits 1255 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 968 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate 0.206700 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses 327 # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_hits 6 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_miss_latency 641 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.202908 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses 321 # number of ReadReq MSHR misses
-system.cpu.icache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles_no_targets no value # average number of cycles each access was blocked
-system.cpu.icache.avg_refs 3.909657 # Average number of references to valid blocks.
-system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.demand_accesses 1582 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 2.960245 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 1.996885 # average overall mshr miss latency
-system.cpu.icache.demand_hits 1255 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 968 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate 0.206700 # miss rate for demand accesses
-system.cpu.icache.demand_misses 327 # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_hits 6 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 641 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate 0.202908 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses 321 # number of demand (read+write) MSHR misses
-system.cpu.icache.fast_writes 0 # number of fast writes performed
-system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.overall_accesses 1582 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 2.960245 # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 1.996885 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits 1255 # number of overall hits
-system.cpu.icache.overall_miss_latency 968 # number of overall miss cycles
-system.cpu.icache.overall_miss_rate 0.206700 # miss rate for overall accesses
-system.cpu.icache.overall_misses 327 # number of overall misses
-system.cpu.icache.overall_mshr_hits 6 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 641 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate 0.202908 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses 321 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.icache.replacements 0 # number of replacements
-system.cpu.icache.sampled_refs 321 # Sample count of references to valid blocks.
-system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 176.393247 # Cycle average of tags in use
-system.cpu.icache.total_refs 1255 # Total number of references to valid blocks.
-system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.iew.EXEC:branches 1206 # Number of branches executed
-system.cpu.iew.EXEC:insts 7969 # Number of executed instructions
-system.cpu.iew.EXEC:loads 1610 # Number of load instructions executed
-system.cpu.iew.EXEC:nop 37 # number of nop insts executed
-system.cpu.iew.EXEC:rate 1.159802 # Inst execution rate
-system.cpu.iew.EXEC:refs 2599 # number of memory reference insts executed
-system.cpu.iew.EXEC:squashedInsts 419 # Number of squashed instructions skipped in execute
-system.cpu.iew.EXEC:stores 989 # Number of stores executed
-system.cpu.iew.EXEC:swp 0 # number of swp insts executed
-system.cpu.iew.WB:consumers 5438 # num instructions consuming a value
-system.cpu.iew.WB:count 7722 # cumulative count of insts written-back
-system.cpu.iew.WB:fanout 0.744575 # average fanout of values written-back
-system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.iew.WB:producers 4049 # num instructions producing a value
-system.cpu.iew.WB:rate 1.123854 # insts written-back per cycle
-system.cpu.iew.WB:sent 7762 # cumulative count of insts sent to commit
-system.cpu.iew.branchMispredicts 393 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewBlockCycles 4 # Number of cycles IEW is blocking
-system.cpu.iew.iewDispLoadInsts 2050 # Number of dispatched load instructions
-system.cpu.iew.iewDispNonSpecInsts 21 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewDispSquashedInsts 272 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispStoreInsts 1221 # Number of dispatched store instructions
-system.cpu.iew.iewDispatchedInsts 9990 # Number of instructions dispatched to IQ
-system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.iewSquashCycles 754 # Number of cycles IEW is squashing
-system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking
-system.cpu.iew.lsq.thread.0.blockedLoads 1 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread.0.cacheBlocked 5 # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.lsq.thread.0.forwLoads 55 # Number of loads that had data forwarded from stores
-system.cpu.iew.lsq.thread.0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
-system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread.0.squashedLoads 1071 # Number of loads squashed
-system.cpu.iew.lsq.thread.0.squashedStores 409 # Number of stores squashed
-system.cpu.iew.memOrderViolationEvents 41 # Number of memory order violations
-system.cpu.iew.predictedNotTakenIncorrect 296 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.predictedTakenIncorrect 97 # Number of branches that were predicted taken incorrectly
-system.cpu.ipc 0.818486 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.818486 # IPC: Total IPC of All Threads
-system.cpu.iq.IQ:residence:(null).start_dist # cycles from dispatch to issue
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-system.cpu.iq.IQ:residence:(null).end_dist
-
-system.cpu.iq.IQ:residence:IntAlu.start_dist # cycles from dispatch to issue
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-system.cpu.iq.IQ:residence:IntAlu.min_value 0
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-system.cpu.iq.IQ:residence:IntAlu.end_dist
-
-system.cpu.iq.IQ:residence:IntMult.start_dist # cycles from dispatch to issue
-system.cpu.iq.IQ:residence:IntMult.samples 0
-system.cpu.iq.IQ:residence:IntMult.min_value 0
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-system.cpu.iq.IQ:residence:IntMult.end_dist
-
-system.cpu.iq.IQ:residence:IntDiv.start_dist # cycles from dispatch to issue
-system.cpu.iq.IQ:residence:IntDiv.samples 0
-system.cpu.iq.IQ:residence:IntDiv.min_value 0
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-system.cpu.iq.IQ:residence:IntDiv.end_dist
-
-system.cpu.iq.IQ:residence:FloatAdd.start_dist # cycles from dispatch to issue
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-system.cpu.iq.IQ:residence:FloatAdd.end_dist
-
-system.cpu.iq.IQ:residence:FloatCmp.start_dist # cycles from dispatch to issue
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-system.cpu.iq.IQ:residence:FloatCmp.min_value 0
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-
-system.cpu.iq.IQ:residence:FloatCvt.start_dist # cycles from dispatch to issue
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-system.cpu.iq.IQ:residence:FloatCvt.min_value 0
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-system.cpu.iq.IQ:residence:FloatCvt.end_dist
-
-system.cpu.iq.IQ:residence:FloatMult.start_dist # cycles from dispatch to issue
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-system.cpu.iq.IQ:residence:FloatMult.min_value 0
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-system.cpu.iq.IQ:residence:FloatMult.end_dist
-
-system.cpu.iq.IQ:residence:FloatDiv.start_dist # cycles from dispatch to issue
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-system.cpu.iq.IQ:residence:FloatDiv.min_value 0
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-system.cpu.iq.IQ:residence:FloatDiv.end_dist
-
-system.cpu.iq.IQ:residence:FloatSqrt.start_dist # cycles from dispatch to issue
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-system.cpu.iq.IQ:residence:FloatSqrt.min_value 0
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-system.cpu.iq.IQ:residence:FloatSqrt.end_dist
-
-system.cpu.iq.IQ:residence:MemRead.start_dist # cycles from dispatch to issue
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-system.cpu.iq.IQ:residence:MemRead.min_value 0
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-system.cpu.iq.IQ:residence:MemRead.end_dist
-
-system.cpu.iq.IQ:residence:MemWrite.start_dist # cycles from dispatch to issue
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-system.cpu.iq.IQ:residence:MemWrite.min_value 0
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-system.cpu.iq.IQ:residence:MemWrite.end_dist
-
-system.cpu.iq.IQ:residence:IprAccess.start_dist # cycles from dispatch to issue
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-system.cpu.iq.IQ:residence:IprAccess.min_value 0
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-system.cpu.iq.IQ:residence:IprAccess.end_dist
-
-system.cpu.iq.IQ:residence:InstPrefetch.start_dist # cycles from dispatch to issue
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-system.cpu.iq.IQ:residence:InstPrefetch.min_value 0
- 0 0
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-
-system.cpu.iq.ISSUE:(null)_delay.start_dist # cycles from operands ready to issue
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-system.cpu.iq.ISSUE:(null)_delay.min_value 0
- 0 0
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-system.cpu.iq.ISSUE:(null)_delay.end_dist
-
-system.cpu.iq.ISSUE:IntAlu_delay.start_dist # cycles from operands ready to issue
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-system.cpu.iq.ISSUE:IntAlu_delay.min_value 0
- 0 0
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-system.cpu.iq.ISSUE:IntAlu_delay.end_dist
-
-system.cpu.iq.ISSUE:IntMult_delay.start_dist # cycles from operands ready to issue
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-system.cpu.iq.ISSUE:IntMult_delay.min_value 0
- 0 0
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-system.cpu.iq.ISSUE:IntMult_delay.end_dist
-
-system.cpu.iq.ISSUE:IntDiv_delay.start_dist # cycles from operands ready to issue
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-system.cpu.iq.ISSUE:IntDiv_delay.min_value 0
- 0 0
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-system.cpu.iq.ISSUE:IntDiv_delay.end_dist
-
-system.cpu.iq.ISSUE:FloatAdd_delay.start_dist # cycles from operands ready to issue
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-system.cpu.iq.ISSUE:FloatAdd_delay.min_value 0
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-system.cpu.iq.ISSUE:FloatAdd_delay.end_dist
-
-system.cpu.iq.ISSUE:FloatCmp_delay.start_dist # cycles from operands ready to issue
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-system.cpu.iq.ISSUE:FloatCmp_delay.min_value 0
- 0 0
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-system.cpu.iq.ISSUE:FloatCmp_delay.end_dist
-
-system.cpu.iq.ISSUE:FloatCvt_delay.start_dist # cycles from operands ready to issue
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-system.cpu.iq.ISSUE:FloatCvt_delay.min_value 0
- 0 0
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- 96 0
- 98 0
-system.cpu.iq.ISSUE:FloatCvt_delay.max_value 0
-system.cpu.iq.ISSUE:FloatCvt_delay.end_dist
-
-system.cpu.iq.ISSUE:FloatMult_delay.start_dist # cycles from operands ready to issue
-system.cpu.iq.ISSUE:FloatMult_delay.samples 0
-system.cpu.iq.ISSUE:FloatMult_delay.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
- 20 0
- 22 0
- 24 0
- 26 0
- 28 0
- 30 0
- 32 0
- 34 0
- 36 0
- 38 0
- 40 0
- 42 0
- 44 0
- 46 0
- 48 0
- 50 0
- 52 0
- 54 0
- 56 0
- 58 0
- 60 0
- 62 0
- 64 0
- 66 0
- 68 0
- 70 0
- 72 0
- 74 0
- 76 0
- 78 0
- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.ISSUE:FloatMult_delay.max_value 0
-system.cpu.iq.ISSUE:FloatMult_delay.end_dist
-
-system.cpu.iq.ISSUE:FloatDiv_delay.start_dist # cycles from operands ready to issue
-system.cpu.iq.ISSUE:FloatDiv_delay.samples 0
-system.cpu.iq.ISSUE:FloatDiv_delay.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
- 20 0
- 22 0
- 24 0
- 26 0
- 28 0
- 30 0
- 32 0
- 34 0
- 36 0
- 38 0
- 40 0
- 42 0
- 44 0
- 46 0
- 48 0
- 50 0
- 52 0
- 54 0
- 56 0
- 58 0
- 60 0
- 62 0
- 64 0
- 66 0
- 68 0
- 70 0
- 72 0
- 74 0
- 76 0
- 78 0
- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.ISSUE:FloatDiv_delay.max_value 0
-system.cpu.iq.ISSUE:FloatDiv_delay.end_dist
-
-system.cpu.iq.ISSUE:FloatSqrt_delay.start_dist # cycles from operands ready to issue
-system.cpu.iq.ISSUE:FloatSqrt_delay.samples 0
-system.cpu.iq.ISSUE:FloatSqrt_delay.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
- 20 0
- 22 0
- 24 0
- 26 0
- 28 0
- 30 0
- 32 0
- 34 0
- 36 0
- 38 0
- 40 0
- 42 0
- 44 0
- 46 0
- 48 0
- 50 0
- 52 0
- 54 0
- 56 0
- 58 0
- 60 0
- 62 0
- 64 0
- 66 0
- 68 0
- 70 0
- 72 0
- 74 0
- 76 0
- 78 0
- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.ISSUE:FloatSqrt_delay.max_value 0
-system.cpu.iq.ISSUE:FloatSqrt_delay.end_dist
-
-system.cpu.iq.ISSUE:MemRead_delay.start_dist # cycles from operands ready to issue
-system.cpu.iq.ISSUE:MemRead_delay.samples 0
-system.cpu.iq.ISSUE:MemRead_delay.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
- 20 0
- 22 0
- 24 0
- 26 0
- 28 0
- 30 0
- 32 0
- 34 0
- 36 0
- 38 0
- 40 0
- 42 0
- 44 0
- 46 0
- 48 0
- 50 0
- 52 0
- 54 0
- 56 0
- 58 0
- 60 0
- 62 0
- 64 0
- 66 0
- 68 0
- 70 0
- 72 0
- 74 0
- 76 0
- 78 0
- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.ISSUE:MemRead_delay.max_value 0
-system.cpu.iq.ISSUE:MemRead_delay.end_dist
-
-system.cpu.iq.ISSUE:MemWrite_delay.start_dist # cycles from operands ready to issue
-system.cpu.iq.ISSUE:MemWrite_delay.samples 0
-system.cpu.iq.ISSUE:MemWrite_delay.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
- 20 0
- 22 0
- 24 0
- 26 0
- 28 0
- 30 0
- 32 0
- 34 0
- 36 0
- 38 0
- 40 0
- 42 0
- 44 0
- 46 0
- 48 0
- 50 0
- 52 0
- 54 0
- 56 0
- 58 0
- 60 0
- 62 0
- 64 0
- 66 0
- 68 0
- 70 0
- 72 0
- 74 0
- 76 0
- 78 0
- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.ISSUE:MemWrite_delay.max_value 0
-system.cpu.iq.ISSUE:MemWrite_delay.end_dist
-
-system.cpu.iq.ISSUE:IprAccess_delay.start_dist # cycles from operands ready to issue
-system.cpu.iq.ISSUE:IprAccess_delay.samples 0
-system.cpu.iq.ISSUE:IprAccess_delay.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
- 20 0
- 22 0
- 24 0
- 26 0
- 28 0
- 30 0
- 32 0
- 34 0
- 36 0
- 38 0
- 40 0
- 42 0
- 44 0
- 46 0
- 48 0
- 50 0
- 52 0
- 54 0
- 56 0
- 58 0
- 60 0
- 62 0
- 64 0
- 66 0
- 68 0
- 70 0
- 72 0
- 74 0
- 76 0
- 78 0
- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.ISSUE:IprAccess_delay.max_value 0
-system.cpu.iq.ISSUE:IprAccess_delay.end_dist
-
-system.cpu.iq.ISSUE:InstPrefetch_delay.start_dist # cycles from operands ready to issue
-system.cpu.iq.ISSUE:InstPrefetch_delay.samples 0
-system.cpu.iq.ISSUE:InstPrefetch_delay.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
- 20 0
- 22 0
- 24 0
- 26 0
- 28 0
- 30 0
- 32 0
- 34 0
- 36 0
- 38 0
- 40 0
- 42 0
- 44 0
- 46 0
- 48 0
- 50 0
- 52 0
- 54 0
- 56 0
- 58 0
- 60 0
- 62 0
- 64 0
- 66 0
- 68 0
- 70 0
- 72 0
- 74 0
- 76 0
- 78 0
- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.ISSUE:InstPrefetch_delay.max_value 0
-system.cpu.iq.ISSUE:InstPrefetch_delay.end_dist
-
-system.cpu.iq.ISSUE:FU_type_0 8388 # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0.start_dist
- (null) 2 0.02% # Type of FU issued
- IntAlu 5594 66.69% # Type of FU issued
- IntMult 1 0.01% # Type of FU issued
- IntDiv 0 0.00% # Type of FU issued
- FloatAdd 2 0.02% # Type of FU issued
- FloatCmp 0 0.00% # Type of FU issued
- FloatCvt 0 0.00% # Type of FU issued
- FloatMult 0 0.00% # Type of FU issued
- FloatDiv 0 0.00% # Type of FU issued
- FloatSqrt 0 0.00% # Type of FU issued
- MemRead 1757 20.95% # Type of FU issued
- MemWrite 1032 12.30% # Type of FU issued
- IprAccess 0 0.00% # Type of FU issued
- InstPrefetch 0 0.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0.end_dist
-system.cpu.iq.ISSUE:fu_busy_cnt 115 # FU busy when requested
-system.cpu.iq.ISSUE:fu_busy_rate 0.013710 # FU busy rate (busy events/executed inst)
-system.cpu.iq.ISSUE:fu_full.start_dist
- (null) 0 0.00% # attempts to use FU when none available
- IntAlu 1 0.87% # attempts to use FU when none available
- IntMult 0 0.00% # attempts to use FU when none available
- IntDiv 0 0.00% # attempts to use FU when none available
- FloatAdd 0 0.00% # attempts to use FU when none available
- FloatCmp 0 0.00% # attempts to use FU when none available
- FloatCvt 0 0.00% # attempts to use FU when none available
- FloatMult 0 0.00% # attempts to use FU when none available
- FloatDiv 0 0.00% # attempts to use FU when none available
- FloatSqrt 0 0.00% # attempts to use FU when none available
- MemRead 76 66.09% # attempts to use FU when none available
- MemWrite 38 33.04% # attempts to use FU when none available
- IprAccess 0 0.00% # attempts to use FU when none available
- InstPrefetch 0 0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full.end_dist
-system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle.samples 6871
-system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
- 0 3753 5462.09%
- 1 894 1301.12%
- 2 723 1052.25%
- 3 614 893.61%
- 4 451 656.38%
- 5 279 406.05%
- 6 104 151.36%
- 7 41 59.67%
- 8 12 17.46%
-system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
-system.cpu.iq.ISSUE:issued_per_cycle.end_dist
-
-system.cpu.iq.ISSUE:rate 1.220783 # Inst issue rate
-system.cpu.iq.iqInstsAdded 9932 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqInstsIssued 8388 # Number of instructions issued
-system.cpu.iq.iqNonSpecInstsAdded 21 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqSquashedInstsExamined 3990 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedInstsIssued 21 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedNonSpecRemoved 4 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.iqSquashedOperandsExamined 2486 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.l2cache.ReadReq_accesses 499 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 2.042254 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency 1015 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate 0.995992 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses 497 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 490 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.981964 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses 490 # number of ReadReq MSHR misses
-system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs 0.004024 # Average number of references to valid blocks.
-system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.demand_accesses 499 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 2.042254 # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 1 # average overall mshr miss latency
-system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 1015 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate 0.995992 # miss rate for demand accesses
-system.cpu.l2cache.demand_misses 497 # number of demand (read+write) misses
-system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency 490 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate 0.981964 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses 490 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.fast_writes 0 # number of fast writes performed
-system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.overall_accesses 499 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 2.042254 # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 1 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits 2 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 1015 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate 0.995992 # miss rate for overall accesses
-system.cpu.l2cache.overall_misses 497 # number of overall misses
-system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 490 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate 0.981964 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses 490 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.l2cache.replacements 0 # number of replacements
-system.cpu.l2cache.sampled_refs 497 # Sample count of references to valid blocks.
-system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 295.773395 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks 0 # number of writebacks
-system.cpu.numCycles 6871 # number of cpu cycles simulated
-system.cpu.rename.RENAME:BlockCycles 4 # Number of cycles rename is blocking
-system.cpu.rename.RENAME:CommittedMaps 4051 # Number of HB maps that are committed
-system.cpu.rename.RENAME:IdleCycles 3758 # Number of cycles rename is idle
-system.cpu.rename.RENAME:LSQFullEvents 62 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RENAME:RenameLookups 14786 # Number of register rename lookups that rename has made
-system.cpu.rename.RENAME:RenamedInsts 11555 # Number of instructions processed by rename
-system.cpu.rename.RENAME:RenamedOperands 8634 # Number of destination operands rename has renamed
-system.cpu.rename.RENAME:RunCycles 1975 # Number of cycles rename is running
-system.cpu.rename.RENAME:SquashCycles 754 # Number of cycles rename is squashing
-system.cpu.rename.RENAME:UnblockCycles 111 # Number of cycles rename is unblocking
-system.cpu.rename.RENAME:UndoneMaps 4583 # Number of HB maps that are undone due to squashing
-system.cpu.rename.RENAME:serializeStallCycles 269 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RENAME:serializingInsts 26 # count of serializing insts renamed
-system.cpu.rename.RENAME:skidInsts 408 # count of insts added to the skid buffer
-system.cpu.rename.RENAME:tempSerializingInsts 21 # count of temporary serializing insts renamed
-system.cpu.workload.PROG:num_syscalls 17 # Number of system calls
-
----------- End Simulation Statistics ----------
diff --git a/tests/long/30.eon/ref/alpha/linux/o3-timing/stderr b/tests/long/30.eon/ref/alpha/linux/o3-timing/stderr
index 8893caac8..e69de29bb 100644
--- a/tests/long/30.eon/ref/alpha/linux/o3-timing/stderr
+++ b/tests/long/30.eon/ref/alpha/linux/o3-timing/stderr
@@ -1,3 +0,0 @@
-warn: Entering event queue @ 0. Starting simulation...
-warn: cycle 0: fault (page_table_fault) detected @ PC 0x000000
-warn: Increasing stack 0x11ff92000:0x11ff9b000 to 0x11ff90000:0x11ff9b000 because of access to 0x11ff91ff0
diff --git a/tests/long/30.eon/ref/alpha/linux/o3-timing/stdout b/tests/long/30.eon/ref/alpha/linux/o3-timing/stdout
index fbb329a2f..e69de29bb 100644
--- a/tests/long/30.eon/ref/alpha/linux/o3-timing/stdout
+++ b/tests/long/30.eon/ref/alpha/linux/o3-timing/stdout
@@ -1,13 +0,0 @@
-Hello world!
-M5 Simulator System
-
-Copyright (c) 2001-2006
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Sep 5 2006 15:28:48
-M5 started Tue Sep 5 15:42:12 2006
-M5 executing on zizzer.eecs.umich.edu
-command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/o3-timing tests/run.py quick/00.hello/alpha/linux/o3-timing
-Exiting @ tick 6870 because target called exit()
diff --git a/tests/long/30.eon/ref/alpha/linux/simple-atomic/config.ini b/tests/long/30.eon/ref/alpha/linux/simple-atomic/config.ini
index c3a59fbce..088cd1a9f 100644
--- a/tests/long/30.eon/ref/alpha/linux/simple-atomic/config.ini
+++ b/tests/long/30.eon/ref/alpha/linux/simple-atomic/config.ini
@@ -7,11 +7,9 @@ max_tick=0
output_file=cout
progress_interval=0
-[debug]
-break_cycles=
-
[exetrace]
intel_format=false
+legion_lockstep=false
pc_symbol=true
print_cpseq=false
print_cycle=true
@@ -53,352 +51,49 @@ mem_mode=atomic
physmem=system.physmem
[system.cpu]
-type=DerivO3CPU
-children=dcache fuPool icache l2cache toL2Bus workload
-BTBEntries=4096
-BTBTagSize=16
-LFSTSize=1024
-LQEntries=32
-RASSize=16
-SQEntries=32
-SSITSize=1024
-activity=0
-backComSize=5
-choiceCtrBits=2
-choicePredictorSize=8192
+type=AtomicSimpleCPU
+children=workload
clock=1
-commitToDecodeDelay=1
-commitToFetchDelay=1
-commitToIEWDelay=1
-commitToRenameDelay=1
-commitWidth=8
-decodeToFetchDelay=1
-decodeToRenameDelay=1
-decodeWidth=8
+cpu_id=0
defer_registration=false
-dispatchWidth=8
-fetchToDecodeDelay=1
-fetchTrapLatency=1
-fetchWidth=8
-forwardComSize=5
-fuPool=system.cpu.fuPool
function_trace=false
function_trace_start=0
-globalCtrBits=2
-globalHistoryBits=13
-globalPredictorSize=8192
-iewToCommitDelay=1
-iewToDecodeDelay=1
-iewToFetchDelay=1
-iewToRenameDelay=1
-instShiftAmt=2
-issueToExecuteDelay=1
-issueWidth=8
-localCtrBits=2
-localHistoryBits=11
-localHistoryTableSize=2048
-localPredictorSize=2048
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
-mem=system.cpu.dcache
-numIQEntries=64
-numPhysFloatRegs=256
-numPhysIntRegs=256
-numROBEntries=192
-numRobs=1
-numThreads=1
-predType=tournament
-renameToDecodeDelay=1
-renameToFetchDelay=1
-renameToIEWDelay=2
-renameToROBDelay=1
-renameWidth=8
-squashWidth=8
+phase=0
+progress_interval=0
+simulate_stalls=false
system=system
-trapLatency=13
-wbDepth=1
-wbWidth=8
+width=1
workload=system.cpu.workload
-dcache_port=system.cpu.dcache.cpu_side
-icache_port=system.cpu.icache.cpu_side
-
-[system.cpu.dcache]
-type=BaseCache
-adaptive_compression=false
-assoc=2
-block_size=64
-compressed_bus=false
-compression_latency=0
-do_copy=false
-hash_delay=1
-hit_latency=1
-latency=1
-lifo=false
-max_miss_count=0
-mshrs=10
-prefetch_access=false
-prefetch_cache_check_push=true
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10
-prefetch_miss=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
-prioritizeRequests=false
-protocol=Null
-repl=Null
-size=262144
-split=false
-split_size=0
-store_compressed=false
-subblock_size=0
-tgts_per_mshr=5
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu.dcache_port
-mem_side=system.cpu.toL2Bus.port[1]
-
-[system.cpu.fuPool]
-type=FUPool
-children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7
-FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7
-
-[system.cpu.fuPool.FUList0]
-type=FUDesc
-children=opList0
-count=6
-opList=system.cpu.fuPool.FUList0.opList0
-
-[system.cpu.fuPool.FUList0.opList0]
-type=OpDesc
-issueLat=1
-opClass=IntAlu
-opLat=1
-
-[system.cpu.fuPool.FUList1]
-type=FUDesc
-children=opList0 opList1
-count=2
-opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
-
-[system.cpu.fuPool.FUList1.opList0]
-type=OpDesc
-issueLat=1
-opClass=IntMult
-opLat=3
-
-[system.cpu.fuPool.FUList1.opList1]
-type=OpDesc
-issueLat=19
-opClass=IntDiv
-opLat=20
-
-[system.cpu.fuPool.FUList2]
-type=FUDesc
-children=opList0 opList1 opList2
-count=4
-opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
-
-[system.cpu.fuPool.FUList2.opList0]
-type=OpDesc
-issueLat=1
-opClass=FloatAdd
-opLat=2
-
-[system.cpu.fuPool.FUList2.opList1]
-type=OpDesc
-issueLat=1
-opClass=FloatCmp
-opLat=2
-
-[system.cpu.fuPool.FUList2.opList2]
-type=OpDesc
-issueLat=1
-opClass=FloatCvt
-opLat=2
-
-[system.cpu.fuPool.FUList3]
-type=FUDesc
-children=opList0 opList1 opList2
-count=2
-opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
-
-[system.cpu.fuPool.FUList3.opList0]
-type=OpDesc
-issueLat=1
-opClass=FloatMult
-opLat=4
-
-[system.cpu.fuPool.FUList3.opList1]
-type=OpDesc
-issueLat=12
-opClass=FloatDiv
-opLat=12
-
-[system.cpu.fuPool.FUList3.opList2]
-type=OpDesc
-issueLat=24
-opClass=FloatSqrt
-opLat=24
-
-[system.cpu.fuPool.FUList4]
-type=FUDesc
-children=opList0
-count=0
-opList=system.cpu.fuPool.FUList4.opList0
-
-[system.cpu.fuPool.FUList4.opList0]
-type=OpDesc
-issueLat=1
-opClass=MemRead
-opLat=1
-
-[system.cpu.fuPool.FUList5]
-type=FUDesc
-children=opList0
-count=0
-opList=system.cpu.fuPool.FUList5.opList0
-
-[system.cpu.fuPool.FUList5.opList0]
-type=OpDesc
-issueLat=1
-opClass=MemWrite
-opLat=1
-
-[system.cpu.fuPool.FUList6]
-type=FUDesc
-children=opList0 opList1
-count=4
-opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1
-
-[system.cpu.fuPool.FUList6.opList0]
-type=OpDesc
-issueLat=1
-opClass=MemRead
-opLat=1
-
-[system.cpu.fuPool.FUList6.opList1]
-type=OpDesc
-issueLat=1
-opClass=MemWrite
-opLat=1
-
-[system.cpu.fuPool.FUList7]
-type=FUDesc
-children=opList0
-count=1
-opList=system.cpu.fuPool.FUList7.opList0
-
-[system.cpu.fuPool.FUList7.opList0]
-type=OpDesc
-issueLat=3
-opClass=IprAccess
-opLat=3
-
-[system.cpu.icache]
-type=BaseCache
-adaptive_compression=false
-assoc=2
-block_size=64
-compressed_bus=false
-compression_latency=0
-do_copy=false
-hash_delay=1
-hit_latency=1
-latency=1
-lifo=false
-max_miss_count=0
-mshrs=10
-prefetch_access=false
-prefetch_cache_check_push=true
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10
-prefetch_miss=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
-prioritizeRequests=false
-protocol=Null
-repl=Null
-size=131072
-split=false
-split_size=0
-store_compressed=false
-subblock_size=0
-tgts_per_mshr=5
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu.icache_port
-mem_side=system.cpu.toL2Bus.port[0]
-
-[system.cpu.l2cache]
-type=BaseCache
-adaptive_compression=false
-assoc=2
-block_size=64
-compressed_bus=false
-compression_latency=0
-do_copy=false
-hash_delay=1
-hit_latency=1
-latency=1
-lifo=false
-max_miss_count=0
-mshrs=10
-prefetch_access=false
-prefetch_cache_check_push=true
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10
-prefetch_miss=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
-prioritizeRequests=false
-protocol=Null
-repl=Null
-size=2097152
-split=false
-split_size=0
-store_compressed=false
-subblock_size=0
-tgts_per_mshr=5
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[1]
-
-[system.cpu.toL2Bus]
-type=Bus
-bus_id=0
-port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+dcache_port=system.membus.port[2]
+icache_port=system.membus.port[1]
[system.cpu.workload]
type=LiveProcess
-cmd=hello
+cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook
+cwd=build/ALPHA_SE/tests/opt/long/30.eon/alpha/linux/simple-atomic
+egid=100
env=
-executable=tests/test-progs/hello/bin/alpha/linux/hello
+euid=100
+executable=/dist/m5/cpu2000/binaries/alpha/tru64/eon
+gid=100
input=cin
output=cout
+pid=100
+ppid=99
system=system
+uid=100
[system.membus]
type=Bus
bus_id=0
-port=system.physmem.port system.cpu.l2cache.mem_side
+clock=1000
+responder_set=false
+width=64
+port=system.physmem.port system.cpu.icache_port system.cpu.dcache_port
[system.physmem]
type=PhysicalMemory
@@ -409,6 +104,7 @@ port=system.membus.port[0]
[trace]
bufsize=0
+cycle=0
dump_on_exit=false
file=cout
flags=
diff --git a/tests/long/30.eon/ref/alpha/linux/simple-atomic/config.out b/tests/long/30.eon/ref/alpha/linux/simple-atomic/config.out
index f491a3081..bec900d0f 100644
--- a/tests/long/30.eon/ref/alpha/linux/simple-atomic/config.out
+++ b/tests/long/30.eon/ref/alpha/linux/simple-atomic/config.out
@@ -19,345 +19,48 @@ mem_mode=atomic
[system.membus]
type=Bus
bus_id=0
+clock=1000
+width=64
+responder_set=false
[system.cpu.workload]
type=LiveProcess
-cmd=hello
-executable=tests/test-progs/hello/bin/alpha/linux/hello
+cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook
+executable=/dist/m5/cpu2000/binaries/alpha/tru64/eon
input=cin
output=cout
env=
+cwd=build/ALPHA_SE/tests/opt/long/30.eon/alpha/linux/simple-atomic
system=system
-
-[system.cpu.dcache]
-type=BaseCache
-size=262144
-assoc=2
-block_size=64
-latency=1
-mshrs=10
-tgts_per_mshr=5
-write_buffers=8
-prioritizeRequests=false
-do_copy=false
-protocol=null
-trace_addr=0
-hash_delay=1
-repl=null
-compressed_bus=false
-store_compressed=false
-adaptive_compression=false
-compression_latency=0
-block_size=64
-max_miss_count=0
-addr_range=[0,18446744073709551615]
-split=false
-split_size=0
-lifo=false
-two_queue=false
-prefetch_miss=false
-prefetch_access=false
-prefetcher_size=100
-prefetch_past_page=false
-prefetch_serial_squash=false
-prefetch_latency=10
-prefetch_degree=1
-prefetch_policy=none
-prefetch_cache_check_push=true
-prefetch_use_cpu_id=true
-prefetch_data_accesses_only=false
-hit_latency=1
-
-[system.cpu.fuPool.FUList0.opList0]
-type=OpDesc
-opClass=IntAlu
-opLat=1
-issueLat=1
-
-[system.cpu.fuPool.FUList0]
-type=FUDesc
-opList=system.cpu.fuPool.FUList0.opList0
-count=6
-
-[system.cpu.fuPool.FUList1.opList0]
-type=OpDesc
-opClass=IntMult
-opLat=3
-issueLat=1
-
-[system.cpu.fuPool.FUList1.opList1]
-type=OpDesc
-opClass=IntDiv
-opLat=20
-issueLat=19
-
-[system.cpu.fuPool.FUList1]
-type=FUDesc
-opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
-count=2
-
-[system.cpu.fuPool.FUList2.opList0]
-type=OpDesc
-opClass=FloatAdd
-opLat=2
-issueLat=1
-
-[system.cpu.fuPool.FUList2.opList1]
-type=OpDesc
-opClass=FloatCmp
-opLat=2
-issueLat=1
-
-[system.cpu.fuPool.FUList2.opList2]
-type=OpDesc
-opClass=FloatCvt
-opLat=2
-issueLat=1
-
-[system.cpu.fuPool.FUList2]
-type=FUDesc
-opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
-count=4
-
-[system.cpu.fuPool.FUList3.opList0]
-type=OpDesc
-opClass=FloatMult
-opLat=4
-issueLat=1
-
-[system.cpu.fuPool.FUList3.opList1]
-type=OpDesc
-opClass=FloatDiv
-opLat=12
-issueLat=12
-
-[system.cpu.fuPool.FUList3.opList2]
-type=OpDesc
-opClass=FloatSqrt
-opLat=24
-issueLat=24
-
-[system.cpu.fuPool.FUList3]
-type=FUDesc
-opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
-count=2
-
-[system.cpu.fuPool.FUList4.opList0]
-type=OpDesc
-opClass=MemRead
-opLat=1
-issueLat=1
-
-[system.cpu.fuPool.FUList4]
-type=FUDesc
-opList=system.cpu.fuPool.FUList4.opList0
-count=0
-
-[system.cpu.fuPool.FUList5.opList0]
-type=OpDesc
-opClass=MemWrite
-opLat=1
-issueLat=1
-
-[system.cpu.fuPool.FUList5]
-type=FUDesc
-opList=system.cpu.fuPool.FUList5.opList0
-count=0
-
-[system.cpu.fuPool.FUList6.opList0]
-type=OpDesc
-opClass=MemRead
-opLat=1
-issueLat=1
-
-[system.cpu.fuPool.FUList6.opList1]
-type=OpDesc
-opClass=MemWrite
-opLat=1
-issueLat=1
-
-[system.cpu.fuPool.FUList6]
-type=FUDesc
-opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1
-count=4
-
-[system.cpu.fuPool.FUList7.opList0]
-type=OpDesc
-opClass=IprAccess
-opLat=3
-issueLat=3
-
-[system.cpu.fuPool.FUList7]
-type=FUDesc
-opList=system.cpu.fuPool.FUList7.opList0
-count=1
-
-[system.cpu.fuPool]
-type=FUPool
-FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7
+uid=100
+euid=100
+gid=100
+egid=100
+pid=100
+ppid=99
[system.cpu]
-type=DerivO3CPU
-clock=1
-numThreads=1
-activity=0
-workload=system.cpu.workload
-mem=system.cpu.dcache
-checker=null
+type=AtomicSimpleCPU
max_insts_any_thread=0
max_insts_all_threads=0
max_loads_any_thread=0
max_loads_all_threads=0
-cachePorts=200
-decodeToFetchDelay=1
-renameToFetchDelay=1
-iewToFetchDelay=1
-commitToFetchDelay=1
-fetchWidth=8
-renameToDecodeDelay=1
-iewToDecodeDelay=1
-commitToDecodeDelay=1
-fetchToDecodeDelay=1
-decodeWidth=8
-iewToRenameDelay=1
-commitToRenameDelay=1
-decodeToRenameDelay=1
-renameWidth=8
-commitToIEWDelay=1
-renameToIEWDelay=2
-issueToExecuteDelay=1
-dispatchWidth=8
-issueWidth=8
-wbWidth=8
-wbDepth=1
-fuPool=system.cpu.fuPool
-iewToCommitDelay=1
-renameToROBDelay=1
-commitWidth=8
-squashWidth=8
-trapLatency=13
-backComSize=5
-forwardComSize=5
-predType=tournament
-localPredictorSize=2048
-localCtrBits=2
-localHistoryTableSize=2048
-localHistoryBits=11
-globalPredictorSize=8192
-globalCtrBits=2
-globalHistoryBits=13
-choicePredictorSize=8192
-choiceCtrBits=2
-BTBEntries=4096
-BTBTagSize=16
-RASSize=16
-LQEntries=32
-SQEntries=32
-LFSTSize=1024
-SSITSize=1024
-numPhysIntRegs=256
-numPhysFloatRegs=256
-numIQEntries=64
-numROBEntries=192
-smtNumFetchingThreads=1
-smtFetchPolicy=SingleThread
-smtLSQPolicy=Partitioned
-smtLSQThreshold=100
-smtIQPolicy=Partitioned
-smtIQThreshold=100
-smtROBPolicy=Partitioned
-smtROBThreshold=100
-smtCommitPolicy=RoundRobin
-instShiftAmt=2
+progress_interval=0
+system=system
+cpu_id=0
+workload=system.cpu.workload
+clock=1
+phase=0
defer_registration=false
+width=1
function_trace=false
function_trace_start=0
-
-[system.cpu.icache]
-type=BaseCache
-size=131072
-assoc=2
-block_size=64
-latency=1
-mshrs=10
-tgts_per_mshr=5
-write_buffers=8
-prioritizeRequests=false
-do_copy=false
-protocol=null
-trace_addr=0
-hash_delay=1
-repl=null
-compressed_bus=false
-store_compressed=false
-adaptive_compression=false
-compression_latency=0
-block_size=64
-max_miss_count=0
-addr_range=[0,18446744073709551615]
-split=false
-split_size=0
-lifo=false
-two_queue=false
-prefetch_miss=false
-prefetch_access=false
-prefetcher_size=100
-prefetch_past_page=false
-prefetch_serial_squash=false
-prefetch_latency=10
-prefetch_degree=1
-prefetch_policy=none
-prefetch_cache_check_push=true
-prefetch_use_cpu_id=true
-prefetch_data_accesses_only=false
-hit_latency=1
-
-[system.cpu.l2cache]
-type=BaseCache
-size=2097152
-assoc=2
-block_size=64
-latency=1
-mshrs=10
-tgts_per_mshr=5
-write_buffers=8
-prioritizeRequests=false
-do_copy=false
-protocol=null
-trace_addr=0
-hash_delay=1
-repl=null
-compressed_bus=false
-store_compressed=false
-adaptive_compression=false
-compression_latency=0
-block_size=64
-max_miss_count=0
-addr_range=[0,18446744073709551615]
-split=false
-split_size=0
-lifo=false
-two_queue=false
-prefetch_miss=false
-prefetch_access=false
-prefetcher_size=100
-prefetch_past_page=false
-prefetch_serial_squash=false
-prefetch_latency=10
-prefetch_degree=1
-prefetch_policy=none
-prefetch_cache_check_push=true
-prefetch_use_cpu_id=true
-prefetch_data_accesses_only=false
-hit_latency=1
-
-[system.cpu.toL2Bus]
-type=Bus
-bus_id=0
+simulate_stalls=false
[trace]
flags=
start=0
+cycle=0
bufsize=0
file=cout
dump_on_exit=false
@@ -396,8 +99,9 @@ print_cpseq=false
print_reg_delta=false
pc_symbol=true
intel_format=false
+legion_lockstep=false
trace_system=client
-[debug]
-break_cycles=
+[statsreset]
+reset_cycle=0
diff --git a/tests/long/30.eon/ref/alpha/linux/simple-atomic/m5stats.txt b/tests/long/30.eon/ref/alpha/linux/simple-atomic/m5stats.txt
index 5d4f9235a..a308f5e36 100644
--- a/tests/long/30.eon/ref/alpha/linux/simple-atomic/m5stats.txt
+++ b/tests/long/30.eon/ref/alpha/linux/simple-atomic/m5stats.txt
@@ -1,1974 +1,18 @@
---------- Begin Simulation Statistics ----------
-global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-global.BPredUnit.BTBHits 542 # Number of BTB hits
-global.BPredUnit.BTBLookups 1938 # Number of BTB lookups
-global.BPredUnit.RASInCorrect 48 # Number of incorrect RAS predictions.
-global.BPredUnit.condIncorrect 420 # Number of conditional branches incorrect
-global.BPredUnit.condPredicted 1304 # Number of conditional branches predicted
-global.BPredUnit.lookups 2256 # Number of BP lookups
-global.BPredUnit.usedRAS 291 # Number of times the RAS was used to get a target.
-host_inst_rate 41797 # Simulator instruction rate (inst/s)
-host_mem_usage 160344 # Number of bytes of host memory used
-host_seconds 0.13 # Real time elapsed on the host
-host_tick_rate 50948 # Simulator tick rate (ticks/s)
-memdepunit.memDep.conflictingLoads 12 # Number of conflicting loads.
-memdepunit.memDep.conflictingStores 259 # Number of conflicting stores.
-memdepunit.memDep.insertedLoads 2050 # Number of loads inserted to the mem dependence unit.
-memdepunit.memDep.insertedStores 1221 # Number of stores inserted to the mem dependence unit.
+host_inst_rate 841426 # Simulator instruction rate (inst/s)
+host_mem_usage 147172 # Number of bytes of host memory used
+host_seconds 473.80 # Real time elapsed on the host
+host_tick_rate 841425 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 5623 # Number of instructions simulated
-sim_seconds 0.000000 # Number of seconds simulated
-sim_ticks 6870 # Number of ticks simulated
-system.cpu.commit.COM:branches 862 # Number of branches committed
-system.cpu.commit.COM:bw_lim_events 74 # number cycles where commit BW limit reached
-system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle.samples 6116
-system.cpu.commit.COM:committed_per_cycle.min_value 0
- 0 3908 6389.80%
- 1 1064 1739.70%
- 2 389 636.04%
- 3 210 343.36%
- 4 153 250.16%
- 5 93 152.06%
- 6 76 124.26%
- 7 149 243.62%
- 8 74 120.99%
-system.cpu.commit.COM:committed_per_cycle.max_value 8
-system.cpu.commit.COM:committed_per_cycle.end_dist
-
-system.cpu.commit.COM:count 5640 # Number of instructions committed
-system.cpu.commit.COM:loads 979 # Number of loads committed
-system.cpu.commit.COM:membars 0 # Number of memory barriers committed
-system.cpu.commit.COM:refs 1791 # Number of memory references committed
-system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.branchMispredicts 337 # The number of times a branch was mispredicted
-system.cpu.commit.commitCommittedInsts 5640 # The number of committed instructions
-system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.commitSquashedInsts 4350 # The number of squashed insts skipped by commit
-system.cpu.committedInsts 5623 # Number of Instructions Simulated
-system.cpu.committedInsts_total 5623 # Number of Instructions Simulated
-system.cpu.cpi 1.221768 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 1.221768 # CPI: Total CPI of All Threads
-system.cpu.dcache.ReadReq_accesses 1538 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 3.072000 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2.240000 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits 1413 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 384 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate 0.081274 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses 125 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_hits 25 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_miss_latency 224 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate 0.065020 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses 100 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_accesses 821 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 2.467742 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2.140845 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 635 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 459 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.226553 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 186 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_hits 108 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_miss_latency 152 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.086480 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 71 # number of WriteReq MSHR misses
-system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles_no_targets 0.800000 # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 11.505618 # Average number of references to valid blocks.
-system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_no_targets 5 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles_no_targets 4 # number of cycles access was blocked
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.demand_accesses 2359 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 2.710611 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 2.198830 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 2048 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 843 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.131836 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 311 # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits 133 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 376 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate 0.072488 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 171 # number of demand (read+write) MSHR misses
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.overall_accesses 2359 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 2.710611 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 2.198830 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 2048 # number of overall hits
-system.cpu.dcache.overall_miss_latency 843 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.131836 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 311 # number of overall misses
-system.cpu.dcache.overall_mshr_hits 133 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 376 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate 0.072488 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 171 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.dcache.replacements 0 # number of replacements
-system.cpu.dcache.sampled_refs 178 # Sample count of references to valid blocks.
-system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 119.831029 # Cycle average of tags in use
-system.cpu.dcache.total_refs 2048 # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks 0 # number of writebacks
-system.cpu.decode.DECODE:BlockedCycles 387 # Number of cycles decode is blocked
-system.cpu.decode.DECODE:BranchMispred 93 # Number of times decode detected a branch misprediction
-system.cpu.decode.DECODE:BranchResolved 185 # Number of times decode resolved a branch
-system.cpu.decode.DECODE:DecodedInsts 12349 # Number of instructions handled by decode
-system.cpu.decode.DECODE:IdleCycles 3542 # Number of cycles decode is idle
-system.cpu.decode.DECODE:RunCycles 2158 # Number of cycles decode is running
-system.cpu.decode.DECODE:SquashCycles 754 # Number of cycles decode is squashing
-system.cpu.decode.DECODE:SquashedInsts 286 # Number of squashed instructions handled by decode
-system.cpu.decode.DECODE:UnblockCycles 30 # Number of cycles decode is unblocking
-system.cpu.fetch.Branches 2256 # Number of branches that fetch encountered
-system.cpu.fetch.CacheLines 1582 # Number of cache lines fetched
-system.cpu.fetch.Cycles 3905 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.IcacheSquashes 148 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.Insts 13707 # Number of instructions fetch has processed
-system.cpu.fetch.SquashCycles 456 # Number of cycles fetch has spent squashing
-system.cpu.fetch.branchRate 0.328336 # Number of branch fetches per cycle
-system.cpu.fetch.icacheStallCycles 1582 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.predictedBranches 833 # Number of branches that fetch has predicted taken
-system.cpu.fetch.rate 1.994906 # Number of inst fetches per cycle
-system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist.samples 6871
-system.cpu.fetch.rateDist.min_value 0
- 0 4549 6620.58%
- 1 174 253.24%
- 2 186 270.70%
- 3 157 228.50%
- 4 211 307.09%
- 5 153 222.68%
- 6 171 248.87%
- 7 105 152.82%
- 8 1165 1695.53%
-system.cpu.fetch.rateDist.max_value 8
-system.cpu.fetch.rateDist.end_dist
-
-system.cpu.icache.ReadReq_accesses 1582 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 2.960245 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 1.996885 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits 1255 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 968 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate 0.206700 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses 327 # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_hits 6 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_miss_latency 641 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.202908 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses 321 # number of ReadReq MSHR misses
-system.cpu.icache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles_no_targets no value # average number of cycles each access was blocked
-system.cpu.icache.avg_refs 3.909657 # Average number of references to valid blocks.
-system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.demand_accesses 1582 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 2.960245 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 1.996885 # average overall mshr miss latency
-system.cpu.icache.demand_hits 1255 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 968 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate 0.206700 # miss rate for demand accesses
-system.cpu.icache.demand_misses 327 # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_hits 6 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 641 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate 0.202908 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses 321 # number of demand (read+write) MSHR misses
-system.cpu.icache.fast_writes 0 # number of fast writes performed
-system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.overall_accesses 1582 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 2.960245 # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 1.996885 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits 1255 # number of overall hits
-system.cpu.icache.overall_miss_latency 968 # number of overall miss cycles
-system.cpu.icache.overall_miss_rate 0.206700 # miss rate for overall accesses
-system.cpu.icache.overall_misses 327 # number of overall misses
-system.cpu.icache.overall_mshr_hits 6 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 641 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate 0.202908 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses 321 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.icache.replacements 0 # number of replacements
-system.cpu.icache.sampled_refs 321 # Sample count of references to valid blocks.
-system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 176.393247 # Cycle average of tags in use
-system.cpu.icache.total_refs 1255 # Total number of references to valid blocks.
-system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.iew.EXEC:branches 1206 # Number of branches executed
-system.cpu.iew.EXEC:insts 7969 # Number of executed instructions
-system.cpu.iew.EXEC:loads 1610 # Number of load instructions executed
-system.cpu.iew.EXEC:nop 37 # number of nop insts executed
-system.cpu.iew.EXEC:rate 1.159802 # Inst execution rate
-system.cpu.iew.EXEC:refs 2599 # number of memory reference insts executed
-system.cpu.iew.EXEC:squashedInsts 419 # Number of squashed instructions skipped in execute
-system.cpu.iew.EXEC:stores 989 # Number of stores executed
-system.cpu.iew.EXEC:swp 0 # number of swp insts executed
-system.cpu.iew.WB:consumers 5438 # num instructions consuming a value
-system.cpu.iew.WB:count 7722 # cumulative count of insts written-back
-system.cpu.iew.WB:fanout 0.744575 # average fanout of values written-back
-system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.iew.WB:producers 4049 # num instructions producing a value
-system.cpu.iew.WB:rate 1.123854 # insts written-back per cycle
-system.cpu.iew.WB:sent 7762 # cumulative count of insts sent to commit
-system.cpu.iew.branchMispredicts 393 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewBlockCycles 4 # Number of cycles IEW is blocking
-system.cpu.iew.iewDispLoadInsts 2050 # Number of dispatched load instructions
-system.cpu.iew.iewDispNonSpecInsts 21 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewDispSquashedInsts 272 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispStoreInsts 1221 # Number of dispatched store instructions
-system.cpu.iew.iewDispatchedInsts 9990 # Number of instructions dispatched to IQ
-system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.iewSquashCycles 754 # Number of cycles IEW is squashing
-system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking
-system.cpu.iew.lsq.thread.0.blockedLoads 1 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread.0.cacheBlocked 5 # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.lsq.thread.0.forwLoads 55 # Number of loads that had data forwarded from stores
-system.cpu.iew.lsq.thread.0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
-system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread.0.squashedLoads 1071 # Number of loads squashed
-system.cpu.iew.lsq.thread.0.squashedStores 409 # Number of stores squashed
-system.cpu.iew.memOrderViolationEvents 41 # Number of memory order violations
-system.cpu.iew.predictedNotTakenIncorrect 296 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.predictedTakenIncorrect 97 # Number of branches that were predicted taken incorrectly
-system.cpu.ipc 0.818486 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.818486 # IPC: Total IPC of All Threads
-system.cpu.iq.IQ:residence:(null).start_dist # cycles from dispatch to issue
-system.cpu.iq.IQ:residence:(null).samples 0
-system.cpu.iq.IQ:residence:(null).min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
- 20 0
- 22 0
- 24 0
- 26 0
- 28 0
- 30 0
- 32 0
- 34 0
- 36 0
- 38 0
- 40 0
- 42 0
- 44 0
- 46 0
- 48 0
- 50 0
- 52 0
- 54 0
- 56 0
- 58 0
- 60 0
- 62 0
- 64 0
- 66 0
- 68 0
- 70 0
- 72 0
- 74 0
- 76 0
- 78 0
- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.IQ:residence:(null).max_value 0
-system.cpu.iq.IQ:residence:(null).end_dist
-
-system.cpu.iq.IQ:residence:IntAlu.start_dist # cycles from dispatch to issue
-system.cpu.iq.IQ:residence:IntAlu.samples 0
-system.cpu.iq.IQ:residence:IntAlu.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
- 20 0
- 22 0
- 24 0
- 26 0
- 28 0
- 30 0
- 32 0
- 34 0
- 36 0
- 38 0
- 40 0
- 42 0
- 44 0
- 46 0
- 48 0
- 50 0
- 52 0
- 54 0
- 56 0
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- 60 0
- 62 0
- 64 0
- 66 0
- 68 0
- 70 0
- 72 0
- 74 0
- 76 0
- 78 0
- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.IQ:residence:IntAlu.max_value 0
-system.cpu.iq.IQ:residence:IntAlu.end_dist
-
-system.cpu.iq.IQ:residence:IntMult.start_dist # cycles from dispatch to issue
-system.cpu.iq.IQ:residence:IntMult.samples 0
-system.cpu.iq.IQ:residence:IntMult.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
- 20 0
- 22 0
- 24 0
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- 28 0
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- 32 0
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- 78 0
- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.IQ:residence:IntMult.max_value 0
-system.cpu.iq.IQ:residence:IntMult.end_dist
-
-system.cpu.iq.IQ:residence:IntDiv.start_dist # cycles from dispatch to issue
-system.cpu.iq.IQ:residence:IntDiv.samples 0
-system.cpu.iq.IQ:residence:IntDiv.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
- 20 0
- 22 0
- 24 0
- 26 0
- 28 0
- 30 0
- 32 0
- 34 0
- 36 0
- 38 0
- 40 0
- 42 0
- 44 0
- 46 0
- 48 0
- 50 0
- 52 0
- 54 0
- 56 0
- 58 0
- 60 0
- 62 0
- 64 0
- 66 0
- 68 0
- 70 0
- 72 0
- 74 0
- 76 0
- 78 0
- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.IQ:residence:IntDiv.max_value 0
-system.cpu.iq.IQ:residence:IntDiv.end_dist
-
-system.cpu.iq.IQ:residence:FloatAdd.start_dist # cycles from dispatch to issue
-system.cpu.iq.IQ:residence:FloatAdd.samples 0
-system.cpu.iq.IQ:residence:FloatAdd.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
- 20 0
- 22 0
- 24 0
- 26 0
- 28 0
- 30 0
- 32 0
- 34 0
- 36 0
- 38 0
- 40 0
- 42 0
- 44 0
- 46 0
- 48 0
- 50 0
- 52 0
- 54 0
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- 58 0
- 60 0
- 62 0
- 64 0
- 66 0
- 68 0
- 70 0
- 72 0
- 74 0
- 76 0
- 78 0
- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.IQ:residence:FloatAdd.max_value 0
-system.cpu.iq.IQ:residence:FloatAdd.end_dist
-
-system.cpu.iq.IQ:residence:FloatCmp.start_dist # cycles from dispatch to issue
-system.cpu.iq.IQ:residence:FloatCmp.samples 0
-system.cpu.iq.IQ:residence:FloatCmp.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
- 20 0
- 22 0
- 24 0
- 26 0
- 28 0
- 30 0
- 32 0
- 34 0
- 36 0
- 38 0
- 40 0
- 42 0
- 44 0
- 46 0
- 48 0
- 50 0
- 52 0
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- 56 0
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- 66 0
- 68 0
- 70 0
- 72 0
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- 76 0
- 78 0
- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.IQ:residence:FloatCmp.max_value 0
-system.cpu.iq.IQ:residence:FloatCmp.end_dist
-
-system.cpu.iq.IQ:residence:FloatCvt.start_dist # cycles from dispatch to issue
-system.cpu.iq.IQ:residence:FloatCvt.samples 0
-system.cpu.iq.IQ:residence:FloatCvt.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
- 20 0
- 22 0
- 24 0
- 26 0
- 28 0
- 30 0
- 32 0
- 34 0
- 36 0
- 38 0
- 40 0
- 42 0
- 44 0
- 46 0
- 48 0
- 50 0
- 52 0
- 54 0
- 56 0
- 58 0
- 60 0
- 62 0
- 64 0
- 66 0
- 68 0
- 70 0
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- 76 0
- 78 0
- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.IQ:residence:FloatCvt.max_value 0
-system.cpu.iq.IQ:residence:FloatCvt.end_dist
-
-system.cpu.iq.IQ:residence:FloatMult.start_dist # cycles from dispatch to issue
-system.cpu.iq.IQ:residence:FloatMult.samples 0
-system.cpu.iq.IQ:residence:FloatMult.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
- 20 0
- 22 0
- 24 0
- 26 0
- 28 0
- 30 0
- 32 0
- 34 0
- 36 0
- 38 0
- 40 0
- 42 0
- 44 0
- 46 0
- 48 0
- 50 0
- 52 0
- 54 0
- 56 0
- 58 0
- 60 0
- 62 0
- 64 0
- 66 0
- 68 0
- 70 0
- 72 0
- 74 0
- 76 0
- 78 0
- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.IQ:residence:FloatMult.max_value 0
-system.cpu.iq.IQ:residence:FloatMult.end_dist
-
-system.cpu.iq.IQ:residence:FloatDiv.start_dist # cycles from dispatch to issue
-system.cpu.iq.IQ:residence:FloatDiv.samples 0
-system.cpu.iq.IQ:residence:FloatDiv.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
- 20 0
- 22 0
- 24 0
- 26 0
- 28 0
- 30 0
- 32 0
- 34 0
- 36 0
- 38 0
- 40 0
- 42 0
- 44 0
- 46 0
- 48 0
- 50 0
- 52 0
- 54 0
- 56 0
- 58 0
- 60 0
- 62 0
- 64 0
- 66 0
- 68 0
- 70 0
- 72 0
- 74 0
- 76 0
- 78 0
- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.IQ:residence:FloatDiv.max_value 0
-system.cpu.iq.IQ:residence:FloatDiv.end_dist
-
-system.cpu.iq.IQ:residence:FloatSqrt.start_dist # cycles from dispatch to issue
-system.cpu.iq.IQ:residence:FloatSqrt.samples 0
-system.cpu.iq.IQ:residence:FloatSqrt.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
- 20 0
- 22 0
- 24 0
- 26 0
- 28 0
- 30 0
- 32 0
- 34 0
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-system.cpu.iq.IQ:residence:FloatSqrt.end_dist
-
-system.cpu.iq.IQ:residence:MemRead.start_dist # cycles from dispatch to issue
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-system.cpu.iq.IQ:residence:MemRead.max_value 0
-system.cpu.iq.IQ:residence:MemRead.end_dist
-
-system.cpu.iq.IQ:residence:MemWrite.start_dist # cycles from dispatch to issue
-system.cpu.iq.IQ:residence:MemWrite.samples 0
-system.cpu.iq.IQ:residence:MemWrite.min_value 0
- 0 0
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-system.cpu.iq.IQ:residence:MemWrite.max_value 0
-system.cpu.iq.IQ:residence:MemWrite.end_dist
-
-system.cpu.iq.IQ:residence:IprAccess.start_dist # cycles from dispatch to issue
-system.cpu.iq.IQ:residence:IprAccess.samples 0
-system.cpu.iq.IQ:residence:IprAccess.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
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-system.cpu.iq.IQ:residence:IprAccess.max_value 0
-system.cpu.iq.IQ:residence:IprAccess.end_dist
-
-system.cpu.iq.IQ:residence:InstPrefetch.start_dist # cycles from dispatch to issue
-system.cpu.iq.IQ:residence:InstPrefetch.samples 0
-system.cpu.iq.IQ:residence:InstPrefetch.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
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-system.cpu.iq.IQ:residence:InstPrefetch.max_value 0
-system.cpu.iq.IQ:residence:InstPrefetch.end_dist
-
-system.cpu.iq.ISSUE:(null)_delay.start_dist # cycles from operands ready to issue
-system.cpu.iq.ISSUE:(null)_delay.samples 0
-system.cpu.iq.ISSUE:(null)_delay.min_value 0
- 0 0
- 2 0
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- 98 0
-system.cpu.iq.ISSUE:(null)_delay.max_value 0
-system.cpu.iq.ISSUE:(null)_delay.end_dist
-
-system.cpu.iq.ISSUE:IntAlu_delay.start_dist # cycles from operands ready to issue
-system.cpu.iq.ISSUE:IntAlu_delay.samples 0
-system.cpu.iq.ISSUE:IntAlu_delay.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
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- 12 0
- 14 0
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- 94 0
- 96 0
- 98 0
-system.cpu.iq.ISSUE:IntAlu_delay.max_value 0
-system.cpu.iq.ISSUE:IntAlu_delay.end_dist
-
-system.cpu.iq.ISSUE:IntMult_delay.start_dist # cycles from operands ready to issue
-system.cpu.iq.ISSUE:IntMult_delay.samples 0
-system.cpu.iq.ISSUE:IntMult_delay.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
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- 98 0
-system.cpu.iq.ISSUE:IntMult_delay.max_value 0
-system.cpu.iq.ISSUE:IntMult_delay.end_dist
-
-system.cpu.iq.ISSUE:IntDiv_delay.start_dist # cycles from operands ready to issue
-system.cpu.iq.ISSUE:IntDiv_delay.samples 0
-system.cpu.iq.ISSUE:IntDiv_delay.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
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- 96 0
- 98 0
-system.cpu.iq.ISSUE:IntDiv_delay.max_value 0
-system.cpu.iq.ISSUE:IntDiv_delay.end_dist
-
-system.cpu.iq.ISSUE:FloatAdd_delay.start_dist # cycles from operands ready to issue
-system.cpu.iq.ISSUE:FloatAdd_delay.samples 0
-system.cpu.iq.ISSUE:FloatAdd_delay.min_value 0
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- 2 0
- 4 0
- 6 0
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- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.ISSUE:FloatAdd_delay.max_value 0
-system.cpu.iq.ISSUE:FloatAdd_delay.end_dist
-
-system.cpu.iq.ISSUE:FloatCmp_delay.start_dist # cycles from operands ready to issue
-system.cpu.iq.ISSUE:FloatCmp_delay.samples 0
-system.cpu.iq.ISSUE:FloatCmp_delay.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
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- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.ISSUE:FloatCmp_delay.max_value 0
-system.cpu.iq.ISSUE:FloatCmp_delay.end_dist
-
-system.cpu.iq.ISSUE:FloatCvt_delay.start_dist # cycles from operands ready to issue
-system.cpu.iq.ISSUE:FloatCvt_delay.samples 0
-system.cpu.iq.ISSUE:FloatCvt_delay.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
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- 98 0
-system.cpu.iq.ISSUE:FloatCvt_delay.max_value 0
-system.cpu.iq.ISSUE:FloatCvt_delay.end_dist
-
-system.cpu.iq.ISSUE:FloatMult_delay.start_dist # cycles from operands ready to issue
-system.cpu.iq.ISSUE:FloatMult_delay.samples 0
-system.cpu.iq.ISSUE:FloatMult_delay.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
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- 98 0
-system.cpu.iq.ISSUE:FloatMult_delay.max_value 0
-system.cpu.iq.ISSUE:FloatMult_delay.end_dist
-
-system.cpu.iq.ISSUE:FloatDiv_delay.start_dist # cycles from operands ready to issue
-system.cpu.iq.ISSUE:FloatDiv_delay.samples 0
-system.cpu.iq.ISSUE:FloatDiv_delay.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
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- 96 0
- 98 0
-system.cpu.iq.ISSUE:FloatDiv_delay.max_value 0
-system.cpu.iq.ISSUE:FloatDiv_delay.end_dist
-
-system.cpu.iq.ISSUE:FloatSqrt_delay.start_dist # cycles from operands ready to issue
-system.cpu.iq.ISSUE:FloatSqrt_delay.samples 0
-system.cpu.iq.ISSUE:FloatSqrt_delay.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
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- 94 0
- 96 0
- 98 0
-system.cpu.iq.ISSUE:FloatSqrt_delay.max_value 0
-system.cpu.iq.ISSUE:FloatSqrt_delay.end_dist
-
-system.cpu.iq.ISSUE:MemRead_delay.start_dist # cycles from operands ready to issue
-system.cpu.iq.ISSUE:MemRead_delay.samples 0
-system.cpu.iq.ISSUE:MemRead_delay.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
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- 96 0
- 98 0
-system.cpu.iq.ISSUE:MemRead_delay.max_value 0
-system.cpu.iq.ISSUE:MemRead_delay.end_dist
-
-system.cpu.iq.ISSUE:MemWrite_delay.start_dist # cycles from operands ready to issue
-system.cpu.iq.ISSUE:MemWrite_delay.samples 0
-system.cpu.iq.ISSUE:MemWrite_delay.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
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- 96 0
- 98 0
-system.cpu.iq.ISSUE:MemWrite_delay.max_value 0
-system.cpu.iq.ISSUE:MemWrite_delay.end_dist
-
-system.cpu.iq.ISSUE:IprAccess_delay.start_dist # cycles from operands ready to issue
-system.cpu.iq.ISSUE:IprAccess_delay.samples 0
-system.cpu.iq.ISSUE:IprAccess_delay.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
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- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.ISSUE:IprAccess_delay.max_value 0
-system.cpu.iq.ISSUE:IprAccess_delay.end_dist
-
-system.cpu.iq.ISSUE:InstPrefetch_delay.start_dist # cycles from operands ready to issue
-system.cpu.iq.ISSUE:InstPrefetch_delay.samples 0
-system.cpu.iq.ISSUE:InstPrefetch_delay.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
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- 94 0
- 96 0
- 98 0
-system.cpu.iq.ISSUE:InstPrefetch_delay.max_value 0
-system.cpu.iq.ISSUE:InstPrefetch_delay.end_dist
-
-system.cpu.iq.ISSUE:FU_type_0 8388 # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0.start_dist
- (null) 2 0.02% # Type of FU issued
- IntAlu 5594 66.69% # Type of FU issued
- IntMult 1 0.01% # Type of FU issued
- IntDiv 0 0.00% # Type of FU issued
- FloatAdd 2 0.02% # Type of FU issued
- FloatCmp 0 0.00% # Type of FU issued
- FloatCvt 0 0.00% # Type of FU issued
- FloatMult 0 0.00% # Type of FU issued
- FloatDiv 0 0.00% # Type of FU issued
- FloatSqrt 0 0.00% # Type of FU issued
- MemRead 1757 20.95% # Type of FU issued
- MemWrite 1032 12.30% # Type of FU issued
- IprAccess 0 0.00% # Type of FU issued
- InstPrefetch 0 0.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0.end_dist
-system.cpu.iq.ISSUE:fu_busy_cnt 115 # FU busy when requested
-system.cpu.iq.ISSUE:fu_busy_rate 0.013710 # FU busy rate (busy events/executed inst)
-system.cpu.iq.ISSUE:fu_full.start_dist
- (null) 0 0.00% # attempts to use FU when none available
- IntAlu 1 0.87% # attempts to use FU when none available
- IntMult 0 0.00% # attempts to use FU when none available
- IntDiv 0 0.00% # attempts to use FU when none available
- FloatAdd 0 0.00% # attempts to use FU when none available
- FloatCmp 0 0.00% # attempts to use FU when none available
- FloatCvt 0 0.00% # attempts to use FU when none available
- FloatMult 0 0.00% # attempts to use FU when none available
- FloatDiv 0 0.00% # attempts to use FU when none available
- FloatSqrt 0 0.00% # attempts to use FU when none available
- MemRead 76 66.09% # attempts to use FU when none available
- MemWrite 38 33.04% # attempts to use FU when none available
- IprAccess 0 0.00% # attempts to use FU when none available
- InstPrefetch 0 0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full.end_dist
-system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle.samples 6871
-system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
- 0 3753 5462.09%
- 1 894 1301.12%
- 2 723 1052.25%
- 3 614 893.61%
- 4 451 656.38%
- 5 279 406.05%
- 6 104 151.36%
- 7 41 59.67%
- 8 12 17.46%
-system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
-system.cpu.iq.ISSUE:issued_per_cycle.end_dist
-
-system.cpu.iq.ISSUE:rate 1.220783 # Inst issue rate
-system.cpu.iq.iqInstsAdded 9932 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqInstsIssued 8388 # Number of instructions issued
-system.cpu.iq.iqNonSpecInstsAdded 21 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqSquashedInstsExamined 3990 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedInstsIssued 21 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedNonSpecRemoved 4 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.iqSquashedOperandsExamined 2486 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.l2cache.ReadReq_accesses 499 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 2.042254 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency 1015 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate 0.995992 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses 497 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 490 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.981964 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses 490 # number of ReadReq MSHR misses
-system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs 0.004024 # Average number of references to valid blocks.
-system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.demand_accesses 499 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 2.042254 # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 1 # average overall mshr miss latency
-system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 1015 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate 0.995992 # miss rate for demand accesses
-system.cpu.l2cache.demand_misses 497 # number of demand (read+write) misses
-system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency 490 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate 0.981964 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses 490 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.fast_writes 0 # number of fast writes performed
-system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.overall_accesses 499 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 2.042254 # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 1 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits 2 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 1015 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate 0.995992 # miss rate for overall accesses
-system.cpu.l2cache.overall_misses 497 # number of overall misses
-system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 490 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate 0.981964 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses 490 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.l2cache.replacements 0 # number of replacements
-system.cpu.l2cache.sampled_refs 497 # Sample count of references to valid blocks.
-system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 295.773395 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks 0 # number of writebacks
-system.cpu.numCycles 6871 # number of cpu cycles simulated
-system.cpu.rename.RENAME:BlockCycles 4 # Number of cycles rename is blocking
-system.cpu.rename.RENAME:CommittedMaps 4051 # Number of HB maps that are committed
-system.cpu.rename.RENAME:IdleCycles 3758 # Number of cycles rename is idle
-system.cpu.rename.RENAME:LSQFullEvents 62 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RENAME:RenameLookups 14786 # Number of register rename lookups that rename has made
-system.cpu.rename.RENAME:RenamedInsts 11555 # Number of instructions processed by rename
-system.cpu.rename.RENAME:RenamedOperands 8634 # Number of destination operands rename has renamed
-system.cpu.rename.RENAME:RunCycles 1975 # Number of cycles rename is running
-system.cpu.rename.RENAME:SquashCycles 754 # Number of cycles rename is squashing
-system.cpu.rename.RENAME:UnblockCycles 111 # Number of cycles rename is unblocking
-system.cpu.rename.RENAME:UndoneMaps 4583 # Number of HB maps that are undone due to squashing
-system.cpu.rename.RENAME:serializeStallCycles 269 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RENAME:serializingInsts 26 # count of serializing insts renamed
-system.cpu.rename.RENAME:skidInsts 408 # count of insts added to the skid buffer
-system.cpu.rename.RENAME:tempSerializingInsts 21 # count of temporary serializing insts renamed
-system.cpu.workload.PROG:num_syscalls 17 # Number of system calls
+sim_insts 398664450 # Number of instructions simulated
+sim_seconds 0.000399 # Number of seconds simulated
+sim_ticks 398664449 # Number of ticks simulated
+system.cpu.idle_fraction 0 # Percentage of idle cycles
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.numCycles 398664450 # number of cpu cycles simulated
+system.cpu.num_insts 398664450 # Number of instructions executed
+system.cpu.num_refs 174183390 # Number of memory references
+system.cpu.workload.PROG:num_syscalls 215 # Number of system calls
---------- End Simulation Statistics ----------
diff --git a/tests/long/30.eon/ref/alpha/linux/simple-atomic/stderr b/tests/long/30.eon/ref/alpha/linux/simple-atomic/stderr
index 8893caac8..1d6957eca 100644
--- a/tests/long/30.eon/ref/alpha/linux/simple-atomic/stderr
+++ b/tests/long/30.eon/ref/alpha/linux/simple-atomic/stderr
@@ -1,3 +1,47 @@
warn: Entering event queue @ 0. Starting simulation...
-warn: cycle 0: fault (page_table_fault) detected @ PC 0x000000
-warn: Increasing stack 0x11ff92000:0x11ff9b000 to 0x11ff90000:0x11ff9b000 because of access to 0x11ff91ff0
+getting pixel output filename pixels_out.cook
+opening control file chair.control.cook
+opening camera file chair.camera
+opening surfaces file chair.surfaces
+reading data
+processing 8parts
+Grid measure is 6 by 3.0001 by 6
+cell dimension is 0.863065
+Creating grid for list of length 21
+Grid size = 7 by 4 by 7
+Total occupancy = 236
+reading control stream
+reading camera stream
+Writing to chair.cook.ppm
+calculating 15 by 15 image with 196 samples
+col 0. . .
+col 1. . .
+col 2. . .
+col 3. . .
+col 4. . .
+col 5. . .
+col 6. . .
+col 7. . .
+col 8. . .
+col 9. . .
+col 10. . .
+col 11. . .
+col 12. . .
+col 13. . .
+col 14. . .
+Writing to chair.cook.ppm
+0 8 14
+1 8 14
+2 8 14
+3 8 14
+4 8 14
+5 8 14
+6 8 14
+7 8 14
+8 8 14
+9 8 14
+10 8 14
+11 8 14
+12 8 14
+13 8 14
+14 8 14
diff --git a/tests/long/30.eon/ref/alpha/linux/simple-atomic/stdout b/tests/long/30.eon/ref/alpha/linux/simple-atomic/stdout
index fbb329a2f..039e2d4ce 100644
--- a/tests/long/30.eon/ref/alpha/linux/simple-atomic/stdout
+++ b/tests/long/30.eon/ref/alpha/linux/simple-atomic/stdout
@@ -1,13 +1,2 @@
-Hello world!
-M5 Simulator System
-
-Copyright (c) 2001-2006
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Sep 5 2006 15:28:48
-M5 started Tue Sep 5 15:42:12 2006
-M5 executing on zizzer.eecs.umich.edu
-command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/o3-timing tests/run.py quick/00.hello/alpha/linux/o3-timing
-Exiting @ tick 6870 because target called exit()
+Eon, Version 1.1
+OO-style eon Time= 0.000000
diff --git a/tests/long/30.eon/ref/alpha/linux/simple-timing/config.ini b/tests/long/30.eon/ref/alpha/linux/simple-timing/config.ini
index c3a59fbce..b56d96049 100644
--- a/tests/long/30.eon/ref/alpha/linux/simple-timing/config.ini
+++ b/tests/long/30.eon/ref/alpha/linux/simple-timing/config.ini
@@ -7,11 +7,9 @@ max_tick=0
output_file=cout
progress_interval=0
-[debug]
-break_cycles=
-
[exetrace]
intel_format=false
+legion_lockstep=false
pc_symbol=true
print_cpseq=false
print_cycle=true
@@ -53,73 +51,20 @@ mem_mode=atomic
physmem=system.physmem
[system.cpu]
-type=DerivO3CPU
-children=dcache fuPool icache l2cache toL2Bus workload
-BTBEntries=4096
-BTBTagSize=16
-LFSTSize=1024
-LQEntries=32
-RASSize=16
-SQEntries=32
-SSITSize=1024
-activity=0
-backComSize=5
-choiceCtrBits=2
-choicePredictorSize=8192
+type=TimingSimpleCPU
+children=dcache icache l2cache toL2Bus workload
clock=1
-commitToDecodeDelay=1
-commitToFetchDelay=1
-commitToIEWDelay=1
-commitToRenameDelay=1
-commitWidth=8
-decodeToFetchDelay=1
-decodeToRenameDelay=1
-decodeWidth=8
+cpu_id=0
defer_registration=false
-dispatchWidth=8
-fetchToDecodeDelay=1
-fetchTrapLatency=1
-fetchWidth=8
-forwardComSize=5
-fuPool=system.cpu.fuPool
function_trace=false
function_trace_start=0
-globalCtrBits=2
-globalHistoryBits=13
-globalPredictorSize=8192
-iewToCommitDelay=1
-iewToDecodeDelay=1
-iewToFetchDelay=1
-iewToRenameDelay=1
-instShiftAmt=2
-issueToExecuteDelay=1
-issueWidth=8
-localCtrBits=2
-localHistoryBits=11
-localHistoryTableSize=2048
-localPredictorSize=2048
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
-mem=system.cpu.dcache
-numIQEntries=64
-numPhysFloatRegs=256
-numPhysIntRegs=256
-numROBEntries=192
-numRobs=1
-numThreads=1
-predType=tournament
-renameToDecodeDelay=1
-renameToFetchDelay=1
-renameToIEWDelay=2
-renameToROBDelay=1
-renameWidth=8
-squashWidth=8
+phase=0
+progress_interval=0
system=system
-trapLatency=13
-wbDepth=1
-wbWidth=8
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
@@ -131,7 +76,6 @@ assoc=2
block_size=64
compressed_bus=false
compression_latency=0
-do_copy=false
hash_delay=1
hit_latency=1
latency=1
@@ -164,143 +108,6 @@ write_buffers=8
cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.port[1]
-[system.cpu.fuPool]
-type=FUPool
-children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7
-FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7
-
-[system.cpu.fuPool.FUList0]
-type=FUDesc
-children=opList0
-count=6
-opList=system.cpu.fuPool.FUList0.opList0
-
-[system.cpu.fuPool.FUList0.opList0]
-type=OpDesc
-issueLat=1
-opClass=IntAlu
-opLat=1
-
-[system.cpu.fuPool.FUList1]
-type=FUDesc
-children=opList0 opList1
-count=2
-opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
-
-[system.cpu.fuPool.FUList1.opList0]
-type=OpDesc
-issueLat=1
-opClass=IntMult
-opLat=3
-
-[system.cpu.fuPool.FUList1.opList1]
-type=OpDesc
-issueLat=19
-opClass=IntDiv
-opLat=20
-
-[system.cpu.fuPool.FUList2]
-type=FUDesc
-children=opList0 opList1 opList2
-count=4
-opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
-
-[system.cpu.fuPool.FUList2.opList0]
-type=OpDesc
-issueLat=1
-opClass=FloatAdd
-opLat=2
-
-[system.cpu.fuPool.FUList2.opList1]
-type=OpDesc
-issueLat=1
-opClass=FloatCmp
-opLat=2
-
-[system.cpu.fuPool.FUList2.opList2]
-type=OpDesc
-issueLat=1
-opClass=FloatCvt
-opLat=2
-
-[system.cpu.fuPool.FUList3]
-type=FUDesc
-children=opList0 opList1 opList2
-count=2
-opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
-
-[system.cpu.fuPool.FUList3.opList0]
-type=OpDesc
-issueLat=1
-opClass=FloatMult
-opLat=4
-
-[system.cpu.fuPool.FUList3.opList1]
-type=OpDesc
-issueLat=12
-opClass=FloatDiv
-opLat=12
-
-[system.cpu.fuPool.FUList3.opList2]
-type=OpDesc
-issueLat=24
-opClass=FloatSqrt
-opLat=24
-
-[system.cpu.fuPool.FUList4]
-type=FUDesc
-children=opList0
-count=0
-opList=system.cpu.fuPool.FUList4.opList0
-
-[system.cpu.fuPool.FUList4.opList0]
-type=OpDesc
-issueLat=1
-opClass=MemRead
-opLat=1
-
-[system.cpu.fuPool.FUList5]
-type=FUDesc
-children=opList0
-count=0
-opList=system.cpu.fuPool.FUList5.opList0
-
-[system.cpu.fuPool.FUList5.opList0]
-type=OpDesc
-issueLat=1
-opClass=MemWrite
-opLat=1
-
-[system.cpu.fuPool.FUList6]
-type=FUDesc
-children=opList0 opList1
-count=4
-opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1
-
-[system.cpu.fuPool.FUList6.opList0]
-type=OpDesc
-issueLat=1
-opClass=MemRead
-opLat=1
-
-[system.cpu.fuPool.FUList6.opList1]
-type=OpDesc
-issueLat=1
-opClass=MemWrite
-opLat=1
-
-[system.cpu.fuPool.FUList7]
-type=FUDesc
-children=opList0
-count=1
-opList=system.cpu.fuPool.FUList7.opList0
-
-[system.cpu.fuPool.FUList7.opList0]
-type=OpDesc
-issueLat=3
-opClass=IprAccess
-opLat=3
-
[system.cpu.icache]
type=BaseCache
adaptive_compression=false
@@ -308,7 +115,6 @@ assoc=2
block_size=64
compressed_bus=false
compression_latency=0
-do_copy=false
hash_delay=1
hit_latency=1
latency=1
@@ -348,7 +154,6 @@ assoc=2
block_size=64
compressed_bus=false
compression_latency=0
-do_copy=false
hash_delay=1
hit_latency=1
latency=1
@@ -384,20 +189,33 @@ mem_side=system.membus.port[1]
[system.cpu.toL2Bus]
type=Bus
bus_id=0
+clock=1000
+responder_set=false
+width=64
port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
[system.cpu.workload]
type=LiveProcess
-cmd=hello
+cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook
+cwd=build/ALPHA_SE/tests/opt/long/30.eon/alpha/linux/simple-timing
+egid=100
env=
-executable=tests/test-progs/hello/bin/alpha/linux/hello
+euid=100
+executable=/dist/m5/cpu2000/binaries/alpha/tru64/eon
+gid=100
input=cin
output=cout
+pid=100
+ppid=99
system=system
+uid=100
[system.membus]
type=Bus
bus_id=0
+clock=1000
+responder_set=false
+width=64
port=system.physmem.port system.cpu.l2cache.mem_side
[system.physmem]
@@ -409,6 +227,7 @@ port=system.membus.port[0]
[trace]
bufsize=0
+cycle=0
dump_on_exit=false
file=cout
flags=
diff --git a/tests/long/30.eon/ref/alpha/linux/simple-timing/config.out b/tests/long/30.eon/ref/alpha/linux/simple-timing/config.out
index f491a3081..0af9e3f29 100644
--- a/tests/long/30.eon/ref/alpha/linux/simple-timing/config.out
+++ b/tests/long/30.eon/ref/alpha/linux/simple-timing/config.out
@@ -19,19 +19,54 @@ mem_mode=atomic
[system.membus]
type=Bus
bus_id=0
+clock=1000
+width=64
+responder_set=false
[system.cpu.workload]
type=LiveProcess
-cmd=hello
-executable=tests/test-progs/hello/bin/alpha/linux/hello
+cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook
+executable=/dist/m5/cpu2000/binaries/alpha/tru64/eon
input=cin
output=cout
env=
+cwd=build/ALPHA_SE/tests/opt/long/30.eon/alpha/linux/simple-timing
system=system
+uid=100
+euid=100
+gid=100
+egid=100
+pid=100
+ppid=99
-[system.cpu.dcache]
+[system.cpu]
+type=TimingSimpleCPU
+max_insts_any_thread=0
+max_insts_all_threads=0
+max_loads_any_thread=0
+max_loads_all_threads=0
+progress_interval=0
+system=system
+cpu_id=0
+workload=system.cpu.workload
+clock=1
+phase=0
+defer_registration=false
+// width not specified
+function_trace=false
+function_trace_start=0
+// simulate_stalls not specified
+
+[system.cpu.toL2Bus]
+type=Bus
+bus_id=0
+clock=1000
+width=64
+responder_set=false
+
+[system.cpu.icache]
type=BaseCache
-size=262144
+size=131072
assoc=2
block_size=64
latency=1
@@ -39,7 +74,6 @@ mshrs=10
tgts_per_mshr=5
write_buffers=8
prioritizeRequests=false
-do_copy=false
protocol=null
trace_addr=0
hash_delay=1
@@ -68,214 +102,9 @@ prefetch_use_cpu_id=true
prefetch_data_accesses_only=false
hit_latency=1
-[system.cpu.fuPool.FUList0.opList0]
-type=OpDesc
-opClass=IntAlu
-opLat=1
-issueLat=1
-
-[system.cpu.fuPool.FUList0]
-type=FUDesc
-opList=system.cpu.fuPool.FUList0.opList0
-count=6
-
-[system.cpu.fuPool.FUList1.opList0]
-type=OpDesc
-opClass=IntMult
-opLat=3
-issueLat=1
-
-[system.cpu.fuPool.FUList1.opList1]
-type=OpDesc
-opClass=IntDiv
-opLat=20
-issueLat=19
-
-[system.cpu.fuPool.FUList1]
-type=FUDesc
-opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
-count=2
-
-[system.cpu.fuPool.FUList2.opList0]
-type=OpDesc
-opClass=FloatAdd
-opLat=2
-issueLat=1
-
-[system.cpu.fuPool.FUList2.opList1]
-type=OpDesc
-opClass=FloatCmp
-opLat=2
-issueLat=1
-
-[system.cpu.fuPool.FUList2.opList2]
-type=OpDesc
-opClass=FloatCvt
-opLat=2
-issueLat=1
-
-[system.cpu.fuPool.FUList2]
-type=FUDesc
-opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
-count=4
-
-[system.cpu.fuPool.FUList3.opList0]
-type=OpDesc
-opClass=FloatMult
-opLat=4
-issueLat=1
-
-[system.cpu.fuPool.FUList3.opList1]
-type=OpDesc
-opClass=FloatDiv
-opLat=12
-issueLat=12
-
-[system.cpu.fuPool.FUList3.opList2]
-type=OpDesc
-opClass=FloatSqrt
-opLat=24
-issueLat=24
-
-[system.cpu.fuPool.FUList3]
-type=FUDesc
-opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
-count=2
-
-[system.cpu.fuPool.FUList4.opList0]
-type=OpDesc
-opClass=MemRead
-opLat=1
-issueLat=1
-
-[system.cpu.fuPool.FUList4]
-type=FUDesc
-opList=system.cpu.fuPool.FUList4.opList0
-count=0
-
-[system.cpu.fuPool.FUList5.opList0]
-type=OpDesc
-opClass=MemWrite
-opLat=1
-issueLat=1
-
-[system.cpu.fuPool.FUList5]
-type=FUDesc
-opList=system.cpu.fuPool.FUList5.opList0
-count=0
-
-[system.cpu.fuPool.FUList6.opList0]
-type=OpDesc
-opClass=MemRead
-opLat=1
-issueLat=1
-
-[system.cpu.fuPool.FUList6.opList1]
-type=OpDesc
-opClass=MemWrite
-opLat=1
-issueLat=1
-
-[system.cpu.fuPool.FUList6]
-type=FUDesc
-opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1
-count=4
-
-[system.cpu.fuPool.FUList7.opList0]
-type=OpDesc
-opClass=IprAccess
-opLat=3
-issueLat=3
-
-[system.cpu.fuPool.FUList7]
-type=FUDesc
-opList=system.cpu.fuPool.FUList7.opList0
-count=1
-
-[system.cpu.fuPool]
-type=FUPool
-FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7
-
-[system.cpu]
-type=DerivO3CPU
-clock=1
-numThreads=1
-activity=0
-workload=system.cpu.workload
-mem=system.cpu.dcache
-checker=null
-max_insts_any_thread=0
-max_insts_all_threads=0
-max_loads_any_thread=0
-max_loads_all_threads=0
-cachePorts=200
-decodeToFetchDelay=1
-renameToFetchDelay=1
-iewToFetchDelay=1
-commitToFetchDelay=1
-fetchWidth=8
-renameToDecodeDelay=1
-iewToDecodeDelay=1
-commitToDecodeDelay=1
-fetchToDecodeDelay=1
-decodeWidth=8
-iewToRenameDelay=1
-commitToRenameDelay=1
-decodeToRenameDelay=1
-renameWidth=8
-commitToIEWDelay=1
-renameToIEWDelay=2
-issueToExecuteDelay=1
-dispatchWidth=8
-issueWidth=8
-wbWidth=8
-wbDepth=1
-fuPool=system.cpu.fuPool
-iewToCommitDelay=1
-renameToROBDelay=1
-commitWidth=8
-squashWidth=8
-trapLatency=13
-backComSize=5
-forwardComSize=5
-predType=tournament
-localPredictorSize=2048
-localCtrBits=2
-localHistoryTableSize=2048
-localHistoryBits=11
-globalPredictorSize=8192
-globalCtrBits=2
-globalHistoryBits=13
-choicePredictorSize=8192
-choiceCtrBits=2
-BTBEntries=4096
-BTBTagSize=16
-RASSize=16
-LQEntries=32
-SQEntries=32
-LFSTSize=1024
-SSITSize=1024
-numPhysIntRegs=256
-numPhysFloatRegs=256
-numIQEntries=64
-numROBEntries=192
-smtNumFetchingThreads=1
-smtFetchPolicy=SingleThread
-smtLSQPolicy=Partitioned
-smtLSQThreshold=100
-smtIQPolicy=Partitioned
-smtIQThreshold=100
-smtROBPolicy=Partitioned
-smtROBThreshold=100
-smtCommitPolicy=RoundRobin
-instShiftAmt=2
-defer_registration=false
-function_trace=false
-function_trace_start=0
-
-[system.cpu.icache]
+[system.cpu.dcache]
type=BaseCache
-size=131072
+size=262144
assoc=2
block_size=64
latency=1
@@ -283,7 +112,6 @@ mshrs=10
tgts_per_mshr=5
write_buffers=8
prioritizeRequests=false
-do_copy=false
protocol=null
trace_addr=0
hash_delay=1
@@ -322,7 +150,6 @@ mshrs=10
tgts_per_mshr=5
write_buffers=8
prioritizeRequests=false
-do_copy=false
protocol=null
trace_addr=0
hash_delay=1
@@ -351,13 +178,10 @@ prefetch_use_cpu_id=true
prefetch_data_accesses_only=false
hit_latency=1
-[system.cpu.toL2Bus]
-type=Bus
-bus_id=0
-
[trace]
flags=
start=0
+cycle=0
bufsize=0
file=cout
dump_on_exit=false
@@ -396,8 +220,9 @@ print_cpseq=false
print_reg_delta=false
pc_symbol=true
intel_format=false
+legion_lockstep=false
trace_system=client
-[debug]
-break_cycles=
+[statsreset]
+reset_cycle=0
diff --git a/tests/long/30.eon/ref/alpha/linux/simple-timing/m5stats.txt b/tests/long/30.eon/ref/alpha/linux/simple-timing/m5stats.txt
index 5d4f9235a..28328cd0e 100644
--- a/tests/long/30.eon/ref/alpha/linux/simple-timing/m5stats.txt
+++ b/tests/long/30.eon/ref/alpha/linux/simple-timing/m5stats.txt
@@ -1,112 +1,67 @@
---------- Begin Simulation Statistics ----------
-global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-global.BPredUnit.BTBHits 542 # Number of BTB hits
-global.BPredUnit.BTBLookups 1938 # Number of BTB lookups
-global.BPredUnit.RASInCorrect 48 # Number of incorrect RAS predictions.
-global.BPredUnit.condIncorrect 420 # Number of conditional branches incorrect
-global.BPredUnit.condPredicted 1304 # Number of conditional branches predicted
-global.BPredUnit.lookups 2256 # Number of BP lookups
-global.BPredUnit.usedRAS 291 # Number of times the RAS was used to get a target.
-host_inst_rate 41797 # Simulator instruction rate (inst/s)
-host_mem_usage 160344 # Number of bytes of host memory used
-host_seconds 0.13 # Real time elapsed on the host
-host_tick_rate 50948 # Simulator tick rate (ticks/s)
-memdepunit.memDep.conflictingLoads 12 # Number of conflicting loads.
-memdepunit.memDep.conflictingStores 259 # Number of conflicting stores.
-memdepunit.memDep.insertedLoads 2050 # Number of loads inserted to the mem dependence unit.
-memdepunit.memDep.insertedStores 1221 # Number of stores inserted to the mem dependence unit.
+host_inst_rate 490401 # Simulator instruction rate (inst/s)
+host_mem_usage 178744 # Number of bytes of host memory used
+host_seconds 812.94 # Real time elapsed on the host
+host_tick_rate 734822 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 5623 # Number of instructions simulated
-sim_seconds 0.000000 # Number of seconds simulated
-sim_ticks 6870 # Number of ticks simulated
-system.cpu.commit.COM:branches 862 # Number of branches committed
-system.cpu.commit.COM:bw_lim_events 74 # number cycles where commit BW limit reached
-system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle.samples 6116
-system.cpu.commit.COM:committed_per_cycle.min_value 0
- 0 3908 6389.80%
- 1 1064 1739.70%
- 2 389 636.04%
- 3 210 343.36%
- 4 153 250.16%
- 5 93 152.06%
- 6 76 124.26%
- 7 149 243.62%
- 8 74 120.99%
-system.cpu.commit.COM:committed_per_cycle.max_value 8
-system.cpu.commit.COM:committed_per_cycle.end_dist
-
-system.cpu.commit.COM:count 5640 # Number of instructions committed
-system.cpu.commit.COM:loads 979 # Number of loads committed
-system.cpu.commit.COM:membars 0 # Number of memory barriers committed
-system.cpu.commit.COM:refs 1791 # Number of memory references committed
-system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.branchMispredicts 337 # The number of times a branch was mispredicted
-system.cpu.commit.commitCommittedInsts 5640 # The number of committed instructions
-system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.commitSquashedInsts 4350 # The number of squashed insts skipped by commit
-system.cpu.committedInsts 5623 # Number of Instructions Simulated
-system.cpu.committedInsts_total 5623 # Number of Instructions Simulated
-system.cpu.cpi 1.221768 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 1.221768 # CPI: Total CPI of All Threads
-system.cpu.dcache.ReadReq_accesses 1538 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 3.072000 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2.240000 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits 1413 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 384 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate 0.081274 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses 125 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_hits 25 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_miss_latency 224 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate 0.065020 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses 100 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_accesses 821 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 2.467742 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2.140845 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 635 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 459 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.226553 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 186 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_hits 108 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_miss_latency 152 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.086480 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 71 # number of WriteReq MSHR misses
+sim_insts 398664450 # Number of instructions simulated
+sim_seconds 0.000597 # Number of seconds simulated
+sim_ticks 597363012 # Number of ticks simulated
+system.cpu.dcache.ReadReq_accesses 94754482 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 3956.610526 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2956.610526 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits 94753532 # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency 3758780 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate 0.000010 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses 950 # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_miss_latency 2808780 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate 0.000010 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_misses 950 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_accesses 73520727 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_avg_miss_latency 3939.646399 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2939.646399 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits 73517520 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 12634446 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate 0.000044 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses 3207 # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_miss_latency 9427446 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.000044 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses 3207 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles_no_targets 0.800000 # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 11.505618 # Average number of references to valid blocks.
+system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu.dcache.avg_refs 40478.963676 # Average number of references to valid blocks.
system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_no_targets 5 # number of cycles access was blocked
+system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles_no_targets 4 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.demand_accesses 2359 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 2.710611 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 2.198830 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 2048 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 843 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.131836 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 311 # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits 133 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 376 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate 0.072488 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 171 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_accesses 168275209 # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency 3943.523214 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 2943.523214 # average overall mshr miss latency
+system.cpu.dcache.demand_hits 168271052 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 16393226 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate 0.000025 # miss rate for demand accesses
+system.cpu.dcache.demand_misses 4157 # number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency 12236226 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate 0.000025 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses 4157 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.overall_accesses 2359 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 2.710611 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 2.198830 # average overall mshr miss latency
+system.cpu.dcache.overall_accesses 168275209 # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency 3943.523214 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 2943.523214 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 2048 # number of overall hits
-system.cpu.dcache.overall_miss_latency 843 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.131836 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 311 # number of overall misses
-system.cpu.dcache.overall_mshr_hits 133 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 376 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate 0.072488 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 171 # number of overall MSHR misses
+system.cpu.dcache.overall_hits 168271052 # number of overall hits
+system.cpu.dcache.overall_miss_latency 16393226 # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate 0.000025 # miss rate for overall accesses
+system.cpu.dcache.overall_misses 4157 # number of overall misses
+system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_miss_latency 12236226 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate 0.000025 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses 4157 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@@ -118,92 +73,57 @@ system.cpu.dcache.prefetcher.num_hwpf_issued 0
system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.dcache.replacements 0 # number of replacements
-system.cpu.dcache.sampled_refs 178 # Sample count of references to valid blocks.
+system.cpu.dcache.replacements 764 # number of replacements
+system.cpu.dcache.sampled_refs 4157 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 119.831029 # Cycle average of tags in use
-system.cpu.dcache.total_refs 2048 # Total number of references to valid blocks.
+system.cpu.dcache.tagsinuse 3222.448687 # Cycle average of tags in use
+system.cpu.dcache.total_refs 168271052 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks 0 # number of writebacks
-system.cpu.decode.DECODE:BlockedCycles 387 # Number of cycles decode is blocked
-system.cpu.decode.DECODE:BranchMispred 93 # Number of times decode detected a branch misprediction
-system.cpu.decode.DECODE:BranchResolved 185 # Number of times decode resolved a branch
-system.cpu.decode.DECODE:DecodedInsts 12349 # Number of instructions handled by decode
-system.cpu.decode.DECODE:IdleCycles 3542 # Number of cycles decode is idle
-system.cpu.decode.DECODE:RunCycles 2158 # Number of cycles decode is running
-system.cpu.decode.DECODE:SquashCycles 754 # Number of cycles decode is squashing
-system.cpu.decode.DECODE:SquashedInsts 286 # Number of squashed instructions handled by decode
-system.cpu.decode.DECODE:UnblockCycles 30 # Number of cycles decode is unblocking
-system.cpu.fetch.Branches 2256 # Number of branches that fetch encountered
-system.cpu.fetch.CacheLines 1582 # Number of cache lines fetched
-system.cpu.fetch.Cycles 3905 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.IcacheSquashes 148 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.Insts 13707 # Number of instructions fetch has processed
-system.cpu.fetch.SquashCycles 456 # Number of cycles fetch has spent squashing
-system.cpu.fetch.branchRate 0.328336 # Number of branch fetches per cycle
-system.cpu.fetch.icacheStallCycles 1582 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.predictedBranches 833 # Number of branches that fetch has predicted taken
-system.cpu.fetch.rate 1.994906 # Number of inst fetches per cycle
-system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist.samples 6871
-system.cpu.fetch.rateDist.min_value 0
- 0 4549 6620.58%
- 1 174 253.24%
- 2 186 270.70%
- 3 157 228.50%
- 4 211 307.09%
- 5 153 222.68%
- 6 171 248.87%
- 7 105 152.82%
- 8 1165 1695.53%
-system.cpu.fetch.rateDist.max_value 8
-system.cpu.fetch.rateDist.end_dist
-
-system.cpu.icache.ReadReq_accesses 1582 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 2.960245 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 1.996885 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits 1255 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 968 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate 0.206700 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses 327 # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_hits 6 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_miss_latency 641 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.202908 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses 321 # number of ReadReq MSHR misses
-system.cpu.icache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles_no_targets no value # average number of cycles each access was blocked
-system.cpu.icache.avg_refs 3.909657 # Average number of references to valid blocks.
+system.cpu.dcache.writebacks 625 # number of writebacks
+system.cpu.icache.ReadReq_accesses 398664451 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency 3820.892216 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 2820.892216 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits 398660777 # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency 14037958 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_rate 0.000009 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_misses 3674 # number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_miss_latency 10363958 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate 0.000009 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_misses 3674 # number of ReadReq MSHR misses
+system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu.icache.avg_refs 108508.649156 # Average number of references to valid blocks.
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.demand_accesses 1582 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 2.960245 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 1.996885 # average overall mshr miss latency
-system.cpu.icache.demand_hits 1255 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 968 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate 0.206700 # miss rate for demand accesses
-system.cpu.icache.demand_misses 327 # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_hits 6 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 641 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate 0.202908 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses 321 # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_accesses 398664451 # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency 3820.892216 # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 2820.892216 # average overall mshr miss latency
+system.cpu.icache.demand_hits 398660777 # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency 14037958 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_rate 0.000009 # miss rate for demand accesses
+system.cpu.icache.demand_misses 3674 # number of demand (read+write) misses
+system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_miss_latency 10363958 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_rate 0.000009 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_misses 3674 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.overall_accesses 1582 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 2.960245 # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 1.996885 # average overall mshr miss latency
+system.cpu.icache.overall_accesses 398664451 # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency 3820.892216 # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 2820.892216 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits 1255 # number of overall hits
-system.cpu.icache.overall_miss_latency 968 # number of overall miss cycles
-system.cpu.icache.overall_miss_rate 0.206700 # miss rate for overall accesses
-system.cpu.icache.overall_misses 327 # number of overall misses
-system.cpu.icache.overall_mshr_hits 6 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 641 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate 0.202908 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses 321 # number of overall MSHR misses
+system.cpu.icache.overall_hits 398660777 # number of overall hits
+system.cpu.icache.overall_miss_latency 14037958 # number of overall miss cycles
+system.cpu.icache.overall_miss_rate 0.000009 # miss rate for overall accesses
+system.cpu.icache.overall_misses 3674 # number of overall misses
+system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_miss_latency 10363958 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_rate 0.000009 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_misses 3674 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@@ -215,1726 +135,60 @@ system.cpu.icache.prefetcher.num_hwpf_issued 0
system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.icache.replacements 0 # number of replacements
-system.cpu.icache.sampled_refs 321 # Sample count of references to valid blocks.
+system.cpu.icache.replacements 1770 # number of replacements
+system.cpu.icache.sampled_refs 3674 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 176.393247 # Cycle average of tags in use
-system.cpu.icache.total_refs 1255 # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse 1765.884663 # Cycle average of tags in use
+system.cpu.icache.total_refs 398660777 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.iew.EXEC:branches 1206 # Number of branches executed
-system.cpu.iew.EXEC:insts 7969 # Number of executed instructions
-system.cpu.iew.EXEC:loads 1610 # Number of load instructions executed
-system.cpu.iew.EXEC:nop 37 # number of nop insts executed
-system.cpu.iew.EXEC:rate 1.159802 # Inst execution rate
-system.cpu.iew.EXEC:refs 2599 # number of memory reference insts executed
-system.cpu.iew.EXEC:squashedInsts 419 # Number of squashed instructions skipped in execute
-system.cpu.iew.EXEC:stores 989 # Number of stores executed
-system.cpu.iew.EXEC:swp 0 # number of swp insts executed
-system.cpu.iew.WB:consumers 5438 # num instructions consuming a value
-system.cpu.iew.WB:count 7722 # cumulative count of insts written-back
-system.cpu.iew.WB:fanout 0.744575 # average fanout of values written-back
-system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.iew.WB:producers 4049 # num instructions producing a value
-system.cpu.iew.WB:rate 1.123854 # insts written-back per cycle
-system.cpu.iew.WB:sent 7762 # cumulative count of insts sent to commit
-system.cpu.iew.branchMispredicts 393 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewBlockCycles 4 # Number of cycles IEW is blocking
-system.cpu.iew.iewDispLoadInsts 2050 # Number of dispatched load instructions
-system.cpu.iew.iewDispNonSpecInsts 21 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewDispSquashedInsts 272 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispStoreInsts 1221 # Number of dispatched store instructions
-system.cpu.iew.iewDispatchedInsts 9990 # Number of instructions dispatched to IQ
-system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.iewSquashCycles 754 # Number of cycles IEW is squashing
-system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking
-system.cpu.iew.lsq.thread.0.blockedLoads 1 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread.0.cacheBlocked 5 # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.lsq.thread.0.forwLoads 55 # Number of loads that had data forwarded from stores
-system.cpu.iew.lsq.thread.0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
-system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread.0.squashedLoads 1071 # Number of loads squashed
-system.cpu.iew.lsq.thread.0.squashedStores 409 # Number of stores squashed
-system.cpu.iew.memOrderViolationEvents 41 # Number of memory order violations
-system.cpu.iew.predictedNotTakenIncorrect 296 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.predictedTakenIncorrect 97 # Number of branches that were predicted taken incorrectly
-system.cpu.ipc 0.818486 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.818486 # IPC: Total IPC of All Threads
-system.cpu.iq.IQ:residence:(null).start_dist # cycles from dispatch to issue
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-
-system.cpu.iq.IQ:residence:IntMult.start_dist # cycles from dispatch to issue
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-
-system.cpu.iq.ISSUE:IntMult_delay.start_dist # cycles from operands ready to issue
-system.cpu.iq.ISSUE:IntMult_delay.samples 0
-system.cpu.iq.ISSUE:IntMult_delay.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
- 20 0
- 22 0
- 24 0
- 26 0
- 28 0
- 30 0
- 32 0
- 34 0
- 36 0
- 38 0
- 40 0
- 42 0
- 44 0
- 46 0
- 48 0
- 50 0
- 52 0
- 54 0
- 56 0
- 58 0
- 60 0
- 62 0
- 64 0
- 66 0
- 68 0
- 70 0
- 72 0
- 74 0
- 76 0
- 78 0
- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.ISSUE:IntMult_delay.max_value 0
-system.cpu.iq.ISSUE:IntMult_delay.end_dist
-
-system.cpu.iq.ISSUE:IntDiv_delay.start_dist # cycles from operands ready to issue
-system.cpu.iq.ISSUE:IntDiv_delay.samples 0
-system.cpu.iq.ISSUE:IntDiv_delay.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
- 20 0
- 22 0
- 24 0
- 26 0
- 28 0
- 30 0
- 32 0
- 34 0
- 36 0
- 38 0
- 40 0
- 42 0
- 44 0
- 46 0
- 48 0
- 50 0
- 52 0
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- 56 0
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- 76 0
- 78 0
- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.ISSUE:IntDiv_delay.max_value 0
-system.cpu.iq.ISSUE:IntDiv_delay.end_dist
-
-system.cpu.iq.ISSUE:FloatAdd_delay.start_dist # cycles from operands ready to issue
-system.cpu.iq.ISSUE:FloatAdd_delay.samples 0
-system.cpu.iq.ISSUE:FloatAdd_delay.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
- 20 0
- 22 0
- 24 0
- 26 0
- 28 0
- 30 0
- 32 0
- 34 0
- 36 0
- 38 0
- 40 0
- 42 0
- 44 0
- 46 0
- 48 0
- 50 0
- 52 0
- 54 0
- 56 0
- 58 0
- 60 0
- 62 0
- 64 0
- 66 0
- 68 0
- 70 0
- 72 0
- 74 0
- 76 0
- 78 0
- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.ISSUE:FloatAdd_delay.max_value 0
-system.cpu.iq.ISSUE:FloatAdd_delay.end_dist
-
-system.cpu.iq.ISSUE:FloatCmp_delay.start_dist # cycles from operands ready to issue
-system.cpu.iq.ISSUE:FloatCmp_delay.samples 0
-system.cpu.iq.ISSUE:FloatCmp_delay.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
- 20 0
- 22 0
- 24 0
- 26 0
- 28 0
- 30 0
- 32 0
- 34 0
- 36 0
- 38 0
- 40 0
- 42 0
- 44 0
- 46 0
- 48 0
- 50 0
- 52 0
- 54 0
- 56 0
- 58 0
- 60 0
- 62 0
- 64 0
- 66 0
- 68 0
- 70 0
- 72 0
- 74 0
- 76 0
- 78 0
- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.ISSUE:FloatCmp_delay.max_value 0
-system.cpu.iq.ISSUE:FloatCmp_delay.end_dist
-
-system.cpu.iq.ISSUE:FloatCvt_delay.start_dist # cycles from operands ready to issue
-system.cpu.iq.ISSUE:FloatCvt_delay.samples 0
-system.cpu.iq.ISSUE:FloatCvt_delay.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
- 20 0
- 22 0
- 24 0
- 26 0
- 28 0
- 30 0
- 32 0
- 34 0
- 36 0
- 38 0
- 40 0
- 42 0
- 44 0
- 46 0
- 48 0
- 50 0
- 52 0
- 54 0
- 56 0
- 58 0
- 60 0
- 62 0
- 64 0
- 66 0
- 68 0
- 70 0
- 72 0
- 74 0
- 76 0
- 78 0
- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.ISSUE:FloatCvt_delay.max_value 0
-system.cpu.iq.ISSUE:FloatCvt_delay.end_dist
-
-system.cpu.iq.ISSUE:FloatMult_delay.start_dist # cycles from operands ready to issue
-system.cpu.iq.ISSUE:FloatMult_delay.samples 0
-system.cpu.iq.ISSUE:FloatMult_delay.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
- 20 0
- 22 0
- 24 0
- 26 0
- 28 0
- 30 0
- 32 0
- 34 0
- 36 0
- 38 0
- 40 0
- 42 0
- 44 0
- 46 0
- 48 0
- 50 0
- 52 0
- 54 0
- 56 0
- 58 0
- 60 0
- 62 0
- 64 0
- 66 0
- 68 0
- 70 0
- 72 0
- 74 0
- 76 0
- 78 0
- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.ISSUE:FloatMult_delay.max_value 0
-system.cpu.iq.ISSUE:FloatMult_delay.end_dist
-
-system.cpu.iq.ISSUE:FloatDiv_delay.start_dist # cycles from operands ready to issue
-system.cpu.iq.ISSUE:FloatDiv_delay.samples 0
-system.cpu.iq.ISSUE:FloatDiv_delay.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
- 20 0
- 22 0
- 24 0
- 26 0
- 28 0
- 30 0
- 32 0
- 34 0
- 36 0
- 38 0
- 40 0
- 42 0
- 44 0
- 46 0
- 48 0
- 50 0
- 52 0
- 54 0
- 56 0
- 58 0
- 60 0
- 62 0
- 64 0
- 66 0
- 68 0
- 70 0
- 72 0
- 74 0
- 76 0
- 78 0
- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.ISSUE:FloatDiv_delay.max_value 0
-system.cpu.iq.ISSUE:FloatDiv_delay.end_dist
-
-system.cpu.iq.ISSUE:FloatSqrt_delay.start_dist # cycles from operands ready to issue
-system.cpu.iq.ISSUE:FloatSqrt_delay.samples 0
-system.cpu.iq.ISSUE:FloatSqrt_delay.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
- 20 0
- 22 0
- 24 0
- 26 0
- 28 0
- 30 0
- 32 0
- 34 0
- 36 0
- 38 0
- 40 0
- 42 0
- 44 0
- 46 0
- 48 0
- 50 0
- 52 0
- 54 0
- 56 0
- 58 0
- 60 0
- 62 0
- 64 0
- 66 0
- 68 0
- 70 0
- 72 0
- 74 0
- 76 0
- 78 0
- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.ISSUE:FloatSqrt_delay.max_value 0
-system.cpu.iq.ISSUE:FloatSqrt_delay.end_dist
-
-system.cpu.iq.ISSUE:MemRead_delay.start_dist # cycles from operands ready to issue
-system.cpu.iq.ISSUE:MemRead_delay.samples 0
-system.cpu.iq.ISSUE:MemRead_delay.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
- 20 0
- 22 0
- 24 0
- 26 0
- 28 0
- 30 0
- 32 0
- 34 0
- 36 0
- 38 0
- 40 0
- 42 0
- 44 0
- 46 0
- 48 0
- 50 0
- 52 0
- 54 0
- 56 0
- 58 0
- 60 0
- 62 0
- 64 0
- 66 0
- 68 0
- 70 0
- 72 0
- 74 0
- 76 0
- 78 0
- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.ISSUE:MemRead_delay.max_value 0
-system.cpu.iq.ISSUE:MemRead_delay.end_dist
-
-system.cpu.iq.ISSUE:MemWrite_delay.start_dist # cycles from operands ready to issue
-system.cpu.iq.ISSUE:MemWrite_delay.samples 0
-system.cpu.iq.ISSUE:MemWrite_delay.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
- 20 0
- 22 0
- 24 0
- 26 0
- 28 0
- 30 0
- 32 0
- 34 0
- 36 0
- 38 0
- 40 0
- 42 0
- 44 0
- 46 0
- 48 0
- 50 0
- 52 0
- 54 0
- 56 0
- 58 0
- 60 0
- 62 0
- 64 0
- 66 0
- 68 0
- 70 0
- 72 0
- 74 0
- 76 0
- 78 0
- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.ISSUE:MemWrite_delay.max_value 0
-system.cpu.iq.ISSUE:MemWrite_delay.end_dist
-
-system.cpu.iq.ISSUE:IprAccess_delay.start_dist # cycles from operands ready to issue
-system.cpu.iq.ISSUE:IprAccess_delay.samples 0
-system.cpu.iq.ISSUE:IprAccess_delay.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
- 20 0
- 22 0
- 24 0
- 26 0
- 28 0
- 30 0
- 32 0
- 34 0
- 36 0
- 38 0
- 40 0
- 42 0
- 44 0
- 46 0
- 48 0
- 50 0
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- 54 0
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- 62 0
- 64 0
- 66 0
- 68 0
- 70 0
- 72 0
- 74 0
- 76 0
- 78 0
- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.ISSUE:IprAccess_delay.max_value 0
-system.cpu.iq.ISSUE:IprAccess_delay.end_dist
-
-system.cpu.iq.ISSUE:InstPrefetch_delay.start_dist # cycles from operands ready to issue
-system.cpu.iq.ISSUE:InstPrefetch_delay.samples 0
-system.cpu.iq.ISSUE:InstPrefetch_delay.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
- 20 0
- 22 0
- 24 0
- 26 0
- 28 0
- 30 0
- 32 0
- 34 0
- 36 0
- 38 0
- 40 0
- 42 0
- 44 0
- 46 0
- 48 0
- 50 0
- 52 0
- 54 0
- 56 0
- 58 0
- 60 0
- 62 0
- 64 0
- 66 0
- 68 0
- 70 0
- 72 0
- 74 0
- 76 0
- 78 0
- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.ISSUE:InstPrefetch_delay.max_value 0
-system.cpu.iq.ISSUE:InstPrefetch_delay.end_dist
-
-system.cpu.iq.ISSUE:FU_type_0 8388 # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0.start_dist
- (null) 2 0.02% # Type of FU issued
- IntAlu 5594 66.69% # Type of FU issued
- IntMult 1 0.01% # Type of FU issued
- IntDiv 0 0.00% # Type of FU issued
- FloatAdd 2 0.02% # Type of FU issued
- FloatCmp 0 0.00% # Type of FU issued
- FloatCvt 0 0.00% # Type of FU issued
- FloatMult 0 0.00% # Type of FU issued
- FloatDiv 0 0.00% # Type of FU issued
- FloatSqrt 0 0.00% # Type of FU issued
- MemRead 1757 20.95% # Type of FU issued
- MemWrite 1032 12.30% # Type of FU issued
- IprAccess 0 0.00% # Type of FU issued
- InstPrefetch 0 0.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0.end_dist
-system.cpu.iq.ISSUE:fu_busy_cnt 115 # FU busy when requested
-system.cpu.iq.ISSUE:fu_busy_rate 0.013710 # FU busy rate (busy events/executed inst)
-system.cpu.iq.ISSUE:fu_full.start_dist
- (null) 0 0.00% # attempts to use FU when none available
- IntAlu 1 0.87% # attempts to use FU when none available
- IntMult 0 0.00% # attempts to use FU when none available
- IntDiv 0 0.00% # attempts to use FU when none available
- FloatAdd 0 0.00% # attempts to use FU when none available
- FloatCmp 0 0.00% # attempts to use FU when none available
- FloatCvt 0 0.00% # attempts to use FU when none available
- FloatMult 0 0.00% # attempts to use FU when none available
- FloatDiv 0 0.00% # attempts to use FU when none available
- FloatSqrt 0 0.00% # attempts to use FU when none available
- MemRead 76 66.09% # attempts to use FU when none available
- MemWrite 38 33.04% # attempts to use FU when none available
- IprAccess 0 0.00% # attempts to use FU when none available
- InstPrefetch 0 0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full.end_dist
-system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle.samples 6871
-system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
- 0 3753 5462.09%
- 1 894 1301.12%
- 2 723 1052.25%
- 3 614 893.61%
- 4 451 656.38%
- 5 279 406.05%
- 6 104 151.36%
- 7 41 59.67%
- 8 12 17.46%
-system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
-system.cpu.iq.ISSUE:issued_per_cycle.end_dist
-
-system.cpu.iq.ISSUE:rate 1.220783 # Inst issue rate
-system.cpu.iq.iqInstsAdded 9932 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqInstsIssued 8388 # Number of instructions issued
-system.cpu.iq.iqNonSpecInstsAdded 21 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqSquashedInstsExamined 3990 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedInstsIssued 21 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedNonSpecRemoved 4 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.iqSquashedOperandsExamined 2486 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.l2cache.ReadReq_accesses 499 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 2.042254 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency 1015 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate 0.995992 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses 497 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 490 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.981964 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses 490 # number of ReadReq MSHR misses
+system.cpu.idle_fraction 0 # Percentage of idle cycles
+system.cpu.l2cache.ReadReq_accesses 7831 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_avg_miss_latency 2982.860028 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1924.618942 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_hits 651 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_miss_latency 21416935 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate 0.916869 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses 7180 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency 13818764 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.916869 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses 7180 # number of ReadReq MSHR misses
+system.cpu.l2cache.WriteReqNoAck|Writeback_accesses 625 # number of WriteReqNoAck|Writeback accesses(hits+misses)
+system.cpu.l2cache.WriteReqNoAck|Writeback_hits 625 # number of WriteReqNoAck|Writeback hits
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs 0.004024 # Average number of references to valid blocks.
+system.cpu.l2cache.avg_refs 0.177716 # Average number of references to valid blocks.
system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.demand_accesses 499 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 2.042254 # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 1 # average overall mshr miss latency
-system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 1015 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate 0.995992 # miss rate for demand accesses
-system.cpu.l2cache.demand_misses 497 # number of demand (read+write) misses
+system.cpu.l2cache.demand_accesses 7831 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_avg_miss_latency 2982.860028 # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 1924.618942 # average overall mshr miss latency
+system.cpu.l2cache.demand_hits 651 # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency 21416935 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate 0.916869 # miss rate for demand accesses
+system.cpu.l2cache.demand_misses 7180 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency 490 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate 0.981964 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses 490 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_miss_latency 13818764 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate 0.916869 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses 7180 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.overall_accesses 499 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 2.042254 # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 1 # average overall mshr miss latency
+system.cpu.l2cache.overall_accesses 8456 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_avg_miss_latency 2982.860028 # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 1924.618942 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits 2 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 1015 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate 0.995992 # miss rate for overall accesses
-system.cpu.l2cache.overall_misses 497 # number of overall misses
+system.cpu.l2cache.overall_hits 1276 # number of overall hits
+system.cpu.l2cache.overall_miss_latency 21416935 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate 0.849101 # miss rate for overall accesses
+system.cpu.l2cache.overall_misses 7180 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 490 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate 0.981964 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses 490 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_miss_latency 13818764 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate 0.849101 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses 7180 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@@ -1947,28 +201,16 @@ system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.l2cache.replacements 0 # number of replacements
-system.cpu.l2cache.sampled_refs 497 # Sample count of references to valid blocks.
+system.cpu.l2cache.sampled_refs 7180 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 295.773395 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks.
+system.cpu.l2cache.tagsinuse 6344.085280 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 1276 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks
-system.cpu.numCycles 6871 # number of cpu cycles simulated
-system.cpu.rename.RENAME:BlockCycles 4 # Number of cycles rename is blocking
-system.cpu.rename.RENAME:CommittedMaps 4051 # Number of HB maps that are committed
-system.cpu.rename.RENAME:IdleCycles 3758 # Number of cycles rename is idle
-system.cpu.rename.RENAME:LSQFullEvents 62 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RENAME:RenameLookups 14786 # Number of register rename lookups that rename has made
-system.cpu.rename.RENAME:RenamedInsts 11555 # Number of instructions processed by rename
-system.cpu.rename.RENAME:RenamedOperands 8634 # Number of destination operands rename has renamed
-system.cpu.rename.RENAME:RunCycles 1975 # Number of cycles rename is running
-system.cpu.rename.RENAME:SquashCycles 754 # Number of cycles rename is squashing
-system.cpu.rename.RENAME:UnblockCycles 111 # Number of cycles rename is unblocking
-system.cpu.rename.RENAME:UndoneMaps 4583 # Number of HB maps that are undone due to squashing
-system.cpu.rename.RENAME:serializeStallCycles 269 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RENAME:serializingInsts 26 # count of serializing insts renamed
-system.cpu.rename.RENAME:skidInsts 408 # count of insts added to the skid buffer
-system.cpu.rename.RENAME:tempSerializingInsts 21 # count of temporary serializing insts renamed
-system.cpu.workload.PROG:num_syscalls 17 # Number of system calls
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.numCycles 597363012 # number of cpu cycles simulated
+system.cpu.num_insts 398664450 # Number of instructions executed
+system.cpu.num_refs 174183390 # Number of memory references
+system.cpu.workload.PROG:num_syscalls 215 # Number of system calls
---------- End Simulation Statistics ----------
diff --git a/tests/long/30.eon/ref/alpha/linux/simple-timing/stderr b/tests/long/30.eon/ref/alpha/linux/simple-timing/stderr
index 8893caac8..1d6957eca 100644
--- a/tests/long/30.eon/ref/alpha/linux/simple-timing/stderr
+++ b/tests/long/30.eon/ref/alpha/linux/simple-timing/stderr
@@ -1,3 +1,47 @@
warn: Entering event queue @ 0. Starting simulation...
-warn: cycle 0: fault (page_table_fault) detected @ PC 0x000000
-warn: Increasing stack 0x11ff92000:0x11ff9b000 to 0x11ff90000:0x11ff9b000 because of access to 0x11ff91ff0
+getting pixel output filename pixels_out.cook
+opening control file chair.control.cook
+opening camera file chair.camera
+opening surfaces file chair.surfaces
+reading data
+processing 8parts
+Grid measure is 6 by 3.0001 by 6
+cell dimension is 0.863065
+Creating grid for list of length 21
+Grid size = 7 by 4 by 7
+Total occupancy = 236
+reading control stream
+reading camera stream
+Writing to chair.cook.ppm
+calculating 15 by 15 image with 196 samples
+col 0. . .
+col 1. . .
+col 2. . .
+col 3. . .
+col 4. . .
+col 5. . .
+col 6. . .
+col 7. . .
+col 8. . .
+col 9. . .
+col 10. . .
+col 11. . .
+col 12. . .
+col 13. . .
+col 14. . .
+Writing to chair.cook.ppm
+0 8 14
+1 8 14
+2 8 14
+3 8 14
+4 8 14
+5 8 14
+6 8 14
+7 8 14
+8 8 14
+9 8 14
+10 8 14
+11 8 14
+12 8 14
+13 8 14
+14 8 14
diff --git a/tests/long/30.eon/ref/alpha/linux/simple-timing/stdout b/tests/long/30.eon/ref/alpha/linux/simple-timing/stdout
index fbb329a2f..039e2d4ce 100644
--- a/tests/long/30.eon/ref/alpha/linux/simple-timing/stdout
+++ b/tests/long/30.eon/ref/alpha/linux/simple-timing/stdout
@@ -1,13 +1,2 @@
-Hello world!
-M5 Simulator System
-
-Copyright (c) 2001-2006
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Sep 5 2006 15:28:48
-M5 started Tue Sep 5 15:42:12 2006
-M5 executing on zizzer.eecs.umich.edu
-command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/o3-timing tests/run.py quick/00.hello/alpha/linux/o3-timing
-Exiting @ tick 6870 because target called exit()
+Eon, Version 1.1
+OO-style eon Time= 0.000000
diff --git a/tests/long/40.perlbmk/ref/alpha/linux/simple-atomic/config.ini b/tests/long/40.perlbmk/ref/alpha/linux/simple-atomic/config.ini
index c3a59fbce..81e1071eb 100644
--- a/tests/long/40.perlbmk/ref/alpha/linux/simple-atomic/config.ini
+++ b/tests/long/40.perlbmk/ref/alpha/linux/simple-atomic/config.ini
@@ -7,11 +7,9 @@ max_tick=0
output_file=cout
progress_interval=0
-[debug]
-break_cycles=
-
[exetrace]
intel_format=false
+legion_lockstep=false
pc_symbol=true
print_cpseq=false
print_cycle=true
@@ -53,352 +51,49 @@ mem_mode=atomic
physmem=system.physmem
[system.cpu]
-type=DerivO3CPU
-children=dcache fuPool icache l2cache toL2Bus workload
-BTBEntries=4096
-BTBTagSize=16
-LFSTSize=1024
-LQEntries=32
-RASSize=16
-SQEntries=32
-SSITSize=1024
-activity=0
-backComSize=5
-choiceCtrBits=2
-choicePredictorSize=8192
+type=AtomicSimpleCPU
+children=workload
clock=1
-commitToDecodeDelay=1
-commitToFetchDelay=1
-commitToIEWDelay=1
-commitToRenameDelay=1
-commitWidth=8
-decodeToFetchDelay=1
-decodeToRenameDelay=1
-decodeWidth=8
+cpu_id=0
defer_registration=false
-dispatchWidth=8
-fetchToDecodeDelay=1
-fetchTrapLatency=1
-fetchWidth=8
-forwardComSize=5
-fuPool=system.cpu.fuPool
function_trace=false
function_trace_start=0
-globalCtrBits=2
-globalHistoryBits=13
-globalPredictorSize=8192
-iewToCommitDelay=1
-iewToDecodeDelay=1
-iewToFetchDelay=1
-iewToRenameDelay=1
-instShiftAmt=2
-issueToExecuteDelay=1
-issueWidth=8
-localCtrBits=2
-localHistoryBits=11
-localHistoryTableSize=2048
-localPredictorSize=2048
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
-mem=system.cpu.dcache
-numIQEntries=64
-numPhysFloatRegs=256
-numPhysIntRegs=256
-numROBEntries=192
-numRobs=1
-numThreads=1
-predType=tournament
-renameToDecodeDelay=1
-renameToFetchDelay=1
-renameToIEWDelay=2
-renameToROBDelay=1
-renameWidth=8
-squashWidth=8
+phase=0
+progress_interval=0
+simulate_stalls=false
system=system
-trapLatency=13
-wbDepth=1
-wbWidth=8
+width=1
workload=system.cpu.workload
-dcache_port=system.cpu.dcache.cpu_side
-icache_port=system.cpu.icache.cpu_side
-
-[system.cpu.dcache]
-type=BaseCache
-adaptive_compression=false
-assoc=2
-block_size=64
-compressed_bus=false
-compression_latency=0
-do_copy=false
-hash_delay=1
-hit_latency=1
-latency=1
-lifo=false
-max_miss_count=0
-mshrs=10
-prefetch_access=false
-prefetch_cache_check_push=true
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10
-prefetch_miss=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
-prioritizeRequests=false
-protocol=Null
-repl=Null
-size=262144
-split=false
-split_size=0
-store_compressed=false
-subblock_size=0
-tgts_per_mshr=5
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu.dcache_port
-mem_side=system.cpu.toL2Bus.port[1]
-
-[system.cpu.fuPool]
-type=FUPool
-children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7
-FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7
-
-[system.cpu.fuPool.FUList0]
-type=FUDesc
-children=opList0
-count=6
-opList=system.cpu.fuPool.FUList0.opList0
-
-[system.cpu.fuPool.FUList0.opList0]
-type=OpDesc
-issueLat=1
-opClass=IntAlu
-opLat=1
-
-[system.cpu.fuPool.FUList1]
-type=FUDesc
-children=opList0 opList1
-count=2
-opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
-
-[system.cpu.fuPool.FUList1.opList0]
-type=OpDesc
-issueLat=1
-opClass=IntMult
-opLat=3
-
-[system.cpu.fuPool.FUList1.opList1]
-type=OpDesc
-issueLat=19
-opClass=IntDiv
-opLat=20
-
-[system.cpu.fuPool.FUList2]
-type=FUDesc
-children=opList0 opList1 opList2
-count=4
-opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
-
-[system.cpu.fuPool.FUList2.opList0]
-type=OpDesc
-issueLat=1
-opClass=FloatAdd
-opLat=2
-
-[system.cpu.fuPool.FUList2.opList1]
-type=OpDesc
-issueLat=1
-opClass=FloatCmp
-opLat=2
-
-[system.cpu.fuPool.FUList2.opList2]
-type=OpDesc
-issueLat=1
-opClass=FloatCvt
-opLat=2
-
-[system.cpu.fuPool.FUList3]
-type=FUDesc
-children=opList0 opList1 opList2
-count=2
-opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
-
-[system.cpu.fuPool.FUList3.opList0]
-type=OpDesc
-issueLat=1
-opClass=FloatMult
-opLat=4
-
-[system.cpu.fuPool.FUList3.opList1]
-type=OpDesc
-issueLat=12
-opClass=FloatDiv
-opLat=12
-
-[system.cpu.fuPool.FUList3.opList2]
-type=OpDesc
-issueLat=24
-opClass=FloatSqrt
-opLat=24
-
-[system.cpu.fuPool.FUList4]
-type=FUDesc
-children=opList0
-count=0
-opList=system.cpu.fuPool.FUList4.opList0
-
-[system.cpu.fuPool.FUList4.opList0]
-type=OpDesc
-issueLat=1
-opClass=MemRead
-opLat=1
-
-[system.cpu.fuPool.FUList5]
-type=FUDesc
-children=opList0
-count=0
-opList=system.cpu.fuPool.FUList5.opList0
-
-[system.cpu.fuPool.FUList5.opList0]
-type=OpDesc
-issueLat=1
-opClass=MemWrite
-opLat=1
-
-[system.cpu.fuPool.FUList6]
-type=FUDesc
-children=opList0 opList1
-count=4
-opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1
-
-[system.cpu.fuPool.FUList6.opList0]
-type=OpDesc
-issueLat=1
-opClass=MemRead
-opLat=1
-
-[system.cpu.fuPool.FUList6.opList1]
-type=OpDesc
-issueLat=1
-opClass=MemWrite
-opLat=1
-
-[system.cpu.fuPool.FUList7]
-type=FUDesc
-children=opList0
-count=1
-opList=system.cpu.fuPool.FUList7.opList0
-
-[system.cpu.fuPool.FUList7.opList0]
-type=OpDesc
-issueLat=3
-opClass=IprAccess
-opLat=3
-
-[system.cpu.icache]
-type=BaseCache
-adaptive_compression=false
-assoc=2
-block_size=64
-compressed_bus=false
-compression_latency=0
-do_copy=false
-hash_delay=1
-hit_latency=1
-latency=1
-lifo=false
-max_miss_count=0
-mshrs=10
-prefetch_access=false
-prefetch_cache_check_push=true
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10
-prefetch_miss=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
-prioritizeRequests=false
-protocol=Null
-repl=Null
-size=131072
-split=false
-split_size=0
-store_compressed=false
-subblock_size=0
-tgts_per_mshr=5
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu.icache_port
-mem_side=system.cpu.toL2Bus.port[0]
-
-[system.cpu.l2cache]
-type=BaseCache
-adaptive_compression=false
-assoc=2
-block_size=64
-compressed_bus=false
-compression_latency=0
-do_copy=false
-hash_delay=1
-hit_latency=1
-latency=1
-lifo=false
-max_miss_count=0
-mshrs=10
-prefetch_access=false
-prefetch_cache_check_push=true
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10
-prefetch_miss=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
-prioritizeRequests=false
-protocol=Null
-repl=Null
-size=2097152
-split=false
-split_size=0
-store_compressed=false
-subblock_size=0
-tgts_per_mshr=5
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[1]
-
-[system.cpu.toL2Bus]
-type=Bus
-bus_id=0
-port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+dcache_port=system.membus.port[2]
+icache_port=system.membus.port[1]
[system.cpu.workload]
type=LiveProcess
-cmd=hello
+cmd=perlbmk -I. -I lib lgred.makerand.pl
+cwd=build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/linux/simple-atomic
+egid=100
env=
-executable=tests/test-progs/hello/bin/alpha/linux/hello
+euid=100
+executable=/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk
+gid=100
input=cin
output=cout
+pid=100
+ppid=99
system=system
+uid=100
[system.membus]
type=Bus
bus_id=0
-port=system.physmem.port system.cpu.l2cache.mem_side
+clock=1000
+responder_set=false
+width=64
+port=system.physmem.port system.cpu.icache_port system.cpu.dcache_port
[system.physmem]
type=PhysicalMemory
@@ -409,6 +104,7 @@ port=system.membus.port[0]
[trace]
bufsize=0
+cycle=0
dump_on_exit=false
file=cout
flags=
diff --git a/tests/long/40.perlbmk/ref/alpha/linux/simple-atomic/config.out b/tests/long/40.perlbmk/ref/alpha/linux/simple-atomic/config.out
index f491a3081..e5012d953 100644
--- a/tests/long/40.perlbmk/ref/alpha/linux/simple-atomic/config.out
+++ b/tests/long/40.perlbmk/ref/alpha/linux/simple-atomic/config.out
@@ -19,345 +19,48 @@ mem_mode=atomic
[system.membus]
type=Bus
bus_id=0
+clock=1000
+width=64
+responder_set=false
[system.cpu.workload]
type=LiveProcess
-cmd=hello
-executable=tests/test-progs/hello/bin/alpha/linux/hello
+cmd=perlbmk -I. -I lib lgred.makerand.pl
+executable=/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk
input=cin
output=cout
env=
+cwd=build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/linux/simple-atomic
system=system
-
-[system.cpu.dcache]
-type=BaseCache
-size=262144
-assoc=2
-block_size=64
-latency=1
-mshrs=10
-tgts_per_mshr=5
-write_buffers=8
-prioritizeRequests=false
-do_copy=false
-protocol=null
-trace_addr=0
-hash_delay=1
-repl=null
-compressed_bus=false
-store_compressed=false
-adaptive_compression=false
-compression_latency=0
-block_size=64
-max_miss_count=0
-addr_range=[0,18446744073709551615]
-split=false
-split_size=0
-lifo=false
-two_queue=false
-prefetch_miss=false
-prefetch_access=false
-prefetcher_size=100
-prefetch_past_page=false
-prefetch_serial_squash=false
-prefetch_latency=10
-prefetch_degree=1
-prefetch_policy=none
-prefetch_cache_check_push=true
-prefetch_use_cpu_id=true
-prefetch_data_accesses_only=false
-hit_latency=1
-
-[system.cpu.fuPool.FUList0.opList0]
-type=OpDesc
-opClass=IntAlu
-opLat=1
-issueLat=1
-
-[system.cpu.fuPool.FUList0]
-type=FUDesc
-opList=system.cpu.fuPool.FUList0.opList0
-count=6
-
-[system.cpu.fuPool.FUList1.opList0]
-type=OpDesc
-opClass=IntMult
-opLat=3
-issueLat=1
-
-[system.cpu.fuPool.FUList1.opList1]
-type=OpDesc
-opClass=IntDiv
-opLat=20
-issueLat=19
-
-[system.cpu.fuPool.FUList1]
-type=FUDesc
-opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
-count=2
-
-[system.cpu.fuPool.FUList2.opList0]
-type=OpDesc
-opClass=FloatAdd
-opLat=2
-issueLat=1
-
-[system.cpu.fuPool.FUList2.opList1]
-type=OpDesc
-opClass=FloatCmp
-opLat=2
-issueLat=1
-
-[system.cpu.fuPool.FUList2.opList2]
-type=OpDesc
-opClass=FloatCvt
-opLat=2
-issueLat=1
-
-[system.cpu.fuPool.FUList2]
-type=FUDesc
-opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
-count=4
-
-[system.cpu.fuPool.FUList3.opList0]
-type=OpDesc
-opClass=FloatMult
-opLat=4
-issueLat=1
-
-[system.cpu.fuPool.FUList3.opList1]
-type=OpDesc
-opClass=FloatDiv
-opLat=12
-issueLat=12
-
-[system.cpu.fuPool.FUList3.opList2]
-type=OpDesc
-opClass=FloatSqrt
-opLat=24
-issueLat=24
-
-[system.cpu.fuPool.FUList3]
-type=FUDesc
-opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
-count=2
-
-[system.cpu.fuPool.FUList4.opList0]
-type=OpDesc
-opClass=MemRead
-opLat=1
-issueLat=1
-
-[system.cpu.fuPool.FUList4]
-type=FUDesc
-opList=system.cpu.fuPool.FUList4.opList0
-count=0
-
-[system.cpu.fuPool.FUList5.opList0]
-type=OpDesc
-opClass=MemWrite
-opLat=1
-issueLat=1
-
-[system.cpu.fuPool.FUList5]
-type=FUDesc
-opList=system.cpu.fuPool.FUList5.opList0
-count=0
-
-[system.cpu.fuPool.FUList6.opList0]
-type=OpDesc
-opClass=MemRead
-opLat=1
-issueLat=1
-
-[system.cpu.fuPool.FUList6.opList1]
-type=OpDesc
-opClass=MemWrite
-opLat=1
-issueLat=1
-
-[system.cpu.fuPool.FUList6]
-type=FUDesc
-opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1
-count=4
-
-[system.cpu.fuPool.FUList7.opList0]
-type=OpDesc
-opClass=IprAccess
-opLat=3
-issueLat=3
-
-[system.cpu.fuPool.FUList7]
-type=FUDesc
-opList=system.cpu.fuPool.FUList7.opList0
-count=1
-
-[system.cpu.fuPool]
-type=FUPool
-FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7
+uid=100
+euid=100
+gid=100
+egid=100
+pid=100
+ppid=99
[system.cpu]
-type=DerivO3CPU
-clock=1
-numThreads=1
-activity=0
-workload=system.cpu.workload
-mem=system.cpu.dcache
-checker=null
+type=AtomicSimpleCPU
max_insts_any_thread=0
max_insts_all_threads=0
max_loads_any_thread=0
max_loads_all_threads=0
-cachePorts=200
-decodeToFetchDelay=1
-renameToFetchDelay=1
-iewToFetchDelay=1
-commitToFetchDelay=1
-fetchWidth=8
-renameToDecodeDelay=1
-iewToDecodeDelay=1
-commitToDecodeDelay=1
-fetchToDecodeDelay=1
-decodeWidth=8
-iewToRenameDelay=1
-commitToRenameDelay=1
-decodeToRenameDelay=1
-renameWidth=8
-commitToIEWDelay=1
-renameToIEWDelay=2
-issueToExecuteDelay=1
-dispatchWidth=8
-issueWidth=8
-wbWidth=8
-wbDepth=1
-fuPool=system.cpu.fuPool
-iewToCommitDelay=1
-renameToROBDelay=1
-commitWidth=8
-squashWidth=8
-trapLatency=13
-backComSize=5
-forwardComSize=5
-predType=tournament
-localPredictorSize=2048
-localCtrBits=2
-localHistoryTableSize=2048
-localHistoryBits=11
-globalPredictorSize=8192
-globalCtrBits=2
-globalHistoryBits=13
-choicePredictorSize=8192
-choiceCtrBits=2
-BTBEntries=4096
-BTBTagSize=16
-RASSize=16
-LQEntries=32
-SQEntries=32
-LFSTSize=1024
-SSITSize=1024
-numPhysIntRegs=256
-numPhysFloatRegs=256
-numIQEntries=64
-numROBEntries=192
-smtNumFetchingThreads=1
-smtFetchPolicy=SingleThread
-smtLSQPolicy=Partitioned
-smtLSQThreshold=100
-smtIQPolicy=Partitioned
-smtIQThreshold=100
-smtROBPolicy=Partitioned
-smtROBThreshold=100
-smtCommitPolicy=RoundRobin
-instShiftAmt=2
+progress_interval=0
+system=system
+cpu_id=0
+workload=system.cpu.workload
+clock=1
+phase=0
defer_registration=false
+width=1
function_trace=false
function_trace_start=0
-
-[system.cpu.icache]
-type=BaseCache
-size=131072
-assoc=2
-block_size=64
-latency=1
-mshrs=10
-tgts_per_mshr=5
-write_buffers=8
-prioritizeRequests=false
-do_copy=false
-protocol=null
-trace_addr=0
-hash_delay=1
-repl=null
-compressed_bus=false
-store_compressed=false
-adaptive_compression=false
-compression_latency=0
-block_size=64
-max_miss_count=0
-addr_range=[0,18446744073709551615]
-split=false
-split_size=0
-lifo=false
-two_queue=false
-prefetch_miss=false
-prefetch_access=false
-prefetcher_size=100
-prefetch_past_page=false
-prefetch_serial_squash=false
-prefetch_latency=10
-prefetch_degree=1
-prefetch_policy=none
-prefetch_cache_check_push=true
-prefetch_use_cpu_id=true
-prefetch_data_accesses_only=false
-hit_latency=1
-
-[system.cpu.l2cache]
-type=BaseCache
-size=2097152
-assoc=2
-block_size=64
-latency=1
-mshrs=10
-tgts_per_mshr=5
-write_buffers=8
-prioritizeRequests=false
-do_copy=false
-protocol=null
-trace_addr=0
-hash_delay=1
-repl=null
-compressed_bus=false
-store_compressed=false
-adaptive_compression=false
-compression_latency=0
-block_size=64
-max_miss_count=0
-addr_range=[0,18446744073709551615]
-split=false
-split_size=0
-lifo=false
-two_queue=false
-prefetch_miss=false
-prefetch_access=false
-prefetcher_size=100
-prefetch_past_page=false
-prefetch_serial_squash=false
-prefetch_latency=10
-prefetch_degree=1
-prefetch_policy=none
-prefetch_cache_check_push=true
-prefetch_use_cpu_id=true
-prefetch_data_accesses_only=false
-hit_latency=1
-
-[system.cpu.toL2Bus]
-type=Bus
-bus_id=0
+simulate_stalls=false
[trace]
flags=
start=0
+cycle=0
bufsize=0
file=cout
dump_on_exit=false
@@ -396,8 +99,9 @@ print_cpseq=false
print_reg_delta=false
pc_symbol=true
intel_format=false
+legion_lockstep=false
trace_system=client
-[debug]
-break_cycles=
+[statsreset]
+reset_cycle=0
diff --git a/tests/long/40.perlbmk/ref/alpha/linux/simple-atomic/m5stats.txt b/tests/long/40.perlbmk/ref/alpha/linux/simple-atomic/m5stats.txt
index 5d4f9235a..f553125a6 100644
--- a/tests/long/40.perlbmk/ref/alpha/linux/simple-atomic/m5stats.txt
+++ b/tests/long/40.perlbmk/ref/alpha/linux/simple-atomic/m5stats.txt
@@ -1,1974 +1,18 @@
---------- Begin Simulation Statistics ----------
-global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-global.BPredUnit.BTBHits 542 # Number of BTB hits
-global.BPredUnit.BTBLookups 1938 # Number of BTB lookups
-global.BPredUnit.RASInCorrect 48 # Number of incorrect RAS predictions.
-global.BPredUnit.condIncorrect 420 # Number of conditional branches incorrect
-global.BPredUnit.condPredicted 1304 # Number of conditional branches predicted
-global.BPredUnit.lookups 2256 # Number of BP lookups
-global.BPredUnit.usedRAS 291 # Number of times the RAS was used to get a target.
-host_inst_rate 41797 # Simulator instruction rate (inst/s)
-host_mem_usage 160344 # Number of bytes of host memory used
-host_seconds 0.13 # Real time elapsed on the host
-host_tick_rate 50948 # Simulator tick rate (ticks/s)
-memdepunit.memDep.conflictingLoads 12 # Number of conflicting loads.
-memdepunit.memDep.conflictingStores 259 # Number of conflicting stores.
-memdepunit.memDep.insertedLoads 2050 # Number of loads inserted to the mem dependence unit.
-memdepunit.memDep.insertedStores 1221 # Number of stores inserted to the mem dependence unit.
+host_inst_rate 906784 # Simulator instruction rate (inst/s)
+host_mem_usage 147280 # Number of bytes of host memory used
+host_seconds 2215.51 # Real time elapsed on the host
+host_tick_rate 906784 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 5623 # Number of instructions simulated
-sim_seconds 0.000000 # Number of seconds simulated
-sim_ticks 6870 # Number of ticks simulated
-system.cpu.commit.COM:branches 862 # Number of branches committed
-system.cpu.commit.COM:bw_lim_events 74 # number cycles where commit BW limit reached
-system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle.samples 6116
-system.cpu.commit.COM:committed_per_cycle.min_value 0
- 0 3908 6389.80%
- 1 1064 1739.70%
- 2 389 636.04%
- 3 210 343.36%
- 4 153 250.16%
- 5 93 152.06%
- 6 76 124.26%
- 7 149 243.62%
- 8 74 120.99%
-system.cpu.commit.COM:committed_per_cycle.max_value 8
-system.cpu.commit.COM:committed_per_cycle.end_dist
-
-system.cpu.commit.COM:count 5640 # Number of instructions committed
-system.cpu.commit.COM:loads 979 # Number of loads committed
-system.cpu.commit.COM:membars 0 # Number of memory barriers committed
-system.cpu.commit.COM:refs 1791 # Number of memory references committed
-system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.branchMispredicts 337 # The number of times a branch was mispredicted
-system.cpu.commit.commitCommittedInsts 5640 # The number of committed instructions
-system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.commitSquashedInsts 4350 # The number of squashed insts skipped by commit
-system.cpu.committedInsts 5623 # Number of Instructions Simulated
-system.cpu.committedInsts_total 5623 # Number of Instructions Simulated
-system.cpu.cpi 1.221768 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 1.221768 # CPI: Total CPI of All Threads
-system.cpu.dcache.ReadReq_accesses 1538 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 3.072000 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2.240000 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits 1413 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 384 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate 0.081274 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses 125 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_hits 25 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_miss_latency 224 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate 0.065020 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses 100 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_accesses 821 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 2.467742 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2.140845 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 635 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 459 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.226553 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 186 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_hits 108 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_miss_latency 152 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.086480 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 71 # number of WriteReq MSHR misses
-system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles_no_targets 0.800000 # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 11.505618 # Average number of references to valid blocks.
-system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_no_targets 5 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles_no_targets 4 # number of cycles access was blocked
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.demand_accesses 2359 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 2.710611 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 2.198830 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 2048 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 843 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.131836 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 311 # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits 133 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 376 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate 0.072488 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 171 # number of demand (read+write) MSHR misses
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.overall_accesses 2359 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 2.710611 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 2.198830 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 2048 # number of overall hits
-system.cpu.dcache.overall_miss_latency 843 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.131836 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 311 # number of overall misses
-system.cpu.dcache.overall_mshr_hits 133 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 376 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate 0.072488 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 171 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.dcache.replacements 0 # number of replacements
-system.cpu.dcache.sampled_refs 178 # Sample count of references to valid blocks.
-system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 119.831029 # Cycle average of tags in use
-system.cpu.dcache.total_refs 2048 # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks 0 # number of writebacks
-system.cpu.decode.DECODE:BlockedCycles 387 # Number of cycles decode is blocked
-system.cpu.decode.DECODE:BranchMispred 93 # Number of times decode detected a branch misprediction
-system.cpu.decode.DECODE:BranchResolved 185 # Number of times decode resolved a branch
-system.cpu.decode.DECODE:DecodedInsts 12349 # Number of instructions handled by decode
-system.cpu.decode.DECODE:IdleCycles 3542 # Number of cycles decode is idle
-system.cpu.decode.DECODE:RunCycles 2158 # Number of cycles decode is running
-system.cpu.decode.DECODE:SquashCycles 754 # Number of cycles decode is squashing
-system.cpu.decode.DECODE:SquashedInsts 286 # Number of squashed instructions handled by decode
-system.cpu.decode.DECODE:UnblockCycles 30 # Number of cycles decode is unblocking
-system.cpu.fetch.Branches 2256 # Number of branches that fetch encountered
-system.cpu.fetch.CacheLines 1582 # Number of cache lines fetched
-system.cpu.fetch.Cycles 3905 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.IcacheSquashes 148 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.Insts 13707 # Number of instructions fetch has processed
-system.cpu.fetch.SquashCycles 456 # Number of cycles fetch has spent squashing
-system.cpu.fetch.branchRate 0.328336 # Number of branch fetches per cycle
-system.cpu.fetch.icacheStallCycles 1582 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.predictedBranches 833 # Number of branches that fetch has predicted taken
-system.cpu.fetch.rate 1.994906 # Number of inst fetches per cycle
-system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist.samples 6871
-system.cpu.fetch.rateDist.min_value 0
- 0 4549 6620.58%
- 1 174 253.24%
- 2 186 270.70%
- 3 157 228.50%
- 4 211 307.09%
- 5 153 222.68%
- 6 171 248.87%
- 7 105 152.82%
- 8 1165 1695.53%
-system.cpu.fetch.rateDist.max_value 8
-system.cpu.fetch.rateDist.end_dist
-
-system.cpu.icache.ReadReq_accesses 1582 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 2.960245 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 1.996885 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits 1255 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 968 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate 0.206700 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses 327 # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_hits 6 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_miss_latency 641 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.202908 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses 321 # number of ReadReq MSHR misses
-system.cpu.icache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles_no_targets no value # average number of cycles each access was blocked
-system.cpu.icache.avg_refs 3.909657 # Average number of references to valid blocks.
-system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.demand_accesses 1582 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 2.960245 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 1.996885 # average overall mshr miss latency
-system.cpu.icache.demand_hits 1255 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 968 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate 0.206700 # miss rate for demand accesses
-system.cpu.icache.demand_misses 327 # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_hits 6 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 641 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate 0.202908 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses 321 # number of demand (read+write) MSHR misses
-system.cpu.icache.fast_writes 0 # number of fast writes performed
-system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.overall_accesses 1582 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 2.960245 # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 1.996885 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits 1255 # number of overall hits
-system.cpu.icache.overall_miss_latency 968 # number of overall miss cycles
-system.cpu.icache.overall_miss_rate 0.206700 # miss rate for overall accesses
-system.cpu.icache.overall_misses 327 # number of overall misses
-system.cpu.icache.overall_mshr_hits 6 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 641 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate 0.202908 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses 321 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.icache.replacements 0 # number of replacements
-system.cpu.icache.sampled_refs 321 # Sample count of references to valid blocks.
-system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 176.393247 # Cycle average of tags in use
-system.cpu.icache.total_refs 1255 # Total number of references to valid blocks.
-system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.iew.EXEC:branches 1206 # Number of branches executed
-system.cpu.iew.EXEC:insts 7969 # Number of executed instructions
-system.cpu.iew.EXEC:loads 1610 # Number of load instructions executed
-system.cpu.iew.EXEC:nop 37 # number of nop insts executed
-system.cpu.iew.EXEC:rate 1.159802 # Inst execution rate
-system.cpu.iew.EXEC:refs 2599 # number of memory reference insts executed
-system.cpu.iew.EXEC:squashedInsts 419 # Number of squashed instructions skipped in execute
-system.cpu.iew.EXEC:stores 989 # Number of stores executed
-system.cpu.iew.EXEC:swp 0 # number of swp insts executed
-system.cpu.iew.WB:consumers 5438 # num instructions consuming a value
-system.cpu.iew.WB:count 7722 # cumulative count of insts written-back
-system.cpu.iew.WB:fanout 0.744575 # average fanout of values written-back
-system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.iew.WB:producers 4049 # num instructions producing a value
-system.cpu.iew.WB:rate 1.123854 # insts written-back per cycle
-system.cpu.iew.WB:sent 7762 # cumulative count of insts sent to commit
-system.cpu.iew.branchMispredicts 393 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewBlockCycles 4 # Number of cycles IEW is blocking
-system.cpu.iew.iewDispLoadInsts 2050 # Number of dispatched load instructions
-system.cpu.iew.iewDispNonSpecInsts 21 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewDispSquashedInsts 272 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispStoreInsts 1221 # Number of dispatched store instructions
-system.cpu.iew.iewDispatchedInsts 9990 # Number of instructions dispatched to IQ
-system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.iewSquashCycles 754 # Number of cycles IEW is squashing
-system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking
-system.cpu.iew.lsq.thread.0.blockedLoads 1 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread.0.cacheBlocked 5 # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.lsq.thread.0.forwLoads 55 # Number of loads that had data forwarded from stores
-system.cpu.iew.lsq.thread.0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
-system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread.0.squashedLoads 1071 # Number of loads squashed
-system.cpu.iew.lsq.thread.0.squashedStores 409 # Number of stores squashed
-system.cpu.iew.memOrderViolationEvents 41 # Number of memory order violations
-system.cpu.iew.predictedNotTakenIncorrect 296 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.predictedTakenIncorrect 97 # Number of branches that were predicted taken incorrectly
-system.cpu.ipc 0.818486 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.818486 # IPC: Total IPC of All Threads
-system.cpu.iq.IQ:residence:(null).start_dist # cycles from dispatch to issue
-system.cpu.iq.IQ:residence:(null).samples 0
-system.cpu.iq.IQ:residence:(null).min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
- 20 0
- 22 0
- 24 0
- 26 0
- 28 0
- 30 0
- 32 0
- 34 0
- 36 0
- 38 0
- 40 0
- 42 0
- 44 0
- 46 0
- 48 0
- 50 0
- 52 0
- 54 0
- 56 0
- 58 0
- 60 0
- 62 0
- 64 0
- 66 0
- 68 0
- 70 0
- 72 0
- 74 0
- 76 0
- 78 0
- 80 0
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-
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-
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-
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-
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-
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-
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-
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-
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- 20 0
- 22 0
- 24 0
- 26 0
- 28 0
- 30 0
- 32 0
- 34 0
- 36 0
- 38 0
- 40 0
- 42 0
- 44 0
- 46 0
- 48 0
- 50 0
- 52 0
- 54 0
- 56 0
- 58 0
- 60 0
- 62 0
- 64 0
- 66 0
- 68 0
- 70 0
- 72 0
- 74 0
- 76 0
- 78 0
- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.ISSUE:FloatSqrt_delay.max_value 0
-system.cpu.iq.ISSUE:FloatSqrt_delay.end_dist
-
-system.cpu.iq.ISSUE:MemRead_delay.start_dist # cycles from operands ready to issue
-system.cpu.iq.ISSUE:MemRead_delay.samples 0
-system.cpu.iq.ISSUE:MemRead_delay.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
- 20 0
- 22 0
- 24 0
- 26 0
- 28 0
- 30 0
- 32 0
- 34 0
- 36 0
- 38 0
- 40 0
- 42 0
- 44 0
- 46 0
- 48 0
- 50 0
- 52 0
- 54 0
- 56 0
- 58 0
- 60 0
- 62 0
- 64 0
- 66 0
- 68 0
- 70 0
- 72 0
- 74 0
- 76 0
- 78 0
- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.ISSUE:MemRead_delay.max_value 0
-system.cpu.iq.ISSUE:MemRead_delay.end_dist
-
-system.cpu.iq.ISSUE:MemWrite_delay.start_dist # cycles from operands ready to issue
-system.cpu.iq.ISSUE:MemWrite_delay.samples 0
-system.cpu.iq.ISSUE:MemWrite_delay.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
- 20 0
- 22 0
- 24 0
- 26 0
- 28 0
- 30 0
- 32 0
- 34 0
- 36 0
- 38 0
- 40 0
- 42 0
- 44 0
- 46 0
- 48 0
- 50 0
- 52 0
- 54 0
- 56 0
- 58 0
- 60 0
- 62 0
- 64 0
- 66 0
- 68 0
- 70 0
- 72 0
- 74 0
- 76 0
- 78 0
- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.ISSUE:MemWrite_delay.max_value 0
-system.cpu.iq.ISSUE:MemWrite_delay.end_dist
-
-system.cpu.iq.ISSUE:IprAccess_delay.start_dist # cycles from operands ready to issue
-system.cpu.iq.ISSUE:IprAccess_delay.samples 0
-system.cpu.iq.ISSUE:IprAccess_delay.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
- 20 0
- 22 0
- 24 0
- 26 0
- 28 0
- 30 0
- 32 0
- 34 0
- 36 0
- 38 0
- 40 0
- 42 0
- 44 0
- 46 0
- 48 0
- 50 0
- 52 0
- 54 0
- 56 0
- 58 0
- 60 0
- 62 0
- 64 0
- 66 0
- 68 0
- 70 0
- 72 0
- 74 0
- 76 0
- 78 0
- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.ISSUE:IprAccess_delay.max_value 0
-system.cpu.iq.ISSUE:IprAccess_delay.end_dist
-
-system.cpu.iq.ISSUE:InstPrefetch_delay.start_dist # cycles from operands ready to issue
-system.cpu.iq.ISSUE:InstPrefetch_delay.samples 0
-system.cpu.iq.ISSUE:InstPrefetch_delay.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
- 20 0
- 22 0
- 24 0
- 26 0
- 28 0
- 30 0
- 32 0
- 34 0
- 36 0
- 38 0
- 40 0
- 42 0
- 44 0
- 46 0
- 48 0
- 50 0
- 52 0
- 54 0
- 56 0
- 58 0
- 60 0
- 62 0
- 64 0
- 66 0
- 68 0
- 70 0
- 72 0
- 74 0
- 76 0
- 78 0
- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.ISSUE:InstPrefetch_delay.max_value 0
-system.cpu.iq.ISSUE:InstPrefetch_delay.end_dist
-
-system.cpu.iq.ISSUE:FU_type_0 8388 # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0.start_dist
- (null) 2 0.02% # Type of FU issued
- IntAlu 5594 66.69% # Type of FU issued
- IntMult 1 0.01% # Type of FU issued
- IntDiv 0 0.00% # Type of FU issued
- FloatAdd 2 0.02% # Type of FU issued
- FloatCmp 0 0.00% # Type of FU issued
- FloatCvt 0 0.00% # Type of FU issued
- FloatMult 0 0.00% # Type of FU issued
- FloatDiv 0 0.00% # Type of FU issued
- FloatSqrt 0 0.00% # Type of FU issued
- MemRead 1757 20.95% # Type of FU issued
- MemWrite 1032 12.30% # Type of FU issued
- IprAccess 0 0.00% # Type of FU issued
- InstPrefetch 0 0.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0.end_dist
-system.cpu.iq.ISSUE:fu_busy_cnt 115 # FU busy when requested
-system.cpu.iq.ISSUE:fu_busy_rate 0.013710 # FU busy rate (busy events/executed inst)
-system.cpu.iq.ISSUE:fu_full.start_dist
- (null) 0 0.00% # attempts to use FU when none available
- IntAlu 1 0.87% # attempts to use FU when none available
- IntMult 0 0.00% # attempts to use FU when none available
- IntDiv 0 0.00% # attempts to use FU when none available
- FloatAdd 0 0.00% # attempts to use FU when none available
- FloatCmp 0 0.00% # attempts to use FU when none available
- FloatCvt 0 0.00% # attempts to use FU when none available
- FloatMult 0 0.00% # attempts to use FU when none available
- FloatDiv 0 0.00% # attempts to use FU when none available
- FloatSqrt 0 0.00% # attempts to use FU when none available
- MemRead 76 66.09% # attempts to use FU when none available
- MemWrite 38 33.04% # attempts to use FU when none available
- IprAccess 0 0.00% # attempts to use FU when none available
- InstPrefetch 0 0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full.end_dist
-system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle.samples 6871
-system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
- 0 3753 5462.09%
- 1 894 1301.12%
- 2 723 1052.25%
- 3 614 893.61%
- 4 451 656.38%
- 5 279 406.05%
- 6 104 151.36%
- 7 41 59.67%
- 8 12 17.46%
-system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
-system.cpu.iq.ISSUE:issued_per_cycle.end_dist
-
-system.cpu.iq.ISSUE:rate 1.220783 # Inst issue rate
-system.cpu.iq.iqInstsAdded 9932 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqInstsIssued 8388 # Number of instructions issued
-system.cpu.iq.iqNonSpecInstsAdded 21 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqSquashedInstsExamined 3990 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedInstsIssued 21 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedNonSpecRemoved 4 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.iqSquashedOperandsExamined 2486 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.l2cache.ReadReq_accesses 499 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 2.042254 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency 1015 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate 0.995992 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses 497 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 490 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.981964 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses 490 # number of ReadReq MSHR misses
-system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs 0.004024 # Average number of references to valid blocks.
-system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.demand_accesses 499 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 2.042254 # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 1 # average overall mshr miss latency
-system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 1015 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate 0.995992 # miss rate for demand accesses
-system.cpu.l2cache.demand_misses 497 # number of demand (read+write) misses
-system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency 490 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate 0.981964 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses 490 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.fast_writes 0 # number of fast writes performed
-system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.overall_accesses 499 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 2.042254 # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 1 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits 2 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 1015 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate 0.995992 # miss rate for overall accesses
-system.cpu.l2cache.overall_misses 497 # number of overall misses
-system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 490 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate 0.981964 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses 490 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.l2cache.replacements 0 # number of replacements
-system.cpu.l2cache.sampled_refs 497 # Sample count of references to valid blocks.
-system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 295.773395 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks 0 # number of writebacks
-system.cpu.numCycles 6871 # number of cpu cycles simulated
-system.cpu.rename.RENAME:BlockCycles 4 # Number of cycles rename is blocking
-system.cpu.rename.RENAME:CommittedMaps 4051 # Number of HB maps that are committed
-system.cpu.rename.RENAME:IdleCycles 3758 # Number of cycles rename is idle
-system.cpu.rename.RENAME:LSQFullEvents 62 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RENAME:RenameLookups 14786 # Number of register rename lookups that rename has made
-system.cpu.rename.RENAME:RenamedInsts 11555 # Number of instructions processed by rename
-system.cpu.rename.RENAME:RenamedOperands 8634 # Number of destination operands rename has renamed
-system.cpu.rename.RENAME:RunCycles 1975 # Number of cycles rename is running
-system.cpu.rename.RENAME:SquashCycles 754 # Number of cycles rename is squashing
-system.cpu.rename.RENAME:UnblockCycles 111 # Number of cycles rename is unblocking
-system.cpu.rename.RENAME:UndoneMaps 4583 # Number of HB maps that are undone due to squashing
-system.cpu.rename.RENAME:serializeStallCycles 269 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RENAME:serializingInsts 26 # count of serializing insts renamed
-system.cpu.rename.RENAME:skidInsts 408 # count of insts added to the skid buffer
-system.cpu.rename.RENAME:tempSerializingInsts 21 # count of temporary serializing insts renamed
-system.cpu.workload.PROG:num_syscalls 17 # Number of system calls
+sim_insts 2008987724 # Number of instructions simulated
+sim_seconds 0.002009 # Number of seconds simulated
+sim_ticks 2008987723 # Number of ticks simulated
+system.cpu.idle_fraction 0 # Percentage of idle cycles
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.numCycles 2008987724 # number of cpu cycles simulated
+system.cpu.num_insts 2008987724 # Number of instructions executed
+system.cpu.num_refs 722390480 # Number of memory references
+system.cpu.workload.PROG:num_syscalls 39 # Number of system calls
---------- End Simulation Statistics ----------
diff --git a/tests/long/40.perlbmk/ref/alpha/linux/simple-atomic/stderr b/tests/long/40.perlbmk/ref/alpha/linux/simple-atomic/stderr
index 8893caac8..9135960d0 100644
--- a/tests/long/40.perlbmk/ref/alpha/linux/simple-atomic/stderr
+++ b/tests/long/40.perlbmk/ref/alpha/linux/simple-atomic/stderr
@@ -1,3 +1,2 @@
warn: Entering event queue @ 0. Starting simulation...
-warn: cycle 0: fault (page_table_fault) detected @ PC 0x000000
-warn: Increasing stack 0x11ff92000:0x11ff9b000 to 0x11ff90000:0x11ff9b000 because of access to 0x11ff91ff0
+warn: ignoring syscall sigprocmask(1, 0, ...)
diff --git a/tests/long/40.perlbmk/ref/alpha/linux/simple-atomic/stdout b/tests/long/40.perlbmk/ref/alpha/linux/simple-atomic/stdout
index fbb329a2f..d4a078b85 100644
--- a/tests/long/40.perlbmk/ref/alpha/linux/simple-atomic/stdout
+++ b/tests/long/40.perlbmk/ref/alpha/linux/simple-atomic/stdout
@@ -1,13 +1,1376 @@
-Hello world!
-M5 Simulator System
-
-Copyright (c) 2001-2006
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Sep 5 2006 15:28:48
-M5 started Tue Sep 5 15:42:12 2006
-M5 executing on zizzer.eecs.umich.edu
-command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/o3-timing tests/run.py quick/00.hello/alpha/linux/o3-timing
-Exiting @ tick 6870 because target called exit()
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diff --git a/tests/long/40.perlbmk/ref/alpha/linux/simple-timing/config.ini b/tests/long/40.perlbmk/ref/alpha/linux/simple-timing/config.ini
index c3a59fbce..fa4ee72da 100644
--- a/tests/long/40.perlbmk/ref/alpha/linux/simple-timing/config.ini
+++ b/tests/long/40.perlbmk/ref/alpha/linux/simple-timing/config.ini
@@ -7,11 +7,9 @@ max_tick=0
output_file=cout
progress_interval=0
-[debug]
-break_cycles=
-
[exetrace]
intel_format=false
+legion_lockstep=false
pc_symbol=true
print_cpseq=false
print_cycle=true
@@ -53,73 +51,20 @@ mem_mode=atomic
physmem=system.physmem
[system.cpu]
-type=DerivO3CPU
-children=dcache fuPool icache l2cache toL2Bus workload
-BTBEntries=4096
-BTBTagSize=16
-LFSTSize=1024
-LQEntries=32
-RASSize=16
-SQEntries=32
-SSITSize=1024
-activity=0
-backComSize=5
-choiceCtrBits=2
-choicePredictorSize=8192
+type=TimingSimpleCPU
+children=dcache icache l2cache toL2Bus workload
clock=1
-commitToDecodeDelay=1
-commitToFetchDelay=1
-commitToIEWDelay=1
-commitToRenameDelay=1
-commitWidth=8
-decodeToFetchDelay=1
-decodeToRenameDelay=1
-decodeWidth=8
+cpu_id=0
defer_registration=false
-dispatchWidth=8
-fetchToDecodeDelay=1
-fetchTrapLatency=1
-fetchWidth=8
-forwardComSize=5
-fuPool=system.cpu.fuPool
function_trace=false
function_trace_start=0
-globalCtrBits=2
-globalHistoryBits=13
-globalPredictorSize=8192
-iewToCommitDelay=1
-iewToDecodeDelay=1
-iewToFetchDelay=1
-iewToRenameDelay=1
-instShiftAmt=2
-issueToExecuteDelay=1
-issueWidth=8
-localCtrBits=2
-localHistoryBits=11
-localHistoryTableSize=2048
-localPredictorSize=2048
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
-mem=system.cpu.dcache
-numIQEntries=64
-numPhysFloatRegs=256
-numPhysIntRegs=256
-numROBEntries=192
-numRobs=1
-numThreads=1
-predType=tournament
-renameToDecodeDelay=1
-renameToFetchDelay=1
-renameToIEWDelay=2
-renameToROBDelay=1
-renameWidth=8
-squashWidth=8
+phase=0
+progress_interval=0
system=system
-trapLatency=13
-wbDepth=1
-wbWidth=8
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
@@ -131,7 +76,6 @@ assoc=2
block_size=64
compressed_bus=false
compression_latency=0
-do_copy=false
hash_delay=1
hit_latency=1
latency=1
@@ -164,143 +108,6 @@ write_buffers=8
cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.port[1]
-[system.cpu.fuPool]
-type=FUPool
-children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7
-FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7
-
-[system.cpu.fuPool.FUList0]
-type=FUDesc
-children=opList0
-count=6
-opList=system.cpu.fuPool.FUList0.opList0
-
-[system.cpu.fuPool.FUList0.opList0]
-type=OpDesc
-issueLat=1
-opClass=IntAlu
-opLat=1
-
-[system.cpu.fuPool.FUList1]
-type=FUDesc
-children=opList0 opList1
-count=2
-opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
-
-[system.cpu.fuPool.FUList1.opList0]
-type=OpDesc
-issueLat=1
-opClass=IntMult
-opLat=3
-
-[system.cpu.fuPool.FUList1.opList1]
-type=OpDesc
-issueLat=19
-opClass=IntDiv
-opLat=20
-
-[system.cpu.fuPool.FUList2]
-type=FUDesc
-children=opList0 opList1 opList2
-count=4
-opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
-
-[system.cpu.fuPool.FUList2.opList0]
-type=OpDesc
-issueLat=1
-opClass=FloatAdd
-opLat=2
-
-[system.cpu.fuPool.FUList2.opList1]
-type=OpDesc
-issueLat=1
-opClass=FloatCmp
-opLat=2
-
-[system.cpu.fuPool.FUList2.opList2]
-type=OpDesc
-issueLat=1
-opClass=FloatCvt
-opLat=2
-
-[system.cpu.fuPool.FUList3]
-type=FUDesc
-children=opList0 opList1 opList2
-count=2
-opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
-
-[system.cpu.fuPool.FUList3.opList0]
-type=OpDesc
-issueLat=1
-opClass=FloatMult
-opLat=4
-
-[system.cpu.fuPool.FUList3.opList1]
-type=OpDesc
-issueLat=12
-opClass=FloatDiv
-opLat=12
-
-[system.cpu.fuPool.FUList3.opList2]
-type=OpDesc
-issueLat=24
-opClass=FloatSqrt
-opLat=24
-
-[system.cpu.fuPool.FUList4]
-type=FUDesc
-children=opList0
-count=0
-opList=system.cpu.fuPool.FUList4.opList0
-
-[system.cpu.fuPool.FUList4.opList0]
-type=OpDesc
-issueLat=1
-opClass=MemRead
-opLat=1
-
-[system.cpu.fuPool.FUList5]
-type=FUDesc
-children=opList0
-count=0
-opList=system.cpu.fuPool.FUList5.opList0
-
-[system.cpu.fuPool.FUList5.opList0]
-type=OpDesc
-issueLat=1
-opClass=MemWrite
-opLat=1
-
-[system.cpu.fuPool.FUList6]
-type=FUDesc
-children=opList0 opList1
-count=4
-opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1
-
-[system.cpu.fuPool.FUList6.opList0]
-type=OpDesc
-issueLat=1
-opClass=MemRead
-opLat=1
-
-[system.cpu.fuPool.FUList6.opList1]
-type=OpDesc
-issueLat=1
-opClass=MemWrite
-opLat=1
-
-[system.cpu.fuPool.FUList7]
-type=FUDesc
-children=opList0
-count=1
-opList=system.cpu.fuPool.FUList7.opList0
-
-[system.cpu.fuPool.FUList7.opList0]
-type=OpDesc
-issueLat=3
-opClass=IprAccess
-opLat=3
-
[system.cpu.icache]
type=BaseCache
adaptive_compression=false
@@ -308,7 +115,6 @@ assoc=2
block_size=64
compressed_bus=false
compression_latency=0
-do_copy=false
hash_delay=1
hit_latency=1
latency=1
@@ -348,7 +154,6 @@ assoc=2
block_size=64
compressed_bus=false
compression_latency=0
-do_copy=false
hash_delay=1
hit_latency=1
latency=1
@@ -384,20 +189,33 @@ mem_side=system.membus.port[1]
[system.cpu.toL2Bus]
type=Bus
bus_id=0
+clock=1000
+responder_set=false
+width=64
port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
[system.cpu.workload]
type=LiveProcess
-cmd=hello
+cmd=perlbmk -I. -I lib lgred.makerand.pl
+cwd=build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/linux/simple-timing
+egid=100
env=
-executable=tests/test-progs/hello/bin/alpha/linux/hello
+euid=100
+executable=/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk
+gid=100
input=cin
output=cout
+pid=100
+ppid=99
system=system
+uid=100
[system.membus]
type=Bus
bus_id=0
+clock=1000
+responder_set=false
+width=64
port=system.physmem.port system.cpu.l2cache.mem_side
[system.physmem]
@@ -409,6 +227,7 @@ port=system.membus.port[0]
[trace]
bufsize=0
+cycle=0
dump_on_exit=false
file=cout
flags=
diff --git a/tests/long/40.perlbmk/ref/alpha/linux/simple-timing/config.out b/tests/long/40.perlbmk/ref/alpha/linux/simple-timing/config.out
index f491a3081..ea12fcb9a 100644
--- a/tests/long/40.perlbmk/ref/alpha/linux/simple-timing/config.out
+++ b/tests/long/40.perlbmk/ref/alpha/linux/simple-timing/config.out
@@ -19,19 +19,54 @@ mem_mode=atomic
[system.membus]
type=Bus
bus_id=0
+clock=1000
+width=64
+responder_set=false
[system.cpu.workload]
type=LiveProcess
-cmd=hello
-executable=tests/test-progs/hello/bin/alpha/linux/hello
+cmd=perlbmk -I. -I lib lgred.makerand.pl
+executable=/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk
input=cin
output=cout
env=
+cwd=build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/linux/simple-timing
system=system
+uid=100
+euid=100
+gid=100
+egid=100
+pid=100
+ppid=99
-[system.cpu.dcache]
+[system.cpu]
+type=TimingSimpleCPU
+max_insts_any_thread=0
+max_insts_all_threads=0
+max_loads_any_thread=0
+max_loads_all_threads=0
+progress_interval=0
+system=system
+cpu_id=0
+workload=system.cpu.workload
+clock=1
+phase=0
+defer_registration=false
+// width not specified
+function_trace=false
+function_trace_start=0
+// simulate_stalls not specified
+
+[system.cpu.toL2Bus]
+type=Bus
+bus_id=0
+clock=1000
+width=64
+responder_set=false
+
+[system.cpu.icache]
type=BaseCache
-size=262144
+size=131072
assoc=2
block_size=64
latency=1
@@ -39,7 +74,6 @@ mshrs=10
tgts_per_mshr=5
write_buffers=8
prioritizeRequests=false
-do_copy=false
protocol=null
trace_addr=0
hash_delay=1
@@ -68,214 +102,9 @@ prefetch_use_cpu_id=true
prefetch_data_accesses_only=false
hit_latency=1
-[system.cpu.fuPool.FUList0.opList0]
-type=OpDesc
-opClass=IntAlu
-opLat=1
-issueLat=1
-
-[system.cpu.fuPool.FUList0]
-type=FUDesc
-opList=system.cpu.fuPool.FUList0.opList0
-count=6
-
-[system.cpu.fuPool.FUList1.opList0]
-type=OpDesc
-opClass=IntMult
-opLat=3
-issueLat=1
-
-[system.cpu.fuPool.FUList1.opList1]
-type=OpDesc
-opClass=IntDiv
-opLat=20
-issueLat=19
-
-[system.cpu.fuPool.FUList1]
-type=FUDesc
-opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
-count=2
-
-[system.cpu.fuPool.FUList2.opList0]
-type=OpDesc
-opClass=FloatAdd
-opLat=2
-issueLat=1
-
-[system.cpu.fuPool.FUList2.opList1]
-type=OpDesc
-opClass=FloatCmp
-opLat=2
-issueLat=1
-
-[system.cpu.fuPool.FUList2.opList2]
-type=OpDesc
-opClass=FloatCvt
-opLat=2
-issueLat=1
-
-[system.cpu.fuPool.FUList2]
-type=FUDesc
-opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
-count=4
-
-[system.cpu.fuPool.FUList3.opList0]
-type=OpDesc
-opClass=FloatMult
-opLat=4
-issueLat=1
-
-[system.cpu.fuPool.FUList3.opList1]
-type=OpDesc
-opClass=FloatDiv
-opLat=12
-issueLat=12
-
-[system.cpu.fuPool.FUList3.opList2]
-type=OpDesc
-opClass=FloatSqrt
-opLat=24
-issueLat=24
-
-[system.cpu.fuPool.FUList3]
-type=FUDesc
-opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
-count=2
-
-[system.cpu.fuPool.FUList4.opList0]
-type=OpDesc
-opClass=MemRead
-opLat=1
-issueLat=1
-
-[system.cpu.fuPool.FUList4]
-type=FUDesc
-opList=system.cpu.fuPool.FUList4.opList0
-count=0
-
-[system.cpu.fuPool.FUList5.opList0]
-type=OpDesc
-opClass=MemWrite
-opLat=1
-issueLat=1
-
-[system.cpu.fuPool.FUList5]
-type=FUDesc
-opList=system.cpu.fuPool.FUList5.opList0
-count=0
-
-[system.cpu.fuPool.FUList6.opList0]
-type=OpDesc
-opClass=MemRead
-opLat=1
-issueLat=1
-
-[system.cpu.fuPool.FUList6.opList1]
-type=OpDesc
-opClass=MemWrite
-opLat=1
-issueLat=1
-
-[system.cpu.fuPool.FUList6]
-type=FUDesc
-opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1
-count=4
-
-[system.cpu.fuPool.FUList7.opList0]
-type=OpDesc
-opClass=IprAccess
-opLat=3
-issueLat=3
-
-[system.cpu.fuPool.FUList7]
-type=FUDesc
-opList=system.cpu.fuPool.FUList7.opList0
-count=1
-
-[system.cpu.fuPool]
-type=FUPool
-FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7
-
-[system.cpu]
-type=DerivO3CPU
-clock=1
-numThreads=1
-activity=0
-workload=system.cpu.workload
-mem=system.cpu.dcache
-checker=null
-max_insts_any_thread=0
-max_insts_all_threads=0
-max_loads_any_thread=0
-max_loads_all_threads=0
-cachePorts=200
-decodeToFetchDelay=1
-renameToFetchDelay=1
-iewToFetchDelay=1
-commitToFetchDelay=1
-fetchWidth=8
-renameToDecodeDelay=1
-iewToDecodeDelay=1
-commitToDecodeDelay=1
-fetchToDecodeDelay=1
-decodeWidth=8
-iewToRenameDelay=1
-commitToRenameDelay=1
-decodeToRenameDelay=1
-renameWidth=8
-commitToIEWDelay=1
-renameToIEWDelay=2
-issueToExecuteDelay=1
-dispatchWidth=8
-issueWidth=8
-wbWidth=8
-wbDepth=1
-fuPool=system.cpu.fuPool
-iewToCommitDelay=1
-renameToROBDelay=1
-commitWidth=8
-squashWidth=8
-trapLatency=13
-backComSize=5
-forwardComSize=5
-predType=tournament
-localPredictorSize=2048
-localCtrBits=2
-localHistoryTableSize=2048
-localHistoryBits=11
-globalPredictorSize=8192
-globalCtrBits=2
-globalHistoryBits=13
-choicePredictorSize=8192
-choiceCtrBits=2
-BTBEntries=4096
-BTBTagSize=16
-RASSize=16
-LQEntries=32
-SQEntries=32
-LFSTSize=1024
-SSITSize=1024
-numPhysIntRegs=256
-numPhysFloatRegs=256
-numIQEntries=64
-numROBEntries=192
-smtNumFetchingThreads=1
-smtFetchPolicy=SingleThread
-smtLSQPolicy=Partitioned
-smtLSQThreshold=100
-smtIQPolicy=Partitioned
-smtIQThreshold=100
-smtROBPolicy=Partitioned
-smtROBThreshold=100
-smtCommitPolicy=RoundRobin
-instShiftAmt=2
-defer_registration=false
-function_trace=false
-function_trace_start=0
-
-[system.cpu.icache]
+[system.cpu.dcache]
type=BaseCache
-size=131072
+size=262144
assoc=2
block_size=64
latency=1
@@ -283,7 +112,6 @@ mshrs=10
tgts_per_mshr=5
write_buffers=8
prioritizeRequests=false
-do_copy=false
protocol=null
trace_addr=0
hash_delay=1
@@ -322,7 +150,6 @@ mshrs=10
tgts_per_mshr=5
write_buffers=8
prioritizeRequests=false
-do_copy=false
protocol=null
trace_addr=0
hash_delay=1
@@ -351,13 +178,10 @@ prefetch_use_cpu_id=true
prefetch_data_accesses_only=false
hit_latency=1
-[system.cpu.toL2Bus]
-type=Bus
-bus_id=0
-
[trace]
flags=
start=0
+cycle=0
bufsize=0
file=cout
dump_on_exit=false
@@ -396,8 +220,9 @@ print_cpseq=false
print_reg_delta=false
pc_symbol=true
intel_format=false
+legion_lockstep=false
trace_system=client
-[debug]
-break_cycles=
+[statsreset]
+reset_cycle=0
diff --git a/tests/long/40.perlbmk/ref/alpha/linux/simple-timing/m5stats.txt b/tests/long/40.perlbmk/ref/alpha/linux/simple-timing/m5stats.txt
index 5d4f9235a..4d20e663a 100644
--- a/tests/long/40.perlbmk/ref/alpha/linux/simple-timing/m5stats.txt
+++ b/tests/long/40.perlbmk/ref/alpha/linux/simple-timing/m5stats.txt
@@ -1,112 +1,67 @@
---------- Begin Simulation Statistics ----------
-global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-global.BPredUnit.BTBHits 542 # Number of BTB hits
-global.BPredUnit.BTBLookups 1938 # Number of BTB lookups
-global.BPredUnit.RASInCorrect 48 # Number of incorrect RAS predictions.
-global.BPredUnit.condIncorrect 420 # Number of conditional branches incorrect
-global.BPredUnit.condPredicted 1304 # Number of conditional branches predicted
-global.BPredUnit.lookups 2256 # Number of BP lookups
-global.BPredUnit.usedRAS 291 # Number of times the RAS was used to get a target.
-host_inst_rate 41797 # Simulator instruction rate (inst/s)
-host_mem_usage 160344 # Number of bytes of host memory used
-host_seconds 0.13 # Real time elapsed on the host
-host_tick_rate 50948 # Simulator tick rate (ticks/s)
-memdepunit.memDep.conflictingLoads 12 # Number of conflicting loads.
-memdepunit.memDep.conflictingStores 259 # Number of conflicting stores.
-memdepunit.memDep.insertedLoads 2050 # Number of loads inserted to the mem dependence unit.
-memdepunit.memDep.insertedStores 1221 # Number of stores inserted to the mem dependence unit.
+host_inst_rate 502967 # Simulator instruction rate (inst/s)
+host_mem_usage 217744 # Number of bytes of host memory used
+host_seconds 3994.27 # Real time elapsed on the host
+host_tick_rate 1895851 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 5623 # Number of instructions simulated
-sim_seconds 0.000000 # Number of seconds simulated
-sim_ticks 6870 # Number of ticks simulated
-system.cpu.commit.COM:branches 862 # Number of branches committed
-system.cpu.commit.COM:bw_lim_events 74 # number cycles where commit BW limit reached
-system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle.samples 6116
-system.cpu.commit.COM:committed_per_cycle.min_value 0
- 0 3908 6389.80%
- 1 1064 1739.70%
- 2 389 636.04%
- 3 210 343.36%
- 4 153 250.16%
- 5 93 152.06%
- 6 76 124.26%
- 7 149 243.62%
- 8 74 120.99%
-system.cpu.commit.COM:committed_per_cycle.max_value 8
-system.cpu.commit.COM:committed_per_cycle.end_dist
-
-system.cpu.commit.COM:count 5640 # Number of instructions committed
-system.cpu.commit.COM:loads 979 # Number of loads committed
-system.cpu.commit.COM:membars 0 # Number of memory barriers committed
-system.cpu.commit.COM:refs 1791 # Number of memory references committed
-system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.branchMispredicts 337 # The number of times a branch was mispredicted
-system.cpu.commit.commitCommittedInsts 5640 # The number of committed instructions
-system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.commitSquashedInsts 4350 # The number of squashed insts skipped by commit
-system.cpu.committedInsts 5623 # Number of Instructions Simulated
-system.cpu.committedInsts_total 5623 # Number of Instructions Simulated
-system.cpu.cpi 1.221768 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 1.221768 # CPI: Total CPI of All Threads
-system.cpu.dcache.ReadReq_accesses 1538 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 3.072000 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2.240000 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits 1413 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 384 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate 0.081274 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses 125 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_hits 25 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_miss_latency 224 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate 0.065020 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses 100 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_accesses 821 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 2.467742 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2.140845 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 635 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 459 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.226553 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 186 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_hits 108 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_miss_latency 152 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.086480 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 71 # number of WriteReq MSHR misses
+sim_insts 2008987724 # Number of instructions simulated
+sim_seconds 0.007573 # Number of seconds simulated
+sim_ticks 7572549003 # Number of ticks simulated
+system.cpu.dcache.ReadReq_accesses 511070058 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 3107.171711 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2107.171711 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits 509611866 # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency 4530852932 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate 0.002853 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses 1458192 # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_miss_latency 3072660932 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate 0.002853 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_misses 1458192 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_accesses 210794909 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_avg_miss_latency 3884.294897 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2884.294897 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits 210722955 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 279490555 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate 0.000341 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses 71954 # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_miss_latency 207536555 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.000341 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses 71954 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles_no_targets 0.800000 # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 11.505618 # Average number of references to valid blocks.
+system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu.dcache.avg_refs 470.762150 # Average number of references to valid blocks.
system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_no_targets 5 # number of cycles access was blocked
+system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles_no_targets 4 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.demand_accesses 2359 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 2.710611 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 2.198830 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 2048 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 843 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.131836 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 311 # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits 133 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 376 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate 0.072488 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 171 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_accesses 721864967 # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency 3143.715362 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 2143.715362 # average overall mshr miss latency
+system.cpu.dcache.demand_hits 720334821 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 4810343487 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate 0.002120 # miss rate for demand accesses
+system.cpu.dcache.demand_misses 1530146 # number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency 3280197487 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate 0.002120 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses 1530146 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.overall_accesses 2359 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 2.710611 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 2.198830 # average overall mshr miss latency
+system.cpu.dcache.overall_accesses 721864967 # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency 3143.715362 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 2143.715362 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 2048 # number of overall hits
-system.cpu.dcache.overall_miss_latency 843 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.131836 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 311 # number of overall misses
-system.cpu.dcache.overall_mshr_hits 133 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 376 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate 0.072488 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 171 # number of overall MSHR misses
+system.cpu.dcache.overall_hits 720334821 # number of overall hits
+system.cpu.dcache.overall_miss_latency 4810343487 # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate 0.002120 # miss rate for overall accesses
+system.cpu.dcache.overall_misses 1530146 # number of overall misses
+system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_miss_latency 3280197487 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate 0.002120 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses 1530146 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@@ -118,92 +73,57 @@ system.cpu.dcache.prefetcher.num_hwpf_issued 0
system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.dcache.replacements 0 # number of replacements
-system.cpu.dcache.sampled_refs 178 # Sample count of references to valid blocks.
+system.cpu.dcache.replacements 1526050 # number of replacements
+system.cpu.dcache.sampled_refs 1530146 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 119.831029 # Cycle average of tags in use
-system.cpu.dcache.total_refs 2048 # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks 0 # number of writebacks
-system.cpu.decode.DECODE:BlockedCycles 387 # Number of cycles decode is blocked
-system.cpu.decode.DECODE:BranchMispred 93 # Number of times decode detected a branch misprediction
-system.cpu.decode.DECODE:BranchResolved 185 # Number of times decode resolved a branch
-system.cpu.decode.DECODE:DecodedInsts 12349 # Number of instructions handled by decode
-system.cpu.decode.DECODE:IdleCycles 3542 # Number of cycles decode is idle
-system.cpu.decode.DECODE:RunCycles 2158 # Number of cycles decode is running
-system.cpu.decode.DECODE:SquashCycles 754 # Number of cycles decode is squashing
-system.cpu.decode.DECODE:SquashedInsts 286 # Number of squashed instructions handled by decode
-system.cpu.decode.DECODE:UnblockCycles 30 # Number of cycles decode is unblocking
-system.cpu.fetch.Branches 2256 # Number of branches that fetch encountered
-system.cpu.fetch.CacheLines 1582 # Number of cache lines fetched
-system.cpu.fetch.Cycles 3905 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.IcacheSquashes 148 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.Insts 13707 # Number of instructions fetch has processed
-system.cpu.fetch.SquashCycles 456 # Number of cycles fetch has spent squashing
-system.cpu.fetch.branchRate 0.328336 # Number of branch fetches per cycle
-system.cpu.fetch.icacheStallCycles 1582 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.predictedBranches 833 # Number of branches that fetch has predicted taken
-system.cpu.fetch.rate 1.994906 # Number of inst fetches per cycle
-system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist.samples 6871
-system.cpu.fetch.rateDist.min_value 0
- 0 4549 6620.58%
- 1 174 253.24%
- 2 186 270.70%
- 3 157 228.50%
- 4 211 307.09%
- 5 153 222.68%
- 6 171 248.87%
- 7 105 152.82%
- 8 1165 1695.53%
-system.cpu.fetch.rateDist.max_value 8
-system.cpu.fetch.rateDist.end_dist
-
-system.cpu.icache.ReadReq_accesses 1582 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 2.960245 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 1.996885 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits 1255 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 968 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate 0.206700 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses 327 # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_hits 6 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_miss_latency 641 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.202908 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses 321 # number of ReadReq MSHR misses
-system.cpu.icache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles_no_targets no value # average number of cycles each access was blocked
-system.cpu.icache.avg_refs 3.909657 # Average number of references to valid blocks.
+system.cpu.dcache.tagsinuse 4087.472566 # Cycle average of tags in use
+system.cpu.dcache.total_refs 720334821 # Total number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 35194000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.writebacks 74591 # number of writebacks
+system.cpu.icache.ReadReq_accesses 2008987725 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency 3103.752500 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 2103.752500 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits 2008977127 # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency 32893569 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_rate 0.000005 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_misses 10598 # number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_miss_latency 22295569 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate 0.000005 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_misses 10598 # number of ReadReq MSHR misses
+system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu.icache.avg_refs 189561.910455 # Average number of references to valid blocks.
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.demand_accesses 1582 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 2.960245 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 1.996885 # average overall mshr miss latency
-system.cpu.icache.demand_hits 1255 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 968 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate 0.206700 # miss rate for demand accesses
-system.cpu.icache.demand_misses 327 # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_hits 6 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 641 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate 0.202908 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses 321 # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_accesses 2008987725 # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency 3103.752500 # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 2103.752500 # average overall mshr miss latency
+system.cpu.icache.demand_hits 2008977127 # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency 32893569 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_rate 0.000005 # miss rate for demand accesses
+system.cpu.icache.demand_misses 10598 # number of demand (read+write) misses
+system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_miss_latency 22295569 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_rate 0.000005 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_misses 10598 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.overall_accesses 1582 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 2.960245 # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 1.996885 # average overall mshr miss latency
+system.cpu.icache.overall_accesses 2008987725 # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency 3103.752500 # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 2103.752500 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits 1255 # number of overall hits
-system.cpu.icache.overall_miss_latency 968 # number of overall miss cycles
-system.cpu.icache.overall_miss_rate 0.206700 # miss rate for overall accesses
-system.cpu.icache.overall_misses 327 # number of overall misses
-system.cpu.icache.overall_mshr_hits 6 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 641 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate 0.202908 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses 321 # number of overall MSHR misses
+system.cpu.icache.overall_hits 2008977127 # number of overall hits
+system.cpu.icache.overall_miss_latency 32893569 # number of overall miss cycles
+system.cpu.icache.overall_miss_rate 0.000005 # miss rate for overall accesses
+system.cpu.icache.overall_misses 10598 # number of overall misses
+system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_miss_latency 22295569 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_rate 0.000005 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_misses 10598 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@@ -215,1726 +135,64 @@ system.cpu.icache.prefetcher.num_hwpf_issued 0
system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.icache.replacements 0 # number of replacements
-system.cpu.icache.sampled_refs 321 # Sample count of references to valid blocks.
+system.cpu.icache.replacements 9048 # number of replacements
+system.cpu.icache.sampled_refs 10598 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 176.393247 # Cycle average of tags in use
-system.cpu.icache.total_refs 1255 # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse 1472.251444 # Cycle average of tags in use
+system.cpu.icache.total_refs 2008977127 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.iew.EXEC:branches 1206 # Number of branches executed
-system.cpu.iew.EXEC:insts 7969 # Number of executed instructions
-system.cpu.iew.EXEC:loads 1610 # Number of load instructions executed
-system.cpu.iew.EXEC:nop 37 # number of nop insts executed
-system.cpu.iew.EXEC:rate 1.159802 # Inst execution rate
-system.cpu.iew.EXEC:refs 2599 # number of memory reference insts executed
-system.cpu.iew.EXEC:squashedInsts 419 # Number of squashed instructions skipped in execute
-system.cpu.iew.EXEC:stores 989 # Number of stores executed
-system.cpu.iew.EXEC:swp 0 # number of swp insts executed
-system.cpu.iew.WB:consumers 5438 # num instructions consuming a value
-system.cpu.iew.WB:count 7722 # cumulative count of insts written-back
-system.cpu.iew.WB:fanout 0.744575 # average fanout of values written-back
-system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.iew.WB:producers 4049 # num instructions producing a value
-system.cpu.iew.WB:rate 1.123854 # insts written-back per cycle
-system.cpu.iew.WB:sent 7762 # cumulative count of insts sent to commit
-system.cpu.iew.branchMispredicts 393 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewBlockCycles 4 # Number of cycles IEW is blocking
-system.cpu.iew.iewDispLoadInsts 2050 # Number of dispatched load instructions
-system.cpu.iew.iewDispNonSpecInsts 21 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewDispSquashedInsts 272 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispStoreInsts 1221 # Number of dispatched store instructions
-system.cpu.iew.iewDispatchedInsts 9990 # Number of instructions dispatched to IQ
-system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.iewSquashCycles 754 # Number of cycles IEW is squashing
-system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking
-system.cpu.iew.lsq.thread.0.blockedLoads 1 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread.0.cacheBlocked 5 # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.lsq.thread.0.forwLoads 55 # Number of loads that had data forwarded from stores
-system.cpu.iew.lsq.thread.0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
-system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread.0.squashedLoads 1071 # Number of loads squashed
-system.cpu.iew.lsq.thread.0.squashedStores 409 # Number of stores squashed
-system.cpu.iew.memOrderViolationEvents 41 # Number of memory order violations
-system.cpu.iew.predictedNotTakenIncorrect 296 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.predictedTakenIncorrect 97 # Number of branches that were predicted taken incorrectly
-system.cpu.ipc 0.818486 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.818486 # IPC: Total IPC of All Threads
-system.cpu.iq.IQ:residence:(null).start_dist # cycles from dispatch to issue
-system.cpu.iq.IQ:residence:(null).samples 0
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-
-system.cpu.iq.IQ:residence:IntAlu.start_dist # cycles from dispatch to issue
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-system.cpu.iq.IQ:residence:IntAlu.end_dist
-
-system.cpu.iq.IQ:residence:IntMult.start_dist # cycles from dispatch to issue
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-system.cpu.iq.IQ:residence:IntMult.end_dist
-
-system.cpu.iq.IQ:residence:IntDiv.start_dist # cycles from dispatch to issue
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-
-system.cpu.iq.IQ:residence:FloatAdd.start_dist # cycles from dispatch to issue
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-
-system.cpu.iq.IQ:residence:FloatCmp.start_dist # cycles from dispatch to issue
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-system.cpu.iq.IQ:residence:FloatCvt.start_dist # cycles from dispatch to issue
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-system.cpu.iq.IQ:residence:FloatMult.start_dist # cycles from dispatch to issue
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-system.cpu.iq.IQ:residence:FloatDiv.start_dist # cycles from dispatch to issue
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-
-system.cpu.iq.IQ:residence:MemWrite.start_dist # cycles from dispatch to issue
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-
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-
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-system.cpu.iq.IQ:residence:InstPrefetch.max_value 0
-system.cpu.iq.IQ:residence:InstPrefetch.end_dist
-
-system.cpu.iq.ISSUE:(null)_delay.start_dist # cycles from operands ready to issue
-system.cpu.iq.ISSUE:(null)_delay.samples 0
-system.cpu.iq.ISSUE:(null)_delay.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
- 20 0
- 22 0
- 24 0
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- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.ISSUE:(null)_delay.max_value 0
-system.cpu.iq.ISSUE:(null)_delay.end_dist
-
-system.cpu.iq.ISSUE:IntAlu_delay.start_dist # cycles from operands ready to issue
-system.cpu.iq.ISSUE:IntAlu_delay.samples 0
-system.cpu.iq.ISSUE:IntAlu_delay.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
- 20 0
- 22 0
- 24 0
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- 30 0
- 32 0
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- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.ISSUE:IntAlu_delay.max_value 0
-system.cpu.iq.ISSUE:IntAlu_delay.end_dist
-
-system.cpu.iq.ISSUE:IntMult_delay.start_dist # cycles from operands ready to issue
-system.cpu.iq.ISSUE:IntMult_delay.samples 0
-system.cpu.iq.ISSUE:IntMult_delay.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
- 20 0
- 22 0
- 24 0
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- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.ISSUE:IntMult_delay.max_value 0
-system.cpu.iq.ISSUE:IntMult_delay.end_dist
-
-system.cpu.iq.ISSUE:IntDiv_delay.start_dist # cycles from operands ready to issue
-system.cpu.iq.ISSUE:IntDiv_delay.samples 0
-system.cpu.iq.ISSUE:IntDiv_delay.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
- 20 0
- 22 0
- 24 0
- 26 0
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- 30 0
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- 78 0
- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.ISSUE:IntDiv_delay.max_value 0
-system.cpu.iq.ISSUE:IntDiv_delay.end_dist
-
-system.cpu.iq.ISSUE:FloatAdd_delay.start_dist # cycles from operands ready to issue
-system.cpu.iq.ISSUE:FloatAdd_delay.samples 0
-system.cpu.iq.ISSUE:FloatAdd_delay.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
- 20 0
- 22 0
- 24 0
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- 30 0
- 32 0
- 34 0
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- 78 0
- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.ISSUE:FloatAdd_delay.max_value 0
-system.cpu.iq.ISSUE:FloatAdd_delay.end_dist
-
-system.cpu.iq.ISSUE:FloatCmp_delay.start_dist # cycles from operands ready to issue
-system.cpu.iq.ISSUE:FloatCmp_delay.samples 0
-system.cpu.iq.ISSUE:FloatCmp_delay.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
- 20 0
- 22 0
- 24 0
- 26 0
- 28 0
- 30 0
- 32 0
- 34 0
- 36 0
- 38 0
- 40 0
- 42 0
- 44 0
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- 78 0
- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.ISSUE:FloatCmp_delay.max_value 0
-system.cpu.iq.ISSUE:FloatCmp_delay.end_dist
-
-system.cpu.iq.ISSUE:FloatCvt_delay.start_dist # cycles from operands ready to issue
-system.cpu.iq.ISSUE:FloatCvt_delay.samples 0
-system.cpu.iq.ISSUE:FloatCvt_delay.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
- 20 0
- 22 0
- 24 0
- 26 0
- 28 0
- 30 0
- 32 0
- 34 0
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- 40 0
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- 44 0
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- 78 0
- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.ISSUE:FloatCvt_delay.max_value 0
-system.cpu.iq.ISSUE:FloatCvt_delay.end_dist
-
-system.cpu.iq.ISSUE:FloatMult_delay.start_dist # cycles from operands ready to issue
-system.cpu.iq.ISSUE:FloatMult_delay.samples 0
-system.cpu.iq.ISSUE:FloatMult_delay.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
- 20 0
- 22 0
- 24 0
- 26 0
- 28 0
- 30 0
- 32 0
- 34 0
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- 40 0
- 42 0
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- 78 0
- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.ISSUE:FloatMult_delay.max_value 0
-system.cpu.iq.ISSUE:FloatMult_delay.end_dist
-
-system.cpu.iq.ISSUE:FloatDiv_delay.start_dist # cycles from operands ready to issue
-system.cpu.iq.ISSUE:FloatDiv_delay.samples 0
-system.cpu.iq.ISSUE:FloatDiv_delay.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
- 20 0
- 22 0
- 24 0
- 26 0
- 28 0
- 30 0
- 32 0
- 34 0
- 36 0
- 38 0
- 40 0
- 42 0
- 44 0
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- 50 0
- 52 0
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- 78 0
- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.ISSUE:FloatDiv_delay.max_value 0
-system.cpu.iq.ISSUE:FloatDiv_delay.end_dist
-
-system.cpu.iq.ISSUE:FloatSqrt_delay.start_dist # cycles from operands ready to issue
-system.cpu.iq.ISSUE:FloatSqrt_delay.samples 0
-system.cpu.iq.ISSUE:FloatSqrt_delay.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
- 20 0
- 22 0
- 24 0
- 26 0
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- 30 0
- 32 0
- 34 0
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- 40 0
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- 44 0
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- 78 0
- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.ISSUE:FloatSqrt_delay.max_value 0
-system.cpu.iq.ISSUE:FloatSqrt_delay.end_dist
-
-system.cpu.iq.ISSUE:MemRead_delay.start_dist # cycles from operands ready to issue
-system.cpu.iq.ISSUE:MemRead_delay.samples 0
-system.cpu.iq.ISSUE:MemRead_delay.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
- 20 0
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- 78 0
- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.ISSUE:MemRead_delay.max_value 0
-system.cpu.iq.ISSUE:MemRead_delay.end_dist
-
-system.cpu.iq.ISSUE:MemWrite_delay.start_dist # cycles from operands ready to issue
-system.cpu.iq.ISSUE:MemWrite_delay.samples 0
-system.cpu.iq.ISSUE:MemWrite_delay.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
- 20 0
- 22 0
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- 30 0
- 32 0
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- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.ISSUE:MemWrite_delay.max_value 0
-system.cpu.iq.ISSUE:MemWrite_delay.end_dist
-
-system.cpu.iq.ISSUE:IprAccess_delay.start_dist # cycles from operands ready to issue
-system.cpu.iq.ISSUE:IprAccess_delay.samples 0
-system.cpu.iq.ISSUE:IprAccess_delay.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
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- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.ISSUE:IprAccess_delay.max_value 0
-system.cpu.iq.ISSUE:IprAccess_delay.end_dist
-
-system.cpu.iq.ISSUE:InstPrefetch_delay.start_dist # cycles from operands ready to issue
-system.cpu.iq.ISSUE:InstPrefetch_delay.samples 0
-system.cpu.iq.ISSUE:InstPrefetch_delay.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
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- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.ISSUE:InstPrefetch_delay.max_value 0
-system.cpu.iq.ISSUE:InstPrefetch_delay.end_dist
-
-system.cpu.iq.ISSUE:FU_type_0 8388 # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0.start_dist
- (null) 2 0.02% # Type of FU issued
- IntAlu 5594 66.69% # Type of FU issued
- IntMult 1 0.01% # Type of FU issued
- IntDiv 0 0.00% # Type of FU issued
- FloatAdd 2 0.02% # Type of FU issued
- FloatCmp 0 0.00% # Type of FU issued
- FloatCvt 0 0.00% # Type of FU issued
- FloatMult 0 0.00% # Type of FU issued
- FloatDiv 0 0.00% # Type of FU issued
- FloatSqrt 0 0.00% # Type of FU issued
- MemRead 1757 20.95% # Type of FU issued
- MemWrite 1032 12.30% # Type of FU issued
- IprAccess 0 0.00% # Type of FU issued
- InstPrefetch 0 0.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0.end_dist
-system.cpu.iq.ISSUE:fu_busy_cnt 115 # FU busy when requested
-system.cpu.iq.ISSUE:fu_busy_rate 0.013710 # FU busy rate (busy events/executed inst)
-system.cpu.iq.ISSUE:fu_full.start_dist
- (null) 0 0.00% # attempts to use FU when none available
- IntAlu 1 0.87% # attempts to use FU when none available
- IntMult 0 0.00% # attempts to use FU when none available
- IntDiv 0 0.00% # attempts to use FU when none available
- FloatAdd 0 0.00% # attempts to use FU when none available
- FloatCmp 0 0.00% # attempts to use FU when none available
- FloatCvt 0 0.00% # attempts to use FU when none available
- FloatMult 0 0.00% # attempts to use FU when none available
- FloatDiv 0 0.00% # attempts to use FU when none available
- FloatSqrt 0 0.00% # attempts to use FU when none available
- MemRead 76 66.09% # attempts to use FU when none available
- MemWrite 38 33.04% # attempts to use FU when none available
- IprAccess 0 0.00% # attempts to use FU when none available
- InstPrefetch 0 0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full.end_dist
-system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle.samples 6871
-system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
- 0 3753 5462.09%
- 1 894 1301.12%
- 2 723 1052.25%
- 3 614 893.61%
- 4 451 656.38%
- 5 279 406.05%
- 6 104 151.36%
- 7 41 59.67%
- 8 12 17.46%
-system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
-system.cpu.iq.ISSUE:issued_per_cycle.end_dist
-
-system.cpu.iq.ISSUE:rate 1.220783 # Inst issue rate
-system.cpu.iq.iqInstsAdded 9932 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqInstsIssued 8388 # Number of instructions issued
-system.cpu.iq.iqNonSpecInstsAdded 21 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqSquashedInstsExamined 3990 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedInstsIssued 21 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedNonSpecRemoved 4 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.iqSquashedOperandsExamined 2486 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.l2cache.ReadReq_accesses 499 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 2.042254 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency 1015 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate 0.995992 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses 497 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 490 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.981964 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses 490 # number of ReadReq MSHR misses
+system.cpu.idle_fraction 0 # Percentage of idle cycles
+system.cpu.l2cache.ReadReq_accesses 1540744 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_avg_miss_latency 2153.831026 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1111.660796 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_hits 33878 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_miss_latency 3245534743 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate 0.978012 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses 1506866 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency 1675123857 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.978012 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses 1506866 # number of ReadReq MSHR misses
+system.cpu.l2cache.WriteReqNoAck|Writeback_accesses 74591 # number of WriteReqNoAck|Writeback accesses(hits+misses)
+system.cpu.l2cache.WriteReqNoAck|Writeback_hits 73517 # number of WriteReqNoAck|Writeback hits
+system.cpu.l2cache.WriteReqNoAck|Writeback_miss_rate 0.014399 # miss rate for WriteReqNoAck|Writeback accesses
+system.cpu.l2cache.WriteReqNoAck|Writeback_misses 1074 # number of WriteReqNoAck|Writeback misses
+system.cpu.l2cache.WriteReqNoAck|Writeback_mshr_miss_rate 0.014399 # mshr miss rate for WriteReqNoAck|Writeback accesses
+system.cpu.l2cache.WriteReqNoAck|Writeback_mshr_misses 1074 # number of WriteReqNoAck|Writeback MSHR misses
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs 0.004024 # Average number of references to valid blocks.
+system.cpu.l2cache.avg_refs 0.071270 # Average number of references to valid blocks.
system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.demand_accesses 499 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 2.042254 # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 1 # average overall mshr miss latency
-system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 1015 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate 0.995992 # miss rate for demand accesses
-system.cpu.l2cache.demand_misses 497 # number of demand (read+write) misses
+system.cpu.l2cache.demand_accesses 1540744 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_avg_miss_latency 2153.831026 # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 1111.660796 # average overall mshr miss latency
+system.cpu.l2cache.demand_hits 33878 # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency 3245534743 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate 0.978012 # miss rate for demand accesses
+system.cpu.l2cache.demand_misses 1506866 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency 490 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate 0.981964 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses 490 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_miss_latency 1675123857 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate 0.978012 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses 1506866 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.overall_accesses 499 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 2.042254 # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 1 # average overall mshr miss latency
+system.cpu.l2cache.overall_accesses 1615335 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_avg_miss_latency 2152.297003 # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 1111.660796 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits 2 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 1015 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate 0.995992 # miss rate for overall accesses
-system.cpu.l2cache.overall_misses 497 # number of overall misses
+system.cpu.l2cache.overall_hits 107395 # number of overall hits
+system.cpu.l2cache.overall_miss_latency 3245534743 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate 0.933515 # miss rate for overall accesses
+system.cpu.l2cache.overall_misses 1507940 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 490 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate 0.981964 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses 490 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_miss_latency 1675123857 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate 0.932850 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses 1506866 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@@ -1946,29 +204,17 @@ system.cpu.l2cache.prefetcher.num_hwpf_issued 0
system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.l2cache.replacements 0 # number of replacements
-system.cpu.l2cache.sampled_refs 497 # Sample count of references to valid blocks.
+system.cpu.l2cache.replacements 1474098 # number of replacements
+system.cpu.l2cache.sampled_refs 1506866 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 295.773395 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks 0 # number of writebacks
-system.cpu.numCycles 6871 # number of cpu cycles simulated
-system.cpu.rename.RENAME:BlockCycles 4 # Number of cycles rename is blocking
-system.cpu.rename.RENAME:CommittedMaps 4051 # Number of HB maps that are committed
-system.cpu.rename.RENAME:IdleCycles 3758 # Number of cycles rename is idle
-system.cpu.rename.RENAME:LSQFullEvents 62 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RENAME:RenameLookups 14786 # Number of register rename lookups that rename has made
-system.cpu.rename.RENAME:RenamedInsts 11555 # Number of instructions processed by rename
-system.cpu.rename.RENAME:RenamedOperands 8634 # Number of destination operands rename has renamed
-system.cpu.rename.RENAME:RunCycles 1975 # Number of cycles rename is running
-system.cpu.rename.RENAME:SquashCycles 754 # Number of cycles rename is squashing
-system.cpu.rename.RENAME:UnblockCycles 111 # Number of cycles rename is unblocking
-system.cpu.rename.RENAME:UndoneMaps 4583 # Number of HB maps that are undone due to squashing
-system.cpu.rename.RENAME:serializeStallCycles 269 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RENAME:serializingInsts 26 # count of serializing insts renamed
-system.cpu.rename.RENAME:skidInsts 408 # count of insts added to the skid buffer
-system.cpu.rename.RENAME:tempSerializingInsts 21 # count of temporary serializing insts renamed
-system.cpu.workload.PROG:num_syscalls 17 # Number of system calls
+system.cpu.l2cache.tagsinuse 32444.673070 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 107395 # Total number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle 164218000 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.writebacks 66806 # number of writebacks
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.numCycles 7572549003 # number of cpu cycles simulated
+system.cpu.num_insts 2008987724 # Number of instructions executed
+system.cpu.num_refs 722390480 # Number of memory references
+system.cpu.workload.PROG:num_syscalls 39 # Number of system calls
---------- End Simulation Statistics ----------
diff --git a/tests/long/40.perlbmk/ref/alpha/linux/simple-timing/stderr b/tests/long/40.perlbmk/ref/alpha/linux/simple-timing/stderr
index 8893caac8..9135960d0 100644
--- a/tests/long/40.perlbmk/ref/alpha/linux/simple-timing/stderr
+++ b/tests/long/40.perlbmk/ref/alpha/linux/simple-timing/stderr
@@ -1,3 +1,2 @@
warn: Entering event queue @ 0. Starting simulation...
-warn: cycle 0: fault (page_table_fault) detected @ PC 0x000000
-warn: Increasing stack 0x11ff92000:0x11ff9b000 to 0x11ff90000:0x11ff9b000 because of access to 0x11ff91ff0
+warn: ignoring syscall sigprocmask(1, 0, ...)
diff --git a/tests/long/40.perlbmk/ref/alpha/linux/simple-timing/stdout b/tests/long/40.perlbmk/ref/alpha/linux/simple-timing/stdout
index fbb329a2f..d4a078b85 100644
--- a/tests/long/40.perlbmk/ref/alpha/linux/simple-timing/stdout
+++ b/tests/long/40.perlbmk/ref/alpha/linux/simple-timing/stdout
@@ -1,13 +1,1376 @@
-Hello world!
-M5 Simulator System
-
-Copyright (c) 2001-2006
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Sep 5 2006 15:28:48
-M5 started Tue Sep 5 15:42:12 2006
-M5 executing on zizzer.eecs.umich.edu
-command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/o3-timing tests/run.py quick/00.hello/alpha/linux/o3-timing
-Exiting @ tick 6870 because target called exit()
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+31000: 2378381393
+30000: 3259365221
+29000: 3960625204
+28000: 3476394666
+27000: 1995310421
+26000: 1884341166
+25000: 3181801013
+24000: 116492838
+23000: 3276567587
+22000: 3693343729
+21000: 2595820568
+20000: 2397879436
+19000: 2692679578
+18000: 2368648652
+17000: 3098196844
+16000: 3913788179
+15000: 1240694507
+14000: 1586030084
+13000: 1211450031
+12000: 3458253062
+11000: 1804606651
+10000: 2128587109
+9000: 1894810186
+8000: 2221431098
+7000: 113605713
+6000: 4020003580
+5000: 2988041351
+4000: 2310084217
+3000: 1475476779
+2000: 760651391
+1000: 4031656975
+0: 2206428413
diff --git a/tests/long/50.vortex/ref/alpha/linux/o3-timing/config.ini b/tests/long/50.vortex/ref/alpha/linux/o3-timing/config.ini
index c3a59fbce..46f72ac13 100644
--- a/tests/long/50.vortex/ref/alpha/linux/o3-timing/config.ini
+++ b/tests/long/50.vortex/ref/alpha/linux/o3-timing/config.ini
@@ -7,11 +7,9 @@ max_tick=0
output_file=cout
progress_interval=0
-[debug]
-break_cycles=
-
[exetrace]
intel_format=false
+legion_lockstep=false
pc_symbol=true
print_cpseq=false
print_cycle=true
@@ -102,14 +100,15 @@ max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
-mem=system.cpu.dcache
numIQEntries=64
numPhysFloatRegs=256
numPhysIntRegs=256
numROBEntries=192
numRobs=1
numThreads=1
+phase=0
predType=tournament
+progress_interval=0
renameToDecodeDelay=1
renameToFetchDelay=1
renameToIEWDelay=2
@@ -131,7 +130,6 @@ assoc=2
block_size=64
compressed_bus=false
compression_latency=0
-do_copy=false
hash_delay=1
hit_latency=1
latency=1
@@ -308,7 +306,6 @@ assoc=2
block_size=64
compressed_bus=false
compression_latency=0
-do_copy=false
hash_delay=1
hit_latency=1
latency=1
@@ -348,7 +345,6 @@ assoc=2
block_size=64
compressed_bus=false
compression_latency=0
-do_copy=false
hash_delay=1
hit_latency=1
latency=1
@@ -384,20 +380,33 @@ mem_side=system.membus.port[1]
[system.cpu.toL2Bus]
type=Bus
bus_id=0
+clock=1000
+responder_set=false
+width=64
port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
[system.cpu.workload]
type=LiveProcess
-cmd=hello
+cmd=vortex lendian.raw
+cwd=build/ALPHA_SE/tests/opt/long/50.vortex/alpha/linux/o3-timing
+egid=100
env=
-executable=tests/test-progs/hello/bin/alpha/linux/hello
+euid=100
+executable=/dist/m5/cpu2000/binaries/alpha/tru64/vortex
+gid=100
input=cin
output=cout
+pid=100
+ppid=99
system=system
+uid=100
[system.membus]
type=Bus
bus_id=0
+clock=1000
+responder_set=false
+width=64
port=system.physmem.port system.cpu.l2cache.mem_side
[system.physmem]
@@ -409,6 +418,7 @@ port=system.membus.port[0]
[trace]
bufsize=0
+cycle=0
dump_on_exit=false
file=cout
flags=
diff --git a/tests/long/50.vortex/ref/alpha/linux/o3-timing/config.out b/tests/long/50.vortex/ref/alpha/linux/o3-timing/config.out
index f491a3081..9e0ede146 100644
--- a/tests/long/50.vortex/ref/alpha/linux/o3-timing/config.out
+++ b/tests/long/50.vortex/ref/alpha/linux/o3-timing/config.out
@@ -19,54 +19,25 @@ mem_mode=atomic
[system.membus]
type=Bus
bus_id=0
+clock=1000
+width=64
+responder_set=false
[system.cpu.workload]
type=LiveProcess
-cmd=hello
-executable=tests/test-progs/hello/bin/alpha/linux/hello
+cmd=vortex lendian.raw
+executable=/dist/m5/cpu2000/binaries/alpha/tru64/vortex
input=cin
output=cout
env=
+cwd=build/ALPHA_SE/tests/opt/long/50.vortex/alpha/linux/o3-timing
system=system
-
-[system.cpu.dcache]
-type=BaseCache
-size=262144
-assoc=2
-block_size=64
-latency=1
-mshrs=10
-tgts_per_mshr=5
-write_buffers=8
-prioritizeRequests=false
-do_copy=false
-protocol=null
-trace_addr=0
-hash_delay=1
-repl=null
-compressed_bus=false
-store_compressed=false
-adaptive_compression=false
-compression_latency=0
-block_size=64
-max_miss_count=0
-addr_range=[0,18446744073709551615]
-split=false
-split_size=0
-lifo=false
-two_queue=false
-prefetch_miss=false
-prefetch_access=false
-prefetcher_size=100
-prefetch_past_page=false
-prefetch_serial_squash=false
-prefetch_latency=10
-prefetch_degree=1
-prefetch_policy=none
-prefetch_cache_check_push=true
-prefetch_use_cpu_id=true
-prefetch_data_accesses_only=false
-hit_latency=1
+uid=100
+euid=100
+gid=100
+egid=100
+pid=100
+ppid=99
[system.cpu.fuPool.FUList0.opList0]
type=OpDesc
@@ -199,15 +170,16 @@ FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUL
[system.cpu]
type=DerivO3CPU
clock=1
+phase=0
numThreads=1
activity=0
workload=system.cpu.workload
-mem=system.cpu.dcache
checker=null
max_insts_any_thread=0
max_insts_all_threads=0
max_loads_any_thread=0
max_loads_all_threads=0
+progress_interval=0
cachePorts=200
decodeToFetchDelay=1
renameToFetchDelay=1
@@ -283,7 +255,44 @@ mshrs=10
tgts_per_mshr=5
write_buffers=8
prioritizeRequests=false
-do_copy=false
+protocol=null
+trace_addr=0
+hash_delay=1
+repl=null
+compressed_bus=false
+store_compressed=false
+adaptive_compression=false
+compression_latency=0
+block_size=64
+max_miss_count=0
+addr_range=[0,18446744073709551615]
+split=false
+split_size=0
+lifo=false
+two_queue=false
+prefetch_miss=false
+prefetch_access=false
+prefetcher_size=100
+prefetch_past_page=false
+prefetch_serial_squash=false
+prefetch_latency=10
+prefetch_degree=1
+prefetch_policy=none
+prefetch_cache_check_push=true
+prefetch_use_cpu_id=true
+prefetch_data_accesses_only=false
+hit_latency=1
+
+[system.cpu.dcache]
+type=BaseCache
+size=262144
+assoc=2
+block_size=64
+latency=1
+mshrs=10
+tgts_per_mshr=5
+write_buffers=8
+prioritizeRequests=false
protocol=null
trace_addr=0
hash_delay=1
@@ -322,7 +331,6 @@ mshrs=10
tgts_per_mshr=5
write_buffers=8
prioritizeRequests=false
-do_copy=false
protocol=null
trace_addr=0
hash_delay=1
@@ -354,10 +362,14 @@ hit_latency=1
[system.cpu.toL2Bus]
type=Bus
bus_id=0
+clock=1000
+width=64
+responder_set=false
[trace]
flags=
start=0
+cycle=0
bufsize=0
file=cout
dump_on_exit=false
@@ -396,8 +408,9 @@ print_cpseq=false
print_reg_delta=false
pc_symbol=true
intel_format=false
+legion_lockstep=false
trace_system=client
-[debug]
-break_cycles=
+[statsreset]
+reset_cycle=0
diff --git a/tests/long/50.vortex/ref/alpha/linux/o3-timing/m5stats.txt b/tests/long/50.vortex/ref/alpha/linux/o3-timing/m5stats.txt
index 5d4f9235a..34a47022b 100644
--- a/tests/long/50.vortex/ref/alpha/linux/o3-timing/m5stats.txt
+++ b/tests/long/50.vortex/ref/alpha/linux/o3-timing/m5stats.txt
@@ -1,112 +1,112 @@
---------- Begin Simulation Statistics ----------
global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-global.BPredUnit.BTBHits 542 # Number of BTB hits
-global.BPredUnit.BTBLookups 1938 # Number of BTB lookups
-global.BPredUnit.RASInCorrect 48 # Number of incorrect RAS predictions.
-global.BPredUnit.condIncorrect 420 # Number of conditional branches incorrect
-global.BPredUnit.condPredicted 1304 # Number of conditional branches predicted
-global.BPredUnit.lookups 2256 # Number of BP lookups
-global.BPredUnit.usedRAS 291 # Number of times the RAS was used to get a target.
-host_inst_rate 41797 # Simulator instruction rate (inst/s)
-host_mem_usage 160344 # Number of bytes of host memory used
-host_seconds 0.13 # Real time elapsed on the host
-host_tick_rate 50948 # Simulator tick rate (ticks/s)
-memdepunit.memDep.conflictingLoads 12 # Number of conflicting loads.
-memdepunit.memDep.conflictingStores 259 # Number of conflicting stores.
-memdepunit.memDep.insertedLoads 2050 # Number of loads inserted to the mem dependence unit.
-memdepunit.memDep.insertedStores 1221 # Number of stores inserted to the mem dependence unit.
+global.BPredUnit.BTBHits 13144986 # Number of BTB hits
+global.BPredUnit.BTBLookups 21876990 # Number of BTB lookups
+global.BPredUnit.RASInCorrect 30485 # Number of incorrect RAS predictions.
+global.BPredUnit.condIncorrect 454636 # Number of conditional branches incorrect
+global.BPredUnit.condPredicted 16268422 # Number of conditional branches predicted
+global.BPredUnit.lookups 26797394 # Number of BP lookups
+global.BPredUnit.usedRAS 4858022 # Number of times the RAS was used to get a target.
+host_inst_rate 52852 # Simulator instruction rate (inst/s)
+host_mem_usage 259420 # Number of bytes of host memory used
+host_seconds 1506.34 # Real time elapsed on the host
+host_tick_rate 744190 # Simulator tick rate (ticks/s)
+memdepunit.memDep.conflictingLoads 14725219 # Number of conflicting loads.
+memdepunit.memDep.conflictingStores 11320400 # Number of conflicting stores.
+memdepunit.memDep.insertedLoads 28503669 # Number of loads inserted to the mem dependence unit.
+memdepunit.memDep.insertedStores 16218894 # Number of stores inserted to the mem dependence unit.
sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 5623 # Number of instructions simulated
-sim_seconds 0.000000 # Number of seconds simulated
-sim_ticks 6870 # Number of ticks simulated
-system.cpu.commit.COM:branches 862 # Number of branches committed
-system.cpu.commit.COM:bw_lim_events 74 # number cycles where commit BW limit reached
+sim_insts 79613339 # Number of instructions simulated
+sim_seconds 0.001121 # Number of seconds simulated
+sim_ticks 1121005014 # Number of ticks simulated
+system.cpu.commit.COM:branches 13759853 # Number of branches committed
+system.cpu.commit.COM:bw_lim_events 3902181 # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle.samples 6116
+system.cpu.commit.COM:committed_per_cycle.samples 88439527
system.cpu.commit.COM:committed_per_cycle.min_value 0
- 0 3908 6389.80%
- 1 1064 1739.70%
- 2 389 636.04%
- 3 210 343.36%
- 4 153 250.16%
- 5 93 152.06%
- 6 76 124.26%
- 7 149 243.62%
- 8 74 120.99%
+ 0 61749847 6982.15%
+ 1 8803671 995.45%
+ 2 5177009 585.37%
+ 3 3274877 370.30%
+ 4 2188473 247.45%
+ 5 1421818 160.77%
+ 6 1152410 130.30%
+ 7 769241 86.98%
+ 8 3902181 441.23%
system.cpu.commit.COM:committed_per_cycle.max_value 8
system.cpu.commit.COM:committed_per_cycle.end_dist
-system.cpu.commit.COM:count 5640 # Number of instructions committed
-system.cpu.commit.COM:loads 979 # Number of loads committed
+system.cpu.commit.COM:count 88361897 # Number of instructions committed
+system.cpu.commit.COM:loads 20383045 # Number of loads committed
system.cpu.commit.COM:membars 0 # Number of memory barriers committed
-system.cpu.commit.COM:refs 1791 # Number of memory references committed
+system.cpu.commit.COM:refs 35229375 # Number of memory references committed
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.branchMispredicts 337 # The number of times a branch was mispredicted
-system.cpu.commit.commitCommittedInsts 5640 # The number of committed instructions
-system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.commitSquashedInsts 4350 # The number of squashed insts skipped by commit
-system.cpu.committedInsts 5623 # Number of Instructions Simulated
-system.cpu.committedInsts_total 5623 # Number of Instructions Simulated
-system.cpu.cpi 1.221768 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 1.221768 # CPI: Total CPI of All Threads
-system.cpu.dcache.ReadReq_accesses 1538 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 3.072000 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2.240000 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits 1413 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 384 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate 0.081274 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses 125 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_hits 25 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_miss_latency 224 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate 0.065020 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses 100 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_accesses 821 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 2.467742 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2.140845 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 635 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 459 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.226553 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 186 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_hits 108 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_miss_latency 152 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.086480 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 71 # number of WriteReq MSHR misses
-system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles_no_targets 0.800000 # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 11.505618 # Average number of references to valid blocks.
-system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_no_targets 5 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles_no_targets 4 # number of cycles access was blocked
+system.cpu.commit.branchMispredicts 360073 # The number of times a branch was mispredicted
+system.cpu.commit.commitCommittedInsts 88361897 # The number of committed instructions
+system.cpu.commit.commitNonSpecStalls 4706 # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.commitSquashedInsts 20725845 # The number of squashed insts skipped by commit
+system.cpu.committedInsts 79613339 # Number of Instructions Simulated
+system.cpu.committedInsts_total 79613339 # Number of Instructions Simulated
+system.cpu.cpi 14.080618 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 14.080618 # CPI: Total CPI of All Threads
+system.cpu.dcache.ReadReq_accesses 19542402 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 4437.586724 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 3280.646620 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits 19388897 # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency 681191750 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate 0.007855 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses 153505 # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_hits 94427 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_miss_latency 193814041 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate 0.003023 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_misses 59078 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_accesses 14615683 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_avg_miss_latency 4852.594089 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 4028.169523 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits 13950409 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 3228304680 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate 0.045518 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses 665274 # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_hits 523305 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_miss_latency 571875199 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.009713 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses 141969 # number of WriteReq MSHR misses
+system.cpu.dcache.avg_blocked_cycles_no_mshrs 3068.165217 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles_no_targets 3779.642588 # average number of cycles each access was blocked
+system.cpu.dcache.avg_refs 165.828418 # Average number of references to valid blocks.
+system.cpu.dcache.blocked_no_mshrs 115 # number of cycles access was blocked
+system.cpu.dcache.blocked_no_targets 125189 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles_no_mshrs 352839 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles_no_targets 473169676 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.demand_accesses 2359 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 2.710611 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 2.198830 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 2048 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 843 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.131836 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 311 # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits 133 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 376 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate 0.072488 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 171 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_accesses 34158085 # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency 4774.788349 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 3808.508657 # average overall mshr miss latency
+system.cpu.dcache.demand_hits 33339306 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 3909496430 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate 0.023970 # miss rate for demand accesses
+system.cpu.dcache.demand_misses 818779 # number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits 617732 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency 765689240 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate 0.005886 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses 201047 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.overall_accesses 2359 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 2.710611 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 2.198830 # average overall mshr miss latency
+system.cpu.dcache.overall_accesses 34158085 # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency 4774.788349 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 3808.508657 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 2048 # number of overall hits
-system.cpu.dcache.overall_miss_latency 843 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.131836 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 311 # number of overall misses
-system.cpu.dcache.overall_mshr_hits 133 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 376 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate 0.072488 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 171 # number of overall MSHR misses
+system.cpu.dcache.overall_hits 33339306 # number of overall hits
+system.cpu.dcache.overall_miss_latency 3909496430 # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate 0.023970 # miss rate for overall accesses
+system.cpu.dcache.overall_misses 818779 # number of overall misses
+system.cpu.dcache.overall_mshr_hits 617732 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_miss_latency 765689240 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate 0.005886 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses 201047 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@@ -118,92 +118,92 @@ system.cpu.dcache.prefetcher.num_hwpf_issued 0
system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.dcache.replacements 0 # number of replacements
-system.cpu.dcache.sampled_refs 178 # Sample count of references to valid blocks.
+system.cpu.dcache.replacements 196951 # number of replacements
+system.cpu.dcache.sampled_refs 201047 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 119.831029 # Cycle average of tags in use
-system.cpu.dcache.total_refs 2048 # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks 0 # number of writebacks
-system.cpu.decode.DECODE:BlockedCycles 387 # Number of cycles decode is blocked
-system.cpu.decode.DECODE:BranchMispred 93 # Number of times decode detected a branch misprediction
-system.cpu.decode.DECODE:BranchResolved 185 # Number of times decode resolved a branch
-system.cpu.decode.DECODE:DecodedInsts 12349 # Number of instructions handled by decode
-system.cpu.decode.DECODE:IdleCycles 3542 # Number of cycles decode is idle
-system.cpu.decode.DECODE:RunCycles 2158 # Number of cycles decode is running
-system.cpu.decode.DECODE:SquashCycles 754 # Number of cycles decode is squashing
-system.cpu.decode.DECODE:SquashedInsts 286 # Number of squashed instructions handled by decode
-system.cpu.decode.DECODE:UnblockCycles 30 # Number of cycles decode is unblocking
-system.cpu.fetch.Branches 2256 # Number of branches that fetch encountered
-system.cpu.fetch.CacheLines 1582 # Number of cache lines fetched
-system.cpu.fetch.Cycles 3905 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.IcacheSquashes 148 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.Insts 13707 # Number of instructions fetch has processed
-system.cpu.fetch.SquashCycles 456 # Number of cycles fetch has spent squashing
-system.cpu.fetch.branchRate 0.328336 # Number of branch fetches per cycle
-system.cpu.fetch.icacheStallCycles 1582 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.predictedBranches 833 # Number of branches that fetch has predicted taken
-system.cpu.fetch.rate 1.994906 # Number of inst fetches per cycle
+system.cpu.dcache.tagsinuse 4057.206862 # Cycle average of tags in use
+system.cpu.dcache.total_refs 33339306 # Total number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 27763000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.writebacks 147199 # number of writebacks
+system.cpu.decode.DECODE:BlockedCycles 11824495 # Number of cycles decode is blocked
+system.cpu.decode.DECODE:BranchMispred 95570 # Number of times decode detected a branch misprediction
+system.cpu.decode.DECODE:BranchResolved 3548160 # Number of times decode resolved a branch
+system.cpu.decode.DECODE:DecodedInsts 129766996 # Number of instructions handled by decode
+system.cpu.decode.DECODE:IdleCycles 51039022 # Number of cycles decode is idle
+system.cpu.decode.DECODE:RunCycles 25179247 # Number of cycles decode is running
+system.cpu.decode.DECODE:SquashCycles 4520828 # Number of cycles decode is squashing
+system.cpu.decode.DECODE:SquashedInsts 280755 # Number of squashed instructions handled by decode
+system.cpu.decode.DECODE:UnblockCycles 396764 # Number of cycles decode is unblocking
+system.cpu.fetch.Branches 26797394 # Number of branches that fetch encountered
+system.cpu.fetch.CacheLines 22435045 # Number of cache lines fetched
+system.cpu.fetch.Cycles 50869599 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.IcacheSquashes 152238 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.Insts 146401648 # Number of instructions fetch has processed
+system.cpu.fetch.SquashCycles 3850495 # Number of cycles fetch has spent squashing
+system.cpu.fetch.branchRate 0.288267 # Number of branch fetches per cycle
+system.cpu.fetch.icacheStallCycles 22435045 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.predictedBranches 18003008 # Number of branches that fetch has predicted taken
+system.cpu.fetch.rate 1.574883 # Number of inst fetches per cycle
system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist.samples 6871
+system.cpu.fetch.rateDist.samples 92960356
system.cpu.fetch.rateDist.min_value 0
- 0 4549 6620.58%
- 1 174 253.24%
- 2 186 270.70%
- 3 157 228.50%
- 4 211 307.09%
- 5 153 222.68%
- 6 171 248.87%
- 7 105 152.82%
- 8 1165 1695.53%
+ 0 64525729 6941.21%
+ 1 1650999 177.60%
+ 2 1736489 186.80%
+ 3 1914591 205.96%
+ 4 6963270 749.06%
+ 5 6073717 653.37%
+ 6 756313 81.36%
+ 7 1939629 208.65%
+ 8 7399619 796.00%
system.cpu.fetch.rateDist.max_value 8
system.cpu.fetch.rateDist.end_dist
-system.cpu.icache.ReadReq_accesses 1582 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 2.960245 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 1.996885 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits 1255 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 968 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate 0.206700 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses 327 # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_hits 6 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_miss_latency 641 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.202908 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses 321 # number of ReadReq MSHR misses
-system.cpu.icache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles_no_targets no value # average number of cycles each access was blocked
-system.cpu.icache.avg_refs 3.909657 # Average number of references to valid blocks.
+system.cpu.icache.ReadReq_accesses 22435044 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency 3343.146524 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 2355.643274 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits 22333491 # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency 339506559 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_rate 0.004527 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_misses 101553 # number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_hits 13791 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_miss_latency 206735965 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate 0.003912 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_misses 87762 # number of ReadReq MSHR misses
+system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles_no_targets 3964.923913 # average number of cycles each access was blocked
+system.cpu.icache.avg_refs 254.480817 # Average number of references to valid blocks.
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu.icache.blocked_no_targets 92 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles_no_targets 364773 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.demand_accesses 1582 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 2.960245 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 1.996885 # average overall mshr miss latency
-system.cpu.icache.demand_hits 1255 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 968 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate 0.206700 # miss rate for demand accesses
-system.cpu.icache.demand_misses 327 # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_hits 6 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 641 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate 0.202908 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses 321 # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_accesses 22435044 # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency 3343.146524 # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 2355.643274 # average overall mshr miss latency
+system.cpu.icache.demand_hits 22333491 # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency 339506559 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_rate 0.004527 # miss rate for demand accesses
+system.cpu.icache.demand_misses 101553 # number of demand (read+write) misses
+system.cpu.icache.demand_mshr_hits 13791 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_miss_latency 206735965 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_rate 0.003912 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_misses 87762 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.overall_accesses 1582 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 2.960245 # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 1.996885 # average overall mshr miss latency
+system.cpu.icache.overall_accesses 22435044 # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency 3343.146524 # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 2355.643274 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits 1255 # number of overall hits
-system.cpu.icache.overall_miss_latency 968 # number of overall miss cycles
-system.cpu.icache.overall_miss_rate 0.206700 # miss rate for overall accesses
-system.cpu.icache.overall_misses 327 # number of overall misses
-system.cpu.icache.overall_mshr_hits 6 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 641 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate 0.202908 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses 321 # number of overall MSHR misses
+system.cpu.icache.overall_hits 22333491 # number of overall hits
+system.cpu.icache.overall_miss_latency 339506559 # number of overall miss cycles
+system.cpu.icache.overall_miss_rate 0.004527 # miss rate for overall accesses
+system.cpu.icache.overall_misses 101553 # number of overall misses
+system.cpu.icache.overall_mshr_hits 13791 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_miss_latency 206735965 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_rate 0.003912 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_misses 87762 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@@ -215,1646 +215,80 @@ system.cpu.icache.prefetcher.num_hwpf_issued 0
system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.icache.replacements 0 # number of replacements
-system.cpu.icache.sampled_refs 321 # Sample count of references to valid blocks.
+system.cpu.icache.replacements 85714 # number of replacements
+system.cpu.icache.sampled_refs 87761 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 176.393247 # Cycle average of tags in use
-system.cpu.icache.total_refs 1255 # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse 1835.660061 # Cycle average of tags in use
+system.cpu.icache.total_refs 22333491 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.iew.EXEC:branches 1206 # Number of branches executed
-system.cpu.iew.EXEC:insts 7969 # Number of executed instructions
-system.cpu.iew.EXEC:loads 1610 # Number of load instructions executed
-system.cpu.iew.EXEC:nop 37 # number of nop insts executed
-system.cpu.iew.EXEC:rate 1.159802 # Inst execution rate
-system.cpu.iew.EXEC:refs 2599 # number of memory reference insts executed
-system.cpu.iew.EXEC:squashedInsts 419 # Number of squashed instructions skipped in execute
-system.cpu.iew.EXEC:stores 989 # Number of stores executed
+system.cpu.idleCycles 1028044659 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.iew.EXEC:branches 14368697 # Number of branches executed
+system.cpu.iew.EXEC:nop 9207761 # number of nop insts executed
+system.cpu.iew.EXEC:rate 0.998957 # Inst execution rate
+system.cpu.iew.EXEC:refs 42889191 # number of memory reference insts executed
+system.cpu.iew.EXEC:stores 15296362 # Number of stores executed
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
-system.cpu.iew.WB:consumers 5438 # num instructions consuming a value
-system.cpu.iew.WB:count 7722 # cumulative count of insts written-back
-system.cpu.iew.WB:fanout 0.744575 # average fanout of values written-back
+system.cpu.iew.WB:consumers 46149810 # num instructions consuming a value
+system.cpu.iew.WB:count 85978243 # cumulative count of insts written-back
+system.cpu.iew.WB:fanout 0.741638 # average fanout of values written-back
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.iew.WB:producers 4049 # num instructions producing a value
-system.cpu.iew.WB:rate 1.123854 # insts written-back per cycle
-system.cpu.iew.WB:sent 7762 # cumulative count of insts sent to commit
-system.cpu.iew.branchMispredicts 393 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewBlockCycles 4 # Number of cycles IEW is blocking
-system.cpu.iew.iewDispLoadInsts 2050 # Number of dispatched load instructions
-system.cpu.iew.iewDispNonSpecInsts 21 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewDispSquashedInsts 272 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispStoreInsts 1221 # Number of dispatched store instructions
-system.cpu.iew.iewDispatchedInsts 9990 # Number of instructions dispatched to IQ
-system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.WB:producers 34226464 # num instructions producing a value
+system.cpu.iew.WB:rate 0.924891 # insts written-back per cycle
+system.cpu.iew.WB:sent 86043563 # cumulative count of insts sent to commit
+system.cpu.iew.branchMispredicts 388948 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewBlockCycles 3476074 # Number of cycles IEW is blocking
+system.cpu.iew.iewDispLoadInsts 28503669 # Number of dispatched load instructions
+system.cpu.iew.iewDispNonSpecInsts 5221 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewDispSquashedInsts 1221579 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispStoreInsts 16218894 # Number of dispatched store instructions
+system.cpu.iew.iewDispatchedInsts 109084579 # Number of instructions dispatched to IQ
+system.cpu.iew.iewExecLoadInsts 27592829 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 454683 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewExecutedInsts 92863355 # Number of executed instructions
+system.cpu.iew.iewIQFullEvents 28537 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.iewSquashCycles 754 # Number of cycles IEW is squashing
-system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking
-system.cpu.iew.lsq.thread.0.blockedLoads 1 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread.0.cacheBlocked 5 # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.lsq.thread.0.forwLoads 55 # Number of loads that had data forwarded from stores
-system.cpu.iew.lsq.thread.0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.iewLSQFullEvents 13436 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.iewSquashCycles 4520828 # Number of cycles IEW is squashing
+system.cpu.iew.iewUnblockCycles 193035 # Number of cycles IEW is unblocking
+system.cpu.iew.lsq.thread.0.blockedLoads 1537 # Number of blocked loads due to partial load-store forwarding
+system.cpu.iew.lsq.thread.0.cacheBlocked 6697780 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread.0.forwLoads 1365345 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread.0.ignoredResponses 4018 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
-system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread.0.squashedLoads 1071 # Number of loads squashed
-system.cpu.iew.lsq.thread.0.squashedStores 409 # Number of stores squashed
-system.cpu.iew.memOrderViolationEvents 41 # Number of memory order violations
-system.cpu.iew.predictedNotTakenIncorrect 296 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.predictedTakenIncorrect 97 # Number of branches that were predicted taken incorrectly
-system.cpu.ipc 0.818486 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.818486 # IPC: Total IPC of All Threads
-system.cpu.iq.IQ:residence:(null).start_dist # cycles from dispatch to issue
-system.cpu.iq.IQ:residence:(null).samples 0
-system.cpu.iq.IQ:residence:(null).min_value 0
- 0 0
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-system.cpu.iq.IQ:residence:(null).max_value 0
-system.cpu.iq.IQ:residence:(null).end_dist
-
-system.cpu.iq.IQ:residence:IntAlu.start_dist # cycles from dispatch to issue
-system.cpu.iq.IQ:residence:IntAlu.samples 0
-system.cpu.iq.IQ:residence:IntAlu.min_value 0
- 0 0
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-system.cpu.iq.IQ:residence:IntAlu.max_value 0
-system.cpu.iq.IQ:residence:IntAlu.end_dist
-
-system.cpu.iq.IQ:residence:IntMult.start_dist # cycles from dispatch to issue
-system.cpu.iq.IQ:residence:IntMult.samples 0
-system.cpu.iq.IQ:residence:IntMult.min_value 0
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-system.cpu.iq.IQ:residence:IntMult.max_value 0
-system.cpu.iq.IQ:residence:IntMult.end_dist
-
-system.cpu.iq.IQ:residence:IntDiv.start_dist # cycles from dispatch to issue
-system.cpu.iq.IQ:residence:IntDiv.samples 0
-system.cpu.iq.IQ:residence:IntDiv.min_value 0
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-system.cpu.iq.IQ:residence:IntDiv.max_value 0
-system.cpu.iq.IQ:residence:IntDiv.end_dist
-
-system.cpu.iq.IQ:residence:FloatAdd.start_dist # cycles from dispatch to issue
-system.cpu.iq.IQ:residence:FloatAdd.samples 0
-system.cpu.iq.IQ:residence:FloatAdd.min_value 0
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-
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-
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-
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-
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-
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-
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-
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-
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-
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-
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- 0 0
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- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
- 20 0
- 22 0
- 24 0
- 26 0
- 28 0
- 30 0
- 32 0
- 34 0
- 36 0
- 38 0
- 40 0
- 42 0
- 44 0
- 46 0
- 48 0
- 50 0
- 52 0
- 54 0
- 56 0
- 58 0
- 60 0
- 62 0
- 64 0
- 66 0
- 68 0
- 70 0
- 72 0
- 74 0
- 76 0
- 78 0
- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.ISSUE:InstPrefetch_delay.max_value 0
-system.cpu.iq.ISSUE:InstPrefetch_delay.end_dist
-
-system.cpu.iq.ISSUE:FU_type_0 8388 # Type of FU issued
+system.cpu.iew.lsq.thread.0.memOrderViolation 3952 # Number of memory ordering violations
+system.cpu.iew.lsq.thread.0.rescheduledLoads 1537 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread.0.squashedLoads 8120624 # Number of loads squashed
+system.cpu.iew.lsq.thread.0.squashedStores 1372564 # Number of stores squashed
+system.cpu.iew.memOrderViolationEvents 3952 # Number of memory order violations
+system.cpu.iew.predictedNotTakenIncorrect 217352 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.predictedTakenIncorrect 171596 # Number of branches that were predicted taken incorrectly
+system.cpu.ipc 0.071020 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.071020 # IPC: Total IPC of All Threads
+system.cpu.iq.ISSUE:FU_type_0 93318038 # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0.start_dist
- (null) 2 0.02% # Type of FU issued
- IntAlu 5594 66.69% # Type of FU issued
- IntMult 1 0.01% # Type of FU issued
+ (null) 0 0.00% # Type of FU issued
+ IntAlu 49917747 53.49% # Type of FU issued
+ IntMult 43212 0.05% # Type of FU issued
IntDiv 0 0.00% # Type of FU issued
- FloatAdd 2 0.02% # Type of FU issued
- FloatCmp 0 0.00% # Type of FU issued
- FloatCvt 0 0.00% # Type of FU issued
- FloatMult 0 0.00% # Type of FU issued
- FloatDiv 0 0.00% # Type of FU issued
+ FloatAdd 123778 0.13% # Type of FU issued
+ FloatCmp 88 0.00% # Type of FU issued
+ FloatCvt 122460 0.13% # Type of FU issued
+ FloatMult 54 0.00% # Type of FU issued
+ FloatDiv 37863 0.04% # Type of FU issued
FloatSqrt 0 0.00% # Type of FU issued
- MemRead 1757 20.95% # Type of FU issued
- MemWrite 1032 12.30% # Type of FU issued
+ MemRead 27694961 29.68% # Type of FU issued
+ MemWrite 15377875 16.48% # Type of FU issued
IprAccess 0 0.00% # Type of FU issued
InstPrefetch 0 0.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0.end_dist
-system.cpu.iq.ISSUE:fu_busy_cnt 115 # FU busy when requested
-system.cpu.iq.ISSUE:fu_busy_rate 0.013710 # FU busy rate (busy events/executed inst)
+system.cpu.iq.ISSUE:fu_busy_cnt 1239796 # FU busy when requested
+system.cpu.iq.ISSUE:fu_busy_rate 0.013286 # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:fu_full.start_dist
(null) 0 0.00% # attempts to use FU when none available
- IntAlu 1 0.87% # attempts to use FU when none available
+ IntAlu 81158 6.55% # attempts to use FU when none available
IntMult 0 0.00% # attempts to use FU when none available
IntDiv 0 0.00% # attempts to use FU when none available
FloatAdd 0 0.00% # attempts to use FU when none available
@@ -1863,78 +297,84 @@ system.cpu.iq.ISSUE:fu_full.start_dist
FloatMult 0 0.00% # attempts to use FU when none available
FloatDiv 0 0.00% # attempts to use FU when none available
FloatSqrt 0 0.00% # attempts to use FU when none available
- MemRead 76 66.09% # attempts to use FU when none available
- MemWrite 38 33.04% # attempts to use FU when none available
+ MemRead 587235 47.37% # attempts to use FU when none available
+ MemWrite 571403 46.09% # attempts to use FU when none available
IprAccess 0 0.00% # attempts to use FU when none available
InstPrefetch 0 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full.end_dist
system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle.samples 6871
+system.cpu.iq.ISSUE:issued_per_cycle.samples 92960356
system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
- 0 3753 5462.09%
- 1 894 1301.12%
- 2 723 1052.25%
- 3 614 893.61%
- 4 451 656.38%
- 5 279 406.05%
- 6 104 151.36%
- 7 41 59.67%
- 8 12 17.46%
+ 0 53328498 5736.69%
+ 1 13184129 1418.25%
+ 2 10577669 1137.87%
+ 3 8760562 942.40%
+ 4 4405028 473.86%
+ 5 1612052 173.41%
+ 6 698100 75.10%
+ 7 326631 35.14%
+ 8 67687 7.28%
system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
system.cpu.iq.ISSUE:issued_per_cycle.end_dist
-system.cpu.iq.ISSUE:rate 1.220783 # Inst issue rate
-system.cpu.iq.iqInstsAdded 9932 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqInstsIssued 8388 # Number of instructions issued
-system.cpu.iq.iqNonSpecInstsAdded 21 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqSquashedInstsExamined 3990 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedInstsIssued 21 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedNonSpecRemoved 4 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.iqSquashedOperandsExamined 2486 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.l2cache.ReadReq_accesses 499 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 2.042254 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency 1015 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate 0.995992 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses 497 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 490 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.981964 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses 490 # number of ReadReq MSHR misses
+system.cpu.iq.ISSUE:rate 1.003848 # Inst issue rate
+system.cpu.iq.iqInstsAdded 99871597 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqInstsIssued 93318038 # Number of instructions issued
+system.cpu.iq.iqNonSpecInstsAdded 5221 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqSquashedInstsExamined 20057396 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedInstsIssued 77651 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedNonSpecRemoved 515 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.iqSquashedOperandsExamined 15480029 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.l2cache.ReadReq_accesses 288801 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_avg_miss_latency 3932.513738 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2042.965502 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_hits 119343 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_miss_latency 666395913 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate 0.586764 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses 169458 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency 346196848 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.586764 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses 169458 # number of ReadReq MSHR misses
+system.cpu.l2cache.WriteReqNoAck|Writeback_accesses 147199 # number of WriteReqNoAck|Writeback accesses(hits+misses)
+system.cpu.l2cache.WriteReqNoAck|Writeback_hits 146588 # number of WriteReqNoAck|Writeback hits
+system.cpu.l2cache.WriteReqNoAck|Writeback_miss_rate 0.004151 # miss rate for WriteReqNoAck|Writeback accesses
+system.cpu.l2cache.WriteReqNoAck|Writeback_misses 611 # number of WriteReqNoAck|Writeback misses
+system.cpu.l2cache.WriteReqNoAck|Writeback_mshr_miss_rate 0.004151 # mshr miss rate for WriteReqNoAck|Writeback accesses
+system.cpu.l2cache.WriteReqNoAck|Writeback_mshr_misses 611 # number of WriteReqNoAck|Writeback MSHR misses
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs 0.004024 # Average number of references to valid blocks.
+system.cpu.l2cache.avg_refs 1.569313 # Average number of references to valid blocks.
system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.demand_accesses 499 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 2.042254 # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 1 # average overall mshr miss latency
-system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 1015 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate 0.995992 # miss rate for demand accesses
-system.cpu.l2cache.demand_misses 497 # number of demand (read+write) misses
+system.cpu.l2cache.demand_accesses 288801 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_avg_miss_latency 3932.513738 # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 2042.965502 # average overall mshr miss latency
+system.cpu.l2cache.demand_hits 119343 # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency 666395913 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate 0.586764 # miss rate for demand accesses
+system.cpu.l2cache.demand_misses 169458 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency 490 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate 0.981964 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses 490 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_miss_latency 346196848 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate 0.586764 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses 169458 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.overall_accesses 499 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 2.042254 # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 1 # average overall mshr miss latency
+system.cpu.l2cache.overall_accesses 436000 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_avg_miss_latency 3918.385555 # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 2042.965502 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits 2 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 1015 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate 0.995992 # miss rate for overall accesses
-system.cpu.l2cache.overall_misses 497 # number of overall misses
+system.cpu.l2cache.overall_hits 265931 # number of overall hits
+system.cpu.l2cache.overall_miss_latency 666395913 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate 0.390067 # miss rate for overall accesses
+system.cpu.l2cache.overall_misses 170069 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 490 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate 0.981964 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses 490 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_miss_latency 346196848 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate 0.388665 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses 169458 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@@ -1946,29 +386,32 @@ system.cpu.l2cache.prefetcher.num_hwpf_issued 0
system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.l2cache.replacements 0 # number of replacements
-system.cpu.l2cache.sampled_refs 497 # Sample count of references to valid blocks.
+system.cpu.l2cache.replacements 136689 # number of replacements
+system.cpu.l2cache.sampled_refs 169457 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 295.773395 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks 0 # number of writebacks
-system.cpu.numCycles 6871 # number of cpu cycles simulated
-system.cpu.rename.RENAME:BlockCycles 4 # Number of cycles rename is blocking
-system.cpu.rename.RENAME:CommittedMaps 4051 # Number of HB maps that are committed
-system.cpu.rename.RENAME:IdleCycles 3758 # Number of cycles rename is idle
-system.cpu.rename.RENAME:LSQFullEvents 62 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RENAME:RenameLookups 14786 # Number of register rename lookups that rename has made
-system.cpu.rename.RENAME:RenamedInsts 11555 # Number of instructions processed by rename
-system.cpu.rename.RENAME:RenamedOperands 8634 # Number of destination operands rename has renamed
-system.cpu.rename.RENAME:RunCycles 1975 # Number of cycles rename is running
-system.cpu.rename.RENAME:SquashCycles 754 # Number of cycles rename is squashing
-system.cpu.rename.RENAME:UnblockCycles 111 # Number of cycles rename is unblocking
-system.cpu.rename.RENAME:UndoneMaps 4583 # Number of HB maps that are undone due to squashing
-system.cpu.rename.RENAME:serializeStallCycles 269 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RENAME:serializingInsts 26 # count of serializing insts renamed
-system.cpu.rename.RENAME:skidInsts 408 # count of insts added to the skid buffer
-system.cpu.rename.RENAME:tempSerializingInsts 21 # count of temporary serializing insts renamed
-system.cpu.workload.PROG:num_syscalls 17 # Number of system calls
+system.cpu.l2cache.tagsinuse 30306.924097 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 265931 # Total number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle 442261000 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.writebacks 115687 # number of writebacks
+system.cpu.numCycles 92960356 # number of cpu cycles simulated
+system.cpu.rename.RENAME:BlockCycles 7634208 # Number of cycles rename is blocking
+system.cpu.rename.RENAME:CommittedMaps 52562815 # Number of HB maps that are committed
+system.cpu.rename.RENAME:IQFullEvents 86713 # Number of times rename has blocked due to IQ full
+system.cpu.rename.RENAME:IdleCycles 51709233 # Number of cycles rename is idle
+system.cpu.rename.RENAME:LSQFullEvents 3226687 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RENAME:ROBFullEvents 2442 # Number of times rename has blocked due to ROB full
+system.cpu.rename.RENAME:RenameLookups 152860701 # Number of register rename lookups that rename has made
+system.cpu.rename.RENAME:RenamedInsts 128373944 # Number of instructions processed by rename
+system.cpu.rename.RENAME:RenamedOperands 81757058 # Number of destination operands rename has renamed
+system.cpu.rename.RENAME:RunCycles 24895195 # Number of cycles rename is running
+system.cpu.rename.RENAME:SquashCycles 4520828 # Number of cycles rename is squashing
+system.cpu.rename.RENAME:UnblockCycles 3457989 # Number of cycles rename is unblocking
+system.cpu.rename.RENAME:UndoneMaps 29194243 # Number of HB maps that are undone due to squashing
+system.cpu.rename.RENAME:serializeStallCycles 742903 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RENAME:serializingInsts 5237 # count of serializing insts renamed
+system.cpu.rename.RENAME:skidInsts 6117149 # count of insts added to the skid buffer
+system.cpu.rename.RENAME:tempSerializingInsts 5235 # count of temporary serializing insts renamed
+system.cpu.timesIdled 271656 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.workload.PROG:num_syscalls 4706 # Number of system calls
---------- End Simulation Statistics ----------
diff --git a/tests/long/50.vortex/ref/alpha/linux/o3-timing/smred.msg b/tests/long/50.vortex/ref/alpha/linux/o3-timing/smred.msg
new file mode 100644
index 000000000..327142d7c
--- /dev/null
+++ b/tests/long/50.vortex/ref/alpha/linux/o3-timing/smred.msg
@@ -0,0 +1,158 @@
+
+ SYSTEM TYPE...
+ __ZTC__ := False
+ __UNIX__ := True
+ __RISC__ := True
+ SPEC_CPU2000_LP64 := True
+ __MAC__ := False
+ __BCC__ := False
+ __BORLANDC__ := False
+ __GUI__ := False
+ __WTC__ := False
+ __HP__ := False
+
+ CODE OPTIONS...
+ __MACROIZE_HM__ := True
+ __MACROIZE_MEM__ := True
+ ENV01 := True
+ USE_HPP_STYPE_HDRS := False
+ USE_H_STYPE_HDRS := False
+
+ CODE INCLUSION PARAMETERS...
+ INCLUDE_ALL_CODE := False
+ INCLUDE_DELETE_CODE := True
+ __SWAP_GRP_POS__ := True
+ __INCLUDE_MTRX__ := False
+ __BAD_CODE__ := False
+ API_INCLUDE := False
+ BE_CAREFUL := False
+ OLDWAY := False
+ NOTUSED := False
+
+ SYSTEM PARAMETERS...
+ EXT_ENUM := 999999999L
+ CHUNK_CONSTANT := 55555555
+ CORE_CONSTANT := 55555555
+ CORE_LIMIT := 20971520
+ CorePage_Size := 384000
+ ALIGN_BYTES := True
+ CORE_BLOCK_ALIGN := 8
+ FAR_MEM := False
+
+ MEMORY MANAGEMENT PARAMETERS...
+ SYSTEM_ALLOC := True
+ SYSTEM_FREESTORE := True
+ __NO_DISKCACHE__ := False
+ __FREEZE_VCHUNKS__ := True
+ __FREEZE_GRP_PACKETS__ := True
+ __MINIMIZE_TREE_CACHE__:= True
+
+ SYSTEM STD PARAMETERS...
+ __STDOUT__ := False
+ NULL := 0
+ LPTR := False
+ False_Status := 1
+ True_Status := 0
+ LARGE := True
+ TWOBYTE_BOOL := False
+ __NOSTR__ := False
+
+ MEMORY VALIDATION PARAMETERS...
+ CORE_CRC_CHECK := False
+ VALIDATE_MEM_CHUNKS := False
+
+ SYSTEM DEBUG OPTIONS...
+ DEBUG := False
+ MCSTAT := False
+ TRACKBACK := False
+ FLUSH_FILES := False
+ DEBUG_CORE0 := False
+ DEBUG_RISC := False
+ __TREE_BUG__ := False
+ __TRACK_FILE_READS__ := False
+ PAGE_SPACE := False
+ LEAVE_NO_TRACE := True
+ NULL_TRACE_STRS := False
+
+ TIME PARAMETERS...
+ CLOCK_IS_LONG := False
+ __DISPLAY_TIME__ := False
+ __TREE_TIME__ := False
+ __DISPLAY_ERRORS__ := False
+
+ API MACROS...
+ __BMT01__ := True
+ OPTIMIZE := True
+
+ END OF DEFINES.
+
+
+
+ ... IMPLODE MEMORY ...
+
+ SWAP to DiskCache := False
+
+ FREEZE_GRP_PACKETS:= True
+
+ QueBug := 1000
+
+ sizeof(boolean) = 4
+ sizeof(sizetype) = 4
+ sizeof(chunkstruc) = 32
+
+ sizeof(shorttype ) = 2
+ sizeof(idtype ) = 2
+ sizeof(sizetype ) = 4
+ sizeof(indextype ) = 4
+ sizeof(numtype ) = 4
+ sizeof(handletype) = 4
+ sizeof(tokentype ) = 8
+
+ sizeof(short ) = 2
+ sizeof(int ) = 4
+
+ sizeof(lt64 ) = 4
+ sizeof(farlongtype) = 4
+ sizeof(long ) = 8
+ sizeof(longaddr ) = 8
+
+ sizeof(float ) = 4
+ sizeof(double ) = 8
+
+ sizeof(addrtype ) = 8
+ sizeof(char * ) = 8
+ ALLOC CORE_1 :: 16
+ BHOOLE NATH
+
+ OPEN File ./input/lendian.rnv
+ *Status = 0
+ DB HDR restored from FileVbn[ 0]
+ DB BlkDirOffset : @ 2030c0
+ DB BlkDirChunk : Chunk[ 10] AT Vbn[3146]
+ DB BlkTknChunk : Chunk[ 11] AT Vbn[3147]
+ DB BlkSizeChunk : Chunk[ 12] AT Vbn[3148]
+ DB Handle Chunk's StackPtr = 20797
+
+ DB[ 1] LOADED; Handles= 20797
+ KERNEL in CORE[ 1] Restored @ 40054800
+
+ OPEN File ./input/lendian.wnv
+ *Status = 0
+ DB HDR restored from FileVbn[ 0]
+ DB BlkDirOffset : @ 21c40
+ DB BlkDirChunk : Chunk[ 31] AT Vbn[ 81]
+ DB BlkTknChunk : Chunk[ 32] AT Vbn[ 82]
+ DB BlkSizeChunk : Chunk[ 33] AT Vbn[ 83]
+ DB Handle Chunk's StackPtr = 17
+
+ DB[ 2] LOADED; Handles= 17
+ VORTEx_Status == -8 || fffffff8
+
+ BE HERE NOW !!!
+
+
+
+ ... VORTEx ON LINE ...
+
+
+ ... END OF SESSION ...
diff --git a/tests/long/50.vortex/ref/alpha/linux/o3-timing/smred.out b/tests/long/50.vortex/ref/alpha/linux/o3-timing/smred.out
new file mode 100644
index 000000000..726b45c60
--- /dev/null
+++ b/tests/long/50.vortex/ref/alpha/linux/o3-timing/smred.out
@@ -0,0 +1,258 @@
+ CREATE Db Header and Db Primal ...
+ NEW DB [ 3] Created.
+
+VORTEX INPUT PARAMETERS::
+ MESSAGE FileName: smred.msg
+ OUTPUT FileName: smred.out
+ DISK CACHE FileName: NULL
+ PART DB FileName: parts.db
+ DRAW DB FileName: draw.db
+ PERSON DB FileName: emp.db
+ PERSONS Data FileName: ./input/persons.250
+ PARTS Count : 100
+ OUTER Loops : 1
+ INNER Loops : 1
+ LOOKUP Parts : 25
+ DELETE Parts : 10
+ STUFF Parts : 10
+ DEPTH Traverse: 5
+ % DECREASE Parts : 0
+ % INCREASE LookUps : 0
+ % INCREASE Deletes : 0
+ % INCREASE Stuffs : 0
+ FREEZE_PACKETS : 1
+ ALLOC_CHUNKS : 10000
+ EXTEND_CHUNKS : 5000
+ DELETE Draw objects : True
+ DELETE Part objects : False
+ QUE_BUG : 1000
+ VOID_BOUNDARY : 67108864
+ VOID_RESERVE : 1048576
+
+ COMMIT_DBS : False
+
+
+
+ BMT TEST :: files...
+ EdbName := PartLib
+ EdbFileName := parts.db
+ DrwName := DrawLib
+ DrwFileName := draw.db
+ EmpName := PersonLib
+ EmpFileName := emp.db
+
+ Swap to DiskCache := False
+ Freeze the cache := True
+
+
+ BMT TEST :: parms...
+ DeBug modulo := 1000
+ Create Parts count:= 100
+ Outer Loops := 1
+ Inner Loops := 1
+ Look Ups := 25
+ Delete Parts := 10
+ Stuff Parts := 10
+ Traverse Limit := 5
+ Delete Draws := True
+ Delete Parts := False
+ Delete ALL Parts := after every <mod 0>Outer Loop
+
+ INITIALIZE LIBRARY ::
+
+ INITIALIZE SCHEMA ::
+ Primal_CreateDb Accessed !!!
+ CREATE Db Header and Db Primal ...
+ NEW DB [ 4] Created.
+ PartLibCreate:: Db[ 4]; VpartsDir= 1
+
+ Part Count= 1
+
+ Initialize the Class maps
+ LIST HEADS loaded ... DbListHead_Class = 207
+ DbListNode_Class = 206
+
+...NOTE... ShellLoadCode:: Class[ 228] will NOT be Activated.
+
+
+...NOTE... ShellLoadCode:: Class[ 229] will NOT be Activated.
+
+ Primal_CreateDb Accessed !!!
+ CREATE Db Header and Db Primal ...
+ NEW DB [ 5] Created.
+ DrawLibCreate:: Db[ 5]; VpartsDir= 1
+
+ Initialize the Class maps of this schema.
+ Primal_CreateDb Accessed !!!
+ CREATE Db Header and Db Primal ...
+ NEW DB [ 6] Created.
+
+ ***NOTE*** Persons Library Extended!
+
+ Create <131072> Persons.
+ ItNum 0. Person[ 6: 5]. Name= Riddell , Robert V. ;
+
+ LAST Person Read::
+ ItNum 250. Person[ 6: 503]. Name= Gonzales , Warren X. ;
+
+ BUILD <Query0> for <Part2> class::
+
+ if (link[1].length >= 5) ::
+
+ Build Query2 for <Address> class::
+
+ if (State == CA || State == T*)
+
+ Build Query1 for <Person> class::
+
+ if (LastName >= H* && LastName <= P* && Query0(Residence)) ::
+
+ BUILD <Query3> for <DrawObj> class::
+
+ if (Id >= 3000
+ && (Id >= 3000 && Id <= 3001)
+ && Id >= 3002)
+
+ BUILD <Query4> for <NamedDrawObj> class::
+
+ if (Nam == Pre*
+ || (Nam == ??Mid??? || == Pre??Mid?? || == ??Post
+ || == Pre??Post || == ??Mid???Post || == Pre??Mid???Post)
+ && Id <= 7)
+ SEED := 1008; Swap = False; RgnEntries = 135
+
+ OUTER LOOP [ 1] : NewParts = 100 LookUps = 25 StuffParts = 10.
+
+ Create 100 New Parts
+ Create Part 1. Token[ 4: 2].
+
+ < 100> Parts Created. CurrentId= 100
+
+ Connect each instantiated Part TO 3 unique Parts
+ Connect Part 1. Token[ 4: 2]
+ Connect Part 25. Token[ 4: 26] FromList= 26.
+ Connect Part 12. Token[ 4: 13] FromList= 13.
+ Connect Part 59. Token[ 4: 60] FromList= 60.
+
+ SET <DrawObjs> entries::
+ 1. [ 5: 5] := <1 >; @[: 6]
+ Iteration count = 100
+
+ SET <NamedDrawObjs> entries::
+ 1. [ 5: 39] := <14 >;
+ Iteration count = 12
+
+ SET <LibRectangles> entries::
+ 1. [ 5: 23] := <8 >; @[: 24]
+ Iteration count = 12
+
+ LIST <DbRectangles> entries::
+ 1. [ 5: 23]
+ Iteration count = 12
+
+ SET <PersonNames > entries::
+ Iteration count = 250
+
+ COMMIT All Image copies:: Release=<True>; Max Parts= 100
+ < 100> Part images' Committed.
+ < 0> are Named.
+ < 50> Point images' Committed.
+ < 81> Person images' Committed.
+
+ COMMIT Parts(* 100)
+
+ Commit TestObj_Class in <Primal> DB.
+ ItNum 0. Token[ 0: 0]. TestObj Committed.
+ < 0> TestObj images' Committed.
+
+ Commit CartesianPoint_Class in <Primal> DB.
+ ItNum 0. Token[ 0: 0]. CartesianPoint Committed.
+ < 0> CartesianPoint images' Committed.
+
+ BEGIN Inner Loop Sequence::.
+
+ INNER LOOP [ 1: 1] :
+
+ LOOK UP 25 Random Parts and Export each Part.
+
+ LookUp for 26 parts; Asserts = 8
+ <Part2 > Asserts = 2; NULL Asserts = 3.
+ <DrawObj > Asserts = 0; NULL Asserts = 5.
+ <NamedObj > Asserts = 0; NULL Asserts = 0.
+ <Person > Asserts = 0; NULL Asserts = 5.
+ <TestObj > Asserts = 60; NULL Asserts = 0.
+
+ DELETE 10 Random Parts.
+
+ PartDelete :: Token[ 4: 91].
+ PartDisconnect:: Token[ 4: 91] id:= 90 for each link.
+ DisConnect link [ 0]:= 50; PartToken[ 51: 51].
+ DisConnect link [ 1]:= 17; PartToken[ 18: 18].
+ DisConnect link [ 2]:= 72; PartToken[ 73: 73].
+ DeleteFromList:: Vchunk[ 4: 91]. (* 1)
+ DisConnect FromList[ 0]:= 56; Token[ 57: 57].
+ Vlists[ 89] := 100;
+
+ Delete for 11 parts;
+
+ Traverse Count= 0
+
+ TRAVERSE PartId[ 6] and all Connections to 5 Levels
+ SEED In Traverse Part [ 4: 65] @ Level = 4.
+
+ Traverse Count= 357
+ Traverse Asserts = 5. True Tests = 1
+ < 5> DrawObj objects DELETED.
+ < 2> are Named.
+ < 2> Point objects DELETED.
+
+ CREATE 10 Additional Parts
+
+ Create 10 New Parts
+ Create Part 101. Token[ 4: 102].
+
+ < 10> Parts Created. CurrentId= 110
+
+ Connect each instantiated Part TO 3 unique Parts
+
+ COMMIT All Image copies:: Release=<True>; Max Parts= 110
+ < 81> Part images' Committed.
+ < 0> are Named.
+ < 38> Point images' Committed.
+ < 31> Person images' Committed.
+
+ COMMIT Parts(* 100)
+
+ Commit TestObj_Class in <Primal> DB.
+ ItNum 0. Token[ 3: 4]. TestObj Committed.
+ < 15> TestObj images' Committed.
+
+ Commit CartesianPoint_Class in <Primal> DB.
+ ItNum 0. Token[ 3: 3]. CartesianPoint Committed.
+ < 16> CartesianPoint images' Committed.
+
+ DELETE All TestObj objects;
+
+ Delete TestObj_Class in <Primal> DB.
+ ItNum 0. Token[ 3: 4]. TestObj Deleted.
+ < 15> TestObj objects Deleted.
+
+ Commit CartesianPoint_Class in <Primal> DB.
+ ItNum 0. Token[ 3: 3]. CartesianPoint Deleted.
+ < 16> CartesianPoint objects Deleted.
+
+ DELETE TestObj and Point objects...
+
+ END INNER LOOP [ 1: 1].
+
+ DELETE All TestObj objects;
+
+ Delete TestObj_Class in <Primal> DB.
+ < 0> TestObj objects Deleted.
+
+ Commit CartesianPoint_Class in <Primal> DB.
+ < 0> CartesianPoint objects Deleted.
+
+ DELETE TestObj and Point objects...
+ STATUS= -201
+V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!
diff --git a/tests/long/50.vortex/ref/alpha/linux/o3-timing/stderr b/tests/long/50.vortex/ref/alpha/linux/o3-timing/stderr
index 8893caac8..87866a2a5 100644
--- a/tests/long/50.vortex/ref/alpha/linux/o3-timing/stderr
+++ b/tests/long/50.vortex/ref/alpha/linux/o3-timing/stderr
@@ -1,3 +1 @@
warn: Entering event queue @ 0. Starting simulation...
-warn: cycle 0: fault (page_table_fault) detected @ PC 0x000000
-warn: Increasing stack 0x11ff92000:0x11ff9b000 to 0x11ff90000:0x11ff9b000 because of access to 0x11ff91ff0
diff --git a/tests/long/50.vortex/ref/alpha/linux/o3-timing/stdout b/tests/long/50.vortex/ref/alpha/linux/o3-timing/stdout
index fbb329a2f..e69de29bb 100644
--- a/tests/long/50.vortex/ref/alpha/linux/o3-timing/stdout
+++ b/tests/long/50.vortex/ref/alpha/linux/o3-timing/stdout
@@ -1,13 +0,0 @@
-Hello world!
-M5 Simulator System
-
-Copyright (c) 2001-2006
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Sep 5 2006 15:28:48
-M5 started Tue Sep 5 15:42:12 2006
-M5 executing on zizzer.eecs.umich.edu
-command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/o3-timing tests/run.py quick/00.hello/alpha/linux/o3-timing
-Exiting @ tick 6870 because target called exit()
diff --git a/tests/long/50.vortex/ref/alpha/linux/simple-atomic/config.ini b/tests/long/50.vortex/ref/alpha/linux/simple-atomic/config.ini
index c3a59fbce..6d8732496 100644
--- a/tests/long/50.vortex/ref/alpha/linux/simple-atomic/config.ini
+++ b/tests/long/50.vortex/ref/alpha/linux/simple-atomic/config.ini
@@ -7,11 +7,9 @@ max_tick=0
output_file=cout
progress_interval=0
-[debug]
-break_cycles=
-
[exetrace]
intel_format=false
+legion_lockstep=false
pc_symbol=true
print_cpseq=false
print_cycle=true
@@ -53,352 +51,49 @@ mem_mode=atomic
physmem=system.physmem
[system.cpu]
-type=DerivO3CPU
-children=dcache fuPool icache l2cache toL2Bus workload
-BTBEntries=4096
-BTBTagSize=16
-LFSTSize=1024
-LQEntries=32
-RASSize=16
-SQEntries=32
-SSITSize=1024
-activity=0
-backComSize=5
-choiceCtrBits=2
-choicePredictorSize=8192
+type=AtomicSimpleCPU
+children=workload
clock=1
-commitToDecodeDelay=1
-commitToFetchDelay=1
-commitToIEWDelay=1
-commitToRenameDelay=1
-commitWidth=8
-decodeToFetchDelay=1
-decodeToRenameDelay=1
-decodeWidth=8
+cpu_id=0
defer_registration=false
-dispatchWidth=8
-fetchToDecodeDelay=1
-fetchTrapLatency=1
-fetchWidth=8
-forwardComSize=5
-fuPool=system.cpu.fuPool
function_trace=false
function_trace_start=0
-globalCtrBits=2
-globalHistoryBits=13
-globalPredictorSize=8192
-iewToCommitDelay=1
-iewToDecodeDelay=1
-iewToFetchDelay=1
-iewToRenameDelay=1
-instShiftAmt=2
-issueToExecuteDelay=1
-issueWidth=8
-localCtrBits=2
-localHistoryBits=11
-localHistoryTableSize=2048
-localPredictorSize=2048
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
-mem=system.cpu.dcache
-numIQEntries=64
-numPhysFloatRegs=256
-numPhysIntRegs=256
-numROBEntries=192
-numRobs=1
-numThreads=1
-predType=tournament
-renameToDecodeDelay=1
-renameToFetchDelay=1
-renameToIEWDelay=2
-renameToROBDelay=1
-renameWidth=8
-squashWidth=8
+phase=0
+progress_interval=0
+simulate_stalls=false
system=system
-trapLatency=13
-wbDepth=1
-wbWidth=8
+width=1
workload=system.cpu.workload
-dcache_port=system.cpu.dcache.cpu_side
-icache_port=system.cpu.icache.cpu_side
-
-[system.cpu.dcache]
-type=BaseCache
-adaptive_compression=false
-assoc=2
-block_size=64
-compressed_bus=false
-compression_latency=0
-do_copy=false
-hash_delay=1
-hit_latency=1
-latency=1
-lifo=false
-max_miss_count=0
-mshrs=10
-prefetch_access=false
-prefetch_cache_check_push=true
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10
-prefetch_miss=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
-prioritizeRequests=false
-protocol=Null
-repl=Null
-size=262144
-split=false
-split_size=0
-store_compressed=false
-subblock_size=0
-tgts_per_mshr=5
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu.dcache_port
-mem_side=system.cpu.toL2Bus.port[1]
-
-[system.cpu.fuPool]
-type=FUPool
-children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7
-FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7
-
-[system.cpu.fuPool.FUList0]
-type=FUDesc
-children=opList0
-count=6
-opList=system.cpu.fuPool.FUList0.opList0
-
-[system.cpu.fuPool.FUList0.opList0]
-type=OpDesc
-issueLat=1
-opClass=IntAlu
-opLat=1
-
-[system.cpu.fuPool.FUList1]
-type=FUDesc
-children=opList0 opList1
-count=2
-opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
-
-[system.cpu.fuPool.FUList1.opList0]
-type=OpDesc
-issueLat=1
-opClass=IntMult
-opLat=3
-
-[system.cpu.fuPool.FUList1.opList1]
-type=OpDesc
-issueLat=19
-opClass=IntDiv
-opLat=20
-
-[system.cpu.fuPool.FUList2]
-type=FUDesc
-children=opList0 opList1 opList2
-count=4
-opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
-
-[system.cpu.fuPool.FUList2.opList0]
-type=OpDesc
-issueLat=1
-opClass=FloatAdd
-opLat=2
-
-[system.cpu.fuPool.FUList2.opList1]
-type=OpDesc
-issueLat=1
-opClass=FloatCmp
-opLat=2
-
-[system.cpu.fuPool.FUList2.opList2]
-type=OpDesc
-issueLat=1
-opClass=FloatCvt
-opLat=2
-
-[system.cpu.fuPool.FUList3]
-type=FUDesc
-children=opList0 opList1 opList2
-count=2
-opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
-
-[system.cpu.fuPool.FUList3.opList0]
-type=OpDesc
-issueLat=1
-opClass=FloatMult
-opLat=4
-
-[system.cpu.fuPool.FUList3.opList1]
-type=OpDesc
-issueLat=12
-opClass=FloatDiv
-opLat=12
-
-[system.cpu.fuPool.FUList3.opList2]
-type=OpDesc
-issueLat=24
-opClass=FloatSqrt
-opLat=24
-
-[system.cpu.fuPool.FUList4]
-type=FUDesc
-children=opList0
-count=0
-opList=system.cpu.fuPool.FUList4.opList0
-
-[system.cpu.fuPool.FUList4.opList0]
-type=OpDesc
-issueLat=1
-opClass=MemRead
-opLat=1
-
-[system.cpu.fuPool.FUList5]
-type=FUDesc
-children=opList0
-count=0
-opList=system.cpu.fuPool.FUList5.opList0
-
-[system.cpu.fuPool.FUList5.opList0]
-type=OpDesc
-issueLat=1
-opClass=MemWrite
-opLat=1
-
-[system.cpu.fuPool.FUList6]
-type=FUDesc
-children=opList0 opList1
-count=4
-opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1
-
-[system.cpu.fuPool.FUList6.opList0]
-type=OpDesc
-issueLat=1
-opClass=MemRead
-opLat=1
-
-[system.cpu.fuPool.FUList6.opList1]
-type=OpDesc
-issueLat=1
-opClass=MemWrite
-opLat=1
-
-[system.cpu.fuPool.FUList7]
-type=FUDesc
-children=opList0
-count=1
-opList=system.cpu.fuPool.FUList7.opList0
-
-[system.cpu.fuPool.FUList7.opList0]
-type=OpDesc
-issueLat=3
-opClass=IprAccess
-opLat=3
-
-[system.cpu.icache]
-type=BaseCache
-adaptive_compression=false
-assoc=2
-block_size=64
-compressed_bus=false
-compression_latency=0
-do_copy=false
-hash_delay=1
-hit_latency=1
-latency=1
-lifo=false
-max_miss_count=0
-mshrs=10
-prefetch_access=false
-prefetch_cache_check_push=true
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10
-prefetch_miss=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
-prioritizeRequests=false
-protocol=Null
-repl=Null
-size=131072
-split=false
-split_size=0
-store_compressed=false
-subblock_size=0
-tgts_per_mshr=5
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu.icache_port
-mem_side=system.cpu.toL2Bus.port[0]
-
-[system.cpu.l2cache]
-type=BaseCache
-adaptive_compression=false
-assoc=2
-block_size=64
-compressed_bus=false
-compression_latency=0
-do_copy=false
-hash_delay=1
-hit_latency=1
-latency=1
-lifo=false
-max_miss_count=0
-mshrs=10
-prefetch_access=false
-prefetch_cache_check_push=true
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10
-prefetch_miss=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
-prioritizeRequests=false
-protocol=Null
-repl=Null
-size=2097152
-split=false
-split_size=0
-store_compressed=false
-subblock_size=0
-tgts_per_mshr=5
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[1]
-
-[system.cpu.toL2Bus]
-type=Bus
-bus_id=0
-port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+dcache_port=system.membus.port[2]
+icache_port=system.membus.port[1]
[system.cpu.workload]
type=LiveProcess
-cmd=hello
+cmd=vortex lendian.raw
+cwd=build/ALPHA_SE/tests/opt/long/50.vortex/alpha/linux/simple-atomic
+egid=100
env=
-executable=tests/test-progs/hello/bin/alpha/linux/hello
+euid=100
+executable=/dist/m5/cpu2000/binaries/alpha/tru64/vortex
+gid=100
input=cin
output=cout
+pid=100
+ppid=99
system=system
+uid=100
[system.membus]
type=Bus
bus_id=0
-port=system.physmem.port system.cpu.l2cache.mem_side
+clock=1000
+responder_set=false
+width=64
+port=system.physmem.port system.cpu.icache_port system.cpu.dcache_port
[system.physmem]
type=PhysicalMemory
@@ -409,6 +104,7 @@ port=system.membus.port[0]
[trace]
bufsize=0
+cycle=0
dump_on_exit=false
file=cout
flags=
diff --git a/tests/long/50.vortex/ref/alpha/linux/simple-atomic/config.out b/tests/long/50.vortex/ref/alpha/linux/simple-atomic/config.out
index f491a3081..38f919464 100644
--- a/tests/long/50.vortex/ref/alpha/linux/simple-atomic/config.out
+++ b/tests/long/50.vortex/ref/alpha/linux/simple-atomic/config.out
@@ -19,345 +19,48 @@ mem_mode=atomic
[system.membus]
type=Bus
bus_id=0
+clock=1000
+width=64
+responder_set=false
[system.cpu.workload]
type=LiveProcess
-cmd=hello
-executable=tests/test-progs/hello/bin/alpha/linux/hello
+cmd=vortex lendian.raw
+executable=/dist/m5/cpu2000/binaries/alpha/tru64/vortex
input=cin
output=cout
env=
+cwd=build/ALPHA_SE/tests/opt/long/50.vortex/alpha/linux/simple-atomic
system=system
-
-[system.cpu.dcache]
-type=BaseCache
-size=262144
-assoc=2
-block_size=64
-latency=1
-mshrs=10
-tgts_per_mshr=5
-write_buffers=8
-prioritizeRequests=false
-do_copy=false
-protocol=null
-trace_addr=0
-hash_delay=1
-repl=null
-compressed_bus=false
-store_compressed=false
-adaptive_compression=false
-compression_latency=0
-block_size=64
-max_miss_count=0
-addr_range=[0,18446744073709551615]
-split=false
-split_size=0
-lifo=false
-two_queue=false
-prefetch_miss=false
-prefetch_access=false
-prefetcher_size=100
-prefetch_past_page=false
-prefetch_serial_squash=false
-prefetch_latency=10
-prefetch_degree=1
-prefetch_policy=none
-prefetch_cache_check_push=true
-prefetch_use_cpu_id=true
-prefetch_data_accesses_only=false
-hit_latency=1
-
-[system.cpu.fuPool.FUList0.opList0]
-type=OpDesc
-opClass=IntAlu
-opLat=1
-issueLat=1
-
-[system.cpu.fuPool.FUList0]
-type=FUDesc
-opList=system.cpu.fuPool.FUList0.opList0
-count=6
-
-[system.cpu.fuPool.FUList1.opList0]
-type=OpDesc
-opClass=IntMult
-opLat=3
-issueLat=1
-
-[system.cpu.fuPool.FUList1.opList1]
-type=OpDesc
-opClass=IntDiv
-opLat=20
-issueLat=19
-
-[system.cpu.fuPool.FUList1]
-type=FUDesc
-opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
-count=2
-
-[system.cpu.fuPool.FUList2.opList0]
-type=OpDesc
-opClass=FloatAdd
-opLat=2
-issueLat=1
-
-[system.cpu.fuPool.FUList2.opList1]
-type=OpDesc
-opClass=FloatCmp
-opLat=2
-issueLat=1
-
-[system.cpu.fuPool.FUList2.opList2]
-type=OpDesc
-opClass=FloatCvt
-opLat=2
-issueLat=1
-
-[system.cpu.fuPool.FUList2]
-type=FUDesc
-opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
-count=4
-
-[system.cpu.fuPool.FUList3.opList0]
-type=OpDesc
-opClass=FloatMult
-opLat=4
-issueLat=1
-
-[system.cpu.fuPool.FUList3.opList1]
-type=OpDesc
-opClass=FloatDiv
-opLat=12
-issueLat=12
-
-[system.cpu.fuPool.FUList3.opList2]
-type=OpDesc
-opClass=FloatSqrt
-opLat=24
-issueLat=24
-
-[system.cpu.fuPool.FUList3]
-type=FUDesc
-opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
-count=2
-
-[system.cpu.fuPool.FUList4.opList0]
-type=OpDesc
-opClass=MemRead
-opLat=1
-issueLat=1
-
-[system.cpu.fuPool.FUList4]
-type=FUDesc
-opList=system.cpu.fuPool.FUList4.opList0
-count=0
-
-[system.cpu.fuPool.FUList5.opList0]
-type=OpDesc
-opClass=MemWrite
-opLat=1
-issueLat=1
-
-[system.cpu.fuPool.FUList5]
-type=FUDesc
-opList=system.cpu.fuPool.FUList5.opList0
-count=0
-
-[system.cpu.fuPool.FUList6.opList0]
-type=OpDesc
-opClass=MemRead
-opLat=1
-issueLat=1
-
-[system.cpu.fuPool.FUList6.opList1]
-type=OpDesc
-opClass=MemWrite
-opLat=1
-issueLat=1
-
-[system.cpu.fuPool.FUList6]
-type=FUDesc
-opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1
-count=4
-
-[system.cpu.fuPool.FUList7.opList0]
-type=OpDesc
-opClass=IprAccess
-opLat=3
-issueLat=3
-
-[system.cpu.fuPool.FUList7]
-type=FUDesc
-opList=system.cpu.fuPool.FUList7.opList0
-count=1
-
-[system.cpu.fuPool]
-type=FUPool
-FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7
+uid=100
+euid=100
+gid=100
+egid=100
+pid=100
+ppid=99
[system.cpu]
-type=DerivO3CPU
-clock=1
-numThreads=1
-activity=0
-workload=system.cpu.workload
-mem=system.cpu.dcache
-checker=null
+type=AtomicSimpleCPU
max_insts_any_thread=0
max_insts_all_threads=0
max_loads_any_thread=0
max_loads_all_threads=0
-cachePorts=200
-decodeToFetchDelay=1
-renameToFetchDelay=1
-iewToFetchDelay=1
-commitToFetchDelay=1
-fetchWidth=8
-renameToDecodeDelay=1
-iewToDecodeDelay=1
-commitToDecodeDelay=1
-fetchToDecodeDelay=1
-decodeWidth=8
-iewToRenameDelay=1
-commitToRenameDelay=1
-decodeToRenameDelay=1
-renameWidth=8
-commitToIEWDelay=1
-renameToIEWDelay=2
-issueToExecuteDelay=1
-dispatchWidth=8
-issueWidth=8
-wbWidth=8
-wbDepth=1
-fuPool=system.cpu.fuPool
-iewToCommitDelay=1
-renameToROBDelay=1
-commitWidth=8
-squashWidth=8
-trapLatency=13
-backComSize=5
-forwardComSize=5
-predType=tournament
-localPredictorSize=2048
-localCtrBits=2
-localHistoryTableSize=2048
-localHistoryBits=11
-globalPredictorSize=8192
-globalCtrBits=2
-globalHistoryBits=13
-choicePredictorSize=8192
-choiceCtrBits=2
-BTBEntries=4096
-BTBTagSize=16
-RASSize=16
-LQEntries=32
-SQEntries=32
-LFSTSize=1024
-SSITSize=1024
-numPhysIntRegs=256
-numPhysFloatRegs=256
-numIQEntries=64
-numROBEntries=192
-smtNumFetchingThreads=1
-smtFetchPolicy=SingleThread
-smtLSQPolicy=Partitioned
-smtLSQThreshold=100
-smtIQPolicy=Partitioned
-smtIQThreshold=100
-smtROBPolicy=Partitioned
-smtROBThreshold=100
-smtCommitPolicy=RoundRobin
-instShiftAmt=2
+progress_interval=0
+system=system
+cpu_id=0
+workload=system.cpu.workload
+clock=1
+phase=0
defer_registration=false
+width=1
function_trace=false
function_trace_start=0
-
-[system.cpu.icache]
-type=BaseCache
-size=131072
-assoc=2
-block_size=64
-latency=1
-mshrs=10
-tgts_per_mshr=5
-write_buffers=8
-prioritizeRequests=false
-do_copy=false
-protocol=null
-trace_addr=0
-hash_delay=1
-repl=null
-compressed_bus=false
-store_compressed=false
-adaptive_compression=false
-compression_latency=0
-block_size=64
-max_miss_count=0
-addr_range=[0,18446744073709551615]
-split=false
-split_size=0
-lifo=false
-two_queue=false
-prefetch_miss=false
-prefetch_access=false
-prefetcher_size=100
-prefetch_past_page=false
-prefetch_serial_squash=false
-prefetch_latency=10
-prefetch_degree=1
-prefetch_policy=none
-prefetch_cache_check_push=true
-prefetch_use_cpu_id=true
-prefetch_data_accesses_only=false
-hit_latency=1
-
-[system.cpu.l2cache]
-type=BaseCache
-size=2097152
-assoc=2
-block_size=64
-latency=1
-mshrs=10
-tgts_per_mshr=5
-write_buffers=8
-prioritizeRequests=false
-do_copy=false
-protocol=null
-trace_addr=0
-hash_delay=1
-repl=null
-compressed_bus=false
-store_compressed=false
-adaptive_compression=false
-compression_latency=0
-block_size=64
-max_miss_count=0
-addr_range=[0,18446744073709551615]
-split=false
-split_size=0
-lifo=false
-two_queue=false
-prefetch_miss=false
-prefetch_access=false
-prefetcher_size=100
-prefetch_past_page=false
-prefetch_serial_squash=false
-prefetch_latency=10
-prefetch_degree=1
-prefetch_policy=none
-prefetch_cache_check_push=true
-prefetch_use_cpu_id=true
-prefetch_data_accesses_only=false
-hit_latency=1
-
-[system.cpu.toL2Bus]
-type=Bus
-bus_id=0
+simulate_stalls=false
[trace]
flags=
start=0
+cycle=0
bufsize=0
file=cout
dump_on_exit=false
@@ -396,8 +99,9 @@ print_cpseq=false
print_reg_delta=false
pc_symbol=true
intel_format=false
+legion_lockstep=false
trace_system=client
-[debug]
-break_cycles=
+[statsreset]
+reset_cycle=0
diff --git a/tests/long/50.vortex/ref/alpha/linux/simple-atomic/m5stats.txt b/tests/long/50.vortex/ref/alpha/linux/simple-atomic/m5stats.txt
index 5d4f9235a..d73ff13a7 100644
--- a/tests/long/50.vortex/ref/alpha/linux/simple-atomic/m5stats.txt
+++ b/tests/long/50.vortex/ref/alpha/linux/simple-atomic/m5stats.txt
@@ -1,1974 +1,18 @@
---------- Begin Simulation Statistics ----------
-global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-global.BPredUnit.BTBHits 542 # Number of BTB hits
-global.BPredUnit.BTBLookups 1938 # Number of BTB lookups
-global.BPredUnit.RASInCorrect 48 # Number of incorrect RAS predictions.
-global.BPredUnit.condIncorrect 420 # Number of conditional branches incorrect
-global.BPredUnit.condPredicted 1304 # Number of conditional branches predicted
-global.BPredUnit.lookups 2256 # Number of BP lookups
-global.BPredUnit.usedRAS 291 # Number of times the RAS was used to get a target.
-host_inst_rate 41797 # Simulator instruction rate (inst/s)
-host_mem_usage 160344 # Number of bytes of host memory used
-host_seconds 0.13 # Real time elapsed on the host
-host_tick_rate 50948 # Simulator tick rate (ticks/s)
-memdepunit.memDep.conflictingLoads 12 # Number of conflicting loads.
-memdepunit.memDep.conflictingStores 259 # Number of conflicting stores.
-memdepunit.memDep.insertedLoads 2050 # Number of loads inserted to the mem dependence unit.
-memdepunit.memDep.insertedStores 1221 # Number of stores inserted to the mem dependence unit.
+host_inst_rate 857494 # Simulator instruction rate (inst/s)
+host_mem_usage 149092 # Number of bytes of host memory used
+host_seconds 103.05 # Real time elapsed on the host
+host_tick_rate 857491 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 5623 # Number of instructions simulated
-sim_seconds 0.000000 # Number of seconds simulated
-sim_ticks 6870 # Number of ticks simulated
-system.cpu.commit.COM:branches 862 # Number of branches committed
-system.cpu.commit.COM:bw_lim_events 74 # number cycles where commit BW limit reached
-system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle.samples 6116
-system.cpu.commit.COM:committed_per_cycle.min_value 0
- 0 3908 6389.80%
- 1 1064 1739.70%
- 2 389 636.04%
- 3 210 343.36%
- 4 153 250.16%
- 5 93 152.06%
- 6 76 124.26%
- 7 149 243.62%
- 8 74 120.99%
-system.cpu.commit.COM:committed_per_cycle.max_value 8
-system.cpu.commit.COM:committed_per_cycle.end_dist
-
-system.cpu.commit.COM:count 5640 # Number of instructions committed
-system.cpu.commit.COM:loads 979 # Number of loads committed
-system.cpu.commit.COM:membars 0 # Number of memory barriers committed
-system.cpu.commit.COM:refs 1791 # Number of memory references committed
-system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.branchMispredicts 337 # The number of times a branch was mispredicted
-system.cpu.commit.commitCommittedInsts 5640 # The number of committed instructions
-system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.commitSquashedInsts 4350 # The number of squashed insts skipped by commit
-system.cpu.committedInsts 5623 # Number of Instructions Simulated
-system.cpu.committedInsts_total 5623 # Number of Instructions Simulated
-system.cpu.cpi 1.221768 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 1.221768 # CPI: Total CPI of All Threads
-system.cpu.dcache.ReadReq_accesses 1538 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 3.072000 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2.240000 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits 1413 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 384 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate 0.081274 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses 125 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_hits 25 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_miss_latency 224 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate 0.065020 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses 100 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_accesses 821 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 2.467742 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2.140845 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 635 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 459 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.226553 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 186 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_hits 108 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_miss_latency 152 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.086480 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 71 # number of WriteReq MSHR misses
-system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles_no_targets 0.800000 # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 11.505618 # Average number of references to valid blocks.
-system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_no_targets 5 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles_no_targets 4 # number of cycles access was blocked
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.demand_accesses 2359 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 2.710611 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 2.198830 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 2048 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 843 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.131836 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 311 # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits 133 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 376 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate 0.072488 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 171 # number of demand (read+write) MSHR misses
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.overall_accesses 2359 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 2.710611 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 2.198830 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 2048 # number of overall hits
-system.cpu.dcache.overall_miss_latency 843 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.131836 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 311 # number of overall misses
-system.cpu.dcache.overall_mshr_hits 133 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 376 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate 0.072488 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 171 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.dcache.replacements 0 # number of replacements
-system.cpu.dcache.sampled_refs 178 # Sample count of references to valid blocks.
-system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 119.831029 # Cycle average of tags in use
-system.cpu.dcache.total_refs 2048 # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks 0 # number of writebacks
-system.cpu.decode.DECODE:BlockedCycles 387 # Number of cycles decode is blocked
-system.cpu.decode.DECODE:BranchMispred 93 # Number of times decode detected a branch misprediction
-system.cpu.decode.DECODE:BranchResolved 185 # Number of times decode resolved a branch
-system.cpu.decode.DECODE:DecodedInsts 12349 # Number of instructions handled by decode
-system.cpu.decode.DECODE:IdleCycles 3542 # Number of cycles decode is idle
-system.cpu.decode.DECODE:RunCycles 2158 # Number of cycles decode is running
-system.cpu.decode.DECODE:SquashCycles 754 # Number of cycles decode is squashing
-system.cpu.decode.DECODE:SquashedInsts 286 # Number of squashed instructions handled by decode
-system.cpu.decode.DECODE:UnblockCycles 30 # Number of cycles decode is unblocking
-system.cpu.fetch.Branches 2256 # Number of branches that fetch encountered
-system.cpu.fetch.CacheLines 1582 # Number of cache lines fetched
-system.cpu.fetch.Cycles 3905 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.IcacheSquashes 148 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.Insts 13707 # Number of instructions fetch has processed
-system.cpu.fetch.SquashCycles 456 # Number of cycles fetch has spent squashing
-system.cpu.fetch.branchRate 0.328336 # Number of branch fetches per cycle
-system.cpu.fetch.icacheStallCycles 1582 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.predictedBranches 833 # Number of branches that fetch has predicted taken
-system.cpu.fetch.rate 1.994906 # Number of inst fetches per cycle
-system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist.samples 6871
-system.cpu.fetch.rateDist.min_value 0
- 0 4549 6620.58%
- 1 174 253.24%
- 2 186 270.70%
- 3 157 228.50%
- 4 211 307.09%
- 5 153 222.68%
- 6 171 248.87%
- 7 105 152.82%
- 8 1165 1695.53%
-system.cpu.fetch.rateDist.max_value 8
-system.cpu.fetch.rateDist.end_dist
-
-system.cpu.icache.ReadReq_accesses 1582 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 2.960245 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 1.996885 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits 1255 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 968 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate 0.206700 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses 327 # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_hits 6 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_miss_latency 641 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.202908 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses 321 # number of ReadReq MSHR misses
-system.cpu.icache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles_no_targets no value # average number of cycles each access was blocked
-system.cpu.icache.avg_refs 3.909657 # Average number of references to valid blocks.
-system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.demand_accesses 1582 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 2.960245 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 1.996885 # average overall mshr miss latency
-system.cpu.icache.demand_hits 1255 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 968 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate 0.206700 # miss rate for demand accesses
-system.cpu.icache.demand_misses 327 # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_hits 6 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 641 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate 0.202908 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses 321 # number of demand (read+write) MSHR misses
-system.cpu.icache.fast_writes 0 # number of fast writes performed
-system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.overall_accesses 1582 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 2.960245 # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 1.996885 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits 1255 # number of overall hits
-system.cpu.icache.overall_miss_latency 968 # number of overall miss cycles
-system.cpu.icache.overall_miss_rate 0.206700 # miss rate for overall accesses
-system.cpu.icache.overall_misses 327 # number of overall misses
-system.cpu.icache.overall_mshr_hits 6 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 641 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate 0.202908 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses 321 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.icache.replacements 0 # number of replacements
-system.cpu.icache.sampled_refs 321 # Sample count of references to valid blocks.
-system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 176.393247 # Cycle average of tags in use
-system.cpu.icache.total_refs 1255 # Total number of references to valid blocks.
-system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.iew.EXEC:branches 1206 # Number of branches executed
-system.cpu.iew.EXEC:insts 7969 # Number of executed instructions
-system.cpu.iew.EXEC:loads 1610 # Number of load instructions executed
-system.cpu.iew.EXEC:nop 37 # number of nop insts executed
-system.cpu.iew.EXEC:rate 1.159802 # Inst execution rate
-system.cpu.iew.EXEC:refs 2599 # number of memory reference insts executed
-system.cpu.iew.EXEC:squashedInsts 419 # Number of squashed instructions skipped in execute
-system.cpu.iew.EXEC:stores 989 # Number of stores executed
-system.cpu.iew.EXEC:swp 0 # number of swp insts executed
-system.cpu.iew.WB:consumers 5438 # num instructions consuming a value
-system.cpu.iew.WB:count 7722 # cumulative count of insts written-back
-system.cpu.iew.WB:fanout 0.744575 # average fanout of values written-back
-system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.iew.WB:producers 4049 # num instructions producing a value
-system.cpu.iew.WB:rate 1.123854 # insts written-back per cycle
-system.cpu.iew.WB:sent 7762 # cumulative count of insts sent to commit
-system.cpu.iew.branchMispredicts 393 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewBlockCycles 4 # Number of cycles IEW is blocking
-system.cpu.iew.iewDispLoadInsts 2050 # Number of dispatched load instructions
-system.cpu.iew.iewDispNonSpecInsts 21 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewDispSquashedInsts 272 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispStoreInsts 1221 # Number of dispatched store instructions
-system.cpu.iew.iewDispatchedInsts 9990 # Number of instructions dispatched to IQ
-system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.iewSquashCycles 754 # Number of cycles IEW is squashing
-system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking
-system.cpu.iew.lsq.thread.0.blockedLoads 1 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread.0.cacheBlocked 5 # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.lsq.thread.0.forwLoads 55 # Number of loads that had data forwarded from stores
-system.cpu.iew.lsq.thread.0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
-system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread.0.squashedLoads 1071 # Number of loads squashed
-system.cpu.iew.lsq.thread.0.squashedStores 409 # Number of stores squashed
-system.cpu.iew.memOrderViolationEvents 41 # Number of memory order violations
-system.cpu.iew.predictedNotTakenIncorrect 296 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.predictedTakenIncorrect 97 # Number of branches that were predicted taken incorrectly
-system.cpu.ipc 0.818486 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.818486 # IPC: Total IPC of All Threads
-system.cpu.iq.IQ:residence:(null).start_dist # cycles from dispatch to issue
-system.cpu.iq.IQ:residence:(null).samples 0
-system.cpu.iq.IQ:residence:(null).min_value 0
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-system.cpu.iq.IQ:residence:(null).max_value 0
-system.cpu.iq.IQ:residence:(null).end_dist
-
-system.cpu.iq.IQ:residence:IntAlu.start_dist # cycles from dispatch to issue
-system.cpu.iq.IQ:residence:IntAlu.samples 0
-system.cpu.iq.IQ:residence:IntAlu.min_value 0
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-system.cpu.iq.IQ:residence:IntAlu.max_value 0
-system.cpu.iq.IQ:residence:IntAlu.end_dist
-
-system.cpu.iq.IQ:residence:IntMult.start_dist # cycles from dispatch to issue
-system.cpu.iq.IQ:residence:IntMult.samples 0
-system.cpu.iq.IQ:residence:IntMult.min_value 0
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-system.cpu.iq.IQ:residence:IntMult.max_value 0
-system.cpu.iq.IQ:residence:IntMult.end_dist
-
-system.cpu.iq.IQ:residence:IntDiv.start_dist # cycles from dispatch to issue
-system.cpu.iq.IQ:residence:IntDiv.samples 0
-system.cpu.iq.IQ:residence:IntDiv.min_value 0
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-system.cpu.iq.IQ:residence:IntDiv.max_value 0
-system.cpu.iq.IQ:residence:IntDiv.end_dist
-
-system.cpu.iq.IQ:residence:FloatAdd.start_dist # cycles from dispatch to issue
-system.cpu.iq.IQ:residence:FloatAdd.samples 0
-system.cpu.iq.IQ:residence:FloatAdd.min_value 0
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-system.cpu.iq.IQ:residence:FloatAdd.max_value 0
-system.cpu.iq.IQ:residence:FloatAdd.end_dist
-
-system.cpu.iq.IQ:residence:FloatCmp.start_dist # cycles from dispatch to issue
-system.cpu.iq.IQ:residence:FloatCmp.samples 0
-system.cpu.iq.IQ:residence:FloatCmp.min_value 0
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-system.cpu.iq.IQ:residence:FloatCmp.max_value 0
-system.cpu.iq.IQ:residence:FloatCmp.end_dist
-
-system.cpu.iq.IQ:residence:FloatCvt.start_dist # cycles from dispatch to issue
-system.cpu.iq.IQ:residence:FloatCvt.samples 0
-system.cpu.iq.IQ:residence:FloatCvt.min_value 0
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-system.cpu.iq.IQ:residence:FloatCvt.end_dist
-
-system.cpu.iq.IQ:residence:FloatMult.start_dist # cycles from dispatch to issue
-system.cpu.iq.IQ:residence:FloatMult.samples 0
-system.cpu.iq.IQ:residence:FloatMult.min_value 0
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-system.cpu.iq.IQ:residence:FloatMult.max_value 0
-system.cpu.iq.IQ:residence:FloatMult.end_dist
-
-system.cpu.iq.IQ:residence:FloatDiv.start_dist # cycles from dispatch to issue
-system.cpu.iq.IQ:residence:FloatDiv.samples 0
-system.cpu.iq.IQ:residence:FloatDiv.min_value 0
- 0 0
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- 98 0
-system.cpu.iq.IQ:residence:FloatDiv.max_value 0
-system.cpu.iq.IQ:residence:FloatDiv.end_dist
-
-system.cpu.iq.IQ:residence:FloatSqrt.start_dist # cycles from dispatch to issue
-system.cpu.iq.IQ:residence:FloatSqrt.samples 0
-system.cpu.iq.IQ:residence:FloatSqrt.min_value 0
- 0 0
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-system.cpu.iq.IQ:residence:FloatSqrt.end_dist
-
-system.cpu.iq.IQ:residence:MemRead.start_dist # cycles from dispatch to issue
-system.cpu.iq.IQ:residence:MemRead.samples 0
-system.cpu.iq.IQ:residence:MemRead.min_value 0
- 0 0
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-system.cpu.iq.IQ:residence:MemRead.max_value 0
-system.cpu.iq.IQ:residence:MemRead.end_dist
-
-system.cpu.iq.IQ:residence:MemWrite.start_dist # cycles from dispatch to issue
-system.cpu.iq.IQ:residence:MemWrite.samples 0
-system.cpu.iq.IQ:residence:MemWrite.min_value 0
- 0 0
- 2 0
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-system.cpu.iq.IQ:residence:MemWrite.max_value 0
-system.cpu.iq.IQ:residence:MemWrite.end_dist
-
-system.cpu.iq.IQ:residence:IprAccess.start_dist # cycles from dispatch to issue
-system.cpu.iq.IQ:residence:IprAccess.samples 0
-system.cpu.iq.IQ:residence:IprAccess.min_value 0
- 0 0
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-system.cpu.iq.IQ:residence:IprAccess.max_value 0
-system.cpu.iq.IQ:residence:IprAccess.end_dist
-
-system.cpu.iq.IQ:residence:InstPrefetch.start_dist # cycles from dispatch to issue
-system.cpu.iq.IQ:residence:InstPrefetch.samples 0
-system.cpu.iq.IQ:residence:InstPrefetch.min_value 0
- 0 0
- 2 0
- 4 0
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- 98 0
-system.cpu.iq.IQ:residence:InstPrefetch.max_value 0
-system.cpu.iq.IQ:residence:InstPrefetch.end_dist
-
-system.cpu.iq.ISSUE:(null)_delay.start_dist # cycles from operands ready to issue
-system.cpu.iq.ISSUE:(null)_delay.samples 0
-system.cpu.iq.ISSUE:(null)_delay.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
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-system.cpu.iq.ISSUE:(null)_delay.max_value 0
-system.cpu.iq.ISSUE:(null)_delay.end_dist
-
-system.cpu.iq.ISSUE:IntAlu_delay.start_dist # cycles from operands ready to issue
-system.cpu.iq.ISSUE:IntAlu_delay.samples 0
-system.cpu.iq.ISSUE:IntAlu_delay.min_value 0
- 0 0
- 2 0
- 4 0
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-system.cpu.iq.ISSUE:IntAlu_delay.max_value 0
-system.cpu.iq.ISSUE:IntAlu_delay.end_dist
-
-system.cpu.iq.ISSUE:IntMult_delay.start_dist # cycles from operands ready to issue
-system.cpu.iq.ISSUE:IntMult_delay.samples 0
-system.cpu.iq.ISSUE:IntMult_delay.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
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-system.cpu.iq.ISSUE:IntMult_delay.max_value 0
-system.cpu.iq.ISSUE:IntMult_delay.end_dist
-
-system.cpu.iq.ISSUE:IntDiv_delay.start_dist # cycles from operands ready to issue
-system.cpu.iq.ISSUE:IntDiv_delay.samples 0
-system.cpu.iq.ISSUE:IntDiv_delay.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
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-system.cpu.iq.ISSUE:IntDiv_delay.max_value 0
-system.cpu.iq.ISSUE:IntDiv_delay.end_dist
-
-system.cpu.iq.ISSUE:FloatAdd_delay.start_dist # cycles from operands ready to issue
-system.cpu.iq.ISSUE:FloatAdd_delay.samples 0
-system.cpu.iq.ISSUE:FloatAdd_delay.min_value 0
- 0 0
- 2 0
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- 98 0
-system.cpu.iq.ISSUE:FloatAdd_delay.max_value 0
-system.cpu.iq.ISSUE:FloatAdd_delay.end_dist
-
-system.cpu.iq.ISSUE:FloatCmp_delay.start_dist # cycles from operands ready to issue
-system.cpu.iq.ISSUE:FloatCmp_delay.samples 0
-system.cpu.iq.ISSUE:FloatCmp_delay.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
- 20 0
- 22 0
- 24 0
- 26 0
- 28 0
- 30 0
- 32 0
- 34 0
- 36 0
- 38 0
- 40 0
- 42 0
- 44 0
- 46 0
- 48 0
- 50 0
- 52 0
- 54 0
- 56 0
- 58 0
- 60 0
- 62 0
- 64 0
- 66 0
- 68 0
- 70 0
- 72 0
- 74 0
- 76 0
- 78 0
- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.ISSUE:FloatCmp_delay.max_value 0
-system.cpu.iq.ISSUE:FloatCmp_delay.end_dist
-
-system.cpu.iq.ISSUE:FloatCvt_delay.start_dist # cycles from operands ready to issue
-system.cpu.iq.ISSUE:FloatCvt_delay.samples 0
-system.cpu.iq.ISSUE:FloatCvt_delay.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
- 20 0
- 22 0
- 24 0
- 26 0
- 28 0
- 30 0
- 32 0
- 34 0
- 36 0
- 38 0
- 40 0
- 42 0
- 44 0
- 46 0
- 48 0
- 50 0
- 52 0
- 54 0
- 56 0
- 58 0
- 60 0
- 62 0
- 64 0
- 66 0
- 68 0
- 70 0
- 72 0
- 74 0
- 76 0
- 78 0
- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.ISSUE:FloatCvt_delay.max_value 0
-system.cpu.iq.ISSUE:FloatCvt_delay.end_dist
-
-system.cpu.iq.ISSUE:FloatMult_delay.start_dist # cycles from operands ready to issue
-system.cpu.iq.ISSUE:FloatMult_delay.samples 0
-system.cpu.iq.ISSUE:FloatMult_delay.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
- 20 0
- 22 0
- 24 0
- 26 0
- 28 0
- 30 0
- 32 0
- 34 0
- 36 0
- 38 0
- 40 0
- 42 0
- 44 0
- 46 0
- 48 0
- 50 0
- 52 0
- 54 0
- 56 0
- 58 0
- 60 0
- 62 0
- 64 0
- 66 0
- 68 0
- 70 0
- 72 0
- 74 0
- 76 0
- 78 0
- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.ISSUE:FloatMult_delay.max_value 0
-system.cpu.iq.ISSUE:FloatMult_delay.end_dist
-
-system.cpu.iq.ISSUE:FloatDiv_delay.start_dist # cycles from operands ready to issue
-system.cpu.iq.ISSUE:FloatDiv_delay.samples 0
-system.cpu.iq.ISSUE:FloatDiv_delay.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
- 20 0
- 22 0
- 24 0
- 26 0
- 28 0
- 30 0
- 32 0
- 34 0
- 36 0
- 38 0
- 40 0
- 42 0
- 44 0
- 46 0
- 48 0
- 50 0
- 52 0
- 54 0
- 56 0
- 58 0
- 60 0
- 62 0
- 64 0
- 66 0
- 68 0
- 70 0
- 72 0
- 74 0
- 76 0
- 78 0
- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.ISSUE:FloatDiv_delay.max_value 0
-system.cpu.iq.ISSUE:FloatDiv_delay.end_dist
-
-system.cpu.iq.ISSUE:FloatSqrt_delay.start_dist # cycles from operands ready to issue
-system.cpu.iq.ISSUE:FloatSqrt_delay.samples 0
-system.cpu.iq.ISSUE:FloatSqrt_delay.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
- 20 0
- 22 0
- 24 0
- 26 0
- 28 0
- 30 0
- 32 0
- 34 0
- 36 0
- 38 0
- 40 0
- 42 0
- 44 0
- 46 0
- 48 0
- 50 0
- 52 0
- 54 0
- 56 0
- 58 0
- 60 0
- 62 0
- 64 0
- 66 0
- 68 0
- 70 0
- 72 0
- 74 0
- 76 0
- 78 0
- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.ISSUE:FloatSqrt_delay.max_value 0
-system.cpu.iq.ISSUE:FloatSqrt_delay.end_dist
-
-system.cpu.iq.ISSUE:MemRead_delay.start_dist # cycles from operands ready to issue
-system.cpu.iq.ISSUE:MemRead_delay.samples 0
-system.cpu.iq.ISSUE:MemRead_delay.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
- 20 0
- 22 0
- 24 0
- 26 0
- 28 0
- 30 0
- 32 0
- 34 0
- 36 0
- 38 0
- 40 0
- 42 0
- 44 0
- 46 0
- 48 0
- 50 0
- 52 0
- 54 0
- 56 0
- 58 0
- 60 0
- 62 0
- 64 0
- 66 0
- 68 0
- 70 0
- 72 0
- 74 0
- 76 0
- 78 0
- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.ISSUE:MemRead_delay.max_value 0
-system.cpu.iq.ISSUE:MemRead_delay.end_dist
-
-system.cpu.iq.ISSUE:MemWrite_delay.start_dist # cycles from operands ready to issue
-system.cpu.iq.ISSUE:MemWrite_delay.samples 0
-system.cpu.iq.ISSUE:MemWrite_delay.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
- 20 0
- 22 0
- 24 0
- 26 0
- 28 0
- 30 0
- 32 0
- 34 0
- 36 0
- 38 0
- 40 0
- 42 0
- 44 0
- 46 0
- 48 0
- 50 0
- 52 0
- 54 0
- 56 0
- 58 0
- 60 0
- 62 0
- 64 0
- 66 0
- 68 0
- 70 0
- 72 0
- 74 0
- 76 0
- 78 0
- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.ISSUE:MemWrite_delay.max_value 0
-system.cpu.iq.ISSUE:MemWrite_delay.end_dist
-
-system.cpu.iq.ISSUE:IprAccess_delay.start_dist # cycles from operands ready to issue
-system.cpu.iq.ISSUE:IprAccess_delay.samples 0
-system.cpu.iq.ISSUE:IprAccess_delay.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
- 20 0
- 22 0
- 24 0
- 26 0
- 28 0
- 30 0
- 32 0
- 34 0
- 36 0
- 38 0
- 40 0
- 42 0
- 44 0
- 46 0
- 48 0
- 50 0
- 52 0
- 54 0
- 56 0
- 58 0
- 60 0
- 62 0
- 64 0
- 66 0
- 68 0
- 70 0
- 72 0
- 74 0
- 76 0
- 78 0
- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.ISSUE:IprAccess_delay.max_value 0
-system.cpu.iq.ISSUE:IprAccess_delay.end_dist
-
-system.cpu.iq.ISSUE:InstPrefetch_delay.start_dist # cycles from operands ready to issue
-system.cpu.iq.ISSUE:InstPrefetch_delay.samples 0
-system.cpu.iq.ISSUE:InstPrefetch_delay.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
- 20 0
- 22 0
- 24 0
- 26 0
- 28 0
- 30 0
- 32 0
- 34 0
- 36 0
- 38 0
- 40 0
- 42 0
- 44 0
- 46 0
- 48 0
- 50 0
- 52 0
- 54 0
- 56 0
- 58 0
- 60 0
- 62 0
- 64 0
- 66 0
- 68 0
- 70 0
- 72 0
- 74 0
- 76 0
- 78 0
- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.ISSUE:InstPrefetch_delay.max_value 0
-system.cpu.iq.ISSUE:InstPrefetch_delay.end_dist
-
-system.cpu.iq.ISSUE:FU_type_0 8388 # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0.start_dist
- (null) 2 0.02% # Type of FU issued
- IntAlu 5594 66.69% # Type of FU issued
- IntMult 1 0.01% # Type of FU issued
- IntDiv 0 0.00% # Type of FU issued
- FloatAdd 2 0.02% # Type of FU issued
- FloatCmp 0 0.00% # Type of FU issued
- FloatCvt 0 0.00% # Type of FU issued
- FloatMult 0 0.00% # Type of FU issued
- FloatDiv 0 0.00% # Type of FU issued
- FloatSqrt 0 0.00% # Type of FU issued
- MemRead 1757 20.95% # Type of FU issued
- MemWrite 1032 12.30% # Type of FU issued
- IprAccess 0 0.00% # Type of FU issued
- InstPrefetch 0 0.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0.end_dist
-system.cpu.iq.ISSUE:fu_busy_cnt 115 # FU busy when requested
-system.cpu.iq.ISSUE:fu_busy_rate 0.013710 # FU busy rate (busy events/executed inst)
-system.cpu.iq.ISSUE:fu_full.start_dist
- (null) 0 0.00% # attempts to use FU when none available
- IntAlu 1 0.87% # attempts to use FU when none available
- IntMult 0 0.00% # attempts to use FU when none available
- IntDiv 0 0.00% # attempts to use FU when none available
- FloatAdd 0 0.00% # attempts to use FU when none available
- FloatCmp 0 0.00% # attempts to use FU when none available
- FloatCvt 0 0.00% # attempts to use FU when none available
- FloatMult 0 0.00% # attempts to use FU when none available
- FloatDiv 0 0.00% # attempts to use FU when none available
- FloatSqrt 0 0.00% # attempts to use FU when none available
- MemRead 76 66.09% # attempts to use FU when none available
- MemWrite 38 33.04% # attempts to use FU when none available
- IprAccess 0 0.00% # attempts to use FU when none available
- InstPrefetch 0 0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full.end_dist
-system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle.samples 6871
-system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
- 0 3753 5462.09%
- 1 894 1301.12%
- 2 723 1052.25%
- 3 614 893.61%
- 4 451 656.38%
- 5 279 406.05%
- 6 104 151.36%
- 7 41 59.67%
- 8 12 17.46%
-system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
-system.cpu.iq.ISSUE:issued_per_cycle.end_dist
-
-system.cpu.iq.ISSUE:rate 1.220783 # Inst issue rate
-system.cpu.iq.iqInstsAdded 9932 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqInstsIssued 8388 # Number of instructions issued
-system.cpu.iq.iqNonSpecInstsAdded 21 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqSquashedInstsExamined 3990 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedInstsIssued 21 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedNonSpecRemoved 4 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.iqSquashedOperandsExamined 2486 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.l2cache.ReadReq_accesses 499 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 2.042254 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency 1015 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate 0.995992 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses 497 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 490 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.981964 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses 490 # number of ReadReq MSHR misses
-system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs 0.004024 # Average number of references to valid blocks.
-system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.demand_accesses 499 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 2.042254 # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 1 # average overall mshr miss latency
-system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 1015 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate 0.995992 # miss rate for demand accesses
-system.cpu.l2cache.demand_misses 497 # number of demand (read+write) misses
-system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency 490 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate 0.981964 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses 490 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.fast_writes 0 # number of fast writes performed
-system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.overall_accesses 499 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 2.042254 # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 1 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits 2 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 1015 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate 0.995992 # miss rate for overall accesses
-system.cpu.l2cache.overall_misses 497 # number of overall misses
-system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 490 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate 0.981964 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses 490 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.l2cache.replacements 0 # number of replacements
-system.cpu.l2cache.sampled_refs 497 # Sample count of references to valid blocks.
-system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 295.773395 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks 0 # number of writebacks
-system.cpu.numCycles 6871 # number of cpu cycles simulated
-system.cpu.rename.RENAME:BlockCycles 4 # Number of cycles rename is blocking
-system.cpu.rename.RENAME:CommittedMaps 4051 # Number of HB maps that are committed
-system.cpu.rename.RENAME:IdleCycles 3758 # Number of cycles rename is idle
-system.cpu.rename.RENAME:LSQFullEvents 62 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RENAME:RenameLookups 14786 # Number of register rename lookups that rename has made
-system.cpu.rename.RENAME:RenamedInsts 11555 # Number of instructions processed by rename
-system.cpu.rename.RENAME:RenamedOperands 8634 # Number of destination operands rename has renamed
-system.cpu.rename.RENAME:RunCycles 1975 # Number of cycles rename is running
-system.cpu.rename.RENAME:SquashCycles 754 # Number of cycles rename is squashing
-system.cpu.rename.RENAME:UnblockCycles 111 # Number of cycles rename is unblocking
-system.cpu.rename.RENAME:UndoneMaps 4583 # Number of HB maps that are undone due to squashing
-system.cpu.rename.RENAME:serializeStallCycles 269 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RENAME:serializingInsts 26 # count of serializing insts renamed
-system.cpu.rename.RENAME:skidInsts 408 # count of insts added to the skid buffer
-system.cpu.rename.RENAME:tempSerializingInsts 21 # count of temporary serializing insts renamed
-system.cpu.workload.PROG:num_syscalls 17 # Number of system calls
+sim_insts 88361899 # Number of instructions simulated
+sim_seconds 0.000088 # Number of seconds simulated
+sim_ticks 88361898 # Number of ticks simulated
+system.cpu.idle_fraction 0 # Percentage of idle cycles
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.numCycles 88361899 # number of cpu cycles simulated
+system.cpu.num_insts 88361899 # Number of instructions executed
+system.cpu.num_refs 35229376 # Number of memory references
+system.cpu.workload.PROG:num_syscalls 4706 # Number of system calls
---------- End Simulation Statistics ----------
diff --git a/tests/long/50.vortex/ref/alpha/linux/simple-atomic/smred.msg b/tests/long/50.vortex/ref/alpha/linux/simple-atomic/smred.msg
new file mode 100644
index 000000000..327142d7c
--- /dev/null
+++ b/tests/long/50.vortex/ref/alpha/linux/simple-atomic/smred.msg
@@ -0,0 +1,158 @@
+
+ SYSTEM TYPE...
+ __ZTC__ := False
+ __UNIX__ := True
+ __RISC__ := True
+ SPEC_CPU2000_LP64 := True
+ __MAC__ := False
+ __BCC__ := False
+ __BORLANDC__ := False
+ __GUI__ := False
+ __WTC__ := False
+ __HP__ := False
+
+ CODE OPTIONS...
+ __MACROIZE_HM__ := True
+ __MACROIZE_MEM__ := True
+ ENV01 := True
+ USE_HPP_STYPE_HDRS := False
+ USE_H_STYPE_HDRS := False
+
+ CODE INCLUSION PARAMETERS...
+ INCLUDE_ALL_CODE := False
+ INCLUDE_DELETE_CODE := True
+ __SWAP_GRP_POS__ := True
+ __INCLUDE_MTRX__ := False
+ __BAD_CODE__ := False
+ API_INCLUDE := False
+ BE_CAREFUL := False
+ OLDWAY := False
+ NOTUSED := False
+
+ SYSTEM PARAMETERS...
+ EXT_ENUM := 999999999L
+ CHUNK_CONSTANT := 55555555
+ CORE_CONSTANT := 55555555
+ CORE_LIMIT := 20971520
+ CorePage_Size := 384000
+ ALIGN_BYTES := True
+ CORE_BLOCK_ALIGN := 8
+ FAR_MEM := False
+
+ MEMORY MANAGEMENT PARAMETERS...
+ SYSTEM_ALLOC := True
+ SYSTEM_FREESTORE := True
+ __NO_DISKCACHE__ := False
+ __FREEZE_VCHUNKS__ := True
+ __FREEZE_GRP_PACKETS__ := True
+ __MINIMIZE_TREE_CACHE__:= True
+
+ SYSTEM STD PARAMETERS...
+ __STDOUT__ := False
+ NULL := 0
+ LPTR := False
+ False_Status := 1
+ True_Status := 0
+ LARGE := True
+ TWOBYTE_BOOL := False
+ __NOSTR__ := False
+
+ MEMORY VALIDATION PARAMETERS...
+ CORE_CRC_CHECK := False
+ VALIDATE_MEM_CHUNKS := False
+
+ SYSTEM DEBUG OPTIONS...
+ DEBUG := False
+ MCSTAT := False
+ TRACKBACK := False
+ FLUSH_FILES := False
+ DEBUG_CORE0 := False
+ DEBUG_RISC := False
+ __TREE_BUG__ := False
+ __TRACK_FILE_READS__ := False
+ PAGE_SPACE := False
+ LEAVE_NO_TRACE := True
+ NULL_TRACE_STRS := False
+
+ TIME PARAMETERS...
+ CLOCK_IS_LONG := False
+ __DISPLAY_TIME__ := False
+ __TREE_TIME__ := False
+ __DISPLAY_ERRORS__ := False
+
+ API MACROS...
+ __BMT01__ := True
+ OPTIMIZE := True
+
+ END OF DEFINES.
+
+
+
+ ... IMPLODE MEMORY ...
+
+ SWAP to DiskCache := False
+
+ FREEZE_GRP_PACKETS:= True
+
+ QueBug := 1000
+
+ sizeof(boolean) = 4
+ sizeof(sizetype) = 4
+ sizeof(chunkstruc) = 32
+
+ sizeof(shorttype ) = 2
+ sizeof(idtype ) = 2
+ sizeof(sizetype ) = 4
+ sizeof(indextype ) = 4
+ sizeof(numtype ) = 4
+ sizeof(handletype) = 4
+ sizeof(tokentype ) = 8
+
+ sizeof(short ) = 2
+ sizeof(int ) = 4
+
+ sizeof(lt64 ) = 4
+ sizeof(farlongtype) = 4
+ sizeof(long ) = 8
+ sizeof(longaddr ) = 8
+
+ sizeof(float ) = 4
+ sizeof(double ) = 8
+
+ sizeof(addrtype ) = 8
+ sizeof(char * ) = 8
+ ALLOC CORE_1 :: 16
+ BHOOLE NATH
+
+ OPEN File ./input/lendian.rnv
+ *Status = 0
+ DB HDR restored from FileVbn[ 0]
+ DB BlkDirOffset : @ 2030c0
+ DB BlkDirChunk : Chunk[ 10] AT Vbn[3146]
+ DB BlkTknChunk : Chunk[ 11] AT Vbn[3147]
+ DB BlkSizeChunk : Chunk[ 12] AT Vbn[3148]
+ DB Handle Chunk's StackPtr = 20797
+
+ DB[ 1] LOADED; Handles= 20797
+ KERNEL in CORE[ 1] Restored @ 40054800
+
+ OPEN File ./input/lendian.wnv
+ *Status = 0
+ DB HDR restored from FileVbn[ 0]
+ DB BlkDirOffset : @ 21c40
+ DB BlkDirChunk : Chunk[ 31] AT Vbn[ 81]
+ DB BlkTknChunk : Chunk[ 32] AT Vbn[ 82]
+ DB BlkSizeChunk : Chunk[ 33] AT Vbn[ 83]
+ DB Handle Chunk's StackPtr = 17
+
+ DB[ 2] LOADED; Handles= 17
+ VORTEx_Status == -8 || fffffff8
+
+ BE HERE NOW !!!
+
+
+
+ ... VORTEx ON LINE ...
+
+
+ ... END OF SESSION ...
diff --git a/tests/long/50.vortex/ref/alpha/linux/simple-atomic/smred.out b/tests/long/50.vortex/ref/alpha/linux/simple-atomic/smred.out
new file mode 100644
index 000000000..726b45c60
--- /dev/null
+++ b/tests/long/50.vortex/ref/alpha/linux/simple-atomic/smred.out
@@ -0,0 +1,258 @@
+ CREATE Db Header and Db Primal ...
+ NEW DB [ 3] Created.
+
+VORTEX INPUT PARAMETERS::
+ MESSAGE FileName: smred.msg
+ OUTPUT FileName: smred.out
+ DISK CACHE FileName: NULL
+ PART DB FileName: parts.db
+ DRAW DB FileName: draw.db
+ PERSON DB FileName: emp.db
+ PERSONS Data FileName: ./input/persons.250
+ PARTS Count : 100
+ OUTER Loops : 1
+ INNER Loops : 1
+ LOOKUP Parts : 25
+ DELETE Parts : 10
+ STUFF Parts : 10
+ DEPTH Traverse: 5
+ % DECREASE Parts : 0
+ % INCREASE LookUps : 0
+ % INCREASE Deletes : 0
+ % INCREASE Stuffs : 0
+ FREEZE_PACKETS : 1
+ ALLOC_CHUNKS : 10000
+ EXTEND_CHUNKS : 5000
+ DELETE Draw objects : True
+ DELETE Part objects : False
+ QUE_BUG : 1000
+ VOID_BOUNDARY : 67108864
+ VOID_RESERVE : 1048576
+
+ COMMIT_DBS : False
+
+
+
+ BMT TEST :: files...
+ EdbName := PartLib
+ EdbFileName := parts.db
+ DrwName := DrawLib
+ DrwFileName := draw.db
+ EmpName := PersonLib
+ EmpFileName := emp.db
+
+ Swap to DiskCache := False
+ Freeze the cache := True
+
+
+ BMT TEST :: parms...
+ DeBug modulo := 1000
+ Create Parts count:= 100
+ Outer Loops := 1
+ Inner Loops := 1
+ Look Ups := 25
+ Delete Parts := 10
+ Stuff Parts := 10
+ Traverse Limit := 5
+ Delete Draws := True
+ Delete Parts := False
+ Delete ALL Parts := after every <mod 0>Outer Loop
+
+ INITIALIZE LIBRARY ::
+
+ INITIALIZE SCHEMA ::
+ Primal_CreateDb Accessed !!!
+ CREATE Db Header and Db Primal ...
+ NEW DB [ 4] Created.
+ PartLibCreate:: Db[ 4]; VpartsDir= 1
+
+ Part Count= 1
+
+ Initialize the Class maps
+ LIST HEADS loaded ... DbListHead_Class = 207
+ DbListNode_Class = 206
+
+...NOTE... ShellLoadCode:: Class[ 228] will NOT be Activated.
+
+
+...NOTE... ShellLoadCode:: Class[ 229] will NOT be Activated.
+
+ Primal_CreateDb Accessed !!!
+ CREATE Db Header and Db Primal ...
+ NEW DB [ 5] Created.
+ DrawLibCreate:: Db[ 5]; VpartsDir= 1
+
+ Initialize the Class maps of this schema.
+ Primal_CreateDb Accessed !!!
+ CREATE Db Header and Db Primal ...
+ NEW DB [ 6] Created.
+
+ ***NOTE*** Persons Library Extended!
+
+ Create <131072> Persons.
+ ItNum 0. Person[ 6: 5]. Name= Riddell , Robert V. ;
+
+ LAST Person Read::
+ ItNum 250. Person[ 6: 503]. Name= Gonzales , Warren X. ;
+
+ BUILD <Query0> for <Part2> class::
+
+ if (link[1].length >= 5) ::
+
+ Build Query2 for <Address> class::
+
+ if (State == CA || State == T*)
+
+ Build Query1 for <Person> class::
+
+ if (LastName >= H* && LastName <= P* && Query0(Residence)) ::
+
+ BUILD <Query3> for <DrawObj> class::
+
+ if (Id >= 3000
+ && (Id >= 3000 && Id <= 3001)
+ && Id >= 3002)
+
+ BUILD <Query4> for <NamedDrawObj> class::
+
+ if (Nam == Pre*
+ || (Nam == ??Mid??? || == Pre??Mid?? || == ??Post
+ || == Pre??Post || == ??Mid???Post || == Pre??Mid???Post)
+ && Id <= 7)
+ SEED := 1008; Swap = False; RgnEntries = 135
+
+ OUTER LOOP [ 1] : NewParts = 100 LookUps = 25 StuffParts = 10.
+
+ Create 100 New Parts
+ Create Part 1. Token[ 4: 2].
+
+ < 100> Parts Created. CurrentId= 100
+
+ Connect each instantiated Part TO 3 unique Parts
+ Connect Part 1. Token[ 4: 2]
+ Connect Part 25. Token[ 4: 26] FromList= 26.
+ Connect Part 12. Token[ 4: 13] FromList= 13.
+ Connect Part 59. Token[ 4: 60] FromList= 60.
+
+ SET <DrawObjs> entries::
+ 1. [ 5: 5] := <1 >; @[: 6]
+ Iteration count = 100
+
+ SET <NamedDrawObjs> entries::
+ 1. [ 5: 39] := <14 >;
+ Iteration count = 12
+
+ SET <LibRectangles> entries::
+ 1. [ 5: 23] := <8 >; @[: 24]
+ Iteration count = 12
+
+ LIST <DbRectangles> entries::
+ 1. [ 5: 23]
+ Iteration count = 12
+
+ SET <PersonNames > entries::
+ Iteration count = 250
+
+ COMMIT All Image copies:: Release=<True>; Max Parts= 100
+ < 100> Part images' Committed.
+ < 0> are Named.
+ < 50> Point images' Committed.
+ < 81> Person images' Committed.
+
+ COMMIT Parts(* 100)
+
+ Commit TestObj_Class in <Primal> DB.
+ ItNum 0. Token[ 0: 0]. TestObj Committed.
+ < 0> TestObj images' Committed.
+
+ Commit CartesianPoint_Class in <Primal> DB.
+ ItNum 0. Token[ 0: 0]. CartesianPoint Committed.
+ < 0> CartesianPoint images' Committed.
+
+ BEGIN Inner Loop Sequence::.
+
+ INNER LOOP [ 1: 1] :
+
+ LOOK UP 25 Random Parts and Export each Part.
+
+ LookUp for 26 parts; Asserts = 8
+ <Part2 > Asserts = 2; NULL Asserts = 3.
+ <DrawObj > Asserts = 0; NULL Asserts = 5.
+ <NamedObj > Asserts = 0; NULL Asserts = 0.
+ <Person > Asserts = 0; NULL Asserts = 5.
+ <TestObj > Asserts = 60; NULL Asserts = 0.
+
+ DELETE 10 Random Parts.
+
+ PartDelete :: Token[ 4: 91].
+ PartDisconnect:: Token[ 4: 91] id:= 90 for each link.
+ DisConnect link [ 0]:= 50; PartToken[ 51: 51].
+ DisConnect link [ 1]:= 17; PartToken[ 18: 18].
+ DisConnect link [ 2]:= 72; PartToken[ 73: 73].
+ DeleteFromList:: Vchunk[ 4: 91]. (* 1)
+ DisConnect FromList[ 0]:= 56; Token[ 57: 57].
+ Vlists[ 89] := 100;
+
+ Delete for 11 parts;
+
+ Traverse Count= 0
+
+ TRAVERSE PartId[ 6] and all Connections to 5 Levels
+ SEED In Traverse Part [ 4: 65] @ Level = 4.
+
+ Traverse Count= 357
+ Traverse Asserts = 5. True Tests = 1
+ < 5> DrawObj objects DELETED.
+ < 2> are Named.
+ < 2> Point objects DELETED.
+
+ CREATE 10 Additional Parts
+
+ Create 10 New Parts
+ Create Part 101. Token[ 4: 102].
+
+ < 10> Parts Created. CurrentId= 110
+
+ Connect each instantiated Part TO 3 unique Parts
+
+ COMMIT All Image copies:: Release=<True>; Max Parts= 110
+ < 81> Part images' Committed.
+ < 0> are Named.
+ < 38> Point images' Committed.
+ < 31> Person images' Committed.
+
+ COMMIT Parts(* 100)
+
+ Commit TestObj_Class in <Primal> DB.
+ ItNum 0. Token[ 3: 4]. TestObj Committed.
+ < 15> TestObj images' Committed.
+
+ Commit CartesianPoint_Class in <Primal> DB.
+ ItNum 0. Token[ 3: 3]. CartesianPoint Committed.
+ < 16> CartesianPoint images' Committed.
+
+ DELETE All TestObj objects;
+
+ Delete TestObj_Class in <Primal> DB.
+ ItNum 0. Token[ 3: 4]. TestObj Deleted.
+ < 15> TestObj objects Deleted.
+
+ Commit CartesianPoint_Class in <Primal> DB.
+ ItNum 0. Token[ 3: 3]. CartesianPoint Deleted.
+ < 16> CartesianPoint objects Deleted.
+
+ DELETE TestObj and Point objects...
+
+ END INNER LOOP [ 1: 1].
+
+ DELETE All TestObj objects;
+
+ Delete TestObj_Class in <Primal> DB.
+ < 0> TestObj objects Deleted.
+
+ Commit CartesianPoint_Class in <Primal> DB.
+ < 0> CartesianPoint objects Deleted.
+
+ DELETE TestObj and Point objects...
+ STATUS= -201
+V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!
diff --git a/tests/long/50.vortex/ref/alpha/linux/simple-atomic/stderr b/tests/long/50.vortex/ref/alpha/linux/simple-atomic/stderr
index 8893caac8..87866a2a5 100644
--- a/tests/long/50.vortex/ref/alpha/linux/simple-atomic/stderr
+++ b/tests/long/50.vortex/ref/alpha/linux/simple-atomic/stderr
@@ -1,3 +1 @@
warn: Entering event queue @ 0. Starting simulation...
-warn: cycle 0: fault (page_table_fault) detected @ PC 0x000000
-warn: Increasing stack 0x11ff92000:0x11ff9b000 to 0x11ff90000:0x11ff9b000 because of access to 0x11ff91ff0
diff --git a/tests/long/50.vortex/ref/alpha/linux/simple-atomic/stdout b/tests/long/50.vortex/ref/alpha/linux/simple-atomic/stdout
index fbb329a2f..e69de29bb 100644
--- a/tests/long/50.vortex/ref/alpha/linux/simple-atomic/stdout
+++ b/tests/long/50.vortex/ref/alpha/linux/simple-atomic/stdout
@@ -1,13 +0,0 @@
-Hello world!
-M5 Simulator System
-
-Copyright (c) 2001-2006
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Sep 5 2006 15:28:48
-M5 started Tue Sep 5 15:42:12 2006
-M5 executing on zizzer.eecs.umich.edu
-command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/o3-timing tests/run.py quick/00.hello/alpha/linux/o3-timing
-Exiting @ tick 6870 because target called exit()
diff --git a/tests/long/50.vortex/ref/alpha/linux/simple-timing/config.ini b/tests/long/50.vortex/ref/alpha/linux/simple-timing/config.ini
index c3a59fbce..3e5bdc569 100644
--- a/tests/long/50.vortex/ref/alpha/linux/simple-timing/config.ini
+++ b/tests/long/50.vortex/ref/alpha/linux/simple-timing/config.ini
@@ -7,11 +7,9 @@ max_tick=0
output_file=cout
progress_interval=0
-[debug]
-break_cycles=
-
[exetrace]
intel_format=false
+legion_lockstep=false
pc_symbol=true
print_cpseq=false
print_cycle=true
@@ -53,73 +51,20 @@ mem_mode=atomic
physmem=system.physmem
[system.cpu]
-type=DerivO3CPU
-children=dcache fuPool icache l2cache toL2Bus workload
-BTBEntries=4096
-BTBTagSize=16
-LFSTSize=1024
-LQEntries=32
-RASSize=16
-SQEntries=32
-SSITSize=1024
-activity=0
-backComSize=5
-choiceCtrBits=2
-choicePredictorSize=8192
+type=TimingSimpleCPU
+children=dcache icache l2cache toL2Bus workload
clock=1
-commitToDecodeDelay=1
-commitToFetchDelay=1
-commitToIEWDelay=1
-commitToRenameDelay=1
-commitWidth=8
-decodeToFetchDelay=1
-decodeToRenameDelay=1
-decodeWidth=8
+cpu_id=0
defer_registration=false
-dispatchWidth=8
-fetchToDecodeDelay=1
-fetchTrapLatency=1
-fetchWidth=8
-forwardComSize=5
-fuPool=system.cpu.fuPool
function_trace=false
function_trace_start=0
-globalCtrBits=2
-globalHistoryBits=13
-globalPredictorSize=8192
-iewToCommitDelay=1
-iewToDecodeDelay=1
-iewToFetchDelay=1
-iewToRenameDelay=1
-instShiftAmt=2
-issueToExecuteDelay=1
-issueWidth=8
-localCtrBits=2
-localHistoryBits=11
-localHistoryTableSize=2048
-localPredictorSize=2048
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
-mem=system.cpu.dcache
-numIQEntries=64
-numPhysFloatRegs=256
-numPhysIntRegs=256
-numROBEntries=192
-numRobs=1
-numThreads=1
-predType=tournament
-renameToDecodeDelay=1
-renameToFetchDelay=1
-renameToIEWDelay=2
-renameToROBDelay=1
-renameWidth=8
-squashWidth=8
+phase=0
+progress_interval=0
system=system
-trapLatency=13
-wbDepth=1
-wbWidth=8
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
@@ -131,7 +76,6 @@ assoc=2
block_size=64
compressed_bus=false
compression_latency=0
-do_copy=false
hash_delay=1
hit_latency=1
latency=1
@@ -164,143 +108,6 @@ write_buffers=8
cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.port[1]
-[system.cpu.fuPool]
-type=FUPool
-children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7
-FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7
-
-[system.cpu.fuPool.FUList0]
-type=FUDesc
-children=opList0
-count=6
-opList=system.cpu.fuPool.FUList0.opList0
-
-[system.cpu.fuPool.FUList0.opList0]
-type=OpDesc
-issueLat=1
-opClass=IntAlu
-opLat=1
-
-[system.cpu.fuPool.FUList1]
-type=FUDesc
-children=opList0 opList1
-count=2
-opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
-
-[system.cpu.fuPool.FUList1.opList0]
-type=OpDesc
-issueLat=1
-opClass=IntMult
-opLat=3
-
-[system.cpu.fuPool.FUList1.opList1]
-type=OpDesc
-issueLat=19
-opClass=IntDiv
-opLat=20
-
-[system.cpu.fuPool.FUList2]
-type=FUDesc
-children=opList0 opList1 opList2
-count=4
-opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
-
-[system.cpu.fuPool.FUList2.opList0]
-type=OpDesc
-issueLat=1
-opClass=FloatAdd
-opLat=2
-
-[system.cpu.fuPool.FUList2.opList1]
-type=OpDesc
-issueLat=1
-opClass=FloatCmp
-opLat=2
-
-[system.cpu.fuPool.FUList2.opList2]
-type=OpDesc
-issueLat=1
-opClass=FloatCvt
-opLat=2
-
-[system.cpu.fuPool.FUList3]
-type=FUDesc
-children=opList0 opList1 opList2
-count=2
-opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
-
-[system.cpu.fuPool.FUList3.opList0]
-type=OpDesc
-issueLat=1
-opClass=FloatMult
-opLat=4
-
-[system.cpu.fuPool.FUList3.opList1]
-type=OpDesc
-issueLat=12
-opClass=FloatDiv
-opLat=12
-
-[system.cpu.fuPool.FUList3.opList2]
-type=OpDesc
-issueLat=24
-opClass=FloatSqrt
-opLat=24
-
-[system.cpu.fuPool.FUList4]
-type=FUDesc
-children=opList0
-count=0
-opList=system.cpu.fuPool.FUList4.opList0
-
-[system.cpu.fuPool.FUList4.opList0]
-type=OpDesc
-issueLat=1
-opClass=MemRead
-opLat=1
-
-[system.cpu.fuPool.FUList5]
-type=FUDesc
-children=opList0
-count=0
-opList=system.cpu.fuPool.FUList5.opList0
-
-[system.cpu.fuPool.FUList5.opList0]
-type=OpDesc
-issueLat=1
-opClass=MemWrite
-opLat=1
-
-[system.cpu.fuPool.FUList6]
-type=FUDesc
-children=opList0 opList1
-count=4
-opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1
-
-[system.cpu.fuPool.FUList6.opList0]
-type=OpDesc
-issueLat=1
-opClass=MemRead
-opLat=1
-
-[system.cpu.fuPool.FUList6.opList1]
-type=OpDesc
-issueLat=1
-opClass=MemWrite
-opLat=1
-
-[system.cpu.fuPool.FUList7]
-type=FUDesc
-children=opList0
-count=1
-opList=system.cpu.fuPool.FUList7.opList0
-
-[system.cpu.fuPool.FUList7.opList0]
-type=OpDesc
-issueLat=3
-opClass=IprAccess
-opLat=3
-
[system.cpu.icache]
type=BaseCache
adaptive_compression=false
@@ -308,7 +115,6 @@ assoc=2
block_size=64
compressed_bus=false
compression_latency=0
-do_copy=false
hash_delay=1
hit_latency=1
latency=1
@@ -348,7 +154,6 @@ assoc=2
block_size=64
compressed_bus=false
compression_latency=0
-do_copy=false
hash_delay=1
hit_latency=1
latency=1
@@ -384,20 +189,33 @@ mem_side=system.membus.port[1]
[system.cpu.toL2Bus]
type=Bus
bus_id=0
+clock=1000
+responder_set=false
+width=64
port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
[system.cpu.workload]
type=LiveProcess
-cmd=hello
+cmd=vortex lendian.raw
+cwd=build/ALPHA_SE/tests/opt/long/50.vortex/alpha/linux/simple-timing
+egid=100
env=
-executable=tests/test-progs/hello/bin/alpha/linux/hello
+euid=100
+executable=/dist/m5/cpu2000/binaries/alpha/tru64/vortex
+gid=100
input=cin
output=cout
+pid=100
+ppid=99
system=system
+uid=100
[system.membus]
type=Bus
bus_id=0
+clock=1000
+responder_set=false
+width=64
port=system.physmem.port system.cpu.l2cache.mem_side
[system.physmem]
@@ -409,6 +227,7 @@ port=system.membus.port[0]
[trace]
bufsize=0
+cycle=0
dump_on_exit=false
file=cout
flags=
diff --git a/tests/long/50.vortex/ref/alpha/linux/simple-timing/config.out b/tests/long/50.vortex/ref/alpha/linux/simple-timing/config.out
index f491a3081..9ecf4b55d 100644
--- a/tests/long/50.vortex/ref/alpha/linux/simple-timing/config.out
+++ b/tests/long/50.vortex/ref/alpha/linux/simple-timing/config.out
@@ -19,19 +19,54 @@ mem_mode=atomic
[system.membus]
type=Bus
bus_id=0
+clock=1000
+width=64
+responder_set=false
[system.cpu.workload]
type=LiveProcess
-cmd=hello
-executable=tests/test-progs/hello/bin/alpha/linux/hello
+cmd=vortex lendian.raw
+executable=/dist/m5/cpu2000/binaries/alpha/tru64/vortex
input=cin
output=cout
env=
+cwd=build/ALPHA_SE/tests/opt/long/50.vortex/alpha/linux/simple-timing
system=system
+uid=100
+euid=100
+gid=100
+egid=100
+pid=100
+ppid=99
-[system.cpu.dcache]
+[system.cpu]
+type=TimingSimpleCPU
+max_insts_any_thread=0
+max_insts_all_threads=0
+max_loads_any_thread=0
+max_loads_all_threads=0
+progress_interval=0
+system=system
+cpu_id=0
+workload=system.cpu.workload
+clock=1
+phase=0
+defer_registration=false
+// width not specified
+function_trace=false
+function_trace_start=0
+// simulate_stalls not specified
+
+[system.cpu.toL2Bus]
+type=Bus
+bus_id=0
+clock=1000
+width=64
+responder_set=false
+
+[system.cpu.icache]
type=BaseCache
-size=262144
+size=131072
assoc=2
block_size=64
latency=1
@@ -39,7 +74,6 @@ mshrs=10
tgts_per_mshr=5
write_buffers=8
prioritizeRequests=false
-do_copy=false
protocol=null
trace_addr=0
hash_delay=1
@@ -68,214 +102,9 @@ prefetch_use_cpu_id=true
prefetch_data_accesses_only=false
hit_latency=1
-[system.cpu.fuPool.FUList0.opList0]
-type=OpDesc
-opClass=IntAlu
-opLat=1
-issueLat=1
-
-[system.cpu.fuPool.FUList0]
-type=FUDesc
-opList=system.cpu.fuPool.FUList0.opList0
-count=6
-
-[system.cpu.fuPool.FUList1.opList0]
-type=OpDesc
-opClass=IntMult
-opLat=3
-issueLat=1
-
-[system.cpu.fuPool.FUList1.opList1]
-type=OpDesc
-opClass=IntDiv
-opLat=20
-issueLat=19
-
-[system.cpu.fuPool.FUList1]
-type=FUDesc
-opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
-count=2
-
-[system.cpu.fuPool.FUList2.opList0]
-type=OpDesc
-opClass=FloatAdd
-opLat=2
-issueLat=1
-
-[system.cpu.fuPool.FUList2.opList1]
-type=OpDesc
-opClass=FloatCmp
-opLat=2
-issueLat=1
-
-[system.cpu.fuPool.FUList2.opList2]
-type=OpDesc
-opClass=FloatCvt
-opLat=2
-issueLat=1
-
-[system.cpu.fuPool.FUList2]
-type=FUDesc
-opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
-count=4
-
-[system.cpu.fuPool.FUList3.opList0]
-type=OpDesc
-opClass=FloatMult
-opLat=4
-issueLat=1
-
-[system.cpu.fuPool.FUList3.opList1]
-type=OpDesc
-opClass=FloatDiv
-opLat=12
-issueLat=12
-
-[system.cpu.fuPool.FUList3.opList2]
-type=OpDesc
-opClass=FloatSqrt
-opLat=24
-issueLat=24
-
-[system.cpu.fuPool.FUList3]
-type=FUDesc
-opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
-count=2
-
-[system.cpu.fuPool.FUList4.opList0]
-type=OpDesc
-opClass=MemRead
-opLat=1
-issueLat=1
-
-[system.cpu.fuPool.FUList4]
-type=FUDesc
-opList=system.cpu.fuPool.FUList4.opList0
-count=0
-
-[system.cpu.fuPool.FUList5.opList0]
-type=OpDesc
-opClass=MemWrite
-opLat=1
-issueLat=1
-
-[system.cpu.fuPool.FUList5]
-type=FUDesc
-opList=system.cpu.fuPool.FUList5.opList0
-count=0
-
-[system.cpu.fuPool.FUList6.opList0]
-type=OpDesc
-opClass=MemRead
-opLat=1
-issueLat=1
-
-[system.cpu.fuPool.FUList6.opList1]
-type=OpDesc
-opClass=MemWrite
-opLat=1
-issueLat=1
-
-[system.cpu.fuPool.FUList6]
-type=FUDesc
-opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1
-count=4
-
-[system.cpu.fuPool.FUList7.opList0]
-type=OpDesc
-opClass=IprAccess
-opLat=3
-issueLat=3
-
-[system.cpu.fuPool.FUList7]
-type=FUDesc
-opList=system.cpu.fuPool.FUList7.opList0
-count=1
-
-[system.cpu.fuPool]
-type=FUPool
-FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7
-
-[system.cpu]
-type=DerivO3CPU
-clock=1
-numThreads=1
-activity=0
-workload=system.cpu.workload
-mem=system.cpu.dcache
-checker=null
-max_insts_any_thread=0
-max_insts_all_threads=0
-max_loads_any_thread=0
-max_loads_all_threads=0
-cachePorts=200
-decodeToFetchDelay=1
-renameToFetchDelay=1
-iewToFetchDelay=1
-commitToFetchDelay=1
-fetchWidth=8
-renameToDecodeDelay=1
-iewToDecodeDelay=1
-commitToDecodeDelay=1
-fetchToDecodeDelay=1
-decodeWidth=8
-iewToRenameDelay=1
-commitToRenameDelay=1
-decodeToRenameDelay=1
-renameWidth=8
-commitToIEWDelay=1
-renameToIEWDelay=2
-issueToExecuteDelay=1
-dispatchWidth=8
-issueWidth=8
-wbWidth=8
-wbDepth=1
-fuPool=system.cpu.fuPool
-iewToCommitDelay=1
-renameToROBDelay=1
-commitWidth=8
-squashWidth=8
-trapLatency=13
-backComSize=5
-forwardComSize=5
-predType=tournament
-localPredictorSize=2048
-localCtrBits=2
-localHistoryTableSize=2048
-localHistoryBits=11
-globalPredictorSize=8192
-globalCtrBits=2
-globalHistoryBits=13
-choicePredictorSize=8192
-choiceCtrBits=2
-BTBEntries=4096
-BTBTagSize=16
-RASSize=16
-LQEntries=32
-SQEntries=32
-LFSTSize=1024
-SSITSize=1024
-numPhysIntRegs=256
-numPhysFloatRegs=256
-numIQEntries=64
-numROBEntries=192
-smtNumFetchingThreads=1
-smtFetchPolicy=SingleThread
-smtLSQPolicy=Partitioned
-smtLSQThreshold=100
-smtIQPolicy=Partitioned
-smtIQThreshold=100
-smtROBPolicy=Partitioned
-smtROBThreshold=100
-smtCommitPolicy=RoundRobin
-instShiftAmt=2
-defer_registration=false
-function_trace=false
-function_trace_start=0
-
-[system.cpu.icache]
+[system.cpu.dcache]
type=BaseCache
-size=131072
+size=262144
assoc=2
block_size=64
latency=1
@@ -283,7 +112,6 @@ mshrs=10
tgts_per_mshr=5
write_buffers=8
prioritizeRequests=false
-do_copy=false
protocol=null
trace_addr=0
hash_delay=1
@@ -322,7 +150,6 @@ mshrs=10
tgts_per_mshr=5
write_buffers=8
prioritizeRequests=false
-do_copy=false
protocol=null
trace_addr=0
hash_delay=1
@@ -351,13 +178,10 @@ prefetch_use_cpu_id=true
prefetch_data_accesses_only=false
hit_latency=1
-[system.cpu.toL2Bus]
-type=Bus
-bus_id=0
-
[trace]
flags=
start=0
+cycle=0
bufsize=0
file=cout
dump_on_exit=false
@@ -396,8 +220,9 @@ print_cpseq=false
print_reg_delta=false
pc_symbol=true
intel_format=false
+legion_lockstep=false
trace_system=client
-[debug]
-break_cycles=
+[statsreset]
+reset_cycle=0
diff --git a/tests/long/50.vortex/ref/alpha/linux/simple-timing/m5stats.txt b/tests/long/50.vortex/ref/alpha/linux/simple-timing/m5stats.txt
index 5d4f9235a..ae340ffef 100644
--- a/tests/long/50.vortex/ref/alpha/linux/simple-timing/m5stats.txt
+++ b/tests/long/50.vortex/ref/alpha/linux/simple-timing/m5stats.txt
@@ -1,112 +1,67 @@
---------- Begin Simulation Statistics ----------
-global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-global.BPredUnit.BTBHits 542 # Number of BTB hits
-global.BPredUnit.BTBLookups 1938 # Number of BTB lookups
-global.BPredUnit.RASInCorrect 48 # Number of incorrect RAS predictions.
-global.BPredUnit.condIncorrect 420 # Number of conditional branches incorrect
-global.BPredUnit.condPredicted 1304 # Number of conditional branches predicted
-global.BPredUnit.lookups 2256 # Number of BP lookups
-global.BPredUnit.usedRAS 291 # Number of times the RAS was used to get a target.
-host_inst_rate 41797 # Simulator instruction rate (inst/s)
-host_mem_usage 160344 # Number of bytes of host memory used
-host_seconds 0.13 # Real time elapsed on the host
-host_tick_rate 50948 # Simulator tick rate (ticks/s)
-memdepunit.memDep.conflictingLoads 12 # Number of conflicting loads.
-memdepunit.memDep.conflictingStores 259 # Number of conflicting stores.
-memdepunit.memDep.insertedLoads 2050 # Number of loads inserted to the mem dependence unit.
-memdepunit.memDep.insertedStores 1221 # Number of stores inserted to the mem dependence unit.
+host_inst_rate 471701 # Simulator instruction rate (inst/s)
+host_mem_usage 255440 # Number of bytes of host memory used
+host_seconds 187.33 # Real time elapsed on the host
+host_tick_rate 6446013 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 5623 # Number of instructions simulated
-sim_seconds 0.000000 # Number of seconds simulated
-sim_ticks 6870 # Number of ticks simulated
-system.cpu.commit.COM:branches 862 # Number of branches committed
-system.cpu.commit.COM:bw_lim_events 74 # number cycles where commit BW limit reached
-system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle.samples 6116
-system.cpu.commit.COM:committed_per_cycle.min_value 0
- 0 3908 6389.80%
- 1 1064 1739.70%
- 2 389 636.04%
- 3 210 343.36%
- 4 153 250.16%
- 5 93 152.06%
- 6 76 124.26%
- 7 149 243.62%
- 8 74 120.99%
-system.cpu.commit.COM:committed_per_cycle.max_value 8
-system.cpu.commit.COM:committed_per_cycle.end_dist
-
-system.cpu.commit.COM:count 5640 # Number of instructions committed
-system.cpu.commit.COM:loads 979 # Number of loads committed
-system.cpu.commit.COM:membars 0 # Number of memory barriers committed
-system.cpu.commit.COM:refs 1791 # Number of memory references committed
-system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.branchMispredicts 337 # The number of times a branch was mispredicted
-system.cpu.commit.commitCommittedInsts 5640 # The number of committed instructions
-system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.commitSquashedInsts 4350 # The number of squashed insts skipped by commit
-system.cpu.committedInsts 5623 # Number of Instructions Simulated
-system.cpu.committedInsts_total 5623 # Number of Instructions Simulated
-system.cpu.cpi 1.221768 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 1.221768 # CPI: Total CPI of All Threads
-system.cpu.dcache.ReadReq_accesses 1538 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 3.072000 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2.240000 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits 1413 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 384 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate 0.081274 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses 125 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_hits 25 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_miss_latency 224 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate 0.065020 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses 100 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_accesses 821 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 2.467742 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2.140845 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 635 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 459 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.226553 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 186 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_hits 108 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_miss_latency 152 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.086480 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 71 # number of WriteReq MSHR misses
+sim_insts 88361899 # Number of instructions simulated
+sim_seconds 0.001208 # Number of seconds simulated
+sim_ticks 1207510003 # Number of ticks simulated
+system.cpu.dcache.ReadReq_accesses 20281385 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 3631.637073 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2631.637073 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits 20223321 # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency 210867375 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate 0.002863 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses 58064 # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_miss_latency 152803375 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate 0.002863 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_misses 58064 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_accesses 14615683 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_avg_miss_latency 4569.538784 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 3569.538784 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits 14473602 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 649244640 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate 0.009721 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses 142081 # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_miss_latency 507163640 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.009721 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses 142081 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles_no_targets 0.800000 # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 11.505618 # Average number of references to valid blocks.
+system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu.dcache.avg_refs 173.358930 # Average number of references to valid blocks.
system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_no_targets 5 # number of cycles access was blocked
+system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles_no_targets 4 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.demand_accesses 2359 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 2.710611 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 2.198830 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 2048 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 843 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.131836 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 311 # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits 133 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 376 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate 0.072488 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 171 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_accesses 34897068 # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency 4297.444428 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 3297.444428 # average overall mshr miss latency
+system.cpu.dcache.demand_hits 34696923 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 860112015 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate 0.005735 # miss rate for demand accesses
+system.cpu.dcache.demand_misses 200145 # number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency 659967015 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate 0.005735 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses 200145 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.overall_accesses 2359 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 2.710611 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 2.198830 # average overall mshr miss latency
+system.cpu.dcache.overall_accesses 34897068 # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency 4297.444428 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 3297.444428 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 2048 # number of overall hits
-system.cpu.dcache.overall_miss_latency 843 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.131836 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 311 # number of overall misses
-system.cpu.dcache.overall_mshr_hits 133 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 376 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate 0.072488 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 171 # number of overall MSHR misses
+system.cpu.dcache.overall_hits 34696923 # number of overall hits
+system.cpu.dcache.overall_miss_latency 860112015 # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate 0.005735 # miss rate for overall accesses
+system.cpu.dcache.overall_misses 200145 # number of overall misses
+system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_miss_latency 659967015 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate 0.005735 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses 200145 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@@ -118,92 +73,57 @@ system.cpu.dcache.prefetcher.num_hwpf_issued 0
system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.dcache.replacements 0 # number of replacements
-system.cpu.dcache.sampled_refs 178 # Sample count of references to valid blocks.
+system.cpu.dcache.replacements 196049 # number of replacements
+system.cpu.dcache.sampled_refs 200145 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 119.831029 # Cycle average of tags in use
-system.cpu.dcache.total_refs 2048 # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks 0 # number of writebacks
-system.cpu.decode.DECODE:BlockedCycles 387 # Number of cycles decode is blocked
-system.cpu.decode.DECODE:BranchMispred 93 # Number of times decode detected a branch misprediction
-system.cpu.decode.DECODE:BranchResolved 185 # Number of times decode resolved a branch
-system.cpu.decode.DECODE:DecodedInsts 12349 # Number of instructions handled by decode
-system.cpu.decode.DECODE:IdleCycles 3542 # Number of cycles decode is idle
-system.cpu.decode.DECODE:RunCycles 2158 # Number of cycles decode is running
-system.cpu.decode.DECODE:SquashCycles 754 # Number of cycles decode is squashing
-system.cpu.decode.DECODE:SquashedInsts 286 # Number of squashed instructions handled by decode
-system.cpu.decode.DECODE:UnblockCycles 30 # Number of cycles decode is unblocking
-system.cpu.fetch.Branches 2256 # Number of branches that fetch encountered
-system.cpu.fetch.CacheLines 1582 # Number of cache lines fetched
-system.cpu.fetch.Cycles 3905 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.IcacheSquashes 148 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.Insts 13707 # Number of instructions fetch has processed
-system.cpu.fetch.SquashCycles 456 # Number of cycles fetch has spent squashing
-system.cpu.fetch.branchRate 0.328336 # Number of branch fetches per cycle
-system.cpu.fetch.icacheStallCycles 1582 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.predictedBranches 833 # Number of branches that fetch has predicted taken
-system.cpu.fetch.rate 1.994906 # Number of inst fetches per cycle
-system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist.samples 6871
-system.cpu.fetch.rateDist.min_value 0
- 0 4549 6620.58%
- 1 174 253.24%
- 2 186 270.70%
- 3 157 228.50%
- 4 211 307.09%
- 5 153 222.68%
- 6 171 248.87%
- 7 105 152.82%
- 8 1165 1695.53%
-system.cpu.fetch.rateDist.max_value 8
-system.cpu.fetch.rateDist.end_dist
-
-system.cpu.icache.ReadReq_accesses 1582 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 2.960245 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 1.996885 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits 1255 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 968 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate 0.206700 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses 327 # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_hits 6 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_miss_latency 641 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.202908 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses 321 # number of ReadReq MSHR misses
-system.cpu.icache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles_no_targets no value # average number of cycles each access was blocked
-system.cpu.icache.avg_refs 3.909657 # Average number of references to valid blocks.
+system.cpu.dcache.tagsinuse 4056.501584 # Cycle average of tags in use
+system.cpu.dcache.total_refs 34696923 # Total number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 28890000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.writebacks 147135 # number of writebacks
+system.cpu.icache.ReadReq_accesses 88361900 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency 2933.039863 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 1933.039863 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits 88285387 # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency 224415679 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_rate 0.000866 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_misses 76513 # number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_miss_latency 147902679 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate 0.000866 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_misses 76513 # number of ReadReq MSHR misses
+system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu.icache.avg_refs 1153.861265 # Average number of references to valid blocks.
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.demand_accesses 1582 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 2.960245 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 1.996885 # average overall mshr miss latency
-system.cpu.icache.demand_hits 1255 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 968 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate 0.206700 # miss rate for demand accesses
-system.cpu.icache.demand_misses 327 # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_hits 6 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 641 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate 0.202908 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses 321 # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_accesses 88361900 # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency 2933.039863 # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 1933.039863 # average overall mshr miss latency
+system.cpu.icache.demand_hits 88285387 # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency 224415679 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_rate 0.000866 # miss rate for demand accesses
+system.cpu.icache.demand_misses 76513 # number of demand (read+write) misses
+system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_miss_latency 147902679 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_rate 0.000866 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_misses 76513 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.overall_accesses 1582 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 2.960245 # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 1.996885 # average overall mshr miss latency
+system.cpu.icache.overall_accesses 88361900 # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency 2933.039863 # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 1933.039863 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits 1255 # number of overall hits
-system.cpu.icache.overall_miss_latency 968 # number of overall miss cycles
-system.cpu.icache.overall_miss_rate 0.206700 # miss rate for overall accesses
-system.cpu.icache.overall_misses 327 # number of overall misses
-system.cpu.icache.overall_mshr_hits 6 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 641 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate 0.202908 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses 321 # number of overall MSHR misses
+system.cpu.icache.overall_hits 88285387 # number of overall hits
+system.cpu.icache.overall_miss_latency 224415679 # number of overall miss cycles
+system.cpu.icache.overall_miss_rate 0.000866 # miss rate for overall accesses
+system.cpu.icache.overall_misses 76513 # number of overall misses
+system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_miss_latency 147902679 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_rate 0.000866 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_misses 76513 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@@ -215,1726 +135,64 @@ system.cpu.icache.prefetcher.num_hwpf_issued 0
system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.icache.replacements 0 # number of replacements
-system.cpu.icache.sampled_refs 321 # Sample count of references to valid blocks.
+system.cpu.icache.replacements 74468 # number of replacements
+system.cpu.icache.sampled_refs 76513 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 176.393247 # Cycle average of tags in use
-system.cpu.icache.total_refs 1255 # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse 1798.721885 # Cycle average of tags in use
+system.cpu.icache.total_refs 88285387 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.iew.EXEC:branches 1206 # Number of branches executed
-system.cpu.iew.EXEC:insts 7969 # Number of executed instructions
-system.cpu.iew.EXEC:loads 1610 # Number of load instructions executed
-system.cpu.iew.EXEC:nop 37 # number of nop insts executed
-system.cpu.iew.EXEC:rate 1.159802 # Inst execution rate
-system.cpu.iew.EXEC:refs 2599 # number of memory reference insts executed
-system.cpu.iew.EXEC:squashedInsts 419 # Number of squashed instructions skipped in execute
-system.cpu.iew.EXEC:stores 989 # Number of stores executed
-system.cpu.iew.EXEC:swp 0 # number of swp insts executed
-system.cpu.iew.WB:consumers 5438 # num instructions consuming a value
-system.cpu.iew.WB:count 7722 # cumulative count of insts written-back
-system.cpu.iew.WB:fanout 0.744575 # average fanout of values written-back
-system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.iew.WB:producers 4049 # num instructions producing a value
-system.cpu.iew.WB:rate 1.123854 # insts written-back per cycle
-system.cpu.iew.WB:sent 7762 # cumulative count of insts sent to commit
-system.cpu.iew.branchMispredicts 393 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewBlockCycles 4 # Number of cycles IEW is blocking
-system.cpu.iew.iewDispLoadInsts 2050 # Number of dispatched load instructions
-system.cpu.iew.iewDispNonSpecInsts 21 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewDispSquashedInsts 272 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispStoreInsts 1221 # Number of dispatched store instructions
-system.cpu.iew.iewDispatchedInsts 9990 # Number of instructions dispatched to IQ
-system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.iewSquashCycles 754 # Number of cycles IEW is squashing
-system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking
-system.cpu.iew.lsq.thread.0.blockedLoads 1 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread.0.cacheBlocked 5 # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.lsq.thread.0.forwLoads 55 # Number of loads that had data forwarded from stores
-system.cpu.iew.lsq.thread.0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
-system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread.0.squashedLoads 1071 # Number of loads squashed
-system.cpu.iew.lsq.thread.0.squashedStores 409 # Number of stores squashed
-system.cpu.iew.memOrderViolationEvents 41 # Number of memory order violations
-system.cpu.iew.predictedNotTakenIncorrect 296 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.predictedTakenIncorrect 97 # Number of branches that were predicted taken incorrectly
-system.cpu.ipc 0.818486 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.818486 # IPC: Total IPC of All Threads
-system.cpu.iq.IQ:residence:(null).start_dist # cycles from dispatch to issue
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-
-system.cpu.iq.IQ:residence:IntMult.start_dist # cycles from dispatch to issue
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-system.cpu.iq.IQ:residence:IntDiv.start_dist # cycles from dispatch to issue
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-system.cpu.iq.IQ:residence:FloatAdd.start_dist # cycles from dispatch to issue
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-system.cpu.iq.IQ:residence:FloatCvt.start_dist # cycles from dispatch to issue
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-system.cpu.iq.IQ:residence:FloatMult.start_dist # cycles from dispatch to issue
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-system.cpu.iq.ISSUE:IntAlu_delay.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
- 20 0
- 22 0
- 24 0
- 26 0
- 28 0
- 30 0
- 32 0
- 34 0
- 36 0
- 38 0
- 40 0
- 42 0
- 44 0
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- 78 0
- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.ISSUE:IntAlu_delay.max_value 0
-system.cpu.iq.ISSUE:IntAlu_delay.end_dist
-
-system.cpu.iq.ISSUE:IntMult_delay.start_dist # cycles from operands ready to issue
-system.cpu.iq.ISSUE:IntMult_delay.samples 0
-system.cpu.iq.ISSUE:IntMult_delay.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
- 20 0
- 22 0
- 24 0
- 26 0
- 28 0
- 30 0
- 32 0
- 34 0
- 36 0
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- 40 0
- 42 0
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- 50 0
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- 76 0
- 78 0
- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.ISSUE:IntMult_delay.max_value 0
-system.cpu.iq.ISSUE:IntMult_delay.end_dist
-
-system.cpu.iq.ISSUE:IntDiv_delay.start_dist # cycles from operands ready to issue
-system.cpu.iq.ISSUE:IntDiv_delay.samples 0
-system.cpu.iq.ISSUE:IntDiv_delay.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
- 20 0
- 22 0
- 24 0
- 26 0
- 28 0
- 30 0
- 32 0
- 34 0
- 36 0
- 38 0
- 40 0
- 42 0
- 44 0
- 46 0
- 48 0
- 50 0
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- 78 0
- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.ISSUE:IntDiv_delay.max_value 0
-system.cpu.iq.ISSUE:IntDiv_delay.end_dist
-
-system.cpu.iq.ISSUE:FloatAdd_delay.start_dist # cycles from operands ready to issue
-system.cpu.iq.ISSUE:FloatAdd_delay.samples 0
-system.cpu.iq.ISSUE:FloatAdd_delay.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
- 20 0
- 22 0
- 24 0
- 26 0
- 28 0
- 30 0
- 32 0
- 34 0
- 36 0
- 38 0
- 40 0
- 42 0
- 44 0
- 46 0
- 48 0
- 50 0
- 52 0
- 54 0
- 56 0
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- 60 0
- 62 0
- 64 0
- 66 0
- 68 0
- 70 0
- 72 0
- 74 0
- 76 0
- 78 0
- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.ISSUE:FloatAdd_delay.max_value 0
-system.cpu.iq.ISSUE:FloatAdd_delay.end_dist
-
-system.cpu.iq.ISSUE:FloatCmp_delay.start_dist # cycles from operands ready to issue
-system.cpu.iq.ISSUE:FloatCmp_delay.samples 0
-system.cpu.iq.ISSUE:FloatCmp_delay.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
- 20 0
- 22 0
- 24 0
- 26 0
- 28 0
- 30 0
- 32 0
- 34 0
- 36 0
- 38 0
- 40 0
- 42 0
- 44 0
- 46 0
- 48 0
- 50 0
- 52 0
- 54 0
- 56 0
- 58 0
- 60 0
- 62 0
- 64 0
- 66 0
- 68 0
- 70 0
- 72 0
- 74 0
- 76 0
- 78 0
- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.ISSUE:FloatCmp_delay.max_value 0
-system.cpu.iq.ISSUE:FloatCmp_delay.end_dist
-
-system.cpu.iq.ISSUE:FloatCvt_delay.start_dist # cycles from operands ready to issue
-system.cpu.iq.ISSUE:FloatCvt_delay.samples 0
-system.cpu.iq.ISSUE:FloatCvt_delay.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
- 20 0
- 22 0
- 24 0
- 26 0
- 28 0
- 30 0
- 32 0
- 34 0
- 36 0
- 38 0
- 40 0
- 42 0
- 44 0
- 46 0
- 48 0
- 50 0
- 52 0
- 54 0
- 56 0
- 58 0
- 60 0
- 62 0
- 64 0
- 66 0
- 68 0
- 70 0
- 72 0
- 74 0
- 76 0
- 78 0
- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.ISSUE:FloatCvt_delay.max_value 0
-system.cpu.iq.ISSUE:FloatCvt_delay.end_dist
-
-system.cpu.iq.ISSUE:FloatMult_delay.start_dist # cycles from operands ready to issue
-system.cpu.iq.ISSUE:FloatMult_delay.samples 0
-system.cpu.iq.ISSUE:FloatMult_delay.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
- 20 0
- 22 0
- 24 0
- 26 0
- 28 0
- 30 0
- 32 0
- 34 0
- 36 0
- 38 0
- 40 0
- 42 0
- 44 0
- 46 0
- 48 0
- 50 0
- 52 0
- 54 0
- 56 0
- 58 0
- 60 0
- 62 0
- 64 0
- 66 0
- 68 0
- 70 0
- 72 0
- 74 0
- 76 0
- 78 0
- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.ISSUE:FloatMult_delay.max_value 0
-system.cpu.iq.ISSUE:FloatMult_delay.end_dist
-
-system.cpu.iq.ISSUE:FloatDiv_delay.start_dist # cycles from operands ready to issue
-system.cpu.iq.ISSUE:FloatDiv_delay.samples 0
-system.cpu.iq.ISSUE:FloatDiv_delay.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
- 20 0
- 22 0
- 24 0
- 26 0
- 28 0
- 30 0
- 32 0
- 34 0
- 36 0
- 38 0
- 40 0
- 42 0
- 44 0
- 46 0
- 48 0
- 50 0
- 52 0
- 54 0
- 56 0
- 58 0
- 60 0
- 62 0
- 64 0
- 66 0
- 68 0
- 70 0
- 72 0
- 74 0
- 76 0
- 78 0
- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.ISSUE:FloatDiv_delay.max_value 0
-system.cpu.iq.ISSUE:FloatDiv_delay.end_dist
-
-system.cpu.iq.ISSUE:FloatSqrt_delay.start_dist # cycles from operands ready to issue
-system.cpu.iq.ISSUE:FloatSqrt_delay.samples 0
-system.cpu.iq.ISSUE:FloatSqrt_delay.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
- 20 0
- 22 0
- 24 0
- 26 0
- 28 0
- 30 0
- 32 0
- 34 0
- 36 0
- 38 0
- 40 0
- 42 0
- 44 0
- 46 0
- 48 0
- 50 0
- 52 0
- 54 0
- 56 0
- 58 0
- 60 0
- 62 0
- 64 0
- 66 0
- 68 0
- 70 0
- 72 0
- 74 0
- 76 0
- 78 0
- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.ISSUE:FloatSqrt_delay.max_value 0
-system.cpu.iq.ISSUE:FloatSqrt_delay.end_dist
-
-system.cpu.iq.ISSUE:MemRead_delay.start_dist # cycles from operands ready to issue
-system.cpu.iq.ISSUE:MemRead_delay.samples 0
-system.cpu.iq.ISSUE:MemRead_delay.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
- 20 0
- 22 0
- 24 0
- 26 0
- 28 0
- 30 0
- 32 0
- 34 0
- 36 0
- 38 0
- 40 0
- 42 0
- 44 0
- 46 0
- 48 0
- 50 0
- 52 0
- 54 0
- 56 0
- 58 0
- 60 0
- 62 0
- 64 0
- 66 0
- 68 0
- 70 0
- 72 0
- 74 0
- 76 0
- 78 0
- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.ISSUE:MemRead_delay.max_value 0
-system.cpu.iq.ISSUE:MemRead_delay.end_dist
-
-system.cpu.iq.ISSUE:MemWrite_delay.start_dist # cycles from operands ready to issue
-system.cpu.iq.ISSUE:MemWrite_delay.samples 0
-system.cpu.iq.ISSUE:MemWrite_delay.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
- 20 0
- 22 0
- 24 0
- 26 0
- 28 0
- 30 0
- 32 0
- 34 0
- 36 0
- 38 0
- 40 0
- 42 0
- 44 0
- 46 0
- 48 0
- 50 0
- 52 0
- 54 0
- 56 0
- 58 0
- 60 0
- 62 0
- 64 0
- 66 0
- 68 0
- 70 0
- 72 0
- 74 0
- 76 0
- 78 0
- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.ISSUE:MemWrite_delay.max_value 0
-system.cpu.iq.ISSUE:MemWrite_delay.end_dist
-
-system.cpu.iq.ISSUE:IprAccess_delay.start_dist # cycles from operands ready to issue
-system.cpu.iq.ISSUE:IprAccess_delay.samples 0
-system.cpu.iq.ISSUE:IprAccess_delay.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
- 20 0
- 22 0
- 24 0
- 26 0
- 28 0
- 30 0
- 32 0
- 34 0
- 36 0
- 38 0
- 40 0
- 42 0
- 44 0
- 46 0
- 48 0
- 50 0
- 52 0
- 54 0
- 56 0
- 58 0
- 60 0
- 62 0
- 64 0
- 66 0
- 68 0
- 70 0
- 72 0
- 74 0
- 76 0
- 78 0
- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.ISSUE:IprAccess_delay.max_value 0
-system.cpu.iq.ISSUE:IprAccess_delay.end_dist
-
-system.cpu.iq.ISSUE:InstPrefetch_delay.start_dist # cycles from operands ready to issue
-system.cpu.iq.ISSUE:InstPrefetch_delay.samples 0
-system.cpu.iq.ISSUE:InstPrefetch_delay.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
- 20 0
- 22 0
- 24 0
- 26 0
- 28 0
- 30 0
- 32 0
- 34 0
- 36 0
- 38 0
- 40 0
- 42 0
- 44 0
- 46 0
- 48 0
- 50 0
- 52 0
- 54 0
- 56 0
- 58 0
- 60 0
- 62 0
- 64 0
- 66 0
- 68 0
- 70 0
- 72 0
- 74 0
- 76 0
- 78 0
- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.ISSUE:InstPrefetch_delay.max_value 0
-system.cpu.iq.ISSUE:InstPrefetch_delay.end_dist
-
-system.cpu.iq.ISSUE:FU_type_0 8388 # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0.start_dist
- (null) 2 0.02% # Type of FU issued
- IntAlu 5594 66.69% # Type of FU issued
- IntMult 1 0.01% # Type of FU issued
- IntDiv 0 0.00% # Type of FU issued
- FloatAdd 2 0.02% # Type of FU issued
- FloatCmp 0 0.00% # Type of FU issued
- FloatCvt 0 0.00% # Type of FU issued
- FloatMult 0 0.00% # Type of FU issued
- FloatDiv 0 0.00% # Type of FU issued
- FloatSqrt 0 0.00% # Type of FU issued
- MemRead 1757 20.95% # Type of FU issued
- MemWrite 1032 12.30% # Type of FU issued
- IprAccess 0 0.00% # Type of FU issued
- InstPrefetch 0 0.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0.end_dist
-system.cpu.iq.ISSUE:fu_busy_cnt 115 # FU busy when requested
-system.cpu.iq.ISSUE:fu_busy_rate 0.013710 # FU busy rate (busy events/executed inst)
-system.cpu.iq.ISSUE:fu_full.start_dist
- (null) 0 0.00% # attempts to use FU when none available
- IntAlu 1 0.87% # attempts to use FU when none available
- IntMult 0 0.00% # attempts to use FU when none available
- IntDiv 0 0.00% # attempts to use FU when none available
- FloatAdd 0 0.00% # attempts to use FU when none available
- FloatCmp 0 0.00% # attempts to use FU when none available
- FloatCvt 0 0.00% # attempts to use FU when none available
- FloatMult 0 0.00% # attempts to use FU when none available
- FloatDiv 0 0.00% # attempts to use FU when none available
- FloatSqrt 0 0.00% # attempts to use FU when none available
- MemRead 76 66.09% # attempts to use FU when none available
- MemWrite 38 33.04% # attempts to use FU when none available
- IprAccess 0 0.00% # attempts to use FU when none available
- InstPrefetch 0 0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full.end_dist
-system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle.samples 6871
-system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
- 0 3753 5462.09%
- 1 894 1301.12%
- 2 723 1052.25%
- 3 614 893.61%
- 4 451 656.38%
- 5 279 406.05%
- 6 104 151.36%
- 7 41 59.67%
- 8 12 17.46%
-system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
-system.cpu.iq.ISSUE:issued_per_cycle.end_dist
-
-system.cpu.iq.ISSUE:rate 1.220783 # Inst issue rate
-system.cpu.iq.iqInstsAdded 9932 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqInstsIssued 8388 # Number of instructions issued
-system.cpu.iq.iqNonSpecInstsAdded 21 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqSquashedInstsExamined 3990 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedInstsIssued 21 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedNonSpecRemoved 4 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.iqSquashedOperandsExamined 2486 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.l2cache.ReadReq_accesses 499 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 2.042254 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency 1015 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate 0.995992 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses 497 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 490 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.981964 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses 490 # number of ReadReq MSHR misses
+system.cpu.idle_fraction 0 # Percentage of idle cycles
+system.cpu.l2cache.ReadReq_accesses 276658 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_avg_miss_latency 3650.746755 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1972.771607 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_hits 108220 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_miss_latency 614924482 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate 0.608831 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses 168438 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency 332289704 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.608831 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses 168438 # number of ReadReq MSHR misses
+system.cpu.l2cache.WriteReqNoAck|Writeback_accesses 147135 # number of WriteReqNoAck|Writeback accesses(hits+misses)
+system.cpu.l2cache.WriteReqNoAck|Writeback_hits 146550 # number of WriteReqNoAck|Writeback hits
+system.cpu.l2cache.WriteReqNoAck|Writeback_miss_rate 0.003976 # miss rate for WriteReqNoAck|Writeback accesses
+system.cpu.l2cache.WriteReqNoAck|Writeback_misses 585 # number of WriteReqNoAck|Writeback misses
+system.cpu.l2cache.WriteReqNoAck|Writeback_mshr_miss_rate 0.003976 # mshr miss rate for WriteReqNoAck|Writeback accesses
+system.cpu.l2cache.WriteReqNoAck|Writeback_mshr_misses 585 # number of WriteReqNoAck|Writeback MSHR misses
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs 0.004024 # Average number of references to valid blocks.
+system.cpu.l2cache.avg_refs 1.512545 # Average number of references to valid blocks.
system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.demand_accesses 499 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 2.042254 # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 1 # average overall mshr miss latency
-system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 1015 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate 0.995992 # miss rate for demand accesses
-system.cpu.l2cache.demand_misses 497 # number of demand (read+write) misses
+system.cpu.l2cache.demand_accesses 276658 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_avg_miss_latency 3650.746755 # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 1972.771607 # average overall mshr miss latency
+system.cpu.l2cache.demand_hits 108220 # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency 614924482 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate 0.608831 # miss rate for demand accesses
+system.cpu.l2cache.demand_misses 168438 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency 490 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate 0.981964 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses 490 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_miss_latency 332289704 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate 0.608831 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses 168438 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.overall_accesses 499 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 2.042254 # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 1 # average overall mshr miss latency
+system.cpu.l2cache.overall_accesses 423793 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_avg_miss_latency 3638.111275 # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 1972.771607 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits 2 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 1015 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate 0.995992 # miss rate for overall accesses
-system.cpu.l2cache.overall_misses 497 # number of overall misses
+system.cpu.l2cache.overall_hits 254770 # number of overall hits
+system.cpu.l2cache.overall_miss_latency 614924482 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate 0.398834 # miss rate for overall accesses
+system.cpu.l2cache.overall_misses 169023 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 490 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate 0.981964 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses 490 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_miss_latency 332289704 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate 0.397453 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses 168438 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@@ -1946,29 +204,17 @@ system.cpu.l2cache.prefetcher.num_hwpf_issued 0
system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.l2cache.replacements 0 # number of replacements
-system.cpu.l2cache.sampled_refs 497 # Sample count of references to valid blocks.
+system.cpu.l2cache.replacements 135670 # number of replacements
+system.cpu.l2cache.sampled_refs 168438 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 295.773395 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks 0 # number of writebacks
-system.cpu.numCycles 6871 # number of cpu cycles simulated
-system.cpu.rename.RENAME:BlockCycles 4 # Number of cycles rename is blocking
-system.cpu.rename.RENAME:CommittedMaps 4051 # Number of HB maps that are committed
-system.cpu.rename.RENAME:IdleCycles 3758 # Number of cycles rename is idle
-system.cpu.rename.RENAME:LSQFullEvents 62 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RENAME:RenameLookups 14786 # Number of register rename lookups that rename has made
-system.cpu.rename.RENAME:RenamedInsts 11555 # Number of instructions processed by rename
-system.cpu.rename.RENAME:RenamedOperands 8634 # Number of destination operands rename has renamed
-system.cpu.rename.RENAME:RunCycles 1975 # Number of cycles rename is running
-system.cpu.rename.RENAME:SquashCycles 754 # Number of cycles rename is squashing
-system.cpu.rename.RENAME:UnblockCycles 111 # Number of cycles rename is unblocking
-system.cpu.rename.RENAME:UndoneMaps 4583 # Number of HB maps that are undone due to squashing
-system.cpu.rename.RENAME:serializeStallCycles 269 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RENAME:serializingInsts 26 # count of serializing insts renamed
-system.cpu.rename.RENAME:skidInsts 408 # count of insts added to the skid buffer
-system.cpu.rename.RENAME:tempSerializingInsts 21 # count of temporary serializing insts renamed
-system.cpu.workload.PROG:num_syscalls 17 # Number of system calls
+system.cpu.l2cache.tagsinuse 30358.430189 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 254770 # Total number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle 475381000 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.writebacks 115647 # number of writebacks
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.numCycles 1207510003 # number of cpu cycles simulated
+system.cpu.num_insts 88361899 # Number of instructions executed
+system.cpu.num_refs 35229376 # Number of memory references
+system.cpu.workload.PROG:num_syscalls 4706 # Number of system calls
---------- End Simulation Statistics ----------
diff --git a/tests/long/50.vortex/ref/alpha/linux/simple-timing/smred.msg b/tests/long/50.vortex/ref/alpha/linux/simple-timing/smred.msg
new file mode 100644
index 000000000..327142d7c
--- /dev/null
+++ b/tests/long/50.vortex/ref/alpha/linux/simple-timing/smred.msg
@@ -0,0 +1,158 @@
+
+ SYSTEM TYPE...
+ __ZTC__ := False
+ __UNIX__ := True
+ __RISC__ := True
+ SPEC_CPU2000_LP64 := True
+ __MAC__ := False
+ __BCC__ := False
+ __BORLANDC__ := False
+ __GUI__ := False
+ __WTC__ := False
+ __HP__ := False
+
+ CODE OPTIONS...
+ __MACROIZE_HM__ := True
+ __MACROIZE_MEM__ := True
+ ENV01 := True
+ USE_HPP_STYPE_HDRS := False
+ USE_H_STYPE_HDRS := False
+
+ CODE INCLUSION PARAMETERS...
+ INCLUDE_ALL_CODE := False
+ INCLUDE_DELETE_CODE := True
+ __SWAP_GRP_POS__ := True
+ __INCLUDE_MTRX__ := False
+ __BAD_CODE__ := False
+ API_INCLUDE := False
+ BE_CAREFUL := False
+ OLDWAY := False
+ NOTUSED := False
+
+ SYSTEM PARAMETERS...
+ EXT_ENUM := 999999999L
+ CHUNK_CONSTANT := 55555555
+ CORE_CONSTANT := 55555555
+ CORE_LIMIT := 20971520
+ CorePage_Size := 384000
+ ALIGN_BYTES := True
+ CORE_BLOCK_ALIGN := 8
+ FAR_MEM := False
+
+ MEMORY MANAGEMENT PARAMETERS...
+ SYSTEM_ALLOC := True
+ SYSTEM_FREESTORE := True
+ __NO_DISKCACHE__ := False
+ __FREEZE_VCHUNKS__ := True
+ __FREEZE_GRP_PACKETS__ := True
+ __MINIMIZE_TREE_CACHE__:= True
+
+ SYSTEM STD PARAMETERS...
+ __STDOUT__ := False
+ NULL := 0
+ LPTR := False
+ False_Status := 1
+ True_Status := 0
+ LARGE := True
+ TWOBYTE_BOOL := False
+ __NOSTR__ := False
+
+ MEMORY VALIDATION PARAMETERS...
+ CORE_CRC_CHECK := False
+ VALIDATE_MEM_CHUNKS := False
+
+ SYSTEM DEBUG OPTIONS...
+ DEBUG := False
+ MCSTAT := False
+ TRACKBACK := False
+ FLUSH_FILES := False
+ DEBUG_CORE0 := False
+ DEBUG_RISC := False
+ __TREE_BUG__ := False
+ __TRACK_FILE_READS__ := False
+ PAGE_SPACE := False
+ LEAVE_NO_TRACE := True
+ NULL_TRACE_STRS := False
+
+ TIME PARAMETERS...
+ CLOCK_IS_LONG := False
+ __DISPLAY_TIME__ := False
+ __TREE_TIME__ := False
+ __DISPLAY_ERRORS__ := False
+
+ API MACROS...
+ __BMT01__ := True
+ OPTIMIZE := True
+
+ END OF DEFINES.
+
+
+
+ ... IMPLODE MEMORY ...
+
+ SWAP to DiskCache := False
+
+ FREEZE_GRP_PACKETS:= True
+
+ QueBug := 1000
+
+ sizeof(boolean) = 4
+ sizeof(sizetype) = 4
+ sizeof(chunkstruc) = 32
+
+ sizeof(shorttype ) = 2
+ sizeof(idtype ) = 2
+ sizeof(sizetype ) = 4
+ sizeof(indextype ) = 4
+ sizeof(numtype ) = 4
+ sizeof(handletype) = 4
+ sizeof(tokentype ) = 8
+
+ sizeof(short ) = 2
+ sizeof(int ) = 4
+
+ sizeof(lt64 ) = 4
+ sizeof(farlongtype) = 4
+ sizeof(long ) = 8
+ sizeof(longaddr ) = 8
+
+ sizeof(float ) = 4
+ sizeof(double ) = 8
+
+ sizeof(addrtype ) = 8
+ sizeof(char * ) = 8
+ ALLOC CORE_1 :: 16
+ BHOOLE NATH
+
+ OPEN File ./input/lendian.rnv
+ *Status = 0
+ DB HDR restored from FileVbn[ 0]
+ DB BlkDirOffset : @ 2030c0
+ DB BlkDirChunk : Chunk[ 10] AT Vbn[3146]
+ DB BlkTknChunk : Chunk[ 11] AT Vbn[3147]
+ DB BlkSizeChunk : Chunk[ 12] AT Vbn[3148]
+ DB Handle Chunk's StackPtr = 20797
+
+ DB[ 1] LOADED; Handles= 20797
+ KERNEL in CORE[ 1] Restored @ 40054800
+
+ OPEN File ./input/lendian.wnv
+ *Status = 0
+ DB HDR restored from FileVbn[ 0]
+ DB BlkDirOffset : @ 21c40
+ DB BlkDirChunk : Chunk[ 31] AT Vbn[ 81]
+ DB BlkTknChunk : Chunk[ 32] AT Vbn[ 82]
+ DB BlkSizeChunk : Chunk[ 33] AT Vbn[ 83]
+ DB Handle Chunk's StackPtr = 17
+
+ DB[ 2] LOADED; Handles= 17
+ VORTEx_Status == -8 || fffffff8
+
+ BE HERE NOW !!!
+
+
+
+ ... VORTEx ON LINE ...
+
+
+ ... END OF SESSION ...
diff --git a/tests/long/50.vortex/ref/alpha/linux/simple-timing/smred.out b/tests/long/50.vortex/ref/alpha/linux/simple-timing/smred.out
new file mode 100644
index 000000000..726b45c60
--- /dev/null
+++ b/tests/long/50.vortex/ref/alpha/linux/simple-timing/smred.out
@@ -0,0 +1,258 @@
+ CREATE Db Header and Db Primal ...
+ NEW DB [ 3] Created.
+
+VORTEX INPUT PARAMETERS::
+ MESSAGE FileName: smred.msg
+ OUTPUT FileName: smred.out
+ DISK CACHE FileName: NULL
+ PART DB FileName: parts.db
+ DRAW DB FileName: draw.db
+ PERSON DB FileName: emp.db
+ PERSONS Data FileName: ./input/persons.250
+ PARTS Count : 100
+ OUTER Loops : 1
+ INNER Loops : 1
+ LOOKUP Parts : 25
+ DELETE Parts : 10
+ STUFF Parts : 10
+ DEPTH Traverse: 5
+ % DECREASE Parts : 0
+ % INCREASE LookUps : 0
+ % INCREASE Deletes : 0
+ % INCREASE Stuffs : 0
+ FREEZE_PACKETS : 1
+ ALLOC_CHUNKS : 10000
+ EXTEND_CHUNKS : 5000
+ DELETE Draw objects : True
+ DELETE Part objects : False
+ QUE_BUG : 1000
+ VOID_BOUNDARY : 67108864
+ VOID_RESERVE : 1048576
+
+ COMMIT_DBS : False
+
+
+
+ BMT TEST :: files...
+ EdbName := PartLib
+ EdbFileName := parts.db
+ DrwName := DrawLib
+ DrwFileName := draw.db
+ EmpName := PersonLib
+ EmpFileName := emp.db
+
+ Swap to DiskCache := False
+ Freeze the cache := True
+
+
+ BMT TEST :: parms...
+ DeBug modulo := 1000
+ Create Parts count:= 100
+ Outer Loops := 1
+ Inner Loops := 1
+ Look Ups := 25
+ Delete Parts := 10
+ Stuff Parts := 10
+ Traverse Limit := 5
+ Delete Draws := True
+ Delete Parts := False
+ Delete ALL Parts := after every <mod 0>Outer Loop
+
+ INITIALIZE LIBRARY ::
+
+ INITIALIZE SCHEMA ::
+ Primal_CreateDb Accessed !!!
+ CREATE Db Header and Db Primal ...
+ NEW DB [ 4] Created.
+ PartLibCreate:: Db[ 4]; VpartsDir= 1
+
+ Part Count= 1
+
+ Initialize the Class maps
+ LIST HEADS loaded ... DbListHead_Class = 207
+ DbListNode_Class = 206
+
+...NOTE... ShellLoadCode:: Class[ 228] will NOT be Activated.
+
+
+...NOTE... ShellLoadCode:: Class[ 229] will NOT be Activated.
+
+ Primal_CreateDb Accessed !!!
+ CREATE Db Header and Db Primal ...
+ NEW DB [ 5] Created.
+ DrawLibCreate:: Db[ 5]; VpartsDir= 1
+
+ Initialize the Class maps of this schema.
+ Primal_CreateDb Accessed !!!
+ CREATE Db Header and Db Primal ...
+ NEW DB [ 6] Created.
+
+ ***NOTE*** Persons Library Extended!
+
+ Create <131072> Persons.
+ ItNum 0. Person[ 6: 5]. Name= Riddell , Robert V. ;
+
+ LAST Person Read::
+ ItNum 250. Person[ 6: 503]. Name= Gonzales , Warren X. ;
+
+ BUILD <Query0> for <Part2> class::
+
+ if (link[1].length >= 5) ::
+
+ Build Query2 for <Address> class::
+
+ if (State == CA || State == T*)
+
+ Build Query1 for <Person> class::
+
+ if (LastName >= H* && LastName <= P* && Query0(Residence)) ::
+
+ BUILD <Query3> for <DrawObj> class::
+
+ if (Id >= 3000
+ && (Id >= 3000 && Id <= 3001)
+ && Id >= 3002)
+
+ BUILD <Query4> for <NamedDrawObj> class::
+
+ if (Nam == Pre*
+ || (Nam == ??Mid??? || == Pre??Mid?? || == ??Post
+ || == Pre??Post || == ??Mid???Post || == Pre??Mid???Post)
+ && Id <= 7)
+ SEED := 1008; Swap = False; RgnEntries = 135
+
+ OUTER LOOP [ 1] : NewParts = 100 LookUps = 25 StuffParts = 10.
+
+ Create 100 New Parts
+ Create Part 1. Token[ 4: 2].
+
+ < 100> Parts Created. CurrentId= 100
+
+ Connect each instantiated Part TO 3 unique Parts
+ Connect Part 1. Token[ 4: 2]
+ Connect Part 25. Token[ 4: 26] FromList= 26.
+ Connect Part 12. Token[ 4: 13] FromList= 13.
+ Connect Part 59. Token[ 4: 60] FromList= 60.
+
+ SET <DrawObjs> entries::
+ 1. [ 5: 5] := <1 >; @[: 6]
+ Iteration count = 100
+
+ SET <NamedDrawObjs> entries::
+ 1. [ 5: 39] := <14 >;
+ Iteration count = 12
+
+ SET <LibRectangles> entries::
+ 1. [ 5: 23] := <8 >; @[: 24]
+ Iteration count = 12
+
+ LIST <DbRectangles> entries::
+ 1. [ 5: 23]
+ Iteration count = 12
+
+ SET <PersonNames > entries::
+ Iteration count = 250
+
+ COMMIT All Image copies:: Release=<True>; Max Parts= 100
+ < 100> Part images' Committed.
+ < 0> are Named.
+ < 50> Point images' Committed.
+ < 81> Person images' Committed.
+
+ COMMIT Parts(* 100)
+
+ Commit TestObj_Class in <Primal> DB.
+ ItNum 0. Token[ 0: 0]. TestObj Committed.
+ < 0> TestObj images' Committed.
+
+ Commit CartesianPoint_Class in <Primal> DB.
+ ItNum 0. Token[ 0: 0]. CartesianPoint Committed.
+ < 0> CartesianPoint images' Committed.
+
+ BEGIN Inner Loop Sequence::.
+
+ INNER LOOP [ 1: 1] :
+
+ LOOK UP 25 Random Parts and Export each Part.
+
+ LookUp for 26 parts; Asserts = 8
+ <Part2 > Asserts = 2; NULL Asserts = 3.
+ <DrawObj > Asserts = 0; NULL Asserts = 5.
+ <NamedObj > Asserts = 0; NULL Asserts = 0.
+ <Person > Asserts = 0; NULL Asserts = 5.
+ <TestObj > Asserts = 60; NULL Asserts = 0.
+
+ DELETE 10 Random Parts.
+
+ PartDelete :: Token[ 4: 91].
+ PartDisconnect:: Token[ 4: 91] id:= 90 for each link.
+ DisConnect link [ 0]:= 50; PartToken[ 51: 51].
+ DisConnect link [ 1]:= 17; PartToken[ 18: 18].
+ DisConnect link [ 2]:= 72; PartToken[ 73: 73].
+ DeleteFromList:: Vchunk[ 4: 91]. (* 1)
+ DisConnect FromList[ 0]:= 56; Token[ 57: 57].
+ Vlists[ 89] := 100;
+
+ Delete for 11 parts;
+
+ Traverse Count= 0
+
+ TRAVERSE PartId[ 6] and all Connections to 5 Levels
+ SEED In Traverse Part [ 4: 65] @ Level = 4.
+
+ Traverse Count= 357
+ Traverse Asserts = 5. True Tests = 1
+ < 5> DrawObj objects DELETED.
+ < 2> are Named.
+ < 2> Point objects DELETED.
+
+ CREATE 10 Additional Parts
+
+ Create 10 New Parts
+ Create Part 101. Token[ 4: 102].
+
+ < 10> Parts Created. CurrentId= 110
+
+ Connect each instantiated Part TO 3 unique Parts
+
+ COMMIT All Image copies:: Release=<True>; Max Parts= 110
+ < 81> Part images' Committed.
+ < 0> are Named.
+ < 38> Point images' Committed.
+ < 31> Person images' Committed.
+
+ COMMIT Parts(* 100)
+
+ Commit TestObj_Class in <Primal> DB.
+ ItNum 0. Token[ 3: 4]. TestObj Committed.
+ < 15> TestObj images' Committed.
+
+ Commit CartesianPoint_Class in <Primal> DB.
+ ItNum 0. Token[ 3: 3]. CartesianPoint Committed.
+ < 16> CartesianPoint images' Committed.
+
+ DELETE All TestObj objects;
+
+ Delete TestObj_Class in <Primal> DB.
+ ItNum 0. Token[ 3: 4]. TestObj Deleted.
+ < 15> TestObj objects Deleted.
+
+ Commit CartesianPoint_Class in <Primal> DB.
+ ItNum 0. Token[ 3: 3]. CartesianPoint Deleted.
+ < 16> CartesianPoint objects Deleted.
+
+ DELETE TestObj and Point objects...
+
+ END INNER LOOP [ 1: 1].
+
+ DELETE All TestObj objects;
+
+ Delete TestObj_Class in <Primal> DB.
+ < 0> TestObj objects Deleted.
+
+ Commit CartesianPoint_Class in <Primal> DB.
+ < 0> CartesianPoint objects Deleted.
+
+ DELETE TestObj and Point objects...
+ STATUS= -201
+V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!
diff --git a/tests/long/50.vortex/ref/alpha/linux/simple-timing/stderr b/tests/long/50.vortex/ref/alpha/linux/simple-timing/stderr
index 8893caac8..87866a2a5 100644
--- a/tests/long/50.vortex/ref/alpha/linux/simple-timing/stderr
+++ b/tests/long/50.vortex/ref/alpha/linux/simple-timing/stderr
@@ -1,3 +1 @@
warn: Entering event queue @ 0. Starting simulation...
-warn: cycle 0: fault (page_table_fault) detected @ PC 0x000000
-warn: Increasing stack 0x11ff92000:0x11ff9b000 to 0x11ff90000:0x11ff9b000 because of access to 0x11ff91ff0
diff --git a/tests/long/50.vortex/ref/alpha/linux/simple-timing/stdout b/tests/long/50.vortex/ref/alpha/linux/simple-timing/stdout
index fbb329a2f..e69de29bb 100644
--- a/tests/long/50.vortex/ref/alpha/linux/simple-timing/stdout
+++ b/tests/long/50.vortex/ref/alpha/linux/simple-timing/stdout
@@ -1,13 +0,0 @@
-Hello world!
-M5 Simulator System
-
-Copyright (c) 2001-2006
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Sep 5 2006 15:28:48
-M5 started Tue Sep 5 15:42:12 2006
-M5 executing on zizzer.eecs.umich.edu
-command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/o3-timing tests/run.py quick/00.hello/alpha/linux/o3-timing
-Exiting @ tick 6870 because target called exit()
diff --git a/tests/long/60.bzip2/ref/alpha/linux/o3-timing/config.ini b/tests/long/60.bzip2/ref/alpha/linux/o3-timing/config.ini
index c3a59fbce..7a3bd9383 100644
--- a/tests/long/60.bzip2/ref/alpha/linux/o3-timing/config.ini
+++ b/tests/long/60.bzip2/ref/alpha/linux/o3-timing/config.ini
@@ -7,11 +7,9 @@ max_tick=0
output_file=cout
progress_interval=0
-[debug]
-break_cycles=
-
[exetrace]
intel_format=false
+legion_lockstep=false
pc_symbol=true
print_cpseq=false
print_cycle=true
@@ -102,14 +100,15 @@ max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
-mem=system.cpu.dcache
numIQEntries=64
numPhysFloatRegs=256
numPhysIntRegs=256
numROBEntries=192
numRobs=1
numThreads=1
+phase=0
predType=tournament
+progress_interval=0
renameToDecodeDelay=1
renameToFetchDelay=1
renameToIEWDelay=2
@@ -131,7 +130,6 @@ assoc=2
block_size=64
compressed_bus=false
compression_latency=0
-do_copy=false
hash_delay=1
hit_latency=1
latency=1
@@ -308,7 +306,6 @@ assoc=2
block_size=64
compressed_bus=false
compression_latency=0
-do_copy=false
hash_delay=1
hit_latency=1
latency=1
@@ -348,7 +345,6 @@ assoc=2
block_size=64
compressed_bus=false
compression_latency=0
-do_copy=false
hash_delay=1
hit_latency=1
latency=1
@@ -384,20 +380,33 @@ mem_side=system.membus.port[1]
[system.cpu.toL2Bus]
type=Bus
bus_id=0
+clock=1000
+responder_set=false
+width=64
port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
[system.cpu.workload]
type=LiveProcess
-cmd=hello
+cmd=bzip2 input.source 1
+cwd=build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/linux/o3-timing
+egid=100
env=
-executable=tests/test-progs/hello/bin/alpha/linux/hello
+euid=100
+executable=/dist/m5/cpu2000/binaries/alpha/tru64/bzip2
+gid=100
input=cin
output=cout
+pid=100
+ppid=99
system=system
+uid=100
[system.membus]
type=Bus
bus_id=0
+clock=1000
+responder_set=false
+width=64
port=system.physmem.port system.cpu.l2cache.mem_side
[system.physmem]
@@ -409,6 +418,7 @@ port=system.membus.port[0]
[trace]
bufsize=0
+cycle=0
dump_on_exit=false
file=cout
flags=
diff --git a/tests/long/60.bzip2/ref/alpha/linux/o3-timing/config.out b/tests/long/60.bzip2/ref/alpha/linux/o3-timing/config.out
index f491a3081..1077b5dd7 100644
--- a/tests/long/60.bzip2/ref/alpha/linux/o3-timing/config.out
+++ b/tests/long/60.bzip2/ref/alpha/linux/o3-timing/config.out
@@ -19,54 +19,25 @@ mem_mode=atomic
[system.membus]
type=Bus
bus_id=0
+clock=1000
+width=64
+responder_set=false
[system.cpu.workload]
type=LiveProcess
-cmd=hello
-executable=tests/test-progs/hello/bin/alpha/linux/hello
+cmd=bzip2 input.source 1
+executable=/dist/m5/cpu2000/binaries/alpha/tru64/bzip2
input=cin
output=cout
env=
+cwd=build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/linux/o3-timing
system=system
-
-[system.cpu.dcache]
-type=BaseCache
-size=262144
-assoc=2
-block_size=64
-latency=1
-mshrs=10
-tgts_per_mshr=5
-write_buffers=8
-prioritizeRequests=false
-do_copy=false
-protocol=null
-trace_addr=0
-hash_delay=1
-repl=null
-compressed_bus=false
-store_compressed=false
-adaptive_compression=false
-compression_latency=0
-block_size=64
-max_miss_count=0
-addr_range=[0,18446744073709551615]
-split=false
-split_size=0
-lifo=false
-two_queue=false
-prefetch_miss=false
-prefetch_access=false
-prefetcher_size=100
-prefetch_past_page=false
-prefetch_serial_squash=false
-prefetch_latency=10
-prefetch_degree=1
-prefetch_policy=none
-prefetch_cache_check_push=true
-prefetch_use_cpu_id=true
-prefetch_data_accesses_only=false
-hit_latency=1
+uid=100
+euid=100
+gid=100
+egid=100
+pid=100
+ppid=99
[system.cpu.fuPool.FUList0.opList0]
type=OpDesc
@@ -199,15 +170,16 @@ FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUL
[system.cpu]
type=DerivO3CPU
clock=1
+phase=0
numThreads=1
activity=0
workload=system.cpu.workload
-mem=system.cpu.dcache
checker=null
max_insts_any_thread=0
max_insts_all_threads=0
max_loads_any_thread=0
max_loads_all_threads=0
+progress_interval=0
cachePorts=200
decodeToFetchDelay=1
renameToFetchDelay=1
@@ -283,7 +255,44 @@ mshrs=10
tgts_per_mshr=5
write_buffers=8
prioritizeRequests=false
-do_copy=false
+protocol=null
+trace_addr=0
+hash_delay=1
+repl=null
+compressed_bus=false
+store_compressed=false
+adaptive_compression=false
+compression_latency=0
+block_size=64
+max_miss_count=0
+addr_range=[0,18446744073709551615]
+split=false
+split_size=0
+lifo=false
+two_queue=false
+prefetch_miss=false
+prefetch_access=false
+prefetcher_size=100
+prefetch_past_page=false
+prefetch_serial_squash=false
+prefetch_latency=10
+prefetch_degree=1
+prefetch_policy=none
+prefetch_cache_check_push=true
+prefetch_use_cpu_id=true
+prefetch_data_accesses_only=false
+hit_latency=1
+
+[system.cpu.dcache]
+type=BaseCache
+size=262144
+assoc=2
+block_size=64
+latency=1
+mshrs=10
+tgts_per_mshr=5
+write_buffers=8
+prioritizeRequests=false
protocol=null
trace_addr=0
hash_delay=1
@@ -322,7 +331,6 @@ mshrs=10
tgts_per_mshr=5
write_buffers=8
prioritizeRequests=false
-do_copy=false
protocol=null
trace_addr=0
hash_delay=1
@@ -354,10 +362,14 @@ hit_latency=1
[system.cpu.toL2Bus]
type=Bus
bus_id=0
+clock=1000
+width=64
+responder_set=false
[trace]
flags=
start=0
+cycle=0
bufsize=0
file=cout
dump_on_exit=false
@@ -396,8 +408,9 @@ print_cpseq=false
print_reg_delta=false
pc_symbol=true
intel_format=false
+legion_lockstep=false
trace_system=client
-[debug]
-break_cycles=
+[statsreset]
+reset_cycle=0
diff --git a/tests/long/60.bzip2/ref/alpha/linux/o3-timing/m5stats.txt b/tests/long/60.bzip2/ref/alpha/linux/o3-timing/m5stats.txt
index 5d4f9235a..73d6efd18 100644
--- a/tests/long/60.bzip2/ref/alpha/linux/o3-timing/m5stats.txt
+++ b/tests/long/60.bzip2/ref/alpha/linux/o3-timing/m5stats.txt
@@ -1,112 +1,112 @@
---------- Begin Simulation Statistics ----------
global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-global.BPredUnit.BTBHits 542 # Number of BTB hits
-global.BPredUnit.BTBLookups 1938 # Number of BTB lookups
-global.BPredUnit.RASInCorrect 48 # Number of incorrect RAS predictions.
-global.BPredUnit.condIncorrect 420 # Number of conditional branches incorrect
-global.BPredUnit.condPredicted 1304 # Number of conditional branches predicted
-global.BPredUnit.lookups 2256 # Number of BP lookups
-global.BPredUnit.usedRAS 291 # Number of times the RAS was used to get a target.
-host_inst_rate 41797 # Simulator instruction rate (inst/s)
-host_mem_usage 160344 # Number of bytes of host memory used
-host_seconds 0.13 # Real time elapsed on the host
-host_tick_rate 50948 # Simulator tick rate (ticks/s)
-memdepunit.memDep.conflictingLoads 12 # Number of conflicting loads.
-memdepunit.memDep.conflictingStores 259 # Number of conflicting stores.
-memdepunit.memDep.insertedLoads 2050 # Number of loads inserted to the mem dependence unit.
-memdepunit.memDep.insertedStores 1221 # Number of stores inserted to the mem dependence unit.
+global.BPredUnit.BTBHits 1060300638 # Number of BTB hits
+global.BPredUnit.BTBLookups 1075264664 # Number of BTB lookups
+global.BPredUnit.RASInCorrect 132 # Number of incorrect RAS predictions.
+global.BPredUnit.condIncorrect 20658855 # Number of conditional branches incorrect
+global.BPredUnit.condPredicted 1028649695 # Number of conditional branches predicted
+global.BPredUnit.lookups 1098978166 # Number of BP lookups
+global.BPredUnit.usedRAS 20738311 # Number of times the RAS was used to get a target.
+host_inst_rate 27542 # Simulator instruction rate (inst/s)
+host_mem_usage 1254844 # Number of bytes of host memory used
+host_seconds 63032.08 # Real time elapsed on the host
+host_tick_rate 395232 # Simulator tick rate (ticks/s)
+memdepunit.memDep.conflictingLoads 114920109 # Number of conflicting loads.
+memdepunit.memDep.conflictingStores 60881817 # Number of conflicting stores.
+memdepunit.memDep.insertedLoads 938731548 # Number of loads inserted to the mem dependence unit.
+memdepunit.memDep.insertedStores 389309694 # Number of stores inserted to the mem dependence unit.
sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 5623 # Number of instructions simulated
-sim_seconds 0.000000 # Number of seconds simulated
-sim_ticks 6870 # Number of ticks simulated
-system.cpu.commit.COM:branches 862 # Number of branches committed
-system.cpu.commit.COM:bw_lim_events 74 # number cycles where commit BW limit reached
+sim_insts 1736043781 # Number of instructions simulated
+sim_seconds 0.024912 # Number of seconds simulated
+sim_ticks 24912272090 # Number of ticks simulated
+system.cpu.commit.COM:branches 214632552 # Number of branches committed
+system.cpu.commit.COM:bw_lim_events 72343657 # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle.samples 6116
+system.cpu.commit.COM:committed_per_cycle.samples 5678957793
system.cpu.commit.COM:committed_per_cycle.min_value 0
- 0 3908 6389.80%
- 1 1064 1739.70%
- 2 389 636.04%
- 3 210 343.36%
- 4 153 250.16%
- 5 93 152.06%
- 6 76 124.26%
- 7 149 243.62%
- 8 74 120.99%
+ 0 5103057521 8985.90%
+ 1 193842571 341.33%
+ 2 126727829 223.15%
+ 3 63255233 111.39%
+ 4 47590442 83.80%
+ 5 34302037 60.40%
+ 6 22774532 40.10%
+ 7 15063971 26.53%
+ 8 72343657 127.39%
system.cpu.commit.COM:committed_per_cycle.max_value 8
system.cpu.commit.COM:committed_per_cycle.end_dist
-system.cpu.commit.COM:count 5640 # Number of instructions committed
-system.cpu.commit.COM:loads 979 # Number of loads committed
+system.cpu.commit.COM:count 1819780126 # Number of instructions committed
+system.cpu.commit.COM:loads 445666361 # Number of loads committed
system.cpu.commit.COM:membars 0 # Number of memory barriers committed
-system.cpu.commit.COM:refs 1791 # Number of memory references committed
+system.cpu.commit.COM:refs 606571343 # Number of memory references committed
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.branchMispredicts 337 # The number of times a branch was mispredicted
-system.cpu.commit.commitCommittedInsts 5640 # The number of committed instructions
-system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.commitSquashedInsts 4350 # The number of squashed insts skipped by commit
-system.cpu.committedInsts 5623 # Number of Instructions Simulated
-system.cpu.committedInsts_total 5623 # Number of Instructions Simulated
-system.cpu.cpi 1.221768 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 1.221768 # CPI: Total CPI of All Threads
-system.cpu.dcache.ReadReq_accesses 1538 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 3.072000 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2.240000 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits 1413 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 384 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate 0.081274 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses 125 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_hits 25 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_miss_latency 224 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate 0.065020 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses 100 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_accesses 821 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 2.467742 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2.140845 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 635 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 459 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.226553 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 186 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_hits 108 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_miss_latency 152 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.086480 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 71 # number of WriteReq MSHR misses
-system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles_no_targets 0.800000 # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 11.505618 # Average number of references to valid blocks.
-system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_no_targets 5 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles_no_targets 4 # number of cycles access was blocked
+system.cpu.commit.branchMispredicts 20658355 # The number of times a branch was mispredicted
+system.cpu.commit.commitCommittedInsts 1819780126 # The number of committed instructions
+system.cpu.commit.commitNonSpecStalls 29 # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.commitSquashedInsts 3012390712 # The number of squashed insts skipped by commit
+system.cpu.committedInsts 1736043781 # Number of Instructions Simulated
+system.cpu.committedInsts_total 1736043781 # Number of Instructions Simulated
+system.cpu.cpi 14.350025 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 14.350025 # CPI: Total CPI of All Threads
+system.cpu.dcache.ReadReq_accesses 466176479 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 5764.172372 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 5678.042412 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits 454097633 # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency 69624550394 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate 0.025910 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses 12078846 # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_hits 4784670 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_miss_latency 41416640690 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate 0.015647 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_misses 7294176 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_accesses 160728502 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_avg_miss_latency 11148.179412 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 14223.476157 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits 157574910 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 35156809407 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate 0.019621 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses 3153592 # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_hits 1270515 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_miss_latency 26783900812 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.011716 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses 1883077 # number of WriteReq MSHR misses
+system.cpu.dcache.avg_blocked_cycles_no_mshrs 972.020892 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles_no_targets 2881.979981 # average number of cycles each access was blocked
+system.cpu.dcache.avg_refs 66.650940 # Average number of references to valid blocks.
+system.cpu.dcache.blocked_no_mshrs 659829 # number of cycles access was blocked
+system.cpu.dcache.blocked_no_targets 896062 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles_no_mshrs 641367573 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles_no_targets 2582432746 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.demand_accesses 2359 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 2.710611 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 2.198830 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 2048 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 843 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.131836 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 311 # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits 133 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 376 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate 0.072488 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 171 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_accesses 626904981 # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency 6878.830546 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 7431.476663 # average overall mshr miss latency
+system.cpu.dcache.demand_hits 611672543 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 104781359801 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate 0.024298 # miss rate for demand accesses
+system.cpu.dcache.demand_misses 15232438 # number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits 6055185 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency 68200541502 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate 0.014639 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses 9177253 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.overall_accesses 2359 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 2.710611 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 2.198830 # average overall mshr miss latency
+system.cpu.dcache.overall_accesses 626904981 # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency 6878.830546 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 7431.476663 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 2048 # number of overall hits
-system.cpu.dcache.overall_miss_latency 843 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.131836 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 311 # number of overall misses
-system.cpu.dcache.overall_mshr_hits 133 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 376 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate 0.072488 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 171 # number of overall MSHR misses
+system.cpu.dcache.overall_hits 611672543 # number of overall hits
+system.cpu.dcache.overall_miss_latency 104781359801 # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate 0.024298 # miss rate for overall accesses
+system.cpu.dcache.overall_misses 15232438 # number of overall misses
+system.cpu.dcache.overall_mshr_hits 6055185 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_miss_latency 68200541502 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate 0.014639 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses 9177253 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@@ -118,92 +118,92 @@ system.cpu.dcache.prefetcher.num_hwpf_issued 0
system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.dcache.replacements 0 # number of replacements
-system.cpu.dcache.sampled_refs 178 # Sample count of references to valid blocks.
+system.cpu.dcache.replacements 9173157 # number of replacements
+system.cpu.dcache.sampled_refs 9177253 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 119.831029 # Cycle average of tags in use
-system.cpu.dcache.total_refs 2048 # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks 0 # number of writebacks
-system.cpu.decode.DECODE:BlockedCycles 387 # Number of cycles decode is blocked
-system.cpu.decode.DECODE:BranchMispred 93 # Number of times decode detected a branch misprediction
-system.cpu.decode.DECODE:BranchResolved 185 # Number of times decode resolved a branch
-system.cpu.decode.DECODE:DecodedInsts 12349 # Number of instructions handled by decode
-system.cpu.decode.DECODE:IdleCycles 3542 # Number of cycles decode is idle
-system.cpu.decode.DECODE:RunCycles 2158 # Number of cycles decode is running
-system.cpu.decode.DECODE:SquashCycles 754 # Number of cycles decode is squashing
-system.cpu.decode.DECODE:SquashedInsts 286 # Number of squashed instructions handled by decode
-system.cpu.decode.DECODE:UnblockCycles 30 # Number of cycles decode is unblocking
-system.cpu.fetch.Branches 2256 # Number of branches that fetch encountered
-system.cpu.fetch.CacheLines 1582 # Number of cache lines fetched
-system.cpu.fetch.Cycles 3905 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.IcacheSquashes 148 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.Insts 13707 # Number of instructions fetch has processed
-system.cpu.fetch.SquashCycles 456 # Number of cycles fetch has spent squashing
-system.cpu.fetch.branchRate 0.328336 # Number of branch fetches per cycle
-system.cpu.fetch.icacheStallCycles 1582 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.predictedBranches 833 # Number of branches that fetch has predicted taken
-system.cpu.fetch.rate 1.994906 # Number of inst fetches per cycle
+system.cpu.dcache.tagsinuse 4093.061614 # Cycle average of tags in use
+system.cpu.dcache.total_refs 611672543 # Total number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 39716000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.writebacks 2244715 # number of writebacks
+system.cpu.decode.DECODE:BlockedCycles 3168036062 # Number of cycles decode is blocked
+system.cpu.decode.DECODE:BranchMispred 511 # Number of times decode detected a branch misprediction
+system.cpu.decode.DECODE:BranchResolved 48557069 # Number of times decode resolved a branch
+system.cpu.decode.DECODE:DecodedInsts 6641345328 # Number of instructions handled by decode
+system.cpu.decode.DECODE:IdleCycles 1298412925 # Number of cycles decode is idle
+system.cpu.decode.DECODE:RunCycles 1202046298 # Number of cycles decode is running
+system.cpu.decode.DECODE:SquashCycles 501929792 # Number of cycles decode is squashing
+system.cpu.decode.DECODE:SquashedInsts 1629 # Number of squashed instructions handled by decode
+system.cpu.decode.DECODE:UnblockCycles 10462509 # Number of cycles decode is unblocking
+system.cpu.fetch.Branches 1098978166 # Number of branches that fetch encountered
+system.cpu.fetch.CacheLines 541280485 # Number of cache lines fetched
+system.cpu.fetch.Cycles 1955627258 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.IcacheSquashes 11328270 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.Insts 7938391391 # Number of instructions fetch has processed
+system.cpu.fetch.SquashCycles 242391708 # Number of cycles fetch has spent squashing
+system.cpu.fetch.branchRate 0.177803 # Number of branch fetches per cycle
+system.cpu.fetch.icacheStallCycles 541280485 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.predictedBranches 1081038949 # Number of branches that fetch has predicted taken
+system.cpu.fetch.rate 1.284345 # Number of inst fetches per cycle
system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist.samples 6871
+system.cpu.fetch.rateDist.samples 6180887586
system.cpu.fetch.rateDist.min_value 0
- 0 4549 6620.58%
- 1 174 253.24%
- 2 186 270.70%
- 3 157 228.50%
- 4 211 307.09%
- 5 153 222.68%
- 6 171 248.87%
- 7 105 152.82%
- 8 1165 1695.53%
+ 0 4766540797 7711.74%
+ 1 80764415 130.67%
+ 2 63598055 102.89%
+ 3 58203597 94.17%
+ 4 424384465 686.61%
+ 5 69131012 111.85%
+ 6 94422767 152.77%
+ 7 44649271 72.24%
+ 8 579193207 937.07%
system.cpu.fetch.rateDist.max_value 8
system.cpu.fetch.rateDist.end_dist
-system.cpu.icache.ReadReq_accesses 1582 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 2.960245 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 1.996885 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits 1255 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 968 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate 0.206700 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses 327 # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_hits 6 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_miss_latency 641 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.202908 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses 321 # number of ReadReq MSHR misses
-system.cpu.icache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles_no_targets no value # average number of cycles each access was blocked
-system.cpu.icache.avg_refs 3.909657 # Average number of references to valid blocks.
+system.cpu.icache.ReadReq_accesses 541280484 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency 5378.819380 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 4616.750831 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits 541279194 # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency 6938677 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_rate 0.000002 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_misses 1290 # number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_hits 387 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_miss_latency 4168926 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate 0.000002 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_misses 903 # number of ReadReq MSHR misses
+system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles_no_targets 4207.523810 # average number of cycles each access was blocked
+system.cpu.icache.avg_refs 599423.249169 # Average number of references to valid blocks.
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu.icache.blocked_no_targets 21 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles_no_targets 88358 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.demand_accesses 1582 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 2.960245 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 1.996885 # average overall mshr miss latency
-system.cpu.icache.demand_hits 1255 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 968 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate 0.206700 # miss rate for demand accesses
-system.cpu.icache.demand_misses 327 # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_hits 6 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 641 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate 0.202908 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses 321 # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_accesses 541280484 # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency 5378.819380 # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 4616.750831 # average overall mshr miss latency
+system.cpu.icache.demand_hits 541279194 # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency 6938677 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_rate 0.000002 # miss rate for demand accesses
+system.cpu.icache.demand_misses 1290 # number of demand (read+write) misses
+system.cpu.icache.demand_mshr_hits 387 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_miss_latency 4168926 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_rate 0.000002 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_misses 903 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.overall_accesses 1582 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 2.960245 # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 1.996885 # average overall mshr miss latency
+system.cpu.icache.overall_accesses 541280484 # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency 5378.819380 # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 4616.750831 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits 1255 # number of overall hits
-system.cpu.icache.overall_miss_latency 968 # number of overall miss cycles
-system.cpu.icache.overall_miss_rate 0.206700 # miss rate for overall accesses
-system.cpu.icache.overall_misses 327 # number of overall misses
-system.cpu.icache.overall_mshr_hits 6 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 641 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate 0.202908 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses 321 # number of overall MSHR misses
+system.cpu.icache.overall_hits 541279194 # number of overall hits
+system.cpu.icache.overall_miss_latency 6938677 # number of overall miss cycles
+system.cpu.icache.overall_miss_rate 0.000002 # miss rate for overall accesses
+system.cpu.icache.overall_misses 1290 # number of overall misses
+system.cpu.icache.overall_mshr_hits 387 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_miss_latency 4168926 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_rate 0.000002 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_misses 903 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@@ -215,1646 +215,80 @@ system.cpu.icache.prefetcher.num_hwpf_issued 0
system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.icache.replacements 0 # number of replacements
-system.cpu.icache.sampled_refs 321 # Sample count of references to valid blocks.
+system.cpu.icache.replacements 1 # number of replacements
+system.cpu.icache.sampled_refs 903 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 176.393247 # Cycle average of tags in use
-system.cpu.icache.total_refs 1255 # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse 716.132429 # Cycle average of tags in use
+system.cpu.icache.total_refs 541279194 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.iew.EXEC:branches 1206 # Number of branches executed
-system.cpu.iew.EXEC:insts 7969 # Number of executed instructions
-system.cpu.iew.EXEC:loads 1610 # Number of load instructions executed
-system.cpu.iew.EXEC:nop 37 # number of nop insts executed
-system.cpu.iew.EXEC:rate 1.159802 # Inst execution rate
-system.cpu.iew.EXEC:refs 2599 # number of memory reference insts executed
-system.cpu.iew.EXEC:squashedInsts 419 # Number of squashed instructions skipped in execute
-system.cpu.iew.EXEC:stores 989 # Number of stores executed
+system.cpu.idleCycles 18731384505 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.iew.EXEC:branches 250098653 # Number of branches executed
+system.cpu.iew.EXEC:nop 147895912 # number of nop insts executed
+system.cpu.iew.EXEC:rate 0.440971 # Inst execution rate
+system.cpu.iew.EXEC:refs 918923683 # number of memory reference insts executed
+system.cpu.iew.EXEC:stores 177016651 # Number of stores executed
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
-system.cpu.iew.WB:consumers 5438 # num instructions consuming a value
-system.cpu.iew.WB:count 7722 # cumulative count of insts written-back
-system.cpu.iew.WB:fanout 0.744575 # average fanout of values written-back
+system.cpu.iew.WB:consumers 1839076786 # num instructions consuming a value
+system.cpu.iew.WB:count 2471794731 # cumulative count of insts written-back
+system.cpu.iew.WB:fanout 0.797100 # average fanout of values written-back
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.iew.WB:producers 4049 # num instructions producing a value
-system.cpu.iew.WB:rate 1.123854 # insts written-back per cycle
-system.cpu.iew.WB:sent 7762 # cumulative count of insts sent to commit
-system.cpu.iew.branchMispredicts 393 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewBlockCycles 4 # Number of cycles IEW is blocking
-system.cpu.iew.iewDispLoadInsts 2050 # Number of dispatched load instructions
-system.cpu.iew.iewDispNonSpecInsts 21 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewDispSquashedInsts 272 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispStoreInsts 1221 # Number of dispatched store instructions
-system.cpu.iew.iewDispatchedInsts 9990 # Number of instructions dispatched to IQ
-system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.WB:producers 1465928228 # num instructions producing a value
+system.cpu.iew.WB:rate 0.399909 # insts written-back per cycle
+system.cpu.iew.WB:sent 2475054397 # cumulative count of insts sent to commit
+system.cpu.iew.branchMispredicts 21956654 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewBlockCycles 2471410228 # Number of cycles IEW is blocking
+system.cpu.iew.iewDispLoadInsts 938731548 # Number of dispatched load instructions
+system.cpu.iew.iewDispNonSpecInsts 45 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewDispSquashedInsts 111073783 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispStoreInsts 389309694 # Number of dispatched store instructions
+system.cpu.iew.iewDispatchedInsts 4831881465 # Number of instructions dispatched to IQ
+system.cpu.iew.iewExecLoadInsts 741907032 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 286170200 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewExecutedInsts 2725595031 # Number of executed instructions
+system.cpu.iew.iewIQFullEvents 1536928 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.iewSquashCycles 754 # Number of cycles IEW is squashing
-system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking
-system.cpu.iew.lsq.thread.0.blockedLoads 1 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread.0.cacheBlocked 5 # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.lsq.thread.0.forwLoads 55 # Number of loads that had data forwarded from stores
-system.cpu.iew.lsq.thread.0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.iewLSQFullEvents 161620 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.iewSquashCycles 501929792 # Number of cycles IEW is squashing
+system.cpu.iew.iewUnblockCycles 6153373 # Number of cycles IEW is unblocking
+system.cpu.iew.lsq.thread.0.blockedLoads 8 # Number of blocked loads due to partial load-store forwarding
+system.cpu.iew.lsq.thread.0.cacheBlocked 233590575 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread.0.forwLoads 41593346 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread.0.ignoredResponses 516978 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
-system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread.0.squashedLoads 1071 # Number of loads squashed
-system.cpu.iew.lsq.thread.0.squashedStores 409 # Number of stores squashed
-system.cpu.iew.memOrderViolationEvents 41 # Number of memory order violations
-system.cpu.iew.predictedNotTakenIncorrect 296 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.predictedTakenIncorrect 97 # Number of branches that were predicted taken incorrectly
-system.cpu.ipc 0.818486 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.818486 # IPC: Total IPC of All Threads
-system.cpu.iq.IQ:residence:(null).start_dist # cycles from dispatch to issue
-system.cpu.iq.IQ:residence:(null).samples 0
-system.cpu.iq.IQ:residence:(null).min_value 0
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-system.cpu.iq.IQ:residence:(null).end_dist
-
-system.cpu.iq.IQ:residence:IntAlu.start_dist # cycles from dispatch to issue
-system.cpu.iq.IQ:residence:IntAlu.samples 0
-system.cpu.iq.IQ:residence:IntAlu.min_value 0
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-system.cpu.iq.IQ:residence:IntAlu.end_dist
-
-system.cpu.iq.IQ:residence:IntMult.start_dist # cycles from dispatch to issue
-system.cpu.iq.IQ:residence:IntMult.samples 0
-system.cpu.iq.IQ:residence:IntMult.min_value 0
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-system.cpu.iq.IQ:residence:IntMult.end_dist
-
-system.cpu.iq.IQ:residence:IntDiv.start_dist # cycles from dispatch to issue
-system.cpu.iq.IQ:residence:IntDiv.samples 0
-system.cpu.iq.IQ:residence:IntDiv.min_value 0
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-
-system.cpu.iq.IQ:residence:FloatAdd.start_dist # cycles from dispatch to issue
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-
-system.cpu.iq.IQ:residence:FloatCmp.start_dist # cycles from dispatch to issue
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-
-system.cpu.iq.IQ:residence:FloatCvt.start_dist # cycles from dispatch to issue
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-
-system.cpu.iq.IQ:residence:FloatMult.start_dist # cycles from dispatch to issue
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-
-system.cpu.iq.IQ:residence:FloatDiv.start_dist # cycles from dispatch to issue
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-
-system.cpu.iq.IQ:residence:FloatSqrt.start_dist # cycles from dispatch to issue
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-
-system.cpu.iq.IQ:residence:MemRead.start_dist # cycles from dispatch to issue
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-
-system.cpu.iq.IQ:residence:MemWrite.start_dist # cycles from dispatch to issue
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-system.cpu.iq.IQ:residence:MemWrite.end_dist
-
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-
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-
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-system.cpu.iq.ISSUE:(null)_delay.end_dist
-
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-system.cpu.iq.ISSUE:IntAlu_delay.min_value 0
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-system.cpu.iq.ISSUE:IntAlu_delay.end_dist
-
-system.cpu.iq.ISSUE:IntMult_delay.start_dist # cycles from operands ready to issue
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-system.cpu.iq.ISSUE:IntMult_delay.min_value 0
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-system.cpu.iq.ISSUE:IntMult_delay.end_dist
-
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-system.cpu.iq.ISSUE:IntDiv_delay.end_dist
-
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-
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-
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-system.cpu.iq.ISSUE:FloatCvt_delay.end_dist
-
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-system.cpu.iq.ISSUE:FloatMult_delay.min_value 0
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-
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-
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-
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-
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-
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-
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-
-system.cpu.iq.ISSUE:FU_type_0 8388 # Type of FU issued
+system.cpu.iew.lsq.thread.0.memOrderViolation 47985 # Number of memory ordering violations
+system.cpu.iew.lsq.thread.0.rescheduledLoads 8 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread.0.squashedLoads 493065187 # Number of loads squashed
+system.cpu.iew.lsq.thread.0.squashedStores 228404712 # Number of stores squashed
+system.cpu.iew.memOrderViolationEvents 47985 # Number of memory order violations
+system.cpu.iew.predictedNotTakenIncorrect 11190791 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.predictedTakenIncorrect 10765863 # Number of branches that were predicted taken incorrectly
+system.cpu.ipc 0.069686 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.069686 # IPC: Total IPC of All Threads
+system.cpu.iq.ISSUE:FU_type_0 3011765231 # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0.start_dist
- (null) 2 0.02% # Type of FU issued
- IntAlu 5594 66.69% # Type of FU issued
- IntMult 1 0.01% # Type of FU issued
+ (null) 0 0.00% # Type of FU issued
+ IntAlu 1970711875 65.43% # Type of FU issued
+ IntMult 679 0.00% # Type of FU issued
IntDiv 0 0.00% # Type of FU issued
- FloatAdd 2 0.02% # Type of FU issued
- FloatCmp 0 0.00% # Type of FU issued
- FloatCvt 0 0.00% # Type of FU issued
- FloatMult 0 0.00% # Type of FU issued
- FloatDiv 0 0.00% # Type of FU issued
+ FloatAdd 206 0.00% # Type of FU issued
+ FloatCmp 15 0.00% # Type of FU issued
+ FloatCvt 146 0.00% # Type of FU issued
+ FloatMult 12 0.00% # Type of FU issued
+ FloatDiv 24 0.00% # Type of FU issued
FloatSqrt 0 0.00% # Type of FU issued
- MemRead 1757 20.95% # Type of FU issued
- MemWrite 1032 12.30% # Type of FU issued
+ MemRead 862446019 28.64% # Type of FU issued
+ MemWrite 178606255 5.93% # Type of FU issued
IprAccess 0 0.00% # Type of FU issued
InstPrefetch 0 0.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0.end_dist
-system.cpu.iq.ISSUE:fu_busy_cnt 115 # FU busy when requested
-system.cpu.iq.ISSUE:fu_busy_rate 0.013710 # FU busy rate (busy events/executed inst)
+system.cpu.iq.ISSUE:fu_busy_cnt 11307551 # FU busy when requested
+system.cpu.iq.ISSUE:fu_busy_rate 0.003754 # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:fu_full.start_dist
(null) 0 0.00% # attempts to use FU when none available
- IntAlu 1 0.87% # attempts to use FU when none available
+ IntAlu 509990 4.51% # attempts to use FU when none available
IntMult 0 0.00% # attempts to use FU when none available
IntDiv 0 0.00% # attempts to use FU when none available
FloatAdd 0 0.00% # attempts to use FU when none available
@@ -1863,78 +297,84 @@ system.cpu.iq.ISSUE:fu_full.start_dist
FloatMult 0 0.00% # attempts to use FU when none available
FloatDiv 0 0.00% # attempts to use FU when none available
FloatSqrt 0 0.00% # attempts to use FU when none available
- MemRead 76 66.09% # attempts to use FU when none available
- MemWrite 38 33.04% # attempts to use FU when none available
+ MemRead 9173598 81.13% # attempts to use FU when none available
+ MemWrite 1623963 14.36% # attempts to use FU when none available
IprAccess 0 0.00% # attempts to use FU when none available
InstPrefetch 0 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full.end_dist
system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle.samples 6871
+system.cpu.iq.ISSUE:issued_per_cycle.samples 6180887586
system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
- 0 3753 5462.09%
- 1 894 1301.12%
- 2 723 1052.25%
- 3 614 893.61%
- 4 451 656.38%
- 5 279 406.05%
- 6 104 151.36%
- 7 41 59.67%
- 8 12 17.46%
+ 0 4878979324 7893.65%
+ 1 360055339 582.53%
+ 2 481197713 778.53%
+ 3 280796976 454.30%
+ 4 94854448 153.46%
+ 5 50760526 82.12%
+ 6 26723872 43.24%
+ 7 6795220 10.99%
+ 8 724168 1.17%
system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
system.cpu.iq.ISSUE:issued_per_cycle.end_dist
-system.cpu.iq.ISSUE:rate 1.220783 # Inst issue rate
-system.cpu.iq.iqInstsAdded 9932 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqInstsIssued 8388 # Number of instructions issued
-system.cpu.iq.iqNonSpecInstsAdded 21 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqSquashedInstsExamined 3990 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedInstsIssued 21 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedNonSpecRemoved 4 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.iqSquashedOperandsExamined 2486 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.l2cache.ReadReq_accesses 499 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 2.042254 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency 1015 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate 0.995992 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses 497 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 490 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.981964 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses 490 # number of ReadReq MSHR misses
+system.cpu.iq.ISSUE:rate 0.487271 # Inst issue rate
+system.cpu.iq.iqInstsAdded 4683985508 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqInstsIssued 3011765231 # Number of instructions issued
+system.cpu.iq.iqNonSpecInstsAdded 45 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqSquashedInstsExamined 2916477755 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedInstsIssued 6096386 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedNonSpecRemoved 16 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.iqSquashedOperandsExamined 3050829124 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.l2cache.ReadReq_accesses 9178154 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_avg_miss_latency 7336.712513 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2076.036854 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_hits 7008989 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_miss_latency 15914539999 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate 0.236340 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses 2169165 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency 4503266483 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.236340 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses 2169165 # number of ReadReq MSHR misses
+system.cpu.l2cache.WriteReqNoAck|Writeback_accesses 2244715 # number of WriteReqNoAck|Writeback accesses(hits+misses)
+system.cpu.l2cache.WriteReqNoAck|Writeback_hits 2215400 # number of WriteReqNoAck|Writeback hits
+system.cpu.l2cache.WriteReqNoAck|Writeback_miss_rate 0.013060 # miss rate for WriteReqNoAck|Writeback accesses
+system.cpu.l2cache.WriteReqNoAck|Writeback_misses 29315 # number of WriteReqNoAck|Writeback misses
+system.cpu.l2cache.WriteReqNoAck|Writeback_mshr_miss_rate 0.013060 # mshr miss rate for WriteReqNoAck|Writeback accesses
+system.cpu.l2cache.WriteReqNoAck|Writeback_mshr_misses 29315 # number of WriteReqNoAck|Writeback MSHR misses
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs 0.004024 # Average number of references to valid blocks.
+system.cpu.l2cache.avg_refs 4.252507 # Average number of references to valid blocks.
system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.demand_accesses 499 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 2.042254 # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 1 # average overall mshr miss latency
-system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 1015 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate 0.995992 # miss rate for demand accesses
-system.cpu.l2cache.demand_misses 497 # number of demand (read+write) misses
+system.cpu.l2cache.demand_accesses 9178154 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_avg_miss_latency 7336.712513 # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 2076.036854 # average overall mshr miss latency
+system.cpu.l2cache.demand_hits 7008989 # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency 15914539999 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate 0.236340 # miss rate for demand accesses
+system.cpu.l2cache.demand_misses 2169165 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency 490 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate 0.981964 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses 490 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_miss_latency 4503266483 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate 0.236340 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses 2169165 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.overall_accesses 499 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 2.042254 # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 1 # average overall mshr miss latency
+system.cpu.l2cache.overall_accesses 11422869 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_avg_miss_latency 7238.883228 # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 2076.036854 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits 2 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 1015 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate 0.995992 # miss rate for overall accesses
-system.cpu.l2cache.overall_misses 497 # number of overall misses
+system.cpu.l2cache.overall_hits 9224389 # number of overall hits
+system.cpu.l2cache.overall_miss_latency 15914539999 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate 0.192463 # miss rate for overall accesses
+system.cpu.l2cache.overall_misses 2198480 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 490 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate 0.981964 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses 490 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_miss_latency 4503266483 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate 0.189897 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses 2169165 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@@ -1946,29 +386,32 @@ system.cpu.l2cache.prefetcher.num_hwpf_issued 0
system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.l2cache.replacements 0 # number of replacements
-system.cpu.l2cache.sampled_refs 497 # Sample count of references to valid blocks.
+system.cpu.l2cache.replacements 2136397 # number of replacements
+system.cpu.l2cache.sampled_refs 2169165 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 295.773395 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks 0 # number of writebacks
-system.cpu.numCycles 6871 # number of cpu cycles simulated
-system.cpu.rename.RENAME:BlockCycles 4 # Number of cycles rename is blocking
-system.cpu.rename.RENAME:CommittedMaps 4051 # Number of HB maps that are committed
-system.cpu.rename.RENAME:IdleCycles 3758 # Number of cycles rename is idle
-system.cpu.rename.RENAME:LSQFullEvents 62 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RENAME:RenameLookups 14786 # Number of register rename lookups that rename has made
-system.cpu.rename.RENAME:RenamedInsts 11555 # Number of instructions processed by rename
-system.cpu.rename.RENAME:RenamedOperands 8634 # Number of destination operands rename has renamed
-system.cpu.rename.RENAME:RunCycles 1975 # Number of cycles rename is running
-system.cpu.rename.RENAME:SquashCycles 754 # Number of cycles rename is squashing
-system.cpu.rename.RENAME:UnblockCycles 111 # Number of cycles rename is unblocking
-system.cpu.rename.RENAME:UndoneMaps 4583 # Number of HB maps that are undone due to squashing
-system.cpu.rename.RENAME:serializeStallCycles 269 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RENAME:serializingInsts 26 # count of serializing insts renamed
-system.cpu.rename.RENAME:skidInsts 408 # count of insts added to the skid buffer
-system.cpu.rename.RENAME:tempSerializingInsts 21 # count of temporary serializing insts renamed
-system.cpu.workload.PROG:num_syscalls 17 # Number of system calls
+system.cpu.l2cache.tagsinuse 32623.472165 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 9224389 # Total number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle 520424000 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.writebacks 1039341 # number of writebacks
+system.cpu.numCycles 6180887586 # number of cpu cycles simulated
+system.cpu.rename.RENAME:BlockCycles 2894504060 # Number of cycles rename is blocking
+system.cpu.rename.RENAME:CommittedMaps 1376202963 # Number of HB maps that are committed
+system.cpu.rename.RENAME:IQFullEvents 6511750 # Number of times rename has blocked due to IQ full
+system.cpu.rename.RENAME:IdleCycles 1451413065 # Number of cycles rename is idle
+system.cpu.rename.RENAME:LSQFullEvents 266047107 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RENAME:ROBFullEvents 3125053 # Number of times rename has blocked due to ROB full
+system.cpu.rename.RENAME:RenameLookups 8501370508 # Number of register rename lookups that rename has made
+system.cpu.rename.RENAME:RenamedInsts 6112671585 # Number of instructions processed by rename
+system.cpu.rename.RENAME:RenamedOperands 4584914520 # Number of destination operands rename has renamed
+system.cpu.rename.RENAME:RunCycles 1056218413 # Number of cycles rename is running
+system.cpu.rename.RENAME:SquashCycles 501929792 # Number of cycles rename is squashing
+system.cpu.rename.RENAME:UnblockCycles 276756270 # Number of cycles rename is unblocking
+system.cpu.rename.RENAME:UndoneMaps 3208711557 # Number of HB maps that are undone due to squashing
+system.cpu.rename.RENAME:serializeStallCycles 65986 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RENAME:serializingInsts 49 # count of serializing insts renamed
+system.cpu.rename.RENAME:skidInsts 1117979447 # count of insts added to the skid buffer
+system.cpu.rename.RENAME:tempSerializingInsts 47 # count of temporary serializing insts renamed
+system.cpu.timesIdled 7293390 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.workload.PROG:num_syscalls 29 # Number of system calls
---------- End Simulation Statistics ----------
diff --git a/tests/long/60.bzip2/ref/alpha/linux/o3-timing/stderr b/tests/long/60.bzip2/ref/alpha/linux/o3-timing/stderr
index 8893caac8..87866a2a5 100644
--- a/tests/long/60.bzip2/ref/alpha/linux/o3-timing/stderr
+++ b/tests/long/60.bzip2/ref/alpha/linux/o3-timing/stderr
@@ -1,3 +1 @@
warn: Entering event queue @ 0. Starting simulation...
-warn: cycle 0: fault (page_table_fault) detected @ PC 0x000000
-warn: Increasing stack 0x11ff92000:0x11ff9b000 to 0x11ff90000:0x11ff9b000 because of access to 0x11ff91ff0
diff --git a/tests/long/60.bzip2/ref/alpha/linux/o3-timing/stdout b/tests/long/60.bzip2/ref/alpha/linux/o3-timing/stdout
index fbb329a2f..0c5c00118 100644
--- a/tests/long/60.bzip2/ref/alpha/linux/o3-timing/stdout
+++ b/tests/long/60.bzip2/ref/alpha/linux/o3-timing/stdout
@@ -1,13 +1,14 @@
-Hello world!
-M5 Simulator System
-
-Copyright (c) 2001-2006
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Sep 5 2006 15:28:48
-M5 started Tue Sep 5 15:42:12 2006
-M5 executing on zizzer.eecs.umich.edu
-command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/o3-timing tests/run.py quick/00.hello/alpha/linux/o3-timing
-Exiting @ tick 6870 because target called exit()
+spec_init
+Loading Input Data
+Input data 1048576 bytes in length
+Compressing Input Data, level 7
+Compressed data 198546 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Compressing Input Data, level 9
+Compressed data 198677 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Tested 1MB buffer: OK!
diff --git a/tests/long/60.bzip2/ref/alpha/linux/simple-atomic/config.ini b/tests/long/60.bzip2/ref/alpha/linux/simple-atomic/config.ini
index c3a59fbce..ad57a5293 100644
--- a/tests/long/60.bzip2/ref/alpha/linux/simple-atomic/config.ini
+++ b/tests/long/60.bzip2/ref/alpha/linux/simple-atomic/config.ini
@@ -7,11 +7,9 @@ max_tick=0
output_file=cout
progress_interval=0
-[debug]
-break_cycles=
-
[exetrace]
intel_format=false
+legion_lockstep=false
pc_symbol=true
print_cpseq=false
print_cycle=true
@@ -53,352 +51,49 @@ mem_mode=atomic
physmem=system.physmem
[system.cpu]
-type=DerivO3CPU
-children=dcache fuPool icache l2cache toL2Bus workload
-BTBEntries=4096
-BTBTagSize=16
-LFSTSize=1024
-LQEntries=32
-RASSize=16
-SQEntries=32
-SSITSize=1024
-activity=0
-backComSize=5
-choiceCtrBits=2
-choicePredictorSize=8192
+type=AtomicSimpleCPU
+children=workload
clock=1
-commitToDecodeDelay=1
-commitToFetchDelay=1
-commitToIEWDelay=1
-commitToRenameDelay=1
-commitWidth=8
-decodeToFetchDelay=1
-decodeToRenameDelay=1
-decodeWidth=8
+cpu_id=0
defer_registration=false
-dispatchWidth=8
-fetchToDecodeDelay=1
-fetchTrapLatency=1
-fetchWidth=8
-forwardComSize=5
-fuPool=system.cpu.fuPool
function_trace=false
function_trace_start=0
-globalCtrBits=2
-globalHistoryBits=13
-globalPredictorSize=8192
-iewToCommitDelay=1
-iewToDecodeDelay=1
-iewToFetchDelay=1
-iewToRenameDelay=1
-instShiftAmt=2
-issueToExecuteDelay=1
-issueWidth=8
-localCtrBits=2
-localHistoryBits=11
-localHistoryTableSize=2048
-localPredictorSize=2048
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
-mem=system.cpu.dcache
-numIQEntries=64
-numPhysFloatRegs=256
-numPhysIntRegs=256
-numROBEntries=192
-numRobs=1
-numThreads=1
-predType=tournament
-renameToDecodeDelay=1
-renameToFetchDelay=1
-renameToIEWDelay=2
-renameToROBDelay=1
-renameWidth=8
-squashWidth=8
+phase=0
+progress_interval=0
+simulate_stalls=false
system=system
-trapLatency=13
-wbDepth=1
-wbWidth=8
+width=1
workload=system.cpu.workload
-dcache_port=system.cpu.dcache.cpu_side
-icache_port=system.cpu.icache.cpu_side
-
-[system.cpu.dcache]
-type=BaseCache
-adaptive_compression=false
-assoc=2
-block_size=64
-compressed_bus=false
-compression_latency=0
-do_copy=false
-hash_delay=1
-hit_latency=1
-latency=1
-lifo=false
-max_miss_count=0
-mshrs=10
-prefetch_access=false
-prefetch_cache_check_push=true
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10
-prefetch_miss=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
-prioritizeRequests=false
-protocol=Null
-repl=Null
-size=262144
-split=false
-split_size=0
-store_compressed=false
-subblock_size=0
-tgts_per_mshr=5
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu.dcache_port
-mem_side=system.cpu.toL2Bus.port[1]
-
-[system.cpu.fuPool]
-type=FUPool
-children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7
-FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7
-
-[system.cpu.fuPool.FUList0]
-type=FUDesc
-children=opList0
-count=6
-opList=system.cpu.fuPool.FUList0.opList0
-
-[system.cpu.fuPool.FUList0.opList0]
-type=OpDesc
-issueLat=1
-opClass=IntAlu
-opLat=1
-
-[system.cpu.fuPool.FUList1]
-type=FUDesc
-children=opList0 opList1
-count=2
-opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
-
-[system.cpu.fuPool.FUList1.opList0]
-type=OpDesc
-issueLat=1
-opClass=IntMult
-opLat=3
-
-[system.cpu.fuPool.FUList1.opList1]
-type=OpDesc
-issueLat=19
-opClass=IntDiv
-opLat=20
-
-[system.cpu.fuPool.FUList2]
-type=FUDesc
-children=opList0 opList1 opList2
-count=4
-opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
-
-[system.cpu.fuPool.FUList2.opList0]
-type=OpDesc
-issueLat=1
-opClass=FloatAdd
-opLat=2
-
-[system.cpu.fuPool.FUList2.opList1]
-type=OpDesc
-issueLat=1
-opClass=FloatCmp
-opLat=2
-
-[system.cpu.fuPool.FUList2.opList2]
-type=OpDesc
-issueLat=1
-opClass=FloatCvt
-opLat=2
-
-[system.cpu.fuPool.FUList3]
-type=FUDesc
-children=opList0 opList1 opList2
-count=2
-opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
-
-[system.cpu.fuPool.FUList3.opList0]
-type=OpDesc
-issueLat=1
-opClass=FloatMult
-opLat=4
-
-[system.cpu.fuPool.FUList3.opList1]
-type=OpDesc
-issueLat=12
-opClass=FloatDiv
-opLat=12
-
-[system.cpu.fuPool.FUList3.opList2]
-type=OpDesc
-issueLat=24
-opClass=FloatSqrt
-opLat=24
-
-[system.cpu.fuPool.FUList4]
-type=FUDesc
-children=opList0
-count=0
-opList=system.cpu.fuPool.FUList4.opList0
-
-[system.cpu.fuPool.FUList4.opList0]
-type=OpDesc
-issueLat=1
-opClass=MemRead
-opLat=1
-
-[system.cpu.fuPool.FUList5]
-type=FUDesc
-children=opList0
-count=0
-opList=system.cpu.fuPool.FUList5.opList0
-
-[system.cpu.fuPool.FUList5.opList0]
-type=OpDesc
-issueLat=1
-opClass=MemWrite
-opLat=1
-
-[system.cpu.fuPool.FUList6]
-type=FUDesc
-children=opList0 opList1
-count=4
-opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1
-
-[system.cpu.fuPool.FUList6.opList0]
-type=OpDesc
-issueLat=1
-opClass=MemRead
-opLat=1
-
-[system.cpu.fuPool.FUList6.opList1]
-type=OpDesc
-issueLat=1
-opClass=MemWrite
-opLat=1
-
-[system.cpu.fuPool.FUList7]
-type=FUDesc
-children=opList0
-count=1
-opList=system.cpu.fuPool.FUList7.opList0
-
-[system.cpu.fuPool.FUList7.opList0]
-type=OpDesc
-issueLat=3
-opClass=IprAccess
-opLat=3
-
-[system.cpu.icache]
-type=BaseCache
-adaptive_compression=false
-assoc=2
-block_size=64
-compressed_bus=false
-compression_latency=0
-do_copy=false
-hash_delay=1
-hit_latency=1
-latency=1
-lifo=false
-max_miss_count=0
-mshrs=10
-prefetch_access=false
-prefetch_cache_check_push=true
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10
-prefetch_miss=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
-prioritizeRequests=false
-protocol=Null
-repl=Null
-size=131072
-split=false
-split_size=0
-store_compressed=false
-subblock_size=0
-tgts_per_mshr=5
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu.icache_port
-mem_side=system.cpu.toL2Bus.port[0]
-
-[system.cpu.l2cache]
-type=BaseCache
-adaptive_compression=false
-assoc=2
-block_size=64
-compressed_bus=false
-compression_latency=0
-do_copy=false
-hash_delay=1
-hit_latency=1
-latency=1
-lifo=false
-max_miss_count=0
-mshrs=10
-prefetch_access=false
-prefetch_cache_check_push=true
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10
-prefetch_miss=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
-prioritizeRequests=false
-protocol=Null
-repl=Null
-size=2097152
-split=false
-split_size=0
-store_compressed=false
-subblock_size=0
-tgts_per_mshr=5
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[1]
-
-[system.cpu.toL2Bus]
-type=Bus
-bus_id=0
-port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+dcache_port=system.membus.port[2]
+icache_port=system.membus.port[1]
[system.cpu.workload]
type=LiveProcess
-cmd=hello
+cmd=bzip2 input.source 1
+cwd=build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/linux/simple-atomic
+egid=100
env=
-executable=tests/test-progs/hello/bin/alpha/linux/hello
+euid=100
+executable=/dist/m5/cpu2000/binaries/alpha/tru64/bzip2
+gid=100
input=cin
output=cout
+pid=100
+ppid=99
system=system
+uid=100
[system.membus]
type=Bus
bus_id=0
-port=system.physmem.port system.cpu.l2cache.mem_side
+clock=1000
+responder_set=false
+width=64
+port=system.physmem.port system.cpu.icache_port system.cpu.dcache_port
[system.physmem]
type=PhysicalMemory
@@ -409,6 +104,7 @@ port=system.membus.port[0]
[trace]
bufsize=0
+cycle=0
dump_on_exit=false
file=cout
flags=
diff --git a/tests/long/60.bzip2/ref/alpha/linux/simple-atomic/config.out b/tests/long/60.bzip2/ref/alpha/linux/simple-atomic/config.out
index f491a3081..891519c26 100644
--- a/tests/long/60.bzip2/ref/alpha/linux/simple-atomic/config.out
+++ b/tests/long/60.bzip2/ref/alpha/linux/simple-atomic/config.out
@@ -19,345 +19,48 @@ mem_mode=atomic
[system.membus]
type=Bus
bus_id=0
+clock=1000
+width=64
+responder_set=false
[system.cpu.workload]
type=LiveProcess
-cmd=hello
-executable=tests/test-progs/hello/bin/alpha/linux/hello
+cmd=bzip2 input.source 1
+executable=/dist/m5/cpu2000/binaries/alpha/tru64/bzip2
input=cin
output=cout
env=
+cwd=build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/linux/simple-atomic
system=system
-
-[system.cpu.dcache]
-type=BaseCache
-size=262144
-assoc=2
-block_size=64
-latency=1
-mshrs=10
-tgts_per_mshr=5
-write_buffers=8
-prioritizeRequests=false
-do_copy=false
-protocol=null
-trace_addr=0
-hash_delay=1
-repl=null
-compressed_bus=false
-store_compressed=false
-adaptive_compression=false
-compression_latency=0
-block_size=64
-max_miss_count=0
-addr_range=[0,18446744073709551615]
-split=false
-split_size=0
-lifo=false
-two_queue=false
-prefetch_miss=false
-prefetch_access=false
-prefetcher_size=100
-prefetch_past_page=false
-prefetch_serial_squash=false
-prefetch_latency=10
-prefetch_degree=1
-prefetch_policy=none
-prefetch_cache_check_push=true
-prefetch_use_cpu_id=true
-prefetch_data_accesses_only=false
-hit_latency=1
-
-[system.cpu.fuPool.FUList0.opList0]
-type=OpDesc
-opClass=IntAlu
-opLat=1
-issueLat=1
-
-[system.cpu.fuPool.FUList0]
-type=FUDesc
-opList=system.cpu.fuPool.FUList0.opList0
-count=6
-
-[system.cpu.fuPool.FUList1.opList0]
-type=OpDesc
-opClass=IntMult
-opLat=3
-issueLat=1
-
-[system.cpu.fuPool.FUList1.opList1]
-type=OpDesc
-opClass=IntDiv
-opLat=20
-issueLat=19
-
-[system.cpu.fuPool.FUList1]
-type=FUDesc
-opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
-count=2
-
-[system.cpu.fuPool.FUList2.opList0]
-type=OpDesc
-opClass=FloatAdd
-opLat=2
-issueLat=1
-
-[system.cpu.fuPool.FUList2.opList1]
-type=OpDesc
-opClass=FloatCmp
-opLat=2
-issueLat=1
-
-[system.cpu.fuPool.FUList2.opList2]
-type=OpDesc
-opClass=FloatCvt
-opLat=2
-issueLat=1
-
-[system.cpu.fuPool.FUList2]
-type=FUDesc
-opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
-count=4
-
-[system.cpu.fuPool.FUList3.opList0]
-type=OpDesc
-opClass=FloatMult
-opLat=4
-issueLat=1
-
-[system.cpu.fuPool.FUList3.opList1]
-type=OpDesc
-opClass=FloatDiv
-opLat=12
-issueLat=12
-
-[system.cpu.fuPool.FUList3.opList2]
-type=OpDesc
-opClass=FloatSqrt
-opLat=24
-issueLat=24
-
-[system.cpu.fuPool.FUList3]
-type=FUDesc
-opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
-count=2
-
-[system.cpu.fuPool.FUList4.opList0]
-type=OpDesc
-opClass=MemRead
-opLat=1
-issueLat=1
-
-[system.cpu.fuPool.FUList4]
-type=FUDesc
-opList=system.cpu.fuPool.FUList4.opList0
-count=0
-
-[system.cpu.fuPool.FUList5.opList0]
-type=OpDesc
-opClass=MemWrite
-opLat=1
-issueLat=1
-
-[system.cpu.fuPool.FUList5]
-type=FUDesc
-opList=system.cpu.fuPool.FUList5.opList0
-count=0
-
-[system.cpu.fuPool.FUList6.opList0]
-type=OpDesc
-opClass=MemRead
-opLat=1
-issueLat=1
-
-[system.cpu.fuPool.FUList6.opList1]
-type=OpDesc
-opClass=MemWrite
-opLat=1
-issueLat=1
-
-[system.cpu.fuPool.FUList6]
-type=FUDesc
-opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1
-count=4
-
-[system.cpu.fuPool.FUList7.opList0]
-type=OpDesc
-opClass=IprAccess
-opLat=3
-issueLat=3
-
-[system.cpu.fuPool.FUList7]
-type=FUDesc
-opList=system.cpu.fuPool.FUList7.opList0
-count=1
-
-[system.cpu.fuPool]
-type=FUPool
-FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7
+uid=100
+euid=100
+gid=100
+egid=100
+pid=100
+ppid=99
[system.cpu]
-type=DerivO3CPU
-clock=1
-numThreads=1
-activity=0
-workload=system.cpu.workload
-mem=system.cpu.dcache
-checker=null
+type=AtomicSimpleCPU
max_insts_any_thread=0
max_insts_all_threads=0
max_loads_any_thread=0
max_loads_all_threads=0
-cachePorts=200
-decodeToFetchDelay=1
-renameToFetchDelay=1
-iewToFetchDelay=1
-commitToFetchDelay=1
-fetchWidth=8
-renameToDecodeDelay=1
-iewToDecodeDelay=1
-commitToDecodeDelay=1
-fetchToDecodeDelay=1
-decodeWidth=8
-iewToRenameDelay=1
-commitToRenameDelay=1
-decodeToRenameDelay=1
-renameWidth=8
-commitToIEWDelay=1
-renameToIEWDelay=2
-issueToExecuteDelay=1
-dispatchWidth=8
-issueWidth=8
-wbWidth=8
-wbDepth=1
-fuPool=system.cpu.fuPool
-iewToCommitDelay=1
-renameToROBDelay=1
-commitWidth=8
-squashWidth=8
-trapLatency=13
-backComSize=5
-forwardComSize=5
-predType=tournament
-localPredictorSize=2048
-localCtrBits=2
-localHistoryTableSize=2048
-localHistoryBits=11
-globalPredictorSize=8192
-globalCtrBits=2
-globalHistoryBits=13
-choicePredictorSize=8192
-choiceCtrBits=2
-BTBEntries=4096
-BTBTagSize=16
-RASSize=16
-LQEntries=32
-SQEntries=32
-LFSTSize=1024
-SSITSize=1024
-numPhysIntRegs=256
-numPhysFloatRegs=256
-numIQEntries=64
-numROBEntries=192
-smtNumFetchingThreads=1
-smtFetchPolicy=SingleThread
-smtLSQPolicy=Partitioned
-smtLSQThreshold=100
-smtIQPolicy=Partitioned
-smtIQThreshold=100
-smtROBPolicy=Partitioned
-smtROBThreshold=100
-smtCommitPolicy=RoundRobin
-instShiftAmt=2
+progress_interval=0
+system=system
+cpu_id=0
+workload=system.cpu.workload
+clock=1
+phase=0
defer_registration=false
+width=1
function_trace=false
function_trace_start=0
-
-[system.cpu.icache]
-type=BaseCache
-size=131072
-assoc=2
-block_size=64
-latency=1
-mshrs=10
-tgts_per_mshr=5
-write_buffers=8
-prioritizeRequests=false
-do_copy=false
-protocol=null
-trace_addr=0
-hash_delay=1
-repl=null
-compressed_bus=false
-store_compressed=false
-adaptive_compression=false
-compression_latency=0
-block_size=64
-max_miss_count=0
-addr_range=[0,18446744073709551615]
-split=false
-split_size=0
-lifo=false
-two_queue=false
-prefetch_miss=false
-prefetch_access=false
-prefetcher_size=100
-prefetch_past_page=false
-prefetch_serial_squash=false
-prefetch_latency=10
-prefetch_degree=1
-prefetch_policy=none
-prefetch_cache_check_push=true
-prefetch_use_cpu_id=true
-prefetch_data_accesses_only=false
-hit_latency=1
-
-[system.cpu.l2cache]
-type=BaseCache
-size=2097152
-assoc=2
-block_size=64
-latency=1
-mshrs=10
-tgts_per_mshr=5
-write_buffers=8
-prioritizeRequests=false
-do_copy=false
-protocol=null
-trace_addr=0
-hash_delay=1
-repl=null
-compressed_bus=false
-store_compressed=false
-adaptive_compression=false
-compression_latency=0
-block_size=64
-max_miss_count=0
-addr_range=[0,18446744073709551615]
-split=false
-split_size=0
-lifo=false
-two_queue=false
-prefetch_miss=false
-prefetch_access=false
-prefetcher_size=100
-prefetch_past_page=false
-prefetch_serial_squash=false
-prefetch_latency=10
-prefetch_degree=1
-prefetch_policy=none
-prefetch_cache_check_push=true
-prefetch_use_cpu_id=true
-prefetch_data_accesses_only=false
-hit_latency=1
-
-[system.cpu.toL2Bus]
-type=Bus
-bus_id=0
+simulate_stalls=false
[trace]
flags=
start=0
+cycle=0
bufsize=0
file=cout
dump_on_exit=false
@@ -396,8 +99,9 @@ print_cpseq=false
print_reg_delta=false
pc_symbol=true
intel_format=false
+legion_lockstep=false
trace_system=client
-[debug]
-break_cycles=
+[statsreset]
+reset_cycle=0
diff --git a/tests/long/60.bzip2/ref/alpha/linux/simple-atomic/m5stats.txt b/tests/long/60.bzip2/ref/alpha/linux/simple-atomic/m5stats.txt
index 5d4f9235a..7422e3ae7 100644
--- a/tests/long/60.bzip2/ref/alpha/linux/simple-atomic/m5stats.txt
+++ b/tests/long/60.bzip2/ref/alpha/linux/simple-atomic/m5stats.txt
@@ -1,1974 +1,18 @@
---------- Begin Simulation Statistics ----------
-global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-global.BPredUnit.BTBHits 542 # Number of BTB hits
-global.BPredUnit.BTBLookups 1938 # Number of BTB lookups
-global.BPredUnit.RASInCorrect 48 # Number of incorrect RAS predictions.
-global.BPredUnit.condIncorrect 420 # Number of conditional branches incorrect
-global.BPredUnit.condPredicted 1304 # Number of conditional branches predicted
-global.BPredUnit.lookups 2256 # Number of BP lookups
-global.BPredUnit.usedRAS 291 # Number of times the RAS was used to get a target.
-host_inst_rate 41797 # Simulator instruction rate (inst/s)
-host_mem_usage 160344 # Number of bytes of host memory used
-host_seconds 0.13 # Real time elapsed on the host
-host_tick_rate 50948 # Simulator tick rate (ticks/s)
-memdepunit.memDep.conflictingLoads 12 # Number of conflicting loads.
-memdepunit.memDep.conflictingStores 259 # Number of conflicting stores.
-memdepunit.memDep.insertedLoads 2050 # Number of loads inserted to the mem dependence unit.
-memdepunit.memDep.insertedStores 1221 # Number of stores inserted to the mem dependence unit.
+host_inst_rate 927424 # Simulator instruction rate (inst/s)
+host_mem_usage 144704 # Number of bytes of host memory used
+host_seconds 1962.19 # Real time elapsed on the host
+host_tick_rate 927424 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 5623 # Number of instructions simulated
-sim_seconds 0.000000 # Number of seconds simulated
-sim_ticks 6870 # Number of ticks simulated
-system.cpu.commit.COM:branches 862 # Number of branches committed
-system.cpu.commit.COM:bw_lim_events 74 # number cycles where commit BW limit reached
-system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle.samples 6116
-system.cpu.commit.COM:committed_per_cycle.min_value 0
- 0 3908 6389.80%
- 1 1064 1739.70%
- 2 389 636.04%
- 3 210 343.36%
- 4 153 250.16%
- 5 93 152.06%
- 6 76 124.26%
- 7 149 243.62%
- 8 74 120.99%
-system.cpu.commit.COM:committed_per_cycle.max_value 8
-system.cpu.commit.COM:committed_per_cycle.end_dist
-
-system.cpu.commit.COM:count 5640 # Number of instructions committed
-system.cpu.commit.COM:loads 979 # Number of loads committed
-system.cpu.commit.COM:membars 0 # Number of memory barriers committed
-system.cpu.commit.COM:refs 1791 # Number of memory references committed
-system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.branchMispredicts 337 # The number of times a branch was mispredicted
-system.cpu.commit.commitCommittedInsts 5640 # The number of committed instructions
-system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.commitSquashedInsts 4350 # The number of squashed insts skipped by commit
-system.cpu.committedInsts 5623 # Number of Instructions Simulated
-system.cpu.committedInsts_total 5623 # Number of Instructions Simulated
-system.cpu.cpi 1.221768 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 1.221768 # CPI: Total CPI of All Threads
-system.cpu.dcache.ReadReq_accesses 1538 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 3.072000 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2.240000 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits 1413 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 384 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate 0.081274 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses 125 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_hits 25 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_miss_latency 224 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate 0.065020 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses 100 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_accesses 821 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 2.467742 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2.140845 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 635 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 459 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.226553 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 186 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_hits 108 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_miss_latency 152 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.086480 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 71 # number of WriteReq MSHR misses
-system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles_no_targets 0.800000 # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 11.505618 # Average number of references to valid blocks.
-system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_no_targets 5 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles_no_targets 4 # number of cycles access was blocked
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.demand_accesses 2359 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 2.710611 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 2.198830 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 2048 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 843 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.131836 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 311 # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits 133 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 376 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate 0.072488 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 171 # number of demand (read+write) MSHR misses
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.overall_accesses 2359 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 2.710611 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 2.198830 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 2048 # number of overall hits
-system.cpu.dcache.overall_miss_latency 843 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.131836 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 311 # number of overall misses
-system.cpu.dcache.overall_mshr_hits 133 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 376 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate 0.072488 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 171 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.dcache.replacements 0 # number of replacements
-system.cpu.dcache.sampled_refs 178 # Sample count of references to valid blocks.
-system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 119.831029 # Cycle average of tags in use
-system.cpu.dcache.total_refs 2048 # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks 0 # number of writebacks
-system.cpu.decode.DECODE:BlockedCycles 387 # Number of cycles decode is blocked
-system.cpu.decode.DECODE:BranchMispred 93 # Number of times decode detected a branch misprediction
-system.cpu.decode.DECODE:BranchResolved 185 # Number of times decode resolved a branch
-system.cpu.decode.DECODE:DecodedInsts 12349 # Number of instructions handled by decode
-system.cpu.decode.DECODE:IdleCycles 3542 # Number of cycles decode is idle
-system.cpu.decode.DECODE:RunCycles 2158 # Number of cycles decode is running
-system.cpu.decode.DECODE:SquashCycles 754 # Number of cycles decode is squashing
-system.cpu.decode.DECODE:SquashedInsts 286 # Number of squashed instructions handled by decode
-system.cpu.decode.DECODE:UnblockCycles 30 # Number of cycles decode is unblocking
-system.cpu.fetch.Branches 2256 # Number of branches that fetch encountered
-system.cpu.fetch.CacheLines 1582 # Number of cache lines fetched
-system.cpu.fetch.Cycles 3905 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.IcacheSquashes 148 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.Insts 13707 # Number of instructions fetch has processed
-system.cpu.fetch.SquashCycles 456 # Number of cycles fetch has spent squashing
-system.cpu.fetch.branchRate 0.328336 # Number of branch fetches per cycle
-system.cpu.fetch.icacheStallCycles 1582 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.predictedBranches 833 # Number of branches that fetch has predicted taken
-system.cpu.fetch.rate 1.994906 # Number of inst fetches per cycle
-system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist.samples 6871
-system.cpu.fetch.rateDist.min_value 0
- 0 4549 6620.58%
- 1 174 253.24%
- 2 186 270.70%
- 3 157 228.50%
- 4 211 307.09%
- 5 153 222.68%
- 6 171 248.87%
- 7 105 152.82%
- 8 1165 1695.53%
-system.cpu.fetch.rateDist.max_value 8
-system.cpu.fetch.rateDist.end_dist
-
-system.cpu.icache.ReadReq_accesses 1582 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 2.960245 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 1.996885 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits 1255 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 968 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate 0.206700 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses 327 # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_hits 6 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_miss_latency 641 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.202908 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses 321 # number of ReadReq MSHR misses
-system.cpu.icache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles_no_targets no value # average number of cycles each access was blocked
-system.cpu.icache.avg_refs 3.909657 # Average number of references to valid blocks.
-system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.demand_accesses 1582 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 2.960245 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 1.996885 # average overall mshr miss latency
-system.cpu.icache.demand_hits 1255 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 968 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate 0.206700 # miss rate for demand accesses
-system.cpu.icache.demand_misses 327 # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_hits 6 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 641 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate 0.202908 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses 321 # number of demand (read+write) MSHR misses
-system.cpu.icache.fast_writes 0 # number of fast writes performed
-system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.overall_accesses 1582 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 2.960245 # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 1.996885 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits 1255 # number of overall hits
-system.cpu.icache.overall_miss_latency 968 # number of overall miss cycles
-system.cpu.icache.overall_miss_rate 0.206700 # miss rate for overall accesses
-system.cpu.icache.overall_misses 327 # number of overall misses
-system.cpu.icache.overall_mshr_hits 6 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 641 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate 0.202908 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses 321 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.icache.replacements 0 # number of replacements
-system.cpu.icache.sampled_refs 321 # Sample count of references to valid blocks.
-system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 176.393247 # Cycle average of tags in use
-system.cpu.icache.total_refs 1255 # Total number of references to valid blocks.
-system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.iew.EXEC:branches 1206 # Number of branches executed
-system.cpu.iew.EXEC:insts 7969 # Number of executed instructions
-system.cpu.iew.EXEC:loads 1610 # Number of load instructions executed
-system.cpu.iew.EXEC:nop 37 # number of nop insts executed
-system.cpu.iew.EXEC:rate 1.159802 # Inst execution rate
-system.cpu.iew.EXEC:refs 2599 # number of memory reference insts executed
-system.cpu.iew.EXEC:squashedInsts 419 # Number of squashed instructions skipped in execute
-system.cpu.iew.EXEC:stores 989 # Number of stores executed
-system.cpu.iew.EXEC:swp 0 # number of swp insts executed
-system.cpu.iew.WB:consumers 5438 # num instructions consuming a value
-system.cpu.iew.WB:count 7722 # cumulative count of insts written-back
-system.cpu.iew.WB:fanout 0.744575 # average fanout of values written-back
-system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.iew.WB:producers 4049 # num instructions producing a value
-system.cpu.iew.WB:rate 1.123854 # insts written-back per cycle
-system.cpu.iew.WB:sent 7762 # cumulative count of insts sent to commit
-system.cpu.iew.branchMispredicts 393 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewBlockCycles 4 # Number of cycles IEW is blocking
-system.cpu.iew.iewDispLoadInsts 2050 # Number of dispatched load instructions
-system.cpu.iew.iewDispNonSpecInsts 21 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewDispSquashedInsts 272 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispStoreInsts 1221 # Number of dispatched store instructions
-system.cpu.iew.iewDispatchedInsts 9990 # Number of instructions dispatched to IQ
-system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.iewSquashCycles 754 # Number of cycles IEW is squashing
-system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking
-system.cpu.iew.lsq.thread.0.blockedLoads 1 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread.0.cacheBlocked 5 # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.lsq.thread.0.forwLoads 55 # Number of loads that had data forwarded from stores
-system.cpu.iew.lsq.thread.0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
-system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread.0.squashedLoads 1071 # Number of loads squashed
-system.cpu.iew.lsq.thread.0.squashedStores 409 # Number of stores squashed
-system.cpu.iew.memOrderViolationEvents 41 # Number of memory order violations
-system.cpu.iew.predictedNotTakenIncorrect 296 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.predictedTakenIncorrect 97 # Number of branches that were predicted taken incorrectly
-system.cpu.ipc 0.818486 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.818486 # IPC: Total IPC of All Threads
-system.cpu.iq.IQ:residence:(null).start_dist # cycles from dispatch to issue
-system.cpu.iq.IQ:residence:(null).samples 0
-system.cpu.iq.IQ:residence:(null).min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
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- 98 0
-system.cpu.iq.IQ:residence:(null).max_value 0
-system.cpu.iq.IQ:residence:(null).end_dist
-
-system.cpu.iq.IQ:residence:IntAlu.start_dist # cycles from dispatch to issue
-system.cpu.iq.IQ:residence:IntAlu.samples 0
-system.cpu.iq.IQ:residence:IntAlu.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
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- 98 0
-system.cpu.iq.IQ:residence:IntAlu.max_value 0
-system.cpu.iq.IQ:residence:IntAlu.end_dist
-
-system.cpu.iq.IQ:residence:IntMult.start_dist # cycles from dispatch to issue
-system.cpu.iq.IQ:residence:IntMult.samples 0
-system.cpu.iq.IQ:residence:IntMult.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
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- 96 0
- 98 0
-system.cpu.iq.IQ:residence:IntMult.max_value 0
-system.cpu.iq.IQ:residence:IntMult.end_dist
-
-system.cpu.iq.IQ:residence:IntDiv.start_dist # cycles from dispatch to issue
-system.cpu.iq.IQ:residence:IntDiv.samples 0
-system.cpu.iq.IQ:residence:IntDiv.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
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- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.IQ:residence:IntDiv.max_value 0
-system.cpu.iq.IQ:residence:IntDiv.end_dist
-
-system.cpu.iq.IQ:residence:FloatAdd.start_dist # cycles from dispatch to issue
-system.cpu.iq.IQ:residence:FloatAdd.samples 0
-system.cpu.iq.IQ:residence:FloatAdd.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
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- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.IQ:residence:FloatAdd.max_value 0
-system.cpu.iq.IQ:residence:FloatAdd.end_dist
-
-system.cpu.iq.IQ:residence:FloatCmp.start_dist # cycles from dispatch to issue
-system.cpu.iq.IQ:residence:FloatCmp.samples 0
-system.cpu.iq.IQ:residence:FloatCmp.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
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- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.IQ:residence:FloatCmp.max_value 0
-system.cpu.iq.IQ:residence:FloatCmp.end_dist
-
-system.cpu.iq.IQ:residence:FloatCvt.start_dist # cycles from dispatch to issue
-system.cpu.iq.IQ:residence:FloatCvt.samples 0
-system.cpu.iq.IQ:residence:FloatCvt.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
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- 94 0
- 96 0
- 98 0
-system.cpu.iq.IQ:residence:FloatCvt.max_value 0
-system.cpu.iq.IQ:residence:FloatCvt.end_dist
-
-system.cpu.iq.IQ:residence:FloatMult.start_dist # cycles from dispatch to issue
-system.cpu.iq.IQ:residence:FloatMult.samples 0
-system.cpu.iq.IQ:residence:FloatMult.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
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- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.IQ:residence:FloatMult.max_value 0
-system.cpu.iq.IQ:residence:FloatMult.end_dist
-
-system.cpu.iq.IQ:residence:FloatDiv.start_dist # cycles from dispatch to issue
-system.cpu.iq.IQ:residence:FloatDiv.samples 0
-system.cpu.iq.IQ:residence:FloatDiv.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
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- 84 0
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- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.IQ:residence:FloatDiv.max_value 0
-system.cpu.iq.IQ:residence:FloatDiv.end_dist
-
-system.cpu.iq.IQ:residence:FloatSqrt.start_dist # cycles from dispatch to issue
-system.cpu.iq.IQ:residence:FloatSqrt.samples 0
-system.cpu.iq.IQ:residence:FloatSqrt.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
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- 20 0
- 22 0
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- 30 0
- 32 0
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- 40 0
- 42 0
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- 46 0
- 48 0
- 50 0
- 52 0
- 54 0
- 56 0
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- 78 0
- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.IQ:residence:FloatSqrt.max_value 0
-system.cpu.iq.IQ:residence:FloatSqrt.end_dist
-
-system.cpu.iq.IQ:residence:MemRead.start_dist # cycles from dispatch to issue
-system.cpu.iq.IQ:residence:MemRead.samples 0
-system.cpu.iq.IQ:residence:MemRead.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
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- 22 0
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- 30 0
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- 48 0
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- 54 0
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- 76 0
- 78 0
- 80 0
- 82 0
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- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.IQ:residence:MemRead.max_value 0
-system.cpu.iq.IQ:residence:MemRead.end_dist
-
-system.cpu.iq.IQ:residence:MemWrite.start_dist # cycles from dispatch to issue
-system.cpu.iq.IQ:residence:MemWrite.samples 0
-system.cpu.iq.IQ:residence:MemWrite.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
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- 14 0
- 16 0
- 18 0
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- 22 0
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- 30 0
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- 40 0
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- 48 0
- 50 0
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- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.IQ:residence:MemWrite.max_value 0
-system.cpu.iq.IQ:residence:MemWrite.end_dist
-
-system.cpu.iq.IQ:residence:IprAccess.start_dist # cycles from dispatch to issue
-system.cpu.iq.IQ:residence:IprAccess.samples 0
-system.cpu.iq.IQ:residence:IprAccess.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
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- 84 0
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- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.IQ:residence:IprAccess.max_value 0
-system.cpu.iq.IQ:residence:IprAccess.end_dist
-
-system.cpu.iq.IQ:residence:InstPrefetch.start_dist # cycles from dispatch to issue
-system.cpu.iq.IQ:residence:InstPrefetch.samples 0
-system.cpu.iq.IQ:residence:InstPrefetch.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
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- 14 0
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- 40 0
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- 50 0
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- 70 0
- 72 0
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- 76 0
- 78 0
- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.IQ:residence:InstPrefetch.max_value 0
-system.cpu.iq.IQ:residence:InstPrefetch.end_dist
-
-system.cpu.iq.ISSUE:(null)_delay.start_dist # cycles from operands ready to issue
-system.cpu.iq.ISSUE:(null)_delay.samples 0
-system.cpu.iq.ISSUE:(null)_delay.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
- 20 0
- 22 0
- 24 0
- 26 0
- 28 0
- 30 0
- 32 0
- 34 0
- 36 0
- 38 0
- 40 0
- 42 0
- 44 0
- 46 0
- 48 0
- 50 0
- 52 0
- 54 0
- 56 0
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- 60 0
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- 64 0
- 66 0
- 68 0
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- 72 0
- 74 0
- 76 0
- 78 0
- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.ISSUE:(null)_delay.max_value 0
-system.cpu.iq.ISSUE:(null)_delay.end_dist
-
-system.cpu.iq.ISSUE:IntAlu_delay.start_dist # cycles from operands ready to issue
-system.cpu.iq.ISSUE:IntAlu_delay.samples 0
-system.cpu.iq.ISSUE:IntAlu_delay.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
- 20 0
- 22 0
- 24 0
- 26 0
- 28 0
- 30 0
- 32 0
- 34 0
- 36 0
- 38 0
- 40 0
- 42 0
- 44 0
- 46 0
- 48 0
- 50 0
- 52 0
- 54 0
- 56 0
- 58 0
- 60 0
- 62 0
- 64 0
- 66 0
- 68 0
- 70 0
- 72 0
- 74 0
- 76 0
- 78 0
- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.ISSUE:IntAlu_delay.max_value 0
-system.cpu.iq.ISSUE:IntAlu_delay.end_dist
-
-system.cpu.iq.ISSUE:IntMult_delay.start_dist # cycles from operands ready to issue
-system.cpu.iq.ISSUE:IntMult_delay.samples 0
-system.cpu.iq.ISSUE:IntMult_delay.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
- 20 0
- 22 0
- 24 0
- 26 0
- 28 0
- 30 0
- 32 0
- 34 0
- 36 0
- 38 0
- 40 0
- 42 0
- 44 0
- 46 0
- 48 0
- 50 0
- 52 0
- 54 0
- 56 0
- 58 0
- 60 0
- 62 0
- 64 0
- 66 0
- 68 0
- 70 0
- 72 0
- 74 0
- 76 0
- 78 0
- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.ISSUE:IntMult_delay.max_value 0
-system.cpu.iq.ISSUE:IntMult_delay.end_dist
-
-system.cpu.iq.ISSUE:IntDiv_delay.start_dist # cycles from operands ready to issue
-system.cpu.iq.ISSUE:IntDiv_delay.samples 0
-system.cpu.iq.ISSUE:IntDiv_delay.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
- 20 0
- 22 0
- 24 0
- 26 0
- 28 0
- 30 0
- 32 0
- 34 0
- 36 0
- 38 0
- 40 0
- 42 0
- 44 0
- 46 0
- 48 0
- 50 0
- 52 0
- 54 0
- 56 0
- 58 0
- 60 0
- 62 0
- 64 0
- 66 0
- 68 0
- 70 0
- 72 0
- 74 0
- 76 0
- 78 0
- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.ISSUE:IntDiv_delay.max_value 0
-system.cpu.iq.ISSUE:IntDiv_delay.end_dist
-
-system.cpu.iq.ISSUE:FloatAdd_delay.start_dist # cycles from operands ready to issue
-system.cpu.iq.ISSUE:FloatAdd_delay.samples 0
-system.cpu.iq.ISSUE:FloatAdd_delay.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
- 20 0
- 22 0
- 24 0
- 26 0
- 28 0
- 30 0
- 32 0
- 34 0
- 36 0
- 38 0
- 40 0
- 42 0
- 44 0
- 46 0
- 48 0
- 50 0
- 52 0
- 54 0
- 56 0
- 58 0
- 60 0
- 62 0
- 64 0
- 66 0
- 68 0
- 70 0
- 72 0
- 74 0
- 76 0
- 78 0
- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.ISSUE:FloatAdd_delay.max_value 0
-system.cpu.iq.ISSUE:FloatAdd_delay.end_dist
-
-system.cpu.iq.ISSUE:FloatCmp_delay.start_dist # cycles from operands ready to issue
-system.cpu.iq.ISSUE:FloatCmp_delay.samples 0
-system.cpu.iq.ISSUE:FloatCmp_delay.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
- 20 0
- 22 0
- 24 0
- 26 0
- 28 0
- 30 0
- 32 0
- 34 0
- 36 0
- 38 0
- 40 0
- 42 0
- 44 0
- 46 0
- 48 0
- 50 0
- 52 0
- 54 0
- 56 0
- 58 0
- 60 0
- 62 0
- 64 0
- 66 0
- 68 0
- 70 0
- 72 0
- 74 0
- 76 0
- 78 0
- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.ISSUE:FloatCmp_delay.max_value 0
-system.cpu.iq.ISSUE:FloatCmp_delay.end_dist
-
-system.cpu.iq.ISSUE:FloatCvt_delay.start_dist # cycles from operands ready to issue
-system.cpu.iq.ISSUE:FloatCvt_delay.samples 0
-system.cpu.iq.ISSUE:FloatCvt_delay.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
- 20 0
- 22 0
- 24 0
- 26 0
- 28 0
- 30 0
- 32 0
- 34 0
- 36 0
- 38 0
- 40 0
- 42 0
- 44 0
- 46 0
- 48 0
- 50 0
- 52 0
- 54 0
- 56 0
- 58 0
- 60 0
- 62 0
- 64 0
- 66 0
- 68 0
- 70 0
- 72 0
- 74 0
- 76 0
- 78 0
- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.ISSUE:FloatCvt_delay.max_value 0
-system.cpu.iq.ISSUE:FloatCvt_delay.end_dist
-
-system.cpu.iq.ISSUE:FloatMult_delay.start_dist # cycles from operands ready to issue
-system.cpu.iq.ISSUE:FloatMult_delay.samples 0
-system.cpu.iq.ISSUE:FloatMult_delay.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
- 20 0
- 22 0
- 24 0
- 26 0
- 28 0
- 30 0
- 32 0
- 34 0
- 36 0
- 38 0
- 40 0
- 42 0
- 44 0
- 46 0
- 48 0
- 50 0
- 52 0
- 54 0
- 56 0
- 58 0
- 60 0
- 62 0
- 64 0
- 66 0
- 68 0
- 70 0
- 72 0
- 74 0
- 76 0
- 78 0
- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.ISSUE:FloatMult_delay.max_value 0
-system.cpu.iq.ISSUE:FloatMult_delay.end_dist
-
-system.cpu.iq.ISSUE:FloatDiv_delay.start_dist # cycles from operands ready to issue
-system.cpu.iq.ISSUE:FloatDiv_delay.samples 0
-system.cpu.iq.ISSUE:FloatDiv_delay.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
- 20 0
- 22 0
- 24 0
- 26 0
- 28 0
- 30 0
- 32 0
- 34 0
- 36 0
- 38 0
- 40 0
- 42 0
- 44 0
- 46 0
- 48 0
- 50 0
- 52 0
- 54 0
- 56 0
- 58 0
- 60 0
- 62 0
- 64 0
- 66 0
- 68 0
- 70 0
- 72 0
- 74 0
- 76 0
- 78 0
- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.ISSUE:FloatDiv_delay.max_value 0
-system.cpu.iq.ISSUE:FloatDiv_delay.end_dist
-
-system.cpu.iq.ISSUE:FloatSqrt_delay.start_dist # cycles from operands ready to issue
-system.cpu.iq.ISSUE:FloatSqrt_delay.samples 0
-system.cpu.iq.ISSUE:FloatSqrt_delay.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
- 20 0
- 22 0
- 24 0
- 26 0
- 28 0
- 30 0
- 32 0
- 34 0
- 36 0
- 38 0
- 40 0
- 42 0
- 44 0
- 46 0
- 48 0
- 50 0
- 52 0
- 54 0
- 56 0
- 58 0
- 60 0
- 62 0
- 64 0
- 66 0
- 68 0
- 70 0
- 72 0
- 74 0
- 76 0
- 78 0
- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.ISSUE:FloatSqrt_delay.max_value 0
-system.cpu.iq.ISSUE:FloatSqrt_delay.end_dist
-
-system.cpu.iq.ISSUE:MemRead_delay.start_dist # cycles from operands ready to issue
-system.cpu.iq.ISSUE:MemRead_delay.samples 0
-system.cpu.iq.ISSUE:MemRead_delay.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
- 20 0
- 22 0
- 24 0
- 26 0
- 28 0
- 30 0
- 32 0
- 34 0
- 36 0
- 38 0
- 40 0
- 42 0
- 44 0
- 46 0
- 48 0
- 50 0
- 52 0
- 54 0
- 56 0
- 58 0
- 60 0
- 62 0
- 64 0
- 66 0
- 68 0
- 70 0
- 72 0
- 74 0
- 76 0
- 78 0
- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.ISSUE:MemRead_delay.max_value 0
-system.cpu.iq.ISSUE:MemRead_delay.end_dist
-
-system.cpu.iq.ISSUE:MemWrite_delay.start_dist # cycles from operands ready to issue
-system.cpu.iq.ISSUE:MemWrite_delay.samples 0
-system.cpu.iq.ISSUE:MemWrite_delay.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
- 20 0
- 22 0
- 24 0
- 26 0
- 28 0
- 30 0
- 32 0
- 34 0
- 36 0
- 38 0
- 40 0
- 42 0
- 44 0
- 46 0
- 48 0
- 50 0
- 52 0
- 54 0
- 56 0
- 58 0
- 60 0
- 62 0
- 64 0
- 66 0
- 68 0
- 70 0
- 72 0
- 74 0
- 76 0
- 78 0
- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.ISSUE:MemWrite_delay.max_value 0
-system.cpu.iq.ISSUE:MemWrite_delay.end_dist
-
-system.cpu.iq.ISSUE:IprAccess_delay.start_dist # cycles from operands ready to issue
-system.cpu.iq.ISSUE:IprAccess_delay.samples 0
-system.cpu.iq.ISSUE:IprAccess_delay.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
- 20 0
- 22 0
- 24 0
- 26 0
- 28 0
- 30 0
- 32 0
- 34 0
- 36 0
- 38 0
- 40 0
- 42 0
- 44 0
- 46 0
- 48 0
- 50 0
- 52 0
- 54 0
- 56 0
- 58 0
- 60 0
- 62 0
- 64 0
- 66 0
- 68 0
- 70 0
- 72 0
- 74 0
- 76 0
- 78 0
- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.ISSUE:IprAccess_delay.max_value 0
-system.cpu.iq.ISSUE:IprAccess_delay.end_dist
-
-system.cpu.iq.ISSUE:InstPrefetch_delay.start_dist # cycles from operands ready to issue
-system.cpu.iq.ISSUE:InstPrefetch_delay.samples 0
-system.cpu.iq.ISSUE:InstPrefetch_delay.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
- 20 0
- 22 0
- 24 0
- 26 0
- 28 0
- 30 0
- 32 0
- 34 0
- 36 0
- 38 0
- 40 0
- 42 0
- 44 0
- 46 0
- 48 0
- 50 0
- 52 0
- 54 0
- 56 0
- 58 0
- 60 0
- 62 0
- 64 0
- 66 0
- 68 0
- 70 0
- 72 0
- 74 0
- 76 0
- 78 0
- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.ISSUE:InstPrefetch_delay.max_value 0
-system.cpu.iq.ISSUE:InstPrefetch_delay.end_dist
-
-system.cpu.iq.ISSUE:FU_type_0 8388 # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0.start_dist
- (null) 2 0.02% # Type of FU issued
- IntAlu 5594 66.69% # Type of FU issued
- IntMult 1 0.01% # Type of FU issued
- IntDiv 0 0.00% # Type of FU issued
- FloatAdd 2 0.02% # Type of FU issued
- FloatCmp 0 0.00% # Type of FU issued
- FloatCvt 0 0.00% # Type of FU issued
- FloatMult 0 0.00% # Type of FU issued
- FloatDiv 0 0.00% # Type of FU issued
- FloatSqrt 0 0.00% # Type of FU issued
- MemRead 1757 20.95% # Type of FU issued
- MemWrite 1032 12.30% # Type of FU issued
- IprAccess 0 0.00% # Type of FU issued
- InstPrefetch 0 0.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0.end_dist
-system.cpu.iq.ISSUE:fu_busy_cnt 115 # FU busy when requested
-system.cpu.iq.ISSUE:fu_busy_rate 0.013710 # FU busy rate (busy events/executed inst)
-system.cpu.iq.ISSUE:fu_full.start_dist
- (null) 0 0.00% # attempts to use FU when none available
- IntAlu 1 0.87% # attempts to use FU when none available
- IntMult 0 0.00% # attempts to use FU when none available
- IntDiv 0 0.00% # attempts to use FU when none available
- FloatAdd 0 0.00% # attempts to use FU when none available
- FloatCmp 0 0.00% # attempts to use FU when none available
- FloatCvt 0 0.00% # attempts to use FU when none available
- FloatMult 0 0.00% # attempts to use FU when none available
- FloatDiv 0 0.00% # attempts to use FU when none available
- FloatSqrt 0 0.00% # attempts to use FU when none available
- MemRead 76 66.09% # attempts to use FU when none available
- MemWrite 38 33.04% # attempts to use FU when none available
- IprAccess 0 0.00% # attempts to use FU when none available
- InstPrefetch 0 0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full.end_dist
-system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle.samples 6871
-system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
- 0 3753 5462.09%
- 1 894 1301.12%
- 2 723 1052.25%
- 3 614 893.61%
- 4 451 656.38%
- 5 279 406.05%
- 6 104 151.36%
- 7 41 59.67%
- 8 12 17.46%
-system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
-system.cpu.iq.ISSUE:issued_per_cycle.end_dist
-
-system.cpu.iq.ISSUE:rate 1.220783 # Inst issue rate
-system.cpu.iq.iqInstsAdded 9932 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqInstsIssued 8388 # Number of instructions issued
-system.cpu.iq.iqNonSpecInstsAdded 21 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqSquashedInstsExamined 3990 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedInstsIssued 21 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedNonSpecRemoved 4 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.iqSquashedOperandsExamined 2486 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.l2cache.ReadReq_accesses 499 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 2.042254 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency 1015 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate 0.995992 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses 497 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 490 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.981964 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses 490 # number of ReadReq MSHR misses
-system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs 0.004024 # Average number of references to valid blocks.
-system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.demand_accesses 499 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 2.042254 # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 1 # average overall mshr miss latency
-system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 1015 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate 0.995992 # miss rate for demand accesses
-system.cpu.l2cache.demand_misses 497 # number of demand (read+write) misses
-system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency 490 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate 0.981964 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses 490 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.fast_writes 0 # number of fast writes performed
-system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.overall_accesses 499 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 2.042254 # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 1 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits 2 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 1015 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate 0.995992 # miss rate for overall accesses
-system.cpu.l2cache.overall_misses 497 # number of overall misses
-system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 490 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate 0.981964 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses 490 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.l2cache.replacements 0 # number of replacements
-system.cpu.l2cache.sampled_refs 497 # Sample count of references to valid blocks.
-system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 295.773395 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks 0 # number of writebacks
-system.cpu.numCycles 6871 # number of cpu cycles simulated
-system.cpu.rename.RENAME:BlockCycles 4 # Number of cycles rename is blocking
-system.cpu.rename.RENAME:CommittedMaps 4051 # Number of HB maps that are committed
-system.cpu.rename.RENAME:IdleCycles 3758 # Number of cycles rename is idle
-system.cpu.rename.RENAME:LSQFullEvents 62 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RENAME:RenameLookups 14786 # Number of register rename lookups that rename has made
-system.cpu.rename.RENAME:RenamedInsts 11555 # Number of instructions processed by rename
-system.cpu.rename.RENAME:RenamedOperands 8634 # Number of destination operands rename has renamed
-system.cpu.rename.RENAME:RunCycles 1975 # Number of cycles rename is running
-system.cpu.rename.RENAME:SquashCycles 754 # Number of cycles rename is squashing
-system.cpu.rename.RENAME:UnblockCycles 111 # Number of cycles rename is unblocking
-system.cpu.rename.RENAME:UndoneMaps 4583 # Number of HB maps that are undone due to squashing
-system.cpu.rename.RENAME:serializeStallCycles 269 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RENAME:serializingInsts 26 # count of serializing insts renamed
-system.cpu.rename.RENAME:skidInsts 408 # count of insts added to the skid buffer
-system.cpu.rename.RENAME:tempSerializingInsts 21 # count of temporary serializing insts renamed
-system.cpu.workload.PROG:num_syscalls 17 # Number of system calls
+sim_insts 1819780129 # Number of instructions simulated
+sim_seconds 0.001820 # Number of seconds simulated
+sim_ticks 1819780128 # Number of ticks simulated
+system.cpu.idle_fraction 0 # Percentage of idle cycles
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.numCycles 1819780129 # number of cpu cycles simulated
+system.cpu.num_insts 1819780129 # Number of instructions executed
+system.cpu.num_refs 606571345 # Number of memory references
+system.cpu.workload.PROG:num_syscalls 29 # Number of system calls
---------- End Simulation Statistics ----------
diff --git a/tests/long/60.bzip2/ref/alpha/linux/simple-atomic/stderr b/tests/long/60.bzip2/ref/alpha/linux/simple-atomic/stderr
index 8893caac8..87866a2a5 100644
--- a/tests/long/60.bzip2/ref/alpha/linux/simple-atomic/stderr
+++ b/tests/long/60.bzip2/ref/alpha/linux/simple-atomic/stderr
@@ -1,3 +1 @@
warn: Entering event queue @ 0. Starting simulation...
-warn: cycle 0: fault (page_table_fault) detected @ PC 0x000000
-warn: Increasing stack 0x11ff92000:0x11ff9b000 to 0x11ff90000:0x11ff9b000 because of access to 0x11ff91ff0
diff --git a/tests/long/60.bzip2/ref/alpha/linux/simple-atomic/stdout b/tests/long/60.bzip2/ref/alpha/linux/simple-atomic/stdout
index fbb329a2f..0c5c00118 100644
--- a/tests/long/60.bzip2/ref/alpha/linux/simple-atomic/stdout
+++ b/tests/long/60.bzip2/ref/alpha/linux/simple-atomic/stdout
@@ -1,13 +1,14 @@
-Hello world!
-M5 Simulator System
-
-Copyright (c) 2001-2006
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Sep 5 2006 15:28:48
-M5 started Tue Sep 5 15:42:12 2006
-M5 executing on zizzer.eecs.umich.edu
-command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/o3-timing tests/run.py quick/00.hello/alpha/linux/o3-timing
-Exiting @ tick 6870 because target called exit()
+spec_init
+Loading Input Data
+Input data 1048576 bytes in length
+Compressing Input Data, level 7
+Compressed data 198546 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Compressing Input Data, level 9
+Compressed data 198677 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Tested 1MB buffer: OK!
diff --git a/tests/long/60.bzip2/ref/alpha/linux/simple-timing/config.ini b/tests/long/60.bzip2/ref/alpha/linux/simple-timing/config.ini
index c3a59fbce..0a123d4a4 100644
--- a/tests/long/60.bzip2/ref/alpha/linux/simple-timing/config.ini
+++ b/tests/long/60.bzip2/ref/alpha/linux/simple-timing/config.ini
@@ -7,11 +7,9 @@ max_tick=0
output_file=cout
progress_interval=0
-[debug]
-break_cycles=
-
[exetrace]
intel_format=false
+legion_lockstep=false
pc_symbol=true
print_cpseq=false
print_cycle=true
@@ -53,73 +51,20 @@ mem_mode=atomic
physmem=system.physmem
[system.cpu]
-type=DerivO3CPU
-children=dcache fuPool icache l2cache toL2Bus workload
-BTBEntries=4096
-BTBTagSize=16
-LFSTSize=1024
-LQEntries=32
-RASSize=16
-SQEntries=32
-SSITSize=1024
-activity=0
-backComSize=5
-choiceCtrBits=2
-choicePredictorSize=8192
+type=TimingSimpleCPU
+children=dcache icache l2cache toL2Bus workload
clock=1
-commitToDecodeDelay=1
-commitToFetchDelay=1
-commitToIEWDelay=1
-commitToRenameDelay=1
-commitWidth=8
-decodeToFetchDelay=1
-decodeToRenameDelay=1
-decodeWidth=8
+cpu_id=0
defer_registration=false
-dispatchWidth=8
-fetchToDecodeDelay=1
-fetchTrapLatency=1
-fetchWidth=8
-forwardComSize=5
-fuPool=system.cpu.fuPool
function_trace=false
function_trace_start=0
-globalCtrBits=2
-globalHistoryBits=13
-globalPredictorSize=8192
-iewToCommitDelay=1
-iewToDecodeDelay=1
-iewToFetchDelay=1
-iewToRenameDelay=1
-instShiftAmt=2
-issueToExecuteDelay=1
-issueWidth=8
-localCtrBits=2
-localHistoryBits=11
-localHistoryTableSize=2048
-localPredictorSize=2048
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
-mem=system.cpu.dcache
-numIQEntries=64
-numPhysFloatRegs=256
-numPhysIntRegs=256
-numROBEntries=192
-numRobs=1
-numThreads=1
-predType=tournament
-renameToDecodeDelay=1
-renameToFetchDelay=1
-renameToIEWDelay=2
-renameToROBDelay=1
-renameWidth=8
-squashWidth=8
+phase=0
+progress_interval=0
system=system
-trapLatency=13
-wbDepth=1
-wbWidth=8
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
@@ -131,7 +76,6 @@ assoc=2
block_size=64
compressed_bus=false
compression_latency=0
-do_copy=false
hash_delay=1
hit_latency=1
latency=1
@@ -164,143 +108,6 @@ write_buffers=8
cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.port[1]
-[system.cpu.fuPool]
-type=FUPool
-children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7
-FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7
-
-[system.cpu.fuPool.FUList0]
-type=FUDesc
-children=opList0
-count=6
-opList=system.cpu.fuPool.FUList0.opList0
-
-[system.cpu.fuPool.FUList0.opList0]
-type=OpDesc
-issueLat=1
-opClass=IntAlu
-opLat=1
-
-[system.cpu.fuPool.FUList1]
-type=FUDesc
-children=opList0 opList1
-count=2
-opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
-
-[system.cpu.fuPool.FUList1.opList0]
-type=OpDesc
-issueLat=1
-opClass=IntMult
-opLat=3
-
-[system.cpu.fuPool.FUList1.opList1]
-type=OpDesc
-issueLat=19
-opClass=IntDiv
-opLat=20
-
-[system.cpu.fuPool.FUList2]
-type=FUDesc
-children=opList0 opList1 opList2
-count=4
-opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
-
-[system.cpu.fuPool.FUList2.opList0]
-type=OpDesc
-issueLat=1
-opClass=FloatAdd
-opLat=2
-
-[system.cpu.fuPool.FUList2.opList1]
-type=OpDesc
-issueLat=1
-opClass=FloatCmp
-opLat=2
-
-[system.cpu.fuPool.FUList2.opList2]
-type=OpDesc
-issueLat=1
-opClass=FloatCvt
-opLat=2
-
-[system.cpu.fuPool.FUList3]
-type=FUDesc
-children=opList0 opList1 opList2
-count=2
-opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
-
-[system.cpu.fuPool.FUList3.opList0]
-type=OpDesc
-issueLat=1
-opClass=FloatMult
-opLat=4
-
-[system.cpu.fuPool.FUList3.opList1]
-type=OpDesc
-issueLat=12
-opClass=FloatDiv
-opLat=12
-
-[system.cpu.fuPool.FUList3.opList2]
-type=OpDesc
-issueLat=24
-opClass=FloatSqrt
-opLat=24
-
-[system.cpu.fuPool.FUList4]
-type=FUDesc
-children=opList0
-count=0
-opList=system.cpu.fuPool.FUList4.opList0
-
-[system.cpu.fuPool.FUList4.opList0]
-type=OpDesc
-issueLat=1
-opClass=MemRead
-opLat=1
-
-[system.cpu.fuPool.FUList5]
-type=FUDesc
-children=opList0
-count=0
-opList=system.cpu.fuPool.FUList5.opList0
-
-[system.cpu.fuPool.FUList5.opList0]
-type=OpDesc
-issueLat=1
-opClass=MemWrite
-opLat=1
-
-[system.cpu.fuPool.FUList6]
-type=FUDesc
-children=opList0 opList1
-count=4
-opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1
-
-[system.cpu.fuPool.FUList6.opList0]
-type=OpDesc
-issueLat=1
-opClass=MemRead
-opLat=1
-
-[system.cpu.fuPool.FUList6.opList1]
-type=OpDesc
-issueLat=1
-opClass=MemWrite
-opLat=1
-
-[system.cpu.fuPool.FUList7]
-type=FUDesc
-children=opList0
-count=1
-opList=system.cpu.fuPool.FUList7.opList0
-
-[system.cpu.fuPool.FUList7.opList0]
-type=OpDesc
-issueLat=3
-opClass=IprAccess
-opLat=3
-
[system.cpu.icache]
type=BaseCache
adaptive_compression=false
@@ -308,7 +115,6 @@ assoc=2
block_size=64
compressed_bus=false
compression_latency=0
-do_copy=false
hash_delay=1
hit_latency=1
latency=1
@@ -348,7 +154,6 @@ assoc=2
block_size=64
compressed_bus=false
compression_latency=0
-do_copy=false
hash_delay=1
hit_latency=1
latency=1
@@ -384,20 +189,33 @@ mem_side=system.membus.port[1]
[system.cpu.toL2Bus]
type=Bus
bus_id=0
+clock=1000
+responder_set=false
+width=64
port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
[system.cpu.workload]
type=LiveProcess
-cmd=hello
+cmd=bzip2 input.source 1
+cwd=build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/linux/simple-timing
+egid=100
env=
-executable=tests/test-progs/hello/bin/alpha/linux/hello
+euid=100
+executable=/dist/m5/cpu2000/binaries/alpha/tru64/bzip2
+gid=100
input=cin
output=cout
+pid=100
+ppid=99
system=system
+uid=100
[system.membus]
type=Bus
bus_id=0
+clock=1000
+responder_set=false
+width=64
port=system.physmem.port system.cpu.l2cache.mem_side
[system.physmem]
@@ -409,6 +227,7 @@ port=system.membus.port[0]
[trace]
bufsize=0
+cycle=0
dump_on_exit=false
file=cout
flags=
diff --git a/tests/long/60.bzip2/ref/alpha/linux/simple-timing/config.out b/tests/long/60.bzip2/ref/alpha/linux/simple-timing/config.out
index f491a3081..4692c5d40 100644
--- a/tests/long/60.bzip2/ref/alpha/linux/simple-timing/config.out
+++ b/tests/long/60.bzip2/ref/alpha/linux/simple-timing/config.out
@@ -19,19 +19,54 @@ mem_mode=atomic
[system.membus]
type=Bus
bus_id=0
+clock=1000
+width=64
+responder_set=false
[system.cpu.workload]
type=LiveProcess
-cmd=hello
-executable=tests/test-progs/hello/bin/alpha/linux/hello
+cmd=bzip2 input.source 1
+executable=/dist/m5/cpu2000/binaries/alpha/tru64/bzip2
input=cin
output=cout
env=
+cwd=build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/linux/simple-timing
system=system
+uid=100
+euid=100
+gid=100
+egid=100
+pid=100
+ppid=99
-[system.cpu.dcache]
+[system.cpu]
+type=TimingSimpleCPU
+max_insts_any_thread=0
+max_insts_all_threads=0
+max_loads_any_thread=0
+max_loads_all_threads=0
+progress_interval=0
+system=system
+cpu_id=0
+workload=system.cpu.workload
+clock=1
+phase=0
+defer_registration=false
+// width not specified
+function_trace=false
+function_trace_start=0
+// simulate_stalls not specified
+
+[system.cpu.toL2Bus]
+type=Bus
+bus_id=0
+clock=1000
+width=64
+responder_set=false
+
+[system.cpu.icache]
type=BaseCache
-size=262144
+size=131072
assoc=2
block_size=64
latency=1
@@ -39,7 +74,6 @@ mshrs=10
tgts_per_mshr=5
write_buffers=8
prioritizeRequests=false
-do_copy=false
protocol=null
trace_addr=0
hash_delay=1
@@ -68,214 +102,9 @@ prefetch_use_cpu_id=true
prefetch_data_accesses_only=false
hit_latency=1
-[system.cpu.fuPool.FUList0.opList0]
-type=OpDesc
-opClass=IntAlu
-opLat=1
-issueLat=1
-
-[system.cpu.fuPool.FUList0]
-type=FUDesc
-opList=system.cpu.fuPool.FUList0.opList0
-count=6
-
-[system.cpu.fuPool.FUList1.opList0]
-type=OpDesc
-opClass=IntMult
-opLat=3
-issueLat=1
-
-[system.cpu.fuPool.FUList1.opList1]
-type=OpDesc
-opClass=IntDiv
-opLat=20
-issueLat=19
-
-[system.cpu.fuPool.FUList1]
-type=FUDesc
-opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
-count=2
-
-[system.cpu.fuPool.FUList2.opList0]
-type=OpDesc
-opClass=FloatAdd
-opLat=2
-issueLat=1
-
-[system.cpu.fuPool.FUList2.opList1]
-type=OpDesc
-opClass=FloatCmp
-opLat=2
-issueLat=1
-
-[system.cpu.fuPool.FUList2.opList2]
-type=OpDesc
-opClass=FloatCvt
-opLat=2
-issueLat=1
-
-[system.cpu.fuPool.FUList2]
-type=FUDesc
-opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
-count=4
-
-[system.cpu.fuPool.FUList3.opList0]
-type=OpDesc
-opClass=FloatMult
-opLat=4
-issueLat=1
-
-[system.cpu.fuPool.FUList3.opList1]
-type=OpDesc
-opClass=FloatDiv
-opLat=12
-issueLat=12
-
-[system.cpu.fuPool.FUList3.opList2]
-type=OpDesc
-opClass=FloatSqrt
-opLat=24
-issueLat=24
-
-[system.cpu.fuPool.FUList3]
-type=FUDesc
-opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
-count=2
-
-[system.cpu.fuPool.FUList4.opList0]
-type=OpDesc
-opClass=MemRead
-opLat=1
-issueLat=1
-
-[system.cpu.fuPool.FUList4]
-type=FUDesc
-opList=system.cpu.fuPool.FUList4.opList0
-count=0
-
-[system.cpu.fuPool.FUList5.opList0]
-type=OpDesc
-opClass=MemWrite
-opLat=1
-issueLat=1
-
-[system.cpu.fuPool.FUList5]
-type=FUDesc
-opList=system.cpu.fuPool.FUList5.opList0
-count=0
-
-[system.cpu.fuPool.FUList6.opList0]
-type=OpDesc
-opClass=MemRead
-opLat=1
-issueLat=1
-
-[system.cpu.fuPool.FUList6.opList1]
-type=OpDesc
-opClass=MemWrite
-opLat=1
-issueLat=1
-
-[system.cpu.fuPool.FUList6]
-type=FUDesc
-opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1
-count=4
-
-[system.cpu.fuPool.FUList7.opList0]
-type=OpDesc
-opClass=IprAccess
-opLat=3
-issueLat=3
-
-[system.cpu.fuPool.FUList7]
-type=FUDesc
-opList=system.cpu.fuPool.FUList7.opList0
-count=1
-
-[system.cpu.fuPool]
-type=FUPool
-FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7
-
-[system.cpu]
-type=DerivO3CPU
-clock=1
-numThreads=1
-activity=0
-workload=system.cpu.workload
-mem=system.cpu.dcache
-checker=null
-max_insts_any_thread=0
-max_insts_all_threads=0
-max_loads_any_thread=0
-max_loads_all_threads=0
-cachePorts=200
-decodeToFetchDelay=1
-renameToFetchDelay=1
-iewToFetchDelay=1
-commitToFetchDelay=1
-fetchWidth=8
-renameToDecodeDelay=1
-iewToDecodeDelay=1
-commitToDecodeDelay=1
-fetchToDecodeDelay=1
-decodeWidth=8
-iewToRenameDelay=1
-commitToRenameDelay=1
-decodeToRenameDelay=1
-renameWidth=8
-commitToIEWDelay=1
-renameToIEWDelay=2
-issueToExecuteDelay=1
-dispatchWidth=8
-issueWidth=8
-wbWidth=8
-wbDepth=1
-fuPool=system.cpu.fuPool
-iewToCommitDelay=1
-renameToROBDelay=1
-commitWidth=8
-squashWidth=8
-trapLatency=13
-backComSize=5
-forwardComSize=5
-predType=tournament
-localPredictorSize=2048
-localCtrBits=2
-localHistoryTableSize=2048
-localHistoryBits=11
-globalPredictorSize=8192
-globalCtrBits=2
-globalHistoryBits=13
-choicePredictorSize=8192
-choiceCtrBits=2
-BTBEntries=4096
-BTBTagSize=16
-RASSize=16
-LQEntries=32
-SQEntries=32
-LFSTSize=1024
-SSITSize=1024
-numPhysIntRegs=256
-numPhysFloatRegs=256
-numIQEntries=64
-numROBEntries=192
-smtNumFetchingThreads=1
-smtFetchPolicy=SingleThread
-smtLSQPolicy=Partitioned
-smtLSQThreshold=100
-smtIQPolicy=Partitioned
-smtIQThreshold=100
-smtROBPolicy=Partitioned
-smtROBThreshold=100
-smtCommitPolicy=RoundRobin
-instShiftAmt=2
-defer_registration=false
-function_trace=false
-function_trace_start=0
-
-[system.cpu.icache]
+[system.cpu.dcache]
type=BaseCache
-size=131072
+size=262144
assoc=2
block_size=64
latency=1
@@ -283,7 +112,6 @@ mshrs=10
tgts_per_mshr=5
write_buffers=8
prioritizeRequests=false
-do_copy=false
protocol=null
trace_addr=0
hash_delay=1
@@ -322,7 +150,6 @@ mshrs=10
tgts_per_mshr=5
write_buffers=8
prioritizeRequests=false
-do_copy=false
protocol=null
trace_addr=0
hash_delay=1
@@ -351,13 +178,10 @@ prefetch_use_cpu_id=true
prefetch_data_accesses_only=false
hit_latency=1
-[system.cpu.toL2Bus]
-type=Bus
-bus_id=0
-
[trace]
flags=
start=0
+cycle=0
bufsize=0
file=cout
dump_on_exit=false
@@ -396,8 +220,9 @@ print_cpseq=false
print_reg_delta=false
pc_symbol=true
intel_format=false
+legion_lockstep=false
trace_system=client
-[debug]
-break_cycles=
+[statsreset]
+reset_cycle=0
diff --git a/tests/long/60.bzip2/ref/alpha/linux/simple-timing/m5stats.txt b/tests/long/60.bzip2/ref/alpha/linux/simple-timing/m5stats.txt
index 5d4f9235a..45b7beb7c 100644
--- a/tests/long/60.bzip2/ref/alpha/linux/simple-timing/m5stats.txt
+++ b/tests/long/60.bzip2/ref/alpha/linux/simple-timing/m5stats.txt
@@ -1,112 +1,67 @@
---------- Begin Simulation Statistics ----------
-global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-global.BPredUnit.BTBHits 542 # Number of BTB hits
-global.BPredUnit.BTBLookups 1938 # Number of BTB lookups
-global.BPredUnit.RASInCorrect 48 # Number of incorrect RAS predictions.
-global.BPredUnit.condIncorrect 420 # Number of conditional branches incorrect
-global.BPredUnit.condPredicted 1304 # Number of conditional branches predicted
-global.BPredUnit.lookups 2256 # Number of BP lookups
-global.BPredUnit.usedRAS 291 # Number of times the RAS was used to get a target.
-host_inst_rate 41797 # Simulator instruction rate (inst/s)
-host_mem_usage 160344 # Number of bytes of host memory used
-host_seconds 0.13 # Real time elapsed on the host
-host_tick_rate 50948 # Simulator tick rate (ticks/s)
-memdepunit.memDep.conflictingLoads 12 # Number of conflicting loads.
-memdepunit.memDep.conflictingStores 259 # Number of conflicting stores.
-memdepunit.memDep.insertedLoads 2050 # Number of loads inserted to the mem dependence unit.
-memdepunit.memDep.insertedStores 1221 # Number of stores inserted to the mem dependence unit.
+host_inst_rate 486900 # Simulator instruction rate (inst/s)
+host_mem_usage 1198232 # Number of bytes of host memory used
+host_seconds 3737.50 # Real time elapsed on the host
+host_tick_rate 8500130 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 5623 # Number of instructions simulated
-sim_seconds 0.000000 # Number of seconds simulated
-sim_ticks 6870 # Number of ticks simulated
-system.cpu.commit.COM:branches 862 # Number of branches committed
-system.cpu.commit.COM:bw_lim_events 74 # number cycles where commit BW limit reached
-system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle.samples 6116
-system.cpu.commit.COM:committed_per_cycle.min_value 0
- 0 3908 6389.80%
- 1 1064 1739.70%
- 2 389 636.04%
- 3 210 343.36%
- 4 153 250.16%
- 5 93 152.06%
- 6 76 124.26%
- 7 149 243.62%
- 8 74 120.99%
-system.cpu.commit.COM:committed_per_cycle.max_value 8
-system.cpu.commit.COM:committed_per_cycle.end_dist
-
-system.cpu.commit.COM:count 5640 # Number of instructions committed
-system.cpu.commit.COM:loads 979 # Number of loads committed
-system.cpu.commit.COM:membars 0 # Number of memory barriers committed
-system.cpu.commit.COM:refs 1791 # Number of memory references committed
-system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.branchMispredicts 337 # The number of times a branch was mispredicted
-system.cpu.commit.commitCommittedInsts 5640 # The number of committed instructions
-system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.commitSquashedInsts 4350 # The number of squashed insts skipped by commit
-system.cpu.committedInsts 5623 # Number of Instructions Simulated
-system.cpu.committedInsts_total 5623 # Number of Instructions Simulated
-system.cpu.cpi 1.221768 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 1.221768 # CPI: Total CPI of All Threads
-system.cpu.dcache.ReadReq_accesses 1538 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 3.072000 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2.240000 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits 1413 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 384 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate 0.081274 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses 125 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_hits 25 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_miss_latency 224 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate 0.065020 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses 100 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_accesses 821 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 2.467742 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2.140845 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 635 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 459 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.226553 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 186 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_hits 108 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_miss_latency 152 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.086480 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 71 # number of WriteReq MSHR misses
+sim_insts 1819780129 # Number of instructions simulated
+sim_seconds 0.031769 # Number of seconds simulated
+sim_ticks 31769223012 # Number of ticks simulated
+system.cpu.dcache.ReadReq_accesses 444595663 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 3121.340330 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2121.340330 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits 437373249 # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency 22543612099 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate 0.016245 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses 7222414 # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_miss_latency 15321198099 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate 0.016245 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_misses 7222414 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_accesses 160728502 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_avg_miss_latency 3602.533807 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2602.533807 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits 158839182 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 6806339173 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate 0.011755 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses 1889320 # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_miss_latency 4917019173 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.011755 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses 1889320 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles_no_targets 0.800000 # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 11.505618 # Average number of references to valid blocks.
+system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu.dcache.avg_refs 65.433476 # Average number of references to valid blocks.
system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_no_targets 5 # number of cycles access was blocked
+system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles_no_targets 4 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.demand_accesses 2359 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 2.710611 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 2.198830 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 2048 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 843 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.131836 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 311 # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits 133 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 376 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate 0.072488 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 171 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_accesses 605324165 # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency 3221.115901 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 2221.115901 # average overall mshr miss latency
+system.cpu.dcache.demand_hits 596212431 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 29349951272 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate 0.015053 # miss rate for demand accesses
+system.cpu.dcache.demand_misses 9111734 # number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency 20238217272 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate 0.015053 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses 9111734 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.overall_accesses 2359 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 2.710611 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 2.198830 # average overall mshr miss latency
+system.cpu.dcache.overall_accesses 605324165 # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency 3221.115901 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 2221.115901 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 2048 # number of overall hits
-system.cpu.dcache.overall_miss_latency 843 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.131836 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 311 # number of overall misses
-system.cpu.dcache.overall_mshr_hits 133 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 376 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate 0.072488 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 171 # number of overall MSHR misses
+system.cpu.dcache.overall_hits 596212431 # number of overall hits
+system.cpu.dcache.overall_miss_latency 29349951272 # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate 0.015053 # miss rate for overall accesses
+system.cpu.dcache.overall_misses 9111734 # number of overall misses
+system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_miss_latency 20238217272 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate 0.015053 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses 9111734 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@@ -118,92 +73,57 @@ system.cpu.dcache.prefetcher.num_hwpf_issued 0
system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.dcache.replacements 0 # number of replacements
-system.cpu.dcache.sampled_refs 178 # Sample count of references to valid blocks.
+system.cpu.dcache.replacements 9107638 # number of replacements
+system.cpu.dcache.sampled_refs 9111734 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 119.831029 # Cycle average of tags in use
-system.cpu.dcache.total_refs 2048 # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks 0 # number of writebacks
-system.cpu.decode.DECODE:BlockedCycles 387 # Number of cycles decode is blocked
-system.cpu.decode.DECODE:BranchMispred 93 # Number of times decode detected a branch misprediction
-system.cpu.decode.DECODE:BranchResolved 185 # Number of times decode resolved a branch
-system.cpu.decode.DECODE:DecodedInsts 12349 # Number of instructions handled by decode
-system.cpu.decode.DECODE:IdleCycles 3542 # Number of cycles decode is idle
-system.cpu.decode.DECODE:RunCycles 2158 # Number of cycles decode is running
-system.cpu.decode.DECODE:SquashCycles 754 # Number of cycles decode is squashing
-system.cpu.decode.DECODE:SquashedInsts 286 # Number of squashed instructions handled by decode
-system.cpu.decode.DECODE:UnblockCycles 30 # Number of cycles decode is unblocking
-system.cpu.fetch.Branches 2256 # Number of branches that fetch encountered
-system.cpu.fetch.CacheLines 1582 # Number of cache lines fetched
-system.cpu.fetch.Cycles 3905 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.IcacheSquashes 148 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.Insts 13707 # Number of instructions fetch has processed
-system.cpu.fetch.SquashCycles 456 # Number of cycles fetch has spent squashing
-system.cpu.fetch.branchRate 0.328336 # Number of branch fetches per cycle
-system.cpu.fetch.icacheStallCycles 1582 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.predictedBranches 833 # Number of branches that fetch has predicted taken
-system.cpu.fetch.rate 1.994906 # Number of inst fetches per cycle
-system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist.samples 6871
-system.cpu.fetch.rateDist.min_value 0
- 0 4549 6620.58%
- 1 174 253.24%
- 2 186 270.70%
- 3 157 228.50%
- 4 211 307.09%
- 5 153 222.68%
- 6 171 248.87%
- 7 105 152.82%
- 8 1165 1695.53%
-system.cpu.fetch.rateDist.max_value 8
-system.cpu.fetch.rateDist.end_dist
-
-system.cpu.icache.ReadReq_accesses 1582 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 2.960245 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 1.996885 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits 1255 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 968 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate 0.206700 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses 327 # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_hits 6 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_miss_latency 641 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.202908 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses 321 # number of ReadReq MSHR misses
-system.cpu.icache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles_no_targets no value # average number of cycles each access was blocked
-system.cpu.icache.avg_refs 3.909657 # Average number of references to valid blocks.
+system.cpu.dcache.tagsinuse 4091.845274 # Cycle average of tags in use
+system.cpu.dcache.total_refs 596212431 # Total number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 75264000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.writebacks 2244708 # number of writebacks
+system.cpu.icache.ReadReq_accesses 1819780130 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency 4089.753117 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 3089.753117 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits 1819779328 # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency 3279982 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_rate 0.000000 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_misses 802 # number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_miss_latency 2477982 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate 0.000000 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_misses 802 # number of ReadReq MSHR misses
+system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu.icache.avg_refs 2269051.531172 # Average number of references to valid blocks.
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.demand_accesses 1582 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 2.960245 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 1.996885 # average overall mshr miss latency
-system.cpu.icache.demand_hits 1255 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 968 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate 0.206700 # miss rate for demand accesses
-system.cpu.icache.demand_misses 327 # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_hits 6 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 641 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate 0.202908 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses 321 # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_accesses 1819780130 # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency 4089.753117 # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 3089.753117 # average overall mshr miss latency
+system.cpu.icache.demand_hits 1819779328 # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency 3279982 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_rate 0.000000 # miss rate for demand accesses
+system.cpu.icache.demand_misses 802 # number of demand (read+write) misses
+system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_miss_latency 2477982 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_rate 0.000000 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_misses 802 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.overall_accesses 1582 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 2.960245 # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 1.996885 # average overall mshr miss latency
+system.cpu.icache.overall_accesses 1819780130 # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency 4089.753117 # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 3089.753117 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits 1255 # number of overall hits
-system.cpu.icache.overall_miss_latency 968 # number of overall miss cycles
-system.cpu.icache.overall_miss_rate 0.206700 # miss rate for overall accesses
-system.cpu.icache.overall_misses 327 # number of overall misses
-system.cpu.icache.overall_mshr_hits 6 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 641 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate 0.202908 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses 321 # number of overall MSHR misses
+system.cpu.icache.overall_hits 1819779328 # number of overall hits
+system.cpu.icache.overall_miss_latency 3279982 # number of overall miss cycles
+system.cpu.icache.overall_miss_rate 0.000000 # miss rate for overall accesses
+system.cpu.icache.overall_misses 802 # number of overall misses
+system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_miss_latency 2477982 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_rate 0.000000 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_misses 802 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@@ -215,1726 +135,64 @@ system.cpu.icache.prefetcher.num_hwpf_issued 0
system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.icache.replacements 0 # number of replacements
-system.cpu.icache.sampled_refs 321 # Sample count of references to valid blocks.
+system.cpu.icache.replacements 1 # number of replacements
+system.cpu.icache.sampled_refs 802 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 176.393247 # Cycle average of tags in use
-system.cpu.icache.total_refs 1255 # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse 625.996248 # Cycle average of tags in use
+system.cpu.icache.total_refs 1819779328 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.iew.EXEC:branches 1206 # Number of branches executed
-system.cpu.iew.EXEC:insts 7969 # Number of executed instructions
-system.cpu.iew.EXEC:loads 1610 # Number of load instructions executed
-system.cpu.iew.EXEC:nop 37 # number of nop insts executed
-system.cpu.iew.EXEC:rate 1.159802 # Inst execution rate
-system.cpu.iew.EXEC:refs 2599 # number of memory reference insts executed
-system.cpu.iew.EXEC:squashedInsts 419 # Number of squashed instructions skipped in execute
-system.cpu.iew.EXEC:stores 989 # Number of stores executed
-system.cpu.iew.EXEC:swp 0 # number of swp insts executed
-system.cpu.iew.WB:consumers 5438 # num instructions consuming a value
-system.cpu.iew.WB:count 7722 # cumulative count of insts written-back
-system.cpu.iew.WB:fanout 0.744575 # average fanout of values written-back
-system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.iew.WB:producers 4049 # num instructions producing a value
-system.cpu.iew.WB:rate 1.123854 # insts written-back per cycle
-system.cpu.iew.WB:sent 7762 # cumulative count of insts sent to commit
-system.cpu.iew.branchMispredicts 393 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewBlockCycles 4 # Number of cycles IEW is blocking
-system.cpu.iew.iewDispLoadInsts 2050 # Number of dispatched load instructions
-system.cpu.iew.iewDispNonSpecInsts 21 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewDispSquashedInsts 272 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispStoreInsts 1221 # Number of dispatched store instructions
-system.cpu.iew.iewDispatchedInsts 9990 # Number of instructions dispatched to IQ
-system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.iewSquashCycles 754 # Number of cycles IEW is squashing
-system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking
-system.cpu.iew.lsq.thread.0.blockedLoads 1 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread.0.cacheBlocked 5 # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.lsq.thread.0.forwLoads 55 # Number of loads that had data forwarded from stores
-system.cpu.iew.lsq.thread.0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
-system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread.0.squashedLoads 1071 # Number of loads squashed
-system.cpu.iew.lsq.thread.0.squashedStores 409 # Number of stores squashed
-system.cpu.iew.memOrderViolationEvents 41 # Number of memory order violations
-system.cpu.iew.predictedNotTakenIncorrect 296 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.predictedTakenIncorrect 97 # Number of branches that were predicted taken incorrectly
-system.cpu.ipc 0.818486 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.818486 # IPC: Total IPC of All Threads
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-
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-
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-
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-
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-
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-
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-
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-
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-
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-
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-
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-
-system.cpu.iq.ISSUE:FloatCvt_delay.start_dist # cycles from operands ready to issue
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-
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- 56 0
- 58 0
- 60 0
- 62 0
- 64 0
- 66 0
- 68 0
- 70 0
- 72 0
- 74 0
- 76 0
- 78 0
- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.ISSUE:FloatMult_delay.max_value 0
-system.cpu.iq.ISSUE:FloatMult_delay.end_dist
-
-system.cpu.iq.ISSUE:FloatDiv_delay.start_dist # cycles from operands ready to issue
-system.cpu.iq.ISSUE:FloatDiv_delay.samples 0
-system.cpu.iq.ISSUE:FloatDiv_delay.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
- 20 0
- 22 0
- 24 0
- 26 0
- 28 0
- 30 0
- 32 0
- 34 0
- 36 0
- 38 0
- 40 0
- 42 0
- 44 0
- 46 0
- 48 0
- 50 0
- 52 0
- 54 0
- 56 0
- 58 0
- 60 0
- 62 0
- 64 0
- 66 0
- 68 0
- 70 0
- 72 0
- 74 0
- 76 0
- 78 0
- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.ISSUE:FloatDiv_delay.max_value 0
-system.cpu.iq.ISSUE:FloatDiv_delay.end_dist
-
-system.cpu.iq.ISSUE:FloatSqrt_delay.start_dist # cycles from operands ready to issue
-system.cpu.iq.ISSUE:FloatSqrt_delay.samples 0
-system.cpu.iq.ISSUE:FloatSqrt_delay.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
- 20 0
- 22 0
- 24 0
- 26 0
- 28 0
- 30 0
- 32 0
- 34 0
- 36 0
- 38 0
- 40 0
- 42 0
- 44 0
- 46 0
- 48 0
- 50 0
- 52 0
- 54 0
- 56 0
- 58 0
- 60 0
- 62 0
- 64 0
- 66 0
- 68 0
- 70 0
- 72 0
- 74 0
- 76 0
- 78 0
- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.ISSUE:FloatSqrt_delay.max_value 0
-system.cpu.iq.ISSUE:FloatSqrt_delay.end_dist
-
-system.cpu.iq.ISSUE:MemRead_delay.start_dist # cycles from operands ready to issue
-system.cpu.iq.ISSUE:MemRead_delay.samples 0
-system.cpu.iq.ISSUE:MemRead_delay.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
- 20 0
- 22 0
- 24 0
- 26 0
- 28 0
- 30 0
- 32 0
- 34 0
- 36 0
- 38 0
- 40 0
- 42 0
- 44 0
- 46 0
- 48 0
- 50 0
- 52 0
- 54 0
- 56 0
- 58 0
- 60 0
- 62 0
- 64 0
- 66 0
- 68 0
- 70 0
- 72 0
- 74 0
- 76 0
- 78 0
- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.ISSUE:MemRead_delay.max_value 0
-system.cpu.iq.ISSUE:MemRead_delay.end_dist
-
-system.cpu.iq.ISSUE:MemWrite_delay.start_dist # cycles from operands ready to issue
-system.cpu.iq.ISSUE:MemWrite_delay.samples 0
-system.cpu.iq.ISSUE:MemWrite_delay.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
- 20 0
- 22 0
- 24 0
- 26 0
- 28 0
- 30 0
- 32 0
- 34 0
- 36 0
- 38 0
- 40 0
- 42 0
- 44 0
- 46 0
- 48 0
- 50 0
- 52 0
- 54 0
- 56 0
- 58 0
- 60 0
- 62 0
- 64 0
- 66 0
- 68 0
- 70 0
- 72 0
- 74 0
- 76 0
- 78 0
- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.ISSUE:MemWrite_delay.max_value 0
-system.cpu.iq.ISSUE:MemWrite_delay.end_dist
-
-system.cpu.iq.ISSUE:IprAccess_delay.start_dist # cycles from operands ready to issue
-system.cpu.iq.ISSUE:IprAccess_delay.samples 0
-system.cpu.iq.ISSUE:IprAccess_delay.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
- 20 0
- 22 0
- 24 0
- 26 0
- 28 0
- 30 0
- 32 0
- 34 0
- 36 0
- 38 0
- 40 0
- 42 0
- 44 0
- 46 0
- 48 0
- 50 0
- 52 0
- 54 0
- 56 0
- 58 0
- 60 0
- 62 0
- 64 0
- 66 0
- 68 0
- 70 0
- 72 0
- 74 0
- 76 0
- 78 0
- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.ISSUE:IprAccess_delay.max_value 0
-system.cpu.iq.ISSUE:IprAccess_delay.end_dist
-
-system.cpu.iq.ISSUE:InstPrefetch_delay.start_dist # cycles from operands ready to issue
-system.cpu.iq.ISSUE:InstPrefetch_delay.samples 0
-system.cpu.iq.ISSUE:InstPrefetch_delay.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
- 20 0
- 22 0
- 24 0
- 26 0
- 28 0
- 30 0
- 32 0
- 34 0
- 36 0
- 38 0
- 40 0
- 42 0
- 44 0
- 46 0
- 48 0
- 50 0
- 52 0
- 54 0
- 56 0
- 58 0
- 60 0
- 62 0
- 64 0
- 66 0
- 68 0
- 70 0
- 72 0
- 74 0
- 76 0
- 78 0
- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.ISSUE:InstPrefetch_delay.max_value 0
-system.cpu.iq.ISSUE:InstPrefetch_delay.end_dist
-
-system.cpu.iq.ISSUE:FU_type_0 8388 # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0.start_dist
- (null) 2 0.02% # Type of FU issued
- IntAlu 5594 66.69% # Type of FU issued
- IntMult 1 0.01% # Type of FU issued
- IntDiv 0 0.00% # Type of FU issued
- FloatAdd 2 0.02% # Type of FU issued
- FloatCmp 0 0.00% # Type of FU issued
- FloatCvt 0 0.00% # Type of FU issued
- FloatMult 0 0.00% # Type of FU issued
- FloatDiv 0 0.00% # Type of FU issued
- FloatSqrt 0 0.00% # Type of FU issued
- MemRead 1757 20.95% # Type of FU issued
- MemWrite 1032 12.30% # Type of FU issued
- IprAccess 0 0.00% # Type of FU issued
- InstPrefetch 0 0.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0.end_dist
-system.cpu.iq.ISSUE:fu_busy_cnt 115 # FU busy when requested
-system.cpu.iq.ISSUE:fu_busy_rate 0.013710 # FU busy rate (busy events/executed inst)
-system.cpu.iq.ISSUE:fu_full.start_dist
- (null) 0 0.00% # attempts to use FU when none available
- IntAlu 1 0.87% # attempts to use FU when none available
- IntMult 0 0.00% # attempts to use FU when none available
- IntDiv 0 0.00% # attempts to use FU when none available
- FloatAdd 0 0.00% # attempts to use FU when none available
- FloatCmp 0 0.00% # attempts to use FU when none available
- FloatCvt 0 0.00% # attempts to use FU when none available
- FloatMult 0 0.00% # attempts to use FU when none available
- FloatDiv 0 0.00% # attempts to use FU when none available
- FloatSqrt 0 0.00% # attempts to use FU when none available
- MemRead 76 66.09% # attempts to use FU when none available
- MemWrite 38 33.04% # attempts to use FU when none available
- IprAccess 0 0.00% # attempts to use FU when none available
- InstPrefetch 0 0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full.end_dist
-system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle.samples 6871
-system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
- 0 3753 5462.09%
- 1 894 1301.12%
- 2 723 1052.25%
- 3 614 893.61%
- 4 451 656.38%
- 5 279 406.05%
- 6 104 151.36%
- 7 41 59.67%
- 8 12 17.46%
-system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
-system.cpu.iq.ISSUE:issued_per_cycle.end_dist
-
-system.cpu.iq.ISSUE:rate 1.220783 # Inst issue rate
-system.cpu.iq.iqInstsAdded 9932 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqInstsIssued 8388 # Number of instructions issued
-system.cpu.iq.iqNonSpecInstsAdded 21 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqSquashedInstsExamined 3990 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedInstsIssued 21 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedNonSpecRemoved 4 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.iqSquashedOperandsExamined 2486 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.l2cache.ReadReq_accesses 499 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 2.042254 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency 1015 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate 0.995992 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses 497 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 490 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.981964 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses 490 # number of ReadReq MSHR misses
+system.cpu.idle_fraction 0 # Percentage of idle cycles
+system.cpu.l2cache.ReadReq_accesses 9112536 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_avg_miss_latency 3215.890455 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1919.394872 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_hits 6952383 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_miss_latency 6946815413 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate 0.237053 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses 2160153 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency 4146186590 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.237053 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses 2160153 # number of ReadReq MSHR misses
+system.cpu.l2cache.WriteReqNoAck|Writeback_accesses 2244708 # number of WriteReqNoAck|Writeback accesses(hits+misses)
+system.cpu.l2cache.WriteReqNoAck|Writeback_hits 2215611 # number of WriteReqNoAck|Writeback hits
+system.cpu.l2cache.WriteReqNoAck|Writeback_miss_rate 0.012962 # miss rate for WriteReqNoAck|Writeback accesses
+system.cpu.l2cache.WriteReqNoAck|Writeback_misses 29097 # number of WriteReqNoAck|Writeback misses
+system.cpu.l2cache.WriteReqNoAck|Writeback_mshr_miss_rate 0.012962 # mshr miss rate for WriteReqNoAck|Writeback accesses
+system.cpu.l2cache.WriteReqNoAck|Writeback_mshr_misses 29097 # number of WriteReqNoAck|Writeback MSHR misses
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs 0.004024 # Average number of references to valid blocks.
+system.cpu.l2cache.avg_refs 4.244141 # Average number of references to valid blocks.
system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.demand_accesses 499 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 2.042254 # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 1 # average overall mshr miss latency
-system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 1015 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate 0.995992 # miss rate for demand accesses
-system.cpu.l2cache.demand_misses 497 # number of demand (read+write) misses
+system.cpu.l2cache.demand_accesses 9112536 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_avg_miss_latency 3215.890455 # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 1919.394872 # average overall mshr miss latency
+system.cpu.l2cache.demand_hits 6952383 # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency 6946815413 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate 0.237053 # miss rate for demand accesses
+system.cpu.l2cache.demand_misses 2160153 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency 490 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate 0.981964 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses 490 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_miss_latency 4146186590 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate 0.237053 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses 2160153 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.overall_accesses 499 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 2.042254 # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 1 # average overall mshr miss latency
+system.cpu.l2cache.overall_accesses 11357244 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_avg_miss_latency 3173.148527 # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 1919.394872 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits 2 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 1015 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate 0.995992 # miss rate for overall accesses
-system.cpu.l2cache.overall_misses 497 # number of overall misses
+system.cpu.l2cache.overall_hits 9167994 # number of overall hits
+system.cpu.l2cache.overall_miss_latency 6946815413 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate 0.192762 # miss rate for overall accesses
+system.cpu.l2cache.overall_misses 2189250 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 490 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate 0.981964 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses 490 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_miss_latency 4146186590 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate 0.190200 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses 2160153 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@@ -1946,29 +204,17 @@ system.cpu.l2cache.prefetcher.num_hwpf_issued 0
system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.l2cache.replacements 0 # number of replacements
-system.cpu.l2cache.sampled_refs 497 # Sample count of references to valid blocks.
+system.cpu.l2cache.replacements 2127385 # number of replacements
+system.cpu.l2cache.sampled_refs 2160153 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 295.773395 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks 0 # number of writebacks
-system.cpu.numCycles 6871 # number of cpu cycles simulated
-system.cpu.rename.RENAME:BlockCycles 4 # Number of cycles rename is blocking
-system.cpu.rename.RENAME:CommittedMaps 4051 # Number of HB maps that are committed
-system.cpu.rename.RENAME:IdleCycles 3758 # Number of cycles rename is idle
-system.cpu.rename.RENAME:LSQFullEvents 62 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RENAME:RenameLookups 14786 # Number of register rename lookups that rename has made
-system.cpu.rename.RENAME:RenamedInsts 11555 # Number of instructions processed by rename
-system.cpu.rename.RENAME:RenamedOperands 8634 # Number of destination operands rename has renamed
-system.cpu.rename.RENAME:RunCycles 1975 # Number of cycles rename is running
-system.cpu.rename.RENAME:SquashCycles 754 # Number of cycles rename is squashing
-system.cpu.rename.RENAME:UnblockCycles 111 # Number of cycles rename is unblocking
-system.cpu.rename.RENAME:UndoneMaps 4583 # Number of HB maps that are undone due to squashing
-system.cpu.rename.RENAME:serializeStallCycles 269 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RENAME:serializingInsts 26 # count of serializing insts renamed
-system.cpu.rename.RENAME:skidInsts 408 # count of insts added to the skid buffer
-system.cpu.rename.RENAME:tempSerializingInsts 21 # count of temporary serializing insts renamed
-system.cpu.workload.PROG:num_syscalls 17 # Number of system calls
+system.cpu.l2cache.tagsinuse 32563.117941 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 9167994 # Total number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle 748591000 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.writebacks 1038202 # number of writebacks
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.numCycles 31769223012 # number of cpu cycles simulated
+system.cpu.num_insts 1819780129 # Number of instructions executed
+system.cpu.num_refs 606571345 # Number of memory references
+system.cpu.workload.PROG:num_syscalls 29 # Number of system calls
---------- End Simulation Statistics ----------
diff --git a/tests/long/60.bzip2/ref/alpha/linux/simple-timing/stderr b/tests/long/60.bzip2/ref/alpha/linux/simple-timing/stderr
index 8893caac8..87866a2a5 100644
--- a/tests/long/60.bzip2/ref/alpha/linux/simple-timing/stderr
+++ b/tests/long/60.bzip2/ref/alpha/linux/simple-timing/stderr
@@ -1,3 +1 @@
warn: Entering event queue @ 0. Starting simulation...
-warn: cycle 0: fault (page_table_fault) detected @ PC 0x000000
-warn: Increasing stack 0x11ff92000:0x11ff9b000 to 0x11ff90000:0x11ff9b000 because of access to 0x11ff91ff0
diff --git a/tests/long/60.bzip2/ref/alpha/linux/simple-timing/stdout b/tests/long/60.bzip2/ref/alpha/linux/simple-timing/stdout
index fbb329a2f..0c5c00118 100644
--- a/tests/long/60.bzip2/ref/alpha/linux/simple-timing/stdout
+++ b/tests/long/60.bzip2/ref/alpha/linux/simple-timing/stdout
@@ -1,13 +1,14 @@
-Hello world!
-M5 Simulator System
-
-Copyright (c) 2001-2006
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Sep 5 2006 15:28:48
-M5 started Tue Sep 5 15:42:12 2006
-M5 executing on zizzer.eecs.umich.edu
-command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/o3-timing tests/run.py quick/00.hello/alpha/linux/o3-timing
-Exiting @ tick 6870 because target called exit()
+spec_init
+Loading Input Data
+Input data 1048576 bytes in length
+Compressing Input Data, level 7
+Compressed data 198546 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Compressing Input Data, level 9
+Compressed data 198677 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Tested 1MB buffer: OK!
diff --git a/tests/long/70.twolf/ref/alpha/linux/o3-timing/config.ini b/tests/long/70.twolf/ref/alpha/linux/o3-timing/config.ini
index c3a59fbce..fb3d24c55 100644
--- a/tests/long/70.twolf/ref/alpha/linux/o3-timing/config.ini
+++ b/tests/long/70.twolf/ref/alpha/linux/o3-timing/config.ini
@@ -7,11 +7,9 @@ max_tick=0
output_file=cout
progress_interval=0
-[debug]
-break_cycles=
-
[exetrace]
intel_format=false
+legion_lockstep=false
pc_symbol=true
print_cpseq=false
print_cycle=true
@@ -102,14 +100,15 @@ max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
-mem=system.cpu.dcache
numIQEntries=64
numPhysFloatRegs=256
numPhysIntRegs=256
numROBEntries=192
numRobs=1
numThreads=1
+phase=0
predType=tournament
+progress_interval=0
renameToDecodeDelay=1
renameToFetchDelay=1
renameToIEWDelay=2
@@ -131,7 +130,6 @@ assoc=2
block_size=64
compressed_bus=false
compression_latency=0
-do_copy=false
hash_delay=1
hit_latency=1
latency=1
@@ -308,7 +306,6 @@ assoc=2
block_size=64
compressed_bus=false
compression_latency=0
-do_copy=false
hash_delay=1
hit_latency=1
latency=1
@@ -348,7 +345,6 @@ assoc=2
block_size=64
compressed_bus=false
compression_latency=0
-do_copy=false
hash_delay=1
hit_latency=1
latency=1
@@ -384,20 +380,33 @@ mem_side=system.membus.port[1]
[system.cpu.toL2Bus]
type=Bus
bus_id=0
+clock=1000
+responder_set=false
+width=64
port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
[system.cpu.workload]
type=LiveProcess
-cmd=hello
+cmd=twolf smred
+cwd=build/ALPHA_SE/tests/opt/long/70.twolf/alpha/linux/o3-timing
+egid=100
env=
-executable=tests/test-progs/hello/bin/alpha/linux/hello
+euid=100
+executable=/dist/m5/cpu2000/binaries/alpha/tru64/twolf
+gid=100
input=cin
output=cout
+pid=100
+ppid=99
system=system
+uid=100
[system.membus]
type=Bus
bus_id=0
+clock=1000
+responder_set=false
+width=64
port=system.physmem.port system.cpu.l2cache.mem_side
[system.physmem]
@@ -409,6 +418,7 @@ port=system.membus.port[0]
[trace]
bufsize=0
+cycle=0
dump_on_exit=false
file=cout
flags=
diff --git a/tests/long/70.twolf/ref/alpha/linux/o3-timing/config.out b/tests/long/70.twolf/ref/alpha/linux/o3-timing/config.out
index f491a3081..e4ed95acf 100644
--- a/tests/long/70.twolf/ref/alpha/linux/o3-timing/config.out
+++ b/tests/long/70.twolf/ref/alpha/linux/o3-timing/config.out
@@ -19,54 +19,25 @@ mem_mode=atomic
[system.membus]
type=Bus
bus_id=0
+clock=1000
+width=64
+responder_set=false
[system.cpu.workload]
type=LiveProcess
-cmd=hello
-executable=tests/test-progs/hello/bin/alpha/linux/hello
+cmd=twolf smred
+executable=/dist/m5/cpu2000/binaries/alpha/tru64/twolf
input=cin
output=cout
env=
+cwd=build/ALPHA_SE/tests/opt/long/70.twolf/alpha/linux/o3-timing
system=system
-
-[system.cpu.dcache]
-type=BaseCache
-size=262144
-assoc=2
-block_size=64
-latency=1
-mshrs=10
-tgts_per_mshr=5
-write_buffers=8
-prioritizeRequests=false
-do_copy=false
-protocol=null
-trace_addr=0
-hash_delay=1
-repl=null
-compressed_bus=false
-store_compressed=false
-adaptive_compression=false
-compression_latency=0
-block_size=64
-max_miss_count=0
-addr_range=[0,18446744073709551615]
-split=false
-split_size=0
-lifo=false
-two_queue=false
-prefetch_miss=false
-prefetch_access=false
-prefetcher_size=100
-prefetch_past_page=false
-prefetch_serial_squash=false
-prefetch_latency=10
-prefetch_degree=1
-prefetch_policy=none
-prefetch_cache_check_push=true
-prefetch_use_cpu_id=true
-prefetch_data_accesses_only=false
-hit_latency=1
+uid=100
+euid=100
+gid=100
+egid=100
+pid=100
+ppid=99
[system.cpu.fuPool.FUList0.opList0]
type=OpDesc
@@ -199,15 +170,16 @@ FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUL
[system.cpu]
type=DerivO3CPU
clock=1
+phase=0
numThreads=1
activity=0
workload=system.cpu.workload
-mem=system.cpu.dcache
checker=null
max_insts_any_thread=0
max_insts_all_threads=0
max_loads_any_thread=0
max_loads_all_threads=0
+progress_interval=0
cachePorts=200
decodeToFetchDelay=1
renameToFetchDelay=1
@@ -283,7 +255,44 @@ mshrs=10
tgts_per_mshr=5
write_buffers=8
prioritizeRequests=false
-do_copy=false
+protocol=null
+trace_addr=0
+hash_delay=1
+repl=null
+compressed_bus=false
+store_compressed=false
+adaptive_compression=false
+compression_latency=0
+block_size=64
+max_miss_count=0
+addr_range=[0,18446744073709551615]
+split=false
+split_size=0
+lifo=false
+two_queue=false
+prefetch_miss=false
+prefetch_access=false
+prefetcher_size=100
+prefetch_past_page=false
+prefetch_serial_squash=false
+prefetch_latency=10
+prefetch_degree=1
+prefetch_policy=none
+prefetch_cache_check_push=true
+prefetch_use_cpu_id=true
+prefetch_data_accesses_only=false
+hit_latency=1
+
+[system.cpu.dcache]
+type=BaseCache
+size=262144
+assoc=2
+block_size=64
+latency=1
+mshrs=10
+tgts_per_mshr=5
+write_buffers=8
+prioritizeRequests=false
protocol=null
trace_addr=0
hash_delay=1
@@ -322,7 +331,6 @@ mshrs=10
tgts_per_mshr=5
write_buffers=8
prioritizeRequests=false
-do_copy=false
protocol=null
trace_addr=0
hash_delay=1
@@ -354,10 +362,14 @@ hit_latency=1
[system.cpu.toL2Bus]
type=Bus
bus_id=0
+clock=1000
+width=64
+responder_set=false
[trace]
flags=
start=0
+cycle=0
bufsize=0
file=cout
dump_on_exit=false
@@ -396,8 +408,9 @@ print_cpseq=false
print_reg_delta=false
pc_symbol=true
intel_format=false
+legion_lockstep=false
trace_system=client
-[debug]
-break_cycles=
+[statsreset]
+reset_cycle=0
diff --git a/tests/long/70.twolf/ref/alpha/linux/o3-timing/m5stats.txt b/tests/long/70.twolf/ref/alpha/linux/o3-timing/m5stats.txt
index 5d4f9235a..dfa1fbe0b 100644
--- a/tests/long/70.twolf/ref/alpha/linux/o3-timing/m5stats.txt
+++ b/tests/long/70.twolf/ref/alpha/linux/o3-timing/m5stats.txt
@@ -1,112 +1,112 @@
---------- Begin Simulation Statistics ----------
global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-global.BPredUnit.BTBHits 542 # Number of BTB hits
-global.BPredUnit.BTBLookups 1938 # Number of BTB lookups
-global.BPredUnit.RASInCorrect 48 # Number of incorrect RAS predictions.
-global.BPredUnit.condIncorrect 420 # Number of conditional branches incorrect
-global.BPredUnit.condPredicted 1304 # Number of conditional branches predicted
-global.BPredUnit.lookups 2256 # Number of BP lookups
-global.BPredUnit.usedRAS 291 # Number of times the RAS was used to get a target.
-host_inst_rate 41797 # Simulator instruction rate (inst/s)
-host_mem_usage 160344 # Number of bytes of host memory used
-host_seconds 0.13 # Real time elapsed on the host
-host_tick_rate 50948 # Simulator tick rate (ticks/s)
-memdepunit.memDep.conflictingLoads 12 # Number of conflicting loads.
-memdepunit.memDep.conflictingStores 259 # Number of conflicting stores.
-memdepunit.memDep.insertedLoads 2050 # Number of loads inserted to the mem dependence unit.
-memdepunit.memDep.insertedStores 1221 # Number of stores inserted to the mem dependence unit.
+global.BPredUnit.BTBHits 11837684 # Number of BTB hits
+global.BPredUnit.BTBLookups 15197122 # Number of BTB lookups
+global.BPredUnit.RASInCorrect 1217 # Number of incorrect RAS predictions.
+global.BPredUnit.condIncorrect 1998573 # Number of conditional branches incorrect
+global.BPredUnit.condPredicted 12917224 # Number of conditional branches predicted
+global.BPredUnit.lookups 17533197 # Number of BP lookups
+global.BPredUnit.usedRAS 1687018 # Number of times the RAS was used to get a target.
+host_inst_rate 57997 # Simulator instruction rate (inst/s)
+host_mem_usage 178748 # Number of bytes of host memory used
+host_seconds 1423.90 # Real time elapsed on the host
+host_tick_rate 73521 # Simulator tick rate (ticks/s)
+memdepunit.memDep.conflictingLoads 10104667 # Number of conflicting loads.
+memdepunit.memDep.conflictingStores 3292311 # Number of conflicting stores.
+memdepunit.memDep.insertedLoads 29530804 # Number of loads inserted to the mem dependence unit.
+memdepunit.memDep.insertedStores 9370879 # Number of stores inserted to the mem dependence unit.
sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 5623 # Number of instructions simulated
-sim_seconds 0.000000 # Number of seconds simulated
-sim_ticks 6870 # Number of ticks simulated
-system.cpu.commit.COM:branches 862 # Number of branches committed
-system.cpu.commit.COM:bw_lim_events 74 # number cycles where commit BW limit reached
+sim_insts 82582323 # Number of instructions simulated
+sim_seconds 0.000105 # Number of seconds simulated
+sim_ticks 104686099 # Number of ticks simulated
+system.cpu.commit.COM:branches 10071057 # Number of branches committed
+system.cpu.commit.COM:bw_lim_events 3175901 # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle.samples 6116
+system.cpu.commit.COM:committed_per_cycle.samples 65490840
system.cpu.commit.COM:committed_per_cycle.min_value 0
- 0 3908 6389.80%
- 1 1064 1739.70%
- 2 389 636.04%
- 3 210 343.36%
- 4 153 250.16%
- 5 93 152.06%
- 6 76 124.26%
- 7 149 243.62%
- 8 74 120.99%
+ 0 32034998 4891.52%
+ 1 13785472 2104.95%
+ 2 8057025 1230.25%
+ 3 3669149 560.25%
+ 4 1988059 303.56%
+ 5 1377349 210.31%
+ 6 785420 119.93%
+ 7 617467 94.28%
+ 8 3175901 484.94%
system.cpu.commit.COM:committed_per_cycle.max_value 8
system.cpu.commit.COM:committed_per_cycle.end_dist
-system.cpu.commit.COM:count 5640 # Number of instructions committed
-system.cpu.commit.COM:loads 979 # Number of loads committed
+system.cpu.commit.COM:count 90187947 # Number of instructions committed
+system.cpu.commit.COM:loads 19613586 # Number of loads committed
system.cpu.commit.COM:membars 0 # Number of memory barriers committed
-system.cpu.commit.COM:refs 1791 # Number of memory references committed
+system.cpu.commit.COM:refs 25981086 # Number of memory references committed
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.branchMispredicts 337 # The number of times a branch was mispredicted
-system.cpu.commit.commitCommittedInsts 5640 # The number of committed instructions
-system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.commitSquashedInsts 4350 # The number of squashed insts skipped by commit
-system.cpu.committedInsts 5623 # Number of Instructions Simulated
-system.cpu.committedInsts_total 5623 # Number of Instructions Simulated
-system.cpu.cpi 1.221768 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 1.221768 # CPI: Total CPI of All Threads
-system.cpu.dcache.ReadReq_accesses 1538 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 3.072000 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2.240000 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits 1413 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 384 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate 0.081274 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses 125 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_hits 25 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_miss_latency 224 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate 0.065020 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses 100 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_accesses 821 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 2.467742 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2.140845 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 635 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 459 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.226553 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 186 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_hits 108 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_miss_latency 152 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.086480 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 71 # number of WriteReq MSHR misses
-system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles_no_targets 0.800000 # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 11.505618 # Average number of references to valid blocks.
-system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_no_targets 5 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles_no_targets 4 # number of cycles access was blocked
+system.cpu.commit.branchMispredicts 1985168 # The number of times a branch was mispredicted
+system.cpu.commit.commitCommittedInsts 90187947 # The number of committed instructions
+system.cpu.commit.commitNonSpecStalls 387 # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.commitSquashedInsts 40679620 # The number of squashed insts skipped by commit
+system.cpu.committedInsts 82582323 # Number of Instructions Simulated
+system.cpu.committedInsts_total 82582323 # Number of Instructions Simulated
+system.cpu.cpi 1.267657 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 1.267657 # CPI: Total CPI of All Threads
+system.cpu.dcache.ReadReq_accesses 22673452 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 5439.841232 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 4838.693712 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits 22672608 # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency 4591226 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate 0.000037 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses 844 # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_hits 351 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_miss_latency 2385476 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate 0.000022 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_misses 493 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_accesses 6365908 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_avg_miss_latency 5074.130393 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 4849.051425 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits 6360739 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 26228180 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate 0.000812 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses 5169 # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_hits 3555 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_miss_latency 7826369 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.000254 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses 1614 # number of WriteReq MSHR misses
+system.cpu.dcache.avg_blocked_cycles_no_mshrs 2811.600000 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles_no_targets 3114.692857 # average number of cycles each access was blocked
+system.cpu.dcache.avg_refs 13779.471761 # Average number of references to valid blocks.
+system.cpu.dcache.blocked_no_mshrs 10 # number of cycles access was blocked
+system.cpu.dcache.blocked_no_targets 700 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles_no_mshrs 28116 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles_no_targets 2180285 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.demand_accesses 2359 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 2.710611 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 2.198830 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 2048 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 843 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.131836 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 311 # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits 133 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 376 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate 0.072488 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 171 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_accesses 29039360 # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency 5125.462498 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 4846.627907 # average overall mshr miss latency
+system.cpu.dcache.demand_hits 29033347 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 30819406 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate 0.000207 # miss rate for demand accesses
+system.cpu.dcache.demand_misses 6013 # number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits 3906 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency 10211845 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate 0.000073 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses 2107 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.overall_accesses 2359 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 2.710611 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 2.198830 # average overall mshr miss latency
+system.cpu.dcache.overall_accesses 29039360 # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency 5125.462498 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 4846.627907 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 2048 # number of overall hits
-system.cpu.dcache.overall_miss_latency 843 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.131836 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 311 # number of overall misses
-system.cpu.dcache.overall_mshr_hits 133 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 376 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate 0.072488 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 171 # number of overall MSHR misses
+system.cpu.dcache.overall_hits 29033347 # number of overall hits
+system.cpu.dcache.overall_miss_latency 30819406 # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate 0.000207 # miss rate for overall accesses
+system.cpu.dcache.overall_misses 6013 # number of overall misses
+system.cpu.dcache.overall_mshr_hits 3906 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_miss_latency 10211845 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate 0.000073 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses 2107 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@@ -118,92 +118,92 @@ system.cpu.dcache.prefetcher.num_hwpf_issued 0
system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.dcache.replacements 0 # number of replacements
-system.cpu.dcache.sampled_refs 178 # Sample count of references to valid blocks.
+system.cpu.dcache.replacements 104 # number of replacements
+system.cpu.dcache.sampled_refs 2107 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 119.831029 # Cycle average of tags in use
-system.cpu.dcache.total_refs 2048 # Total number of references to valid blocks.
+system.cpu.dcache.tagsinuse 1404.053454 # Cycle average of tags in use
+system.cpu.dcache.total_refs 29033347 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks 0 # number of writebacks
-system.cpu.decode.DECODE:BlockedCycles 387 # Number of cycles decode is blocked
-system.cpu.decode.DECODE:BranchMispred 93 # Number of times decode detected a branch misprediction
-system.cpu.decode.DECODE:BranchResolved 185 # Number of times decode resolved a branch
-system.cpu.decode.DECODE:DecodedInsts 12349 # Number of instructions handled by decode
-system.cpu.decode.DECODE:IdleCycles 3542 # Number of cycles decode is idle
-system.cpu.decode.DECODE:RunCycles 2158 # Number of cycles decode is running
-system.cpu.decode.DECODE:SquashCycles 754 # Number of cycles decode is squashing
-system.cpu.decode.DECODE:SquashedInsts 286 # Number of squashed instructions handled by decode
-system.cpu.decode.DECODE:UnblockCycles 30 # Number of cycles decode is unblocking
-system.cpu.fetch.Branches 2256 # Number of branches that fetch encountered
-system.cpu.fetch.CacheLines 1582 # Number of cache lines fetched
-system.cpu.fetch.Cycles 3905 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.IcacheSquashes 148 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.Insts 13707 # Number of instructions fetch has processed
-system.cpu.fetch.SquashCycles 456 # Number of cycles fetch has spent squashing
-system.cpu.fetch.branchRate 0.328336 # Number of branch fetches per cycle
-system.cpu.fetch.icacheStallCycles 1582 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.predictedBranches 833 # Number of branches that fetch has predicted taken
-system.cpu.fetch.rate 1.994906 # Number of inst fetches per cycle
+system.cpu.dcache.writebacks 75 # number of writebacks
+system.cpu.decode.DECODE:BlockedCycles 2221252 # Number of cycles decode is blocked
+system.cpu.decode.DECODE:BranchMispred 13564 # Number of times decode detected a branch misprediction
+system.cpu.decode.DECODE:BranchResolved 2815361 # Number of times decode resolved a branch
+system.cpu.decode.DECODE:DecodedInsts 145659694 # Number of instructions handled by decode
+system.cpu.decode.DECODE:IdleCycles 36080141 # Number of cycles decode is idle
+system.cpu.decode.DECODE:RunCycles 27108364 # Number of cycles decode is running
+system.cpu.decode.DECODE:SquashCycles 6243203 # Number of cycles decode is squashing
+system.cpu.decode.DECODE:SquashedInsts 50032 # Number of squashed instructions handled by decode
+system.cpu.decode.DECODE:UnblockCycles 81084 # Number of cycles decode is unblocking
+system.cpu.fetch.Branches 17533197 # Number of branches that fetch encountered
+system.cpu.fetch.CacheLines 17509399 # Number of cache lines fetched
+system.cpu.fetch.Cycles 45531133 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.IcacheSquashes 484323 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.Insts 150299775 # Number of instructions fetch has processed
+system.cpu.fetch.SquashCycles 2040341 # Number of cycles fetch has spent squashing
+system.cpu.fetch.branchRate 0.244419 # Number of branch fetches per cycle
+system.cpu.fetch.icacheStallCycles 17509399 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.predictedBranches 13524702 # Number of branches that fetch has predicted taken
+system.cpu.fetch.rate 2.095236 # Number of inst fetches per cycle
system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist.samples 6871
+system.cpu.fetch.rateDist.samples 71734044
system.cpu.fetch.rateDist.min_value 0
- 0 4549 6620.58%
- 1 174 253.24%
- 2 186 270.70%
- 3 157 228.50%
- 4 211 307.09%
- 5 153 222.68%
- 6 171 248.87%
- 7 105 152.82%
- 8 1165 1695.53%
+ 0 43713095 6093.77%
+ 1 2792314 389.26%
+ 2 2129360 296.84%
+ 3 3194083 445.27%
+ 4 4028588 561.60%
+ 5 1363321 190.05%
+ 6 1870461 260.75%
+ 7 1629807 227.20%
+ 8 11013015 1535.26%
system.cpu.fetch.rateDist.max_value 8
system.cpu.fetch.rateDist.end_dist
-system.cpu.icache.ReadReq_accesses 1582 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 2.960245 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 1.996885 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits 1255 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 968 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate 0.206700 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses 327 # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_hits 6 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_miss_latency 641 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.202908 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses 321 # number of ReadReq MSHR misses
-system.cpu.icache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles_no_targets no value # average number of cycles each access was blocked
-system.cpu.icache.avg_refs 3.909657 # Average number of references to valid blocks.
+system.cpu.icache.ReadReq_accesses 17509399 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency 3388.211547 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 2494.269154 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits 17495889 # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency 45774738 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_rate 0.000772 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_misses 13510 # number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_hits 3486 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_miss_latency 25002554 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate 0.000572 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_misses 10024 # number of ReadReq MSHR misses
+system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles_no_targets 3400.454545 # average number of cycles each access was blocked
+system.cpu.icache.avg_refs 1745.399940 # Average number of references to valid blocks.
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu.icache.blocked_no_targets 22 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles_no_targets 74810 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.demand_accesses 1582 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 2.960245 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 1.996885 # average overall mshr miss latency
-system.cpu.icache.demand_hits 1255 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 968 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate 0.206700 # miss rate for demand accesses
-system.cpu.icache.demand_misses 327 # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_hits 6 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 641 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate 0.202908 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses 321 # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_accesses 17509399 # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency 3388.211547 # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 2494.269154 # average overall mshr miss latency
+system.cpu.icache.demand_hits 17495889 # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency 45774738 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_rate 0.000772 # miss rate for demand accesses
+system.cpu.icache.demand_misses 13510 # number of demand (read+write) misses
+system.cpu.icache.demand_mshr_hits 3486 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_miss_latency 25002554 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_rate 0.000572 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_misses 10024 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.overall_accesses 1582 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 2.960245 # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 1.996885 # average overall mshr miss latency
+system.cpu.icache.overall_accesses 17509399 # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency 3388.211547 # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 2494.269154 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits 1255 # number of overall hits
-system.cpu.icache.overall_miss_latency 968 # number of overall miss cycles
-system.cpu.icache.overall_miss_rate 0.206700 # miss rate for overall accesses
-system.cpu.icache.overall_misses 327 # number of overall misses
-system.cpu.icache.overall_mshr_hits 6 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 641 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate 0.202908 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses 321 # number of overall MSHR misses
+system.cpu.icache.overall_hits 17495889 # number of overall hits
+system.cpu.icache.overall_miss_latency 45774738 # number of overall miss cycles
+system.cpu.icache.overall_miss_rate 0.000772 # miss rate for overall accesses
+system.cpu.icache.overall_misses 13510 # number of overall misses
+system.cpu.icache.overall_mshr_hits 3486 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_miss_latency 25002554 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_rate 0.000572 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_misses 10024 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@@ -215,1726 +215,162 @@ system.cpu.icache.prefetcher.num_hwpf_issued 0
system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.icache.replacements 0 # number of replacements
-system.cpu.icache.sampled_refs 321 # Sample count of references to valid blocks.
+system.cpu.icache.replacements 8115 # number of replacements
+system.cpu.icache.sampled_refs 10024 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 176.393247 # Cycle average of tags in use
-system.cpu.icache.total_refs 1255 # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse 1481.631027 # Cycle average of tags in use
+system.cpu.icache.total_refs 17495889 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.iew.EXEC:branches 1206 # Number of branches executed
-system.cpu.iew.EXEC:insts 7969 # Number of executed instructions
-system.cpu.iew.EXEC:loads 1610 # Number of load instructions executed
-system.cpu.iew.EXEC:nop 37 # number of nop insts executed
-system.cpu.iew.EXEC:rate 1.159802 # Inst execution rate
-system.cpu.iew.EXEC:refs 2599 # number of memory reference insts executed
-system.cpu.iew.EXEC:squashedInsts 419 # Number of squashed instructions skipped in execute
-system.cpu.iew.EXEC:stores 989 # Number of stores executed
+system.cpu.idleCycles 32952056 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.iew.EXEC:branches 12456785 # Number of branches executed
+system.cpu.iew.EXEC:nop 11559797 # number of nop insts executed
+system.cpu.iew.EXEC:rate 1.365191 # Inst execution rate
+system.cpu.iew.EXEC:refs 30958353 # number of memory reference insts executed
+system.cpu.iew.EXEC:stores 7006627 # Number of stores executed
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
-system.cpu.iew.WB:consumers 5438 # num instructions consuming a value
-system.cpu.iew.WB:count 7722 # cumulative count of insts written-back
-system.cpu.iew.WB:fanout 0.744575 # average fanout of values written-back
+system.cpu.iew.WB:consumers 86914579 # num instructions consuming a value
+system.cpu.iew.WB:count 96291361 # cumulative count of insts written-back
+system.cpu.iew.WB:fanout 0.729319 # average fanout of values written-back
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.iew.WB:producers 4049 # num instructions producing a value
-system.cpu.iew.WB:rate 1.123854 # insts written-back per cycle
-system.cpu.iew.WB:sent 7762 # cumulative count of insts sent to commit
-system.cpu.iew.branchMispredicts 393 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewBlockCycles 4 # Number of cycles IEW is blocking
-system.cpu.iew.iewDispLoadInsts 2050 # Number of dispatched load instructions
-system.cpu.iew.iewDispNonSpecInsts 21 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewDispSquashedInsts 272 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispStoreInsts 1221 # Number of dispatched store instructions
-system.cpu.iew.iewDispatchedInsts 9990 # Number of instructions dispatched to IQ
-system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.WB:producers 63388475 # num instructions producing a value
+system.cpu.iew.WB:rate 1.342338 # insts written-back per cycle
+system.cpu.iew.WB:sent 96947832 # cumulative count of insts sent to commit
+system.cpu.iew.branchMispredicts 2153450 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewBlockCycles 156060 # Number of cycles IEW is blocking
+system.cpu.iew.iewDispLoadInsts 29530804 # Number of dispatched load instructions
+system.cpu.iew.iewDispNonSpecInsts 437 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewDispSquashedInsts 2057217 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispStoreInsts 9370879 # Number of dispatched store instructions
+system.cpu.iew.iewDispatchedInsts 130866464 # Number of instructions dispatched to IQ
+system.cpu.iew.iewExecLoadInsts 23951726 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 2095770 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewExecutedInsts 97930658 # Number of executed instructions
+system.cpu.iew.iewIQFullEvents 43929 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.iewSquashCycles 754 # Number of cycles IEW is squashing
-system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking
-system.cpu.iew.lsq.thread.0.blockedLoads 1 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread.0.cacheBlocked 5 # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.lsq.thread.0.forwLoads 55 # Number of loads that had data forwarded from stores
-system.cpu.iew.lsq.thread.0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.iewLSQFullEvents 720 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.iewSquashCycles 6243203 # Number of cycles IEW is squashing
+system.cpu.iew.iewUnblockCycles 62133 # Number of cycles IEW is unblocking
+system.cpu.iew.lsq.thread.0.blockedLoads 9874 # Number of blocked loads due to partial load-store forwarding
+system.cpu.iew.lsq.thread.0.cacheBlocked 40553 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread.0.forwLoads 855538 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread.0.ignoredResponses 3321 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
-system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread.0.squashedLoads 1071 # Number of loads squashed
-system.cpu.iew.lsq.thread.0.squashedStores 409 # Number of stores squashed
-system.cpu.iew.memOrderViolationEvents 41 # Number of memory order violations
-system.cpu.iew.predictedNotTakenIncorrect 296 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.predictedTakenIncorrect 97 # Number of branches that were predicted taken incorrectly
-system.cpu.ipc 0.818486 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.818486 # IPC: Total IPC of All Threads
-system.cpu.iq.IQ:residence:(null).start_dist # cycles from dispatch to issue
-system.cpu.iq.IQ:residence:(null).samples 0
-system.cpu.iq.IQ:residence:(null).min_value 0
- 0 0
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-system.cpu.iq.IQ:residence:(null).max_value 0
-system.cpu.iq.IQ:residence:(null).end_dist
-
-system.cpu.iq.IQ:residence:IntAlu.start_dist # cycles from dispatch to issue
-system.cpu.iq.IQ:residence:IntAlu.samples 0
-system.cpu.iq.IQ:residence:IntAlu.min_value 0
- 0 0
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-system.cpu.iq.IQ:residence:IntAlu.max_value 0
-system.cpu.iq.IQ:residence:IntAlu.end_dist
-
-system.cpu.iq.IQ:residence:IntMult.start_dist # cycles from dispatch to issue
-system.cpu.iq.IQ:residence:IntMult.samples 0
-system.cpu.iq.IQ:residence:IntMult.min_value 0
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-system.cpu.iq.IQ:residence:IntMult.max_value 0
-system.cpu.iq.IQ:residence:IntMult.end_dist
-
-system.cpu.iq.IQ:residence:IntDiv.start_dist # cycles from dispatch to issue
-system.cpu.iq.IQ:residence:IntDiv.samples 0
-system.cpu.iq.IQ:residence:IntDiv.min_value 0
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-system.cpu.iq.IQ:residence:IntDiv.max_value 0
-system.cpu.iq.IQ:residence:IntDiv.end_dist
-
-system.cpu.iq.IQ:residence:FloatAdd.start_dist # cycles from dispatch to issue
-system.cpu.iq.IQ:residence:FloatAdd.samples 0
-system.cpu.iq.IQ:residence:FloatAdd.min_value 0
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-system.cpu.iq.IQ:residence:FloatAdd.max_value 0
-system.cpu.iq.IQ:residence:FloatAdd.end_dist
-
-system.cpu.iq.IQ:residence:FloatCmp.start_dist # cycles from dispatch to issue
-system.cpu.iq.IQ:residence:FloatCmp.samples 0
-system.cpu.iq.IQ:residence:FloatCmp.min_value 0
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-system.cpu.iq.IQ:residence:FloatCmp.end_dist
-
-system.cpu.iq.IQ:residence:FloatCvt.start_dist # cycles from dispatch to issue
-system.cpu.iq.IQ:residence:FloatCvt.samples 0
-system.cpu.iq.IQ:residence:FloatCvt.min_value 0
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-system.cpu.iq.IQ:residence:FloatCvt.end_dist
-
-system.cpu.iq.IQ:residence:FloatMult.start_dist # cycles from dispatch to issue
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-
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-
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-
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-
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-
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-
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-
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-
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-
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-
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-
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-
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-
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+system.cpu.iew.predictedNotTakenIncorrect 1143572 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.predictedTakenIncorrect 1009878 # Number of branches that were predicted taken incorrectly
+system.cpu.ipc 0.788857 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.788857 # IPC: Total IPC of All Threads
+system.cpu.iq.ISSUE:FU_type_0 100026428 # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0.start_dist
- (null) 2 0.02% # Type of FU issued
- IntAlu 5594 66.69% # Type of FU issued
- IntMult 1 0.01% # Type of FU issued
+ (null) 7 0.00% # Type of FU issued
+ IntAlu 61666427 61.65% # Type of FU issued
+ IntMult 468908 0.47% # Type of FU issued
IntDiv 0 0.00% # Type of FU issued
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- FloatMult 0 0.00% # Type of FU issued
- FloatDiv 0 0.00% # Type of FU issued
- FloatSqrt 0 0.00% # Type of FU issued
- MemRead 1757 20.95% # Type of FU issued
- MemWrite 1032 12.30% # Type of FU issued
+ FloatAdd 2704055 2.70% # Type of FU issued
+ FloatCmp 112834 0.11% # Type of FU issued
+ FloatCvt 2307257 2.31% # Type of FU issued
+ FloatMult 295394 0.30% # Type of FU issued
+ FloatDiv 735688 0.74% # Type of FU issued
+ FloatSqrt 122 0.00% # Type of FU issued
+ MemRead 24586382 24.58% # Type of FU issued
+ MemWrite 7149354 7.15% # Type of FU issued
IprAccess 0 0.00% # Type of FU issued
InstPrefetch 0 0.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0.end_dist
-system.cpu.iq.ISSUE:fu_busy_cnt 115 # FU busy when requested
-system.cpu.iq.ISSUE:fu_busy_rate 0.013710 # FU busy rate (busy events/executed inst)
+system.cpu.iq.ISSUE:fu_busy_cnt 1620744 # FU busy when requested
+system.cpu.iq.ISSUE:fu_busy_rate 0.016203 # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:fu_full.start_dist
(null) 0 0.00% # attempts to use FU when none available
- IntAlu 1 0.87% # attempts to use FU when none available
+ IntAlu 195067 12.04% # attempts to use FU when none available
IntMult 0 0.00% # attempts to use FU when none available
IntDiv 0 0.00% # attempts to use FU when none available
- FloatAdd 0 0.00% # attempts to use FU when none available
- FloatCmp 0 0.00% # attempts to use FU when none available
- FloatCvt 0 0.00% # attempts to use FU when none available
- FloatMult 0 0.00% # attempts to use FU when none available
- FloatDiv 0 0.00% # attempts to use FU when none available
+ FloatAdd 1678 0.10% # attempts to use FU when none available
+ FloatCmp 197 0.01% # attempts to use FU when none available
+ FloatCvt 4552 0.28% # attempts to use FU when none available
+ FloatMult 2392 0.15% # attempts to use FU when none available
+ FloatDiv 951463 58.71% # attempts to use FU when none available
FloatSqrt 0 0.00% # attempts to use FU when none available
- MemRead 76 66.09% # attempts to use FU when none available
- MemWrite 38 33.04% # attempts to use FU when none available
+ MemRead 401417 24.77% # attempts to use FU when none available
+ MemWrite 63978 3.95% # attempts to use FU when none available
IprAccess 0 0.00% # attempts to use FU when none available
InstPrefetch 0 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full.end_dist
system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle.samples 6871
+system.cpu.iq.ISSUE:issued_per_cycle.samples 71734044
system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
- 0 3753 5462.09%
- 1 894 1301.12%
- 2 723 1052.25%
- 3 614 893.61%
- 4 451 656.38%
- 5 279 406.05%
- 6 104 151.36%
- 7 41 59.67%
- 8 12 17.46%
+ 0 28631398 3991.33%
+ 1 15448994 2153.65%
+ 2 12333631 1719.36%
+ 3 7046540 982.31%
+ 4 4503539 627.81%
+ 5 2295007 319.93%
+ 6 1113179 155.18%
+ 7 291761 40.67%
+ 8 69995 9.76%
system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
system.cpu.iq.ISSUE:issued_per_cycle.end_dist
-system.cpu.iq.ISSUE:rate 1.220783 # Inst issue rate
-system.cpu.iq.iqInstsAdded 9932 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqInstsIssued 8388 # Number of instructions issued
-system.cpu.iq.iqNonSpecInstsAdded 21 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqSquashedInstsExamined 3990 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedInstsIssued 21 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedNonSpecRemoved 4 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.iqSquashedOperandsExamined 2486 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.l2cache.ReadReq_accesses 499 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 2.042254 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency 1015 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate 0.995992 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses 497 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 490 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.981964 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses 490 # number of ReadReq MSHR misses
+system.cpu.iq.ISSUE:rate 1.394407 # Inst issue rate
+system.cpu.iq.iqInstsAdded 119306230 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqInstsIssued 100026428 # Number of instructions issued
+system.cpu.iq.iqNonSpecInstsAdded 437 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqSquashedInstsExamined 35838359 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedInstsIssued 150449 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedNonSpecRemoved 50 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.iqSquashedOperandsExamined 30462150 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.l2cache.ReadReq_accesses 12131 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_avg_miss_latency 3919.717352 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2067.943230 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_hits 7146 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_miss_latency 19539791 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate 0.410931 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses 4985 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency 10308697 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.410931 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses 4985 # number of ReadReq MSHR misses
+system.cpu.l2cache.WriteReqNoAck|Writeback_accesses 75 # number of WriteReqNoAck|Writeback accesses(hits+misses)
+system.cpu.l2cache.WriteReqNoAck|Writeback_hits 75 # number of WriteReqNoAck|Writeback hits
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs 0.004024 # Average number of references to valid blocks.
+system.cpu.l2cache.avg_refs 1.448546 # Average number of references to valid blocks.
system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.demand_accesses 499 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 2.042254 # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 1 # average overall mshr miss latency
-system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 1015 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate 0.995992 # miss rate for demand accesses
-system.cpu.l2cache.demand_misses 497 # number of demand (read+write) misses
+system.cpu.l2cache.demand_accesses 12131 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_avg_miss_latency 3919.717352 # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 2067.943230 # average overall mshr miss latency
+system.cpu.l2cache.demand_hits 7146 # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency 19539791 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate 0.410931 # miss rate for demand accesses
+system.cpu.l2cache.demand_misses 4985 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency 490 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate 0.981964 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses 490 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_miss_latency 10308697 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate 0.410931 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses 4985 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.overall_accesses 499 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 2.042254 # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 1 # average overall mshr miss latency
+system.cpu.l2cache.overall_accesses 12206 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_avg_miss_latency 3919.717352 # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 2067.943230 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits 2 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 1015 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate 0.995992 # miss rate for overall accesses
-system.cpu.l2cache.overall_misses 497 # number of overall misses
+system.cpu.l2cache.overall_hits 7221 # number of overall hits
+system.cpu.l2cache.overall_miss_latency 19539791 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate 0.408406 # miss rate for overall accesses
+system.cpu.l2cache.overall_misses 4985 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 490 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate 0.981964 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses 490 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_miss_latency 10308697 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate 0.408406 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses 4985 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@@ -1947,28 +383,31 @@ system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.l2cache.replacements 0 # number of replacements
-system.cpu.l2cache.sampled_refs 497 # Sample count of references to valid blocks.
+system.cpu.l2cache.sampled_refs 4985 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 295.773395 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks.
+system.cpu.l2cache.tagsinuse 3244.539242 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 7221 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks
-system.cpu.numCycles 6871 # number of cpu cycles simulated
-system.cpu.rename.RENAME:BlockCycles 4 # Number of cycles rename is blocking
-system.cpu.rename.RENAME:CommittedMaps 4051 # Number of HB maps that are committed
-system.cpu.rename.RENAME:IdleCycles 3758 # Number of cycles rename is idle
-system.cpu.rename.RENAME:LSQFullEvents 62 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RENAME:RenameLookups 14786 # Number of register rename lookups that rename has made
-system.cpu.rename.RENAME:RenamedInsts 11555 # Number of instructions processed by rename
-system.cpu.rename.RENAME:RenamedOperands 8634 # Number of destination operands rename has renamed
-system.cpu.rename.RENAME:RunCycles 1975 # Number of cycles rename is running
-system.cpu.rename.RENAME:SquashCycles 754 # Number of cycles rename is squashing
-system.cpu.rename.RENAME:UnblockCycles 111 # Number of cycles rename is unblocking
-system.cpu.rename.RENAME:UndoneMaps 4583 # Number of HB maps that are undone due to squashing
-system.cpu.rename.RENAME:serializeStallCycles 269 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RENAME:serializingInsts 26 # count of serializing insts renamed
-system.cpu.rename.RENAME:skidInsts 408 # count of insts added to the skid buffer
-system.cpu.rename.RENAME:tempSerializingInsts 21 # count of temporary serializing insts renamed
-system.cpu.workload.PROG:num_syscalls 17 # Number of system calls
+system.cpu.numCycles 71734044 # number of cpu cycles simulated
+system.cpu.rename.RENAME:BlockCycles 969328 # Number of cycles rename is blocking
+system.cpu.rename.RENAME:CommittedMaps 67122956 # Number of HB maps that are committed
+system.cpu.rename.RENAME:IQFullEvents 411688 # Number of times rename has blocked due to IQ full
+system.cpu.rename.RENAME:IdleCycles 37058676 # Number of cycles rename is idle
+system.cpu.rename.RENAME:LSQFullEvents 742595 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RENAME:ROBFullEvents 109 # Number of times rename has blocked due to ROB full
+system.cpu.rename.RENAME:RenameLookups 181728449 # Number of register rename lookups that rename has made
+system.cpu.rename.RENAME:RenamedInsts 141044897 # Number of instructions processed by rename
+system.cpu.rename.RENAME:RenamedOperands 103457127 # Number of destination operands rename has renamed
+system.cpu.rename.RENAME:RunCycles 26196123 # Number of cycles rename is running
+system.cpu.rename.RENAME:SquashCycles 6243203 # Number of cycles rename is squashing
+system.cpu.rename.RENAME:UnblockCycles 1187915 # Number of cycles rename is unblocking
+system.cpu.rename.RENAME:UndoneMaps 36334171 # Number of HB maps that are undone due to squashing
+system.cpu.rename.RENAME:serializeStallCycles 78799 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RENAME:serializingInsts 513 # count of serializing insts renamed
+system.cpu.rename.RENAME:skidInsts 2731208 # count of insts added to the skid buffer
+system.cpu.rename.RENAME:tempSerializingInsts 502 # count of temporary serializing insts renamed
+system.cpu.timesIdled 10186 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.workload.PROG:num_syscalls 387 # Number of system calls
---------- End Simulation Statistics ----------
diff --git a/tests/long/70.twolf/ref/alpha/linux/o3-timing/smred.out b/tests/long/70.twolf/ref/alpha/linux/o3-timing/smred.out
new file mode 100644
index 000000000..00387ae5c
--- /dev/null
+++ b/tests/long/70.twolf/ref/alpha/linux/o3-timing/smred.out
@@ -0,0 +1,276 @@
+
+TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988
+Standard Cell Placement and Global Routing Program
+Authors: Carl Sechen, Bill Swartz
+ Yale University
+
+
+NOTE: Restart file .rs2 not used
+
+TimberWolf will perform a global route step
+rowSep: 1.000000
+feedThruWidth: 4
+
+******************
+BLOCK DATA
+block:1 desire:85
+block:2 desire:85
+Total Desired Length: 170
+total cell length: 168
+total block length: 168
+block x-span:84 block y-span:78
+implicit feed thru range: -84
+Using default value of bin.penalty.control:1.000000
+numBins automatically set to:5
+binWidth = average_cell_width + 0 sigma= 17
+average_cell_width is:16
+standard deviation of cell length is:23.6305
+TimberWolfSC starting from the beginning
+
+
+
+THIS IS THE ROUTE COST OF THE ORIGINAL PLACEMENT: 645
+The number of nets with 1 pin is 4
+The number of nets with 2 pin is 9
+The number of nets with 3 pin is 0
+The number of nets with 4 pin is 2
+The number of nets with 5 pin is 0
+The number of nets with 6 pin is 0
+The number of nets with 7 pin is 0
+The number of nets with 8 pin is 0
+The number of nets with 9 pin is 0
+The number of nets with 10 pin or more is 0
+
+New Cost Function: Initial Horizontal Cost:242
+New Cost Function: FEEDS:0 MISSING_ROWS:-46
+
+bdxlen:86 bdylen:78
+l:0 t:78 r:86 b:0
+
+
+
+THIS IS THE ROUTE COST OF THE CURRENT PLACEMENT: 645
+
+
+
+THIS IS THE PENALTY OF THE CURRENT PLACEMENT: 44
+
+The rand generator seed was at utemp() : 1
+
+
+ tempfile[0][0] = 0.982500 tempfile[0][1] = 90.000000
+ tempfile[1][0] = 0.915000 tempfile[1][1] = 20.000000
+ tempfile[2][0] = 0.700000 tempfile[2][1] = 10.000000
+ tempfile[3][0] = 0.100000 tempfile[3][1] = 0.000000
+
+ I T fds Wire Penalty P_lim Epct binC rowC acc s/p early FDs MRs
+ 1 500 0 929 592 160 30.0 1.0 3.0 84.2 34.7 0.0 0 40
+ 2 491 0 876 106 726 0.0 0.8 2.5 80.0 18.5 0.0 0 46
+ 3 482 0 822 273 372 0.0 0.5 1.5 80.8 21.2 0.0 0 46
+ 4 474 0 826 53 247 0.0 0.5 0.9 65.0 21.9 0.0 0 48
+ 5 465 8 987 73 190 0.0 0.5 0.5 50.0 38.3 0.0 0 46
+ 6 457 8 851 67 226 0.0 0.5 0.5 53.8 42.9 0.0 0 52
+ 7 449 8 1067 108 190 0.0 0.5 0.5 46.2 53.8 0.0 0 50
+ 8 441 8 918 106 171 0.0 0.5 0.5 47.1 40.4 0.0 0 48
+ 9 434 8 812 101 197 0.0 0.5 0.5 53.6 21.0 0.0 0 48
+ 10 426 8 1038 121 181 0.0 0.5 0.5 43.6 27.1 0.0 0 48
+ 11 419 8 898 93 187 0.0 0.5 0.5 45.3 47.8 0.0 0 50
+ 12 411 4 857 94 240 0.0 0.5 0.5 62.7 51.6 0.0 0 44
+ 13 404 8 1043 88 185 0.0 0.5 0.5 54.0 52.8 0.0 0 50
+ 14 397 8 767 94 154 0.0 0.5 0.5 33.8 35.0 0.0 0 50
+ 15 390 8 862 89 183 0.0 0.5 0.5 55.6 29.0 0.0 0 46
+ 16 383 4 798 79 173 0.0 0.5 0.5 57.5 35.3 0.0 0 52
+ 17 376 8 827 100 152 0.0 0.5 0.5 35.3 81.8 0.0 0 50
+ 18 370 8 878 101 208 0.0 0.5 0.5 44.7 46.2 0.0 0 48
+ 19 363 4 921 67 167 0.0 0.5 0.5 57.1 34.7 0.0 0 48
+ 20 357 8 933 93 154 0.0 0.5 0.5 46.5 43.6 0.0 0 52
+ 21 351 8 930 89 147 0.0 0.5 0.5 39.4 36.5 0.0 0 52
+ 22 345 8 951 79 142 0.0 0.5 0.5 32.8 51.3 0.0 0 50
+ 23 339 8 1046 87 207 0.0 0.5 0.5 52.8 61.0 0.0 0 48
+ 24 333 4 989 96 185 0.0 0.5 0.5 45.3 43.3 0.0 0 42
+ 25 327 4 577 86 157 0.0 0.5 0.5 31.1 55.3 0.0 0 52
+ 26 321 8 776 97 174 0.0 0.5 0.5 47.9 62.5 0.0 0 52
+ 27 315 8 850 81 188 0.0 0.5 0.5 45.0 55.2 0.0 0 50
+ 28 310 8 898 97 148 0.0 0.5 0.5 43.0 45.8 0.0 0 48
+ 29 304 8 889 65 173 0.0 0.5 0.5 32.5 41.3 0.0 0 50
+ 30 299 8 858 81 153 0.0 0.5 0.5 44.3 29.2 0.0 0 46
+ 31 294 8 871 82 187 0.0 0.5 0.5 45.7 47.7 0.0 0 48
+ 32 289 8 782 109 173 0.0 0.5 0.5 35.2 57.4 0.0 0 48
+ 33 284 8 743 98 189 0.0 0.6 0.5 41.8 64.3 0.0 0 52
+ 34 279 8 943 90 147 0.0 0.5 0.5 38.6 32.8 0.0 0 48
+ 35 274 8 907 57 166 0.0 0.5 0.5 33.6 51.0 0.0 0 48
+ 36 269 8 900 70 148 0.0 0.5 0.5 45.0 41.4 0.0 0 50
+ 37 264 4 875 106 133 0.0 0.5 0.5 31.7 55.3 0.0 0 52
+ 38 260 8 1023 145 149 0.0 0.6 0.5 28.7 65.0 0.0 0 52
+ 39 255 8 801 151 173 0.0 0.9 0.5 41.7 41.2 0.0 0 48
+ 40 251 8 741 104 159 0.0 0.8 0.5 36.2 47.5 0.0 0 48
+ 41 246 8 828 108 149 0.0 0.5 0.5 34.6 50.9 0.0 0 50
+ 42 242 8 947 128 132 0.0 0.7 0.5 34.2 39.0 0.0 0 50
+ 43 238 8 917 101 142 0.0 0.8 0.5 34.4 50.9 0.0 0 48
+ 44 234 8 761 86 129 0.0 0.5 0.5 42.0 36.4 0.0 0 52
+ 45 229 8 979 106 137 0.0 0.5 0.5 29.2 55.3 0.0 0 50
+ 46 225 8 806 74 130 0.0 0.7 0.5 33.1 65.4 0.0 0 52
+ 47 221 8 971 125 114 0.0 0.5 0.5 31.9 45.6 0.0 0 52
+ 48 218 8 869 125 104 0.0 0.9 0.5 30.0 56.0 0.0 0 48
+ 49 214 8 999 153 140 0.0 0.8 0.5 30.4 46.4 0.0 0 52
+ 50 210 8 798 192 139 0.0 1.0 0.5 28.9 50.0 0.0 0 52
+ 51 206 8 860 125 157 0.0 1.2 0.5 31.5 26.9 0.0 0 52
+ 52 203 8 893 186 127 5.9 0.9 0.5 26.4 42.3 0.0 0 46
+ 53 199 8 863 126 141 0.0 1.2 0.5 32.5 44.4 0.0 0 44
+ 54 196 8 788 97 133 0.0 0.9 0.5 37.5 40.0 0.0 0 50
+ 55 192 8 926 119 116 0.0 0.6 0.5 26.1 55.3 0.0 0 52
+ 56 189 8 789 162 107 0.0 0.8 0.5 25.2 40.4 0.0 0 48
+ 57 186 8 878 107 128 0.0 1.1 0.5 23.1 34.0 0.0 0 52
+ 58 182 8 775 105 122 0.0 0.8 0.5 25.5 57.4 0.0 0 50
+ 59 179 8 747 94 129 0.0 0.7 0.5 34.3 37.3 0.0 0 50
+ 60 176 8 845 96 138 0.0 0.6 0.5 28.3 41.7 0.0 0 52
+ 61 173 8 961 121 110 0.0 0.6 0.5 29.0 52.6 0.0 0 48
+ 62 170 4 911 110 109 0.0 0.9 0.5 33.5 33.3 0.0 0 48
+ 63 167 8 656 109 109 0.0 0.8 0.5 21.9 44.7 0.0 0 52
+ 64 164 8 934 117 105 0.0 0.8 0.5 15.5 50.0 0.0 0 52
+ 65 161 8 972 125 95 0.0 0.8 0.5 24.4 50.0 0.0 0 50
+ 66 158 8 894 125 101 0.0 0.9 0.5 27.2 35.9 0.0 0 52
+ 67 155 8 798 146 129 0.0 1.0 0.5 22.8 58.7 0.0 0 52
+ 68 153 8 901 183 92 0.0 1.1 0.5 23.6 34.5 0.0 0 52
+ 69 150 8 977 197 103 0.0 1.4 0.5 23.6 36.8 0.0 0 52
+ 70 147 8 905 262 93 0.0 1.5 0.5 20.3 63.4 0.0 0 52
+ 71 145 8 995 148 122 0.0 1.9 0.5 20.9 35.3 0.0 0 52
+ 72 142 8 934 230 99 0.0 1.6 0.5 20.0 65.9 0.0 0 52
+ 73 140 8 862 173 100 0.0 1.8 0.5 26.8 46.8 0.0 0 52
+ 74 137 8 924 139 90 0.0 1.7 0.5 16.8 42.5 0.0 0 52
+ 75 135 8 888 168 113 0.0 1.6 0.5 22.9 40.4 0.0 0 52
+ 76 133 8 712 212 84 0.0 1.6 0.5 13.4 46.9 0.0 0 52
+ 77 130 8 868 210 91 0.0 1.7 0.5 17.7 51.2 0.0 0 52
+ 78 128 8 952 307 92 0.0 1.9 0.5 19.7 44.9 0.0 0 50
+ 79 126 8 801 157 107 0.0 2.2 0.5 15.8 39.0 0.0 0 52
+ 80 123 8 849 147 93 0.0 2.1 0.5 15.6 51.4 0.0 0 52
+ 81 121 8 799 154 86 0.0 1.9 0.5 12.2 50.0 0.0 0 52
+ 82 119 8 941 213 82 0.0 1.8 0.5 19.5 41.2 0.0 0 50
+ 83 117 8 751 268 94 0.0 2.0 0.5 20.8 42.6 0.0 0 50
+ 84 115 8 828 198 102 0.0 2.2 0.5 15.5 59.5 0.0 0 52
+ 85 113 8 898 266 123 0.0 2.2 0.5 13.2 85.2 0.0 0 52
+ 86 111 8 943 190 93 0.0 2.4 0.5 19.5 45.1 0.0 0 52
+ 87 109 8 864 183 65 0.0 2.4 0.5 14.9 31.8 0.0 0 52
+ 88 107 8 793 203 93 0.0 2.4 0.5 11.8 35.3 0.0 0 52
+ 89 105 8 752 162 74 1.2 2.4 0.5 13.1 21.4 0.0 0 52
+ 90 103 8 801 149 77 0.0 2.3 0.5 9.7 58.3 0.0 0 52
+ 91 102 8 901 230 99 0.0 2.2 0.5 16.0 25.5 0.0 0 52
+ 92 100 8 826 201 87 0.0 2.4 0.5 12.8 45.7 0.0 0 52
+ 93 98 8 810 196 83 0.0 2.5 0.5 14.0 24.4 0.0 0 52
+ 94 96 8 857 209 68 1.0 2.5 0.5 11.5 27.0 5.1 0 52
+ 95 95 8 771 174 91 0.0 2.6 0.5 10.5 26.5 0.0 0 52
+ 96 93 8 955 210 59 0.0 2.6 0.5 10.0 36.7 0.7 0 52
+ 97 91 8 833 206 53 0.0 2.7 0.5 10.2 19.4 1.4 0 52
+ 98 90 8 888 229 86 0.0 2.8 0.5 8.1 36.0 0.0 0 52
+ 99 88 8 794 186 91 1.0 2.9 0.5 8.3 25.0 0.5 0 52
+100 81 8 756 170 72 1.0 2.9 0.5 6.0 23.8 7.0 0 52
+101 74 8 791 176 67 0.0 2.9 0.5 4.4 58.3 4.0 0 52
+102 67 8 813 213 43 0.0 3.0 0.5 7.0 150.0 4.2 0 52
+103 62 8 779 245 39 0.0 3.1 0.5 3.2 16.7 13.0 0 52
+104 56 8 767 303 63 0.0 3.2 0.5 4.1 20.0 0.7 0 52
+105 52 8 757 270 57 0.0 3.5 0.5 6.4 3.7 0.5 0 52
+106 47 8 763 283 41 0.0 3.7 0.5 4.5 0.0 0.0 0 52
+107 43 8 768 283 36 0.0 3.7 0.5 2.9 18.2 3.6 0 52
+108 39 8 804 283 25 0.0 3.7 0.5 3.1 0.0 6.2 0 52
+109 36 8 781 283 24 0.0 3.7 0.5 3.6 6.7 6.7 0 52
+110 33 8 738 298 42 0.0 3.7 0.5 3.3 15.4 3.5 0 52
+111 30 8 761 298 36 0.0 3.7 0.5 2.2 0.0 4.3 0 52
+112 27 8 769 298 37 0.0 3.7 0.5 0.9 0.0 2.2 0 52
+113 25 8 745 298 31 0.0 3.7 0.5 1.5 0.0 6.6 0 52
+114 23 8 753 298 16 0.0 3.7 0.5 1.3 0.0 2.8 0 52
+115 21 8 745 298 11 0.0 3.7 0.5 1.5 0.0 14.0 0 52
+116 19 8 747 298 21 0.0 3.7 0.5 2.1 0.0 5.8 0 52
+117 13 8 737 298 12 0.0 3.7 0.5 1.0 0.0 10.0 0 52
+118 9 8 736 298 4 0.0 3.7 0.5 1.5 0.0 18.5 0 52
+119 0 8 739 298 0 0.0 3.7 0.5 1.8 0.0 18.0 0 52
+120 0 8 732 298 0 0.0 3.7 0.5 1.2 0.0 21.8 0 52
+121 0 8 732 19 -1 0.0 0.0 0.5 0.0 100.0 54.8
+
+Initial Wiring Cost: 645 Final Wiring Cost: 732
+############## Percent Wire Cost Reduction: -13
+
+
+Initial Wire Length: 645 Final Wire Length: 732
+************** Percent Wire Length Reduction: -13
+
+
+Initial Horiz. Wire: 216 Final Horiz. Wire: 147
+$$$$$$$$$$$ Percent H-Wire Length Reduction: 32
+
+
+Initial Vert. Wire: 429 Final Vert. Wire: 585
+@@@@@@@@@@@ Percent V-Wire Length Reduction: -36
+
+Before Feeds are Added:
+BLOCK TOTAL CELL LENGTHS OVER/UNDER TARGET
+ 1 82 -20
+ 2 86 -16
+
+LONGEST Block is:2 Its length is:86
+BLOCK TOTAL CELL LENGTHS OVER/UNDER TARGET
+ 1 86 -16
+ 2 86 -16
+
+LONGEST Block is:1 Its length is:86
+Added: 1 feed-through cells
+
+Removed the cell overlaps --- Will do neighbor interchanges only now
+
+TOTAL INTERCONNECT LENGTH: 994
+OVERLAP PENALTY: 0
+
+initialRowControl: 1.650
+finalRowControl: 0.300
+iter T Wire accept
+ 122 0.001 976 16%
+ 123 0.001 971 0%
+ 124 0.001 971 0%
+Total Feed-Alignment Movement (Pass 1): 0
+Total Feed-Alignment Movement (Pass 2): 0
+Total Feed-Alignment Movement (Pass 3): 0
+Total Feed-Alignment Movement (Pass 4): 0
+Total Feed-Alignment Movement (Pass 5): 0
+Total Feed-Alignment Movement (Pass 6): 0
+Total Feed-Alignment Movement (Pass 7): 0
+Total Feed-Alignment Movement (Pass 8): 0
+
+The rand generator seed was at globroute() : 987654321
+
+
+Total Number of Net Segments: 9
+Number of Switchable Net Segments: 0
+
+Number of channels: 3
+
+
+
+THIS IS THE ORIGINAL NUMBER OF TRACKS: 5
+
+
+no. of accepted flips: 0
+no. of attempted flips: 0
+THIS IS THE NUMBER OF TRACKS: 5
+
+
+
+FINAL NUMBER OF ROUTING TRACKS: 5
+
+MAX OF CHANNEL: 1 is: 0
+MAX OF CHANNEL: 2 is: 4
+MAX OF CHANNEL: 3 is: 1
+FINAL TOTAL INTERCONNECT LENGTH: 978
+FINAL OVERLAP PENALTY: 0 FINAL VALUE OF TOTAL COST IS: 978
+MAX NUMBER OF ATTEMPTED FLIPS PER T: 55
+
+
+cost_scale_factor:3.90616
+
+Number of Feed Thrus: 0
+Number of Implicit Feed Thrus: 0
+
+Statistics:
+Number of Standard Cells: 10
+Number of Pads: 0
+Number of Nets: 15
+Number of Pins: 46
+Usage statistics not available
diff --git a/tests/long/70.twolf/ref/alpha/linux/o3-timing/smred.pin b/tests/long/70.twolf/ref/alpha/linux/o3-timing/smred.pin
new file mode 100644
index 000000000..62b922e4e
--- /dev/null
+++ b/tests/long/70.twolf/ref/alpha/linux/o3-timing/smred.pin
@@ -0,0 +1,17 @@
+$COUNT_1/$AND2_1/$ND2_1$Z 1 $COUNT_1/$AND2_1/$ND2_1 00#Z 17 52 2 1 0
+$COUNT_1/$AND2_1/$ND2_1$Z 1 ACOUNT_1 00#A 15 26 2 -1 0
+B7 2 $COUNT_1/$FJK3_2 00#K 25 78 3 -1 0
+B7 2 $COUNT_1/$FJK3_2 00#J 23 78 3 -1 0
+B7 3 $COUNT_1/$AND2_2/$ND2_1 00#A 9 26 2 -1 0
+B7 3 ACOUNT_1 01#Z 17 26 2 -1 0
+B6 5 $COUNT_1/$FJK3_1 00#K 25 26 2 -1 0
+B6 5 $COUNT_1/$FJK3_1 00#J 23 26 2 -1 0
+B6 5 $COUNT_1/$AND2_3/$IV_1 01#Z 7 26 2 -1 0
+$COUNT_1/$FJK3_1$Q 6 $COUNT_1/$FJK3_1 01#Q 81 26 2 -1 0
+$COUNT_1/$FJK3_1$Q 6 $COUNT_1/$AND2_1/$ND2_1 00#B 19 52 2 1 0
+$COUNT_1/$FJK3_2$Q 7 $COUNT_1/$FJK3_2 00#Q 81 52 2 1 0
+$COUNT_1/$FJK3_2$Q 7 $COUNT_1/$AND2_2/$ND2_1 01#B 11 26 2 -1 0
+$COUNT_1/$AND2_3/$ND2_1$Z 8 $COUNT_1/$AND2_3/$ND2_1 00#Z 5 52 2 1 0
+$COUNT_1/$AND2_3/$ND2_1$Z 8 $COUNT_1/$AND2_3/$IV_1 00#A 5 26 2 -1 0
+$COUNT_1/$AND2_4/$ND2_1$Z 9 $COUNT_1/$AND2_4/$ND2_1 00#Z 7 52 2 1 0
+$COUNT_1/$AND2_4/$ND2_1$Z 9 $COUNT_1/$AND2_4/$IV_1 00#A 3 26 2 -1 0
diff --git a/tests/long/70.twolf/ref/alpha/linux/o3-timing/smred.pl1 b/tests/long/70.twolf/ref/alpha/linux/o3-timing/smred.pl1
new file mode 100644
index 000000000..bdc569e39
--- /dev/null
+++ b/tests/long/70.twolf/ref/alpha/linux/o3-timing/smred.pl1
@@ -0,0 +1,11 @@
+$COUNT_1/$AND2_4/$IV_1 0 0 4 26 0 1
+$COUNT_1/$AND2_3/$IV_1 4 0 8 26 2 1
+$COUNT_1/$AND2_2/$ND2_1 8 0 14 26 0 1
+ACOUNT_1 14 0 18 26 2 1
+twfeed1 18 0 22 26 0 1
+$COUNT_1/$FJK3_1 22 0 86 26 0 1
+$COUNT_1/$AND2_3/$ND2_1 0 52 6 78 0 2
+$COUNT_1/$AND2_4/$ND2_1 6 52 12 78 2 2
+$COUNT_1/$AND2_2/$IV_1 12 52 16 78 2 2
+$COUNT_1/$AND2_1/$ND2_1 16 52 22 78 2 2
+$COUNT_1/$FJK3_2 22 52 86 78 0 2
diff --git a/tests/long/70.twolf/ref/alpha/linux/o3-timing/smred.pl2 b/tests/long/70.twolf/ref/alpha/linux/o3-timing/smred.pl2
new file mode 100644
index 000000000..6e2601e82
--- /dev/null
+++ b/tests/long/70.twolf/ref/alpha/linux/o3-timing/smred.pl2
@@ -0,0 +1,2 @@
+1 0 0 86 26 0 0
+2 0 52 86 78 0 0
diff --git a/tests/long/70.twolf/ref/alpha/linux/o3-timing/smred.sav b/tests/long/70.twolf/ref/alpha/linux/o3-timing/smred.sav
new file mode 100644
index 000000000..04c8e9935
--- /dev/null
+++ b/tests/long/70.twolf/ref/alpha/linux/o3-timing/smred.sav
@@ -0,0 +1,18 @@
+0.009592
+121
+0
+1
+0.000000
+0.500000
+3.906156
+1
+1 1 2 37 13
+2 2 0 34 65
+3 2 2 63 65
+4 1 0 59 13
+5 1 2 32 13
+6 2 0 23 65
+7 1 2 12 13
+8 2 0 6 65
+9 1 0 70 13
+10 2 0 70 65
diff --git a/tests/long/70.twolf/ref/alpha/linux/o3-timing/smred.sv2 b/tests/long/70.twolf/ref/alpha/linux/o3-timing/smred.sv2
new file mode 100644
index 000000000..9dd68ecdb
--- /dev/null
+++ b/tests/long/70.twolf/ref/alpha/linux/o3-timing/smred.sv2
@@ -0,0 +1,19 @@
+0.001000
+123
+0
+2
+0.000000
+0.500000
+3.906156
+1
+1 1 2 16 13
+2 2 2 19 65
+3 2 2 14 65
+4 1 0 11 13
+5 1 2 6 13
+6 2 0 3 65
+7 1 0 2 13
+8 2 2 9 65
+9 1 0 50 13
+10 2 0 54 65
+11 1 0 84 13
diff --git a/tests/long/70.twolf/ref/alpha/linux/o3-timing/smred.twf b/tests/long/70.twolf/ref/alpha/linux/o3-timing/smred.twf
new file mode 100644
index 000000000..a4c2eac35
--- /dev/null
+++ b/tests/long/70.twolf/ref/alpha/linux/o3-timing/smred.twf
@@ -0,0 +1,29 @@
+net 1
+segment channel 2
+ pin1 1 pin2 7 0 0
+net 2
+segment channel 3
+pin1 41 pin2 42 0 0
+segment channel 2
+pin1 12 pin2 3 0 0
+net 3
+segment channel 2
+pin1 35 pin2 36 0 0
+segment channel 2
+pin1 19 pin2 35 0 0
+net 4
+segment channel 2
+ pin1 5 pin2 38 0 0
+net 5
+net 7
+segment channel 2
+ pin1 14 pin2 43 0 0
+net 8
+segment channel 2
+ pin1 23 pin2 17 0 0
+net 9
+net 11
+segment channel 2
+ pin1 25 pin2 31 0 0
+net 14
+net 15
diff --git a/tests/long/70.twolf/ref/alpha/linux/o3-timing/stderr b/tests/long/70.twolf/ref/alpha/linux/o3-timing/stderr
index 8893caac8..87866a2a5 100644
--- a/tests/long/70.twolf/ref/alpha/linux/o3-timing/stderr
+++ b/tests/long/70.twolf/ref/alpha/linux/o3-timing/stderr
@@ -1,3 +1 @@
warn: Entering event queue @ 0. Starting simulation...
-warn: cycle 0: fault (page_table_fault) detected @ PC 0x000000
-warn: Increasing stack 0x11ff92000:0x11ff9b000 to 0x11ff90000:0x11ff9b000 because of access to 0x11ff91ff0
diff --git a/tests/long/70.twolf/ref/alpha/linux/o3-timing/stdout b/tests/long/70.twolf/ref/alpha/linux/o3-timing/stdout
index fbb329a2f..f32f0a972 100644
--- a/tests/long/70.twolf/ref/alpha/linux/o3-timing/stdout
+++ b/tests/long/70.twolf/ref/alpha/linux/o3-timing/stdout
@@ -1,13 +1,14 @@
-Hello world!
-M5 Simulator System
-Copyright (c) 2001-2006
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Sep 5 2006 15:28:48
-M5 started Tue Sep 5 15:42:12 2006
-M5 executing on zizzer.eecs.umich.edu
-command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/o3-timing tests/run.py quick/00.hello/alpha/linux/o3-timing
-Exiting @ tick 6870 because target called exit()
+TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988
+Standard Cell Placement and Global Routing Program
+Authors: Carl Sechen, Bill Swartz
+ Yale University
+ 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
+ 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
+ 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
+ 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
+ 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75
+ 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
+ 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
+106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
+122 123 124 \ No newline at end of file
diff --git a/tests/long/70.twolf/ref/alpha/linux/simple-atomic/config.ini b/tests/long/70.twolf/ref/alpha/linux/simple-atomic/config.ini
index c3a59fbce..fbf8dd865 100644
--- a/tests/long/70.twolf/ref/alpha/linux/simple-atomic/config.ini
+++ b/tests/long/70.twolf/ref/alpha/linux/simple-atomic/config.ini
@@ -7,11 +7,9 @@ max_tick=0
output_file=cout
progress_interval=0
-[debug]
-break_cycles=
-
[exetrace]
intel_format=false
+legion_lockstep=false
pc_symbol=true
print_cpseq=false
print_cycle=true
@@ -53,352 +51,49 @@ mem_mode=atomic
physmem=system.physmem
[system.cpu]
-type=DerivO3CPU
-children=dcache fuPool icache l2cache toL2Bus workload
-BTBEntries=4096
-BTBTagSize=16
-LFSTSize=1024
-LQEntries=32
-RASSize=16
-SQEntries=32
-SSITSize=1024
-activity=0
-backComSize=5
-choiceCtrBits=2
-choicePredictorSize=8192
+type=AtomicSimpleCPU
+children=workload
clock=1
-commitToDecodeDelay=1
-commitToFetchDelay=1
-commitToIEWDelay=1
-commitToRenameDelay=1
-commitWidth=8
-decodeToFetchDelay=1
-decodeToRenameDelay=1
-decodeWidth=8
+cpu_id=0
defer_registration=false
-dispatchWidth=8
-fetchToDecodeDelay=1
-fetchTrapLatency=1
-fetchWidth=8
-forwardComSize=5
-fuPool=system.cpu.fuPool
function_trace=false
function_trace_start=0
-globalCtrBits=2
-globalHistoryBits=13
-globalPredictorSize=8192
-iewToCommitDelay=1
-iewToDecodeDelay=1
-iewToFetchDelay=1
-iewToRenameDelay=1
-instShiftAmt=2
-issueToExecuteDelay=1
-issueWidth=8
-localCtrBits=2
-localHistoryBits=11
-localHistoryTableSize=2048
-localPredictorSize=2048
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
-mem=system.cpu.dcache
-numIQEntries=64
-numPhysFloatRegs=256
-numPhysIntRegs=256
-numROBEntries=192
-numRobs=1
-numThreads=1
-predType=tournament
-renameToDecodeDelay=1
-renameToFetchDelay=1
-renameToIEWDelay=2
-renameToROBDelay=1
-renameWidth=8
-squashWidth=8
+phase=0
+progress_interval=0
+simulate_stalls=false
system=system
-trapLatency=13
-wbDepth=1
-wbWidth=8
+width=1
workload=system.cpu.workload
-dcache_port=system.cpu.dcache.cpu_side
-icache_port=system.cpu.icache.cpu_side
-
-[system.cpu.dcache]
-type=BaseCache
-adaptive_compression=false
-assoc=2
-block_size=64
-compressed_bus=false
-compression_latency=0
-do_copy=false
-hash_delay=1
-hit_latency=1
-latency=1
-lifo=false
-max_miss_count=0
-mshrs=10
-prefetch_access=false
-prefetch_cache_check_push=true
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10
-prefetch_miss=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
-prioritizeRequests=false
-protocol=Null
-repl=Null
-size=262144
-split=false
-split_size=0
-store_compressed=false
-subblock_size=0
-tgts_per_mshr=5
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu.dcache_port
-mem_side=system.cpu.toL2Bus.port[1]
-
-[system.cpu.fuPool]
-type=FUPool
-children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7
-FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7
-
-[system.cpu.fuPool.FUList0]
-type=FUDesc
-children=opList0
-count=6
-opList=system.cpu.fuPool.FUList0.opList0
-
-[system.cpu.fuPool.FUList0.opList0]
-type=OpDesc
-issueLat=1
-opClass=IntAlu
-opLat=1
-
-[system.cpu.fuPool.FUList1]
-type=FUDesc
-children=opList0 opList1
-count=2
-opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
-
-[system.cpu.fuPool.FUList1.opList0]
-type=OpDesc
-issueLat=1
-opClass=IntMult
-opLat=3
-
-[system.cpu.fuPool.FUList1.opList1]
-type=OpDesc
-issueLat=19
-opClass=IntDiv
-opLat=20
-
-[system.cpu.fuPool.FUList2]
-type=FUDesc
-children=opList0 opList1 opList2
-count=4
-opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
-
-[system.cpu.fuPool.FUList2.opList0]
-type=OpDesc
-issueLat=1
-opClass=FloatAdd
-opLat=2
-
-[system.cpu.fuPool.FUList2.opList1]
-type=OpDesc
-issueLat=1
-opClass=FloatCmp
-opLat=2
-
-[system.cpu.fuPool.FUList2.opList2]
-type=OpDesc
-issueLat=1
-opClass=FloatCvt
-opLat=2
-
-[system.cpu.fuPool.FUList3]
-type=FUDesc
-children=opList0 opList1 opList2
-count=2
-opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
-
-[system.cpu.fuPool.FUList3.opList0]
-type=OpDesc
-issueLat=1
-opClass=FloatMult
-opLat=4
-
-[system.cpu.fuPool.FUList3.opList1]
-type=OpDesc
-issueLat=12
-opClass=FloatDiv
-opLat=12
-
-[system.cpu.fuPool.FUList3.opList2]
-type=OpDesc
-issueLat=24
-opClass=FloatSqrt
-opLat=24
-
-[system.cpu.fuPool.FUList4]
-type=FUDesc
-children=opList0
-count=0
-opList=system.cpu.fuPool.FUList4.opList0
-
-[system.cpu.fuPool.FUList4.opList0]
-type=OpDesc
-issueLat=1
-opClass=MemRead
-opLat=1
-
-[system.cpu.fuPool.FUList5]
-type=FUDesc
-children=opList0
-count=0
-opList=system.cpu.fuPool.FUList5.opList0
-
-[system.cpu.fuPool.FUList5.opList0]
-type=OpDesc
-issueLat=1
-opClass=MemWrite
-opLat=1
-
-[system.cpu.fuPool.FUList6]
-type=FUDesc
-children=opList0 opList1
-count=4
-opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1
-
-[system.cpu.fuPool.FUList6.opList0]
-type=OpDesc
-issueLat=1
-opClass=MemRead
-opLat=1
-
-[system.cpu.fuPool.FUList6.opList1]
-type=OpDesc
-issueLat=1
-opClass=MemWrite
-opLat=1
-
-[system.cpu.fuPool.FUList7]
-type=FUDesc
-children=opList0
-count=1
-opList=system.cpu.fuPool.FUList7.opList0
-
-[system.cpu.fuPool.FUList7.opList0]
-type=OpDesc
-issueLat=3
-opClass=IprAccess
-opLat=3
-
-[system.cpu.icache]
-type=BaseCache
-adaptive_compression=false
-assoc=2
-block_size=64
-compressed_bus=false
-compression_latency=0
-do_copy=false
-hash_delay=1
-hit_latency=1
-latency=1
-lifo=false
-max_miss_count=0
-mshrs=10
-prefetch_access=false
-prefetch_cache_check_push=true
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10
-prefetch_miss=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
-prioritizeRequests=false
-protocol=Null
-repl=Null
-size=131072
-split=false
-split_size=0
-store_compressed=false
-subblock_size=0
-tgts_per_mshr=5
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu.icache_port
-mem_side=system.cpu.toL2Bus.port[0]
-
-[system.cpu.l2cache]
-type=BaseCache
-adaptive_compression=false
-assoc=2
-block_size=64
-compressed_bus=false
-compression_latency=0
-do_copy=false
-hash_delay=1
-hit_latency=1
-latency=1
-lifo=false
-max_miss_count=0
-mshrs=10
-prefetch_access=false
-prefetch_cache_check_push=true
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10
-prefetch_miss=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
-prioritizeRequests=false
-protocol=Null
-repl=Null
-size=2097152
-split=false
-split_size=0
-store_compressed=false
-subblock_size=0
-tgts_per_mshr=5
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[1]
-
-[system.cpu.toL2Bus]
-type=Bus
-bus_id=0
-port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+dcache_port=system.membus.port[2]
+icache_port=system.membus.port[1]
[system.cpu.workload]
type=LiveProcess
-cmd=hello
+cmd=twolf smred
+cwd=build/ALPHA_SE/tests/opt/long/70.twolf/alpha/linux/simple-atomic
+egid=100
env=
-executable=tests/test-progs/hello/bin/alpha/linux/hello
+euid=100
+executable=/dist/m5/cpu2000/binaries/alpha/tru64/twolf
+gid=100
input=cin
output=cout
+pid=100
+ppid=99
system=system
+uid=100
[system.membus]
type=Bus
bus_id=0
-port=system.physmem.port system.cpu.l2cache.mem_side
+clock=1000
+responder_set=false
+width=64
+port=system.physmem.port system.cpu.icache_port system.cpu.dcache_port
[system.physmem]
type=PhysicalMemory
@@ -409,6 +104,7 @@ port=system.membus.port[0]
[trace]
bufsize=0
+cycle=0
dump_on_exit=false
file=cout
flags=
diff --git a/tests/long/70.twolf/ref/alpha/linux/simple-atomic/config.out b/tests/long/70.twolf/ref/alpha/linux/simple-atomic/config.out
index f491a3081..5375d2a8f 100644
--- a/tests/long/70.twolf/ref/alpha/linux/simple-atomic/config.out
+++ b/tests/long/70.twolf/ref/alpha/linux/simple-atomic/config.out
@@ -19,345 +19,48 @@ mem_mode=atomic
[system.membus]
type=Bus
bus_id=0
+clock=1000
+width=64
+responder_set=false
[system.cpu.workload]
type=LiveProcess
-cmd=hello
-executable=tests/test-progs/hello/bin/alpha/linux/hello
+cmd=twolf smred
+executable=/dist/m5/cpu2000/binaries/alpha/tru64/twolf
input=cin
output=cout
env=
+cwd=build/ALPHA_SE/tests/opt/long/70.twolf/alpha/linux/simple-atomic
system=system
-
-[system.cpu.dcache]
-type=BaseCache
-size=262144
-assoc=2
-block_size=64
-latency=1
-mshrs=10
-tgts_per_mshr=5
-write_buffers=8
-prioritizeRequests=false
-do_copy=false
-protocol=null
-trace_addr=0
-hash_delay=1
-repl=null
-compressed_bus=false
-store_compressed=false
-adaptive_compression=false
-compression_latency=0
-block_size=64
-max_miss_count=0
-addr_range=[0,18446744073709551615]
-split=false
-split_size=0
-lifo=false
-two_queue=false
-prefetch_miss=false
-prefetch_access=false
-prefetcher_size=100
-prefetch_past_page=false
-prefetch_serial_squash=false
-prefetch_latency=10
-prefetch_degree=1
-prefetch_policy=none
-prefetch_cache_check_push=true
-prefetch_use_cpu_id=true
-prefetch_data_accesses_only=false
-hit_latency=1
-
-[system.cpu.fuPool.FUList0.opList0]
-type=OpDesc
-opClass=IntAlu
-opLat=1
-issueLat=1
-
-[system.cpu.fuPool.FUList0]
-type=FUDesc
-opList=system.cpu.fuPool.FUList0.opList0
-count=6
-
-[system.cpu.fuPool.FUList1.opList0]
-type=OpDesc
-opClass=IntMult
-opLat=3
-issueLat=1
-
-[system.cpu.fuPool.FUList1.opList1]
-type=OpDesc
-opClass=IntDiv
-opLat=20
-issueLat=19
-
-[system.cpu.fuPool.FUList1]
-type=FUDesc
-opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
-count=2
-
-[system.cpu.fuPool.FUList2.opList0]
-type=OpDesc
-opClass=FloatAdd
-opLat=2
-issueLat=1
-
-[system.cpu.fuPool.FUList2.opList1]
-type=OpDesc
-opClass=FloatCmp
-opLat=2
-issueLat=1
-
-[system.cpu.fuPool.FUList2.opList2]
-type=OpDesc
-opClass=FloatCvt
-opLat=2
-issueLat=1
-
-[system.cpu.fuPool.FUList2]
-type=FUDesc
-opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
-count=4
-
-[system.cpu.fuPool.FUList3.opList0]
-type=OpDesc
-opClass=FloatMult
-opLat=4
-issueLat=1
-
-[system.cpu.fuPool.FUList3.opList1]
-type=OpDesc
-opClass=FloatDiv
-opLat=12
-issueLat=12
-
-[system.cpu.fuPool.FUList3.opList2]
-type=OpDesc
-opClass=FloatSqrt
-opLat=24
-issueLat=24
-
-[system.cpu.fuPool.FUList3]
-type=FUDesc
-opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
-count=2
-
-[system.cpu.fuPool.FUList4.opList0]
-type=OpDesc
-opClass=MemRead
-opLat=1
-issueLat=1
-
-[system.cpu.fuPool.FUList4]
-type=FUDesc
-opList=system.cpu.fuPool.FUList4.opList0
-count=0
-
-[system.cpu.fuPool.FUList5.opList0]
-type=OpDesc
-opClass=MemWrite
-opLat=1
-issueLat=1
-
-[system.cpu.fuPool.FUList5]
-type=FUDesc
-opList=system.cpu.fuPool.FUList5.opList0
-count=0
-
-[system.cpu.fuPool.FUList6.opList0]
-type=OpDesc
-opClass=MemRead
-opLat=1
-issueLat=1
-
-[system.cpu.fuPool.FUList6.opList1]
-type=OpDesc
-opClass=MemWrite
-opLat=1
-issueLat=1
-
-[system.cpu.fuPool.FUList6]
-type=FUDesc
-opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1
-count=4
-
-[system.cpu.fuPool.FUList7.opList0]
-type=OpDesc
-opClass=IprAccess
-opLat=3
-issueLat=3
-
-[system.cpu.fuPool.FUList7]
-type=FUDesc
-opList=system.cpu.fuPool.FUList7.opList0
-count=1
-
-[system.cpu.fuPool]
-type=FUPool
-FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7
+uid=100
+euid=100
+gid=100
+egid=100
+pid=100
+ppid=99
[system.cpu]
-type=DerivO3CPU
-clock=1
-numThreads=1
-activity=0
-workload=system.cpu.workload
-mem=system.cpu.dcache
-checker=null
+type=AtomicSimpleCPU
max_insts_any_thread=0
max_insts_all_threads=0
max_loads_any_thread=0
max_loads_all_threads=0
-cachePorts=200
-decodeToFetchDelay=1
-renameToFetchDelay=1
-iewToFetchDelay=1
-commitToFetchDelay=1
-fetchWidth=8
-renameToDecodeDelay=1
-iewToDecodeDelay=1
-commitToDecodeDelay=1
-fetchToDecodeDelay=1
-decodeWidth=8
-iewToRenameDelay=1
-commitToRenameDelay=1
-decodeToRenameDelay=1
-renameWidth=8
-commitToIEWDelay=1
-renameToIEWDelay=2
-issueToExecuteDelay=1
-dispatchWidth=8
-issueWidth=8
-wbWidth=8
-wbDepth=1
-fuPool=system.cpu.fuPool
-iewToCommitDelay=1
-renameToROBDelay=1
-commitWidth=8
-squashWidth=8
-trapLatency=13
-backComSize=5
-forwardComSize=5
-predType=tournament
-localPredictorSize=2048
-localCtrBits=2
-localHistoryTableSize=2048
-localHistoryBits=11
-globalPredictorSize=8192
-globalCtrBits=2
-globalHistoryBits=13
-choicePredictorSize=8192
-choiceCtrBits=2
-BTBEntries=4096
-BTBTagSize=16
-RASSize=16
-LQEntries=32
-SQEntries=32
-LFSTSize=1024
-SSITSize=1024
-numPhysIntRegs=256
-numPhysFloatRegs=256
-numIQEntries=64
-numROBEntries=192
-smtNumFetchingThreads=1
-smtFetchPolicy=SingleThread
-smtLSQPolicy=Partitioned
-smtLSQThreshold=100
-smtIQPolicy=Partitioned
-smtIQThreshold=100
-smtROBPolicy=Partitioned
-smtROBThreshold=100
-smtCommitPolicy=RoundRobin
-instShiftAmt=2
+progress_interval=0
+system=system
+cpu_id=0
+workload=system.cpu.workload
+clock=1
+phase=0
defer_registration=false
+width=1
function_trace=false
function_trace_start=0
-
-[system.cpu.icache]
-type=BaseCache
-size=131072
-assoc=2
-block_size=64
-latency=1
-mshrs=10
-tgts_per_mshr=5
-write_buffers=8
-prioritizeRequests=false
-do_copy=false
-protocol=null
-trace_addr=0
-hash_delay=1
-repl=null
-compressed_bus=false
-store_compressed=false
-adaptive_compression=false
-compression_latency=0
-block_size=64
-max_miss_count=0
-addr_range=[0,18446744073709551615]
-split=false
-split_size=0
-lifo=false
-two_queue=false
-prefetch_miss=false
-prefetch_access=false
-prefetcher_size=100
-prefetch_past_page=false
-prefetch_serial_squash=false
-prefetch_latency=10
-prefetch_degree=1
-prefetch_policy=none
-prefetch_cache_check_push=true
-prefetch_use_cpu_id=true
-prefetch_data_accesses_only=false
-hit_latency=1
-
-[system.cpu.l2cache]
-type=BaseCache
-size=2097152
-assoc=2
-block_size=64
-latency=1
-mshrs=10
-tgts_per_mshr=5
-write_buffers=8
-prioritizeRequests=false
-do_copy=false
-protocol=null
-trace_addr=0
-hash_delay=1
-repl=null
-compressed_bus=false
-store_compressed=false
-adaptive_compression=false
-compression_latency=0
-block_size=64
-max_miss_count=0
-addr_range=[0,18446744073709551615]
-split=false
-split_size=0
-lifo=false
-two_queue=false
-prefetch_miss=false
-prefetch_access=false
-prefetcher_size=100
-prefetch_past_page=false
-prefetch_serial_squash=false
-prefetch_latency=10
-prefetch_degree=1
-prefetch_policy=none
-prefetch_cache_check_push=true
-prefetch_use_cpu_id=true
-prefetch_data_accesses_only=false
-hit_latency=1
-
-[system.cpu.toL2Bus]
-type=Bus
-bus_id=0
+simulate_stalls=false
[trace]
flags=
start=0
+cycle=0
bufsize=0
file=cout
dump_on_exit=false
@@ -396,8 +99,9 @@ print_cpseq=false
print_reg_delta=false
pc_symbol=true
intel_format=false
+legion_lockstep=false
trace_system=client
-[debug]
-break_cycles=
+[statsreset]
+reset_cycle=0
diff --git a/tests/long/70.twolf/ref/alpha/linux/simple-atomic/m5stats.txt b/tests/long/70.twolf/ref/alpha/linux/simple-atomic/m5stats.txt
index 5d4f9235a..e5e0a4991 100644
--- a/tests/long/70.twolf/ref/alpha/linux/simple-atomic/m5stats.txt
+++ b/tests/long/70.twolf/ref/alpha/linux/simple-atomic/m5stats.txt
@@ -1,1974 +1,18 @@
---------- Begin Simulation Statistics ----------
-global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-global.BPredUnit.BTBHits 542 # Number of BTB hits
-global.BPredUnit.BTBLookups 1938 # Number of BTB lookups
-global.BPredUnit.RASInCorrect 48 # Number of incorrect RAS predictions.
-global.BPredUnit.condIncorrect 420 # Number of conditional branches incorrect
-global.BPredUnit.condPredicted 1304 # Number of conditional branches predicted
-global.BPredUnit.lookups 2256 # Number of BP lookups
-global.BPredUnit.usedRAS 291 # Number of times the RAS was used to get a target.
-host_inst_rate 41797 # Simulator instruction rate (inst/s)
-host_mem_usage 160344 # Number of bytes of host memory used
-host_seconds 0.13 # Real time elapsed on the host
-host_tick_rate 50948 # Simulator tick rate (ticks/s)
-memdepunit.memDep.conflictingLoads 12 # Number of conflicting loads.
-memdepunit.memDep.conflictingStores 259 # Number of conflicting stores.
-memdepunit.memDep.insertedLoads 2050 # Number of loads inserted to the mem dependence unit.
-memdepunit.memDep.insertedStores 1221 # Number of stores inserted to the mem dependence unit.
+host_inst_rate 827042 # Simulator instruction rate (inst/s)
+host_mem_usage 146736 # Number of bytes of host memory used
+host_seconds 111.12 # Real time elapsed on the host
+host_tick_rate 827039 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 5623 # Number of instructions simulated
-sim_seconds 0.000000 # Number of seconds simulated
-sim_ticks 6870 # Number of ticks simulated
-system.cpu.commit.COM:branches 862 # Number of branches committed
-system.cpu.commit.COM:bw_lim_events 74 # number cycles where commit BW limit reached
-system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle.samples 6116
-system.cpu.commit.COM:committed_per_cycle.min_value 0
- 0 3908 6389.80%
- 1 1064 1739.70%
- 2 389 636.04%
- 3 210 343.36%
- 4 153 250.16%
- 5 93 152.06%
- 6 76 124.26%
- 7 149 243.62%
- 8 74 120.99%
-system.cpu.commit.COM:committed_per_cycle.max_value 8
-system.cpu.commit.COM:committed_per_cycle.end_dist
-
-system.cpu.commit.COM:count 5640 # Number of instructions committed
-system.cpu.commit.COM:loads 979 # Number of loads committed
-system.cpu.commit.COM:membars 0 # Number of memory barriers committed
-system.cpu.commit.COM:refs 1791 # Number of memory references committed
-system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.branchMispredicts 337 # The number of times a branch was mispredicted
-system.cpu.commit.commitCommittedInsts 5640 # The number of committed instructions
-system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.commitSquashedInsts 4350 # The number of squashed insts skipped by commit
-system.cpu.committedInsts 5623 # Number of Instructions Simulated
-system.cpu.committedInsts_total 5623 # Number of Instructions Simulated
-system.cpu.cpi 1.221768 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 1.221768 # CPI: Total CPI of All Threads
-system.cpu.dcache.ReadReq_accesses 1538 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 3.072000 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2.240000 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits 1413 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 384 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate 0.081274 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses 125 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_hits 25 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_miss_latency 224 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate 0.065020 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses 100 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_accesses 821 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 2.467742 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2.140845 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 635 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 459 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.226553 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 186 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_hits 108 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_miss_latency 152 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.086480 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 71 # number of WriteReq MSHR misses
-system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles_no_targets 0.800000 # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 11.505618 # Average number of references to valid blocks.
-system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_no_targets 5 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles_no_targets 4 # number of cycles access was blocked
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.demand_accesses 2359 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 2.710611 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 2.198830 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 2048 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 843 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.131836 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 311 # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits 133 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 376 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate 0.072488 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 171 # number of demand (read+write) MSHR misses
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.overall_accesses 2359 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 2.710611 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 2.198830 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 2048 # number of overall hits
-system.cpu.dcache.overall_miss_latency 843 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.131836 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 311 # number of overall misses
-system.cpu.dcache.overall_mshr_hits 133 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 376 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate 0.072488 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 171 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.dcache.replacements 0 # number of replacements
-system.cpu.dcache.sampled_refs 178 # Sample count of references to valid blocks.
-system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 119.831029 # Cycle average of tags in use
-system.cpu.dcache.total_refs 2048 # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks 0 # number of writebacks
-system.cpu.decode.DECODE:BlockedCycles 387 # Number of cycles decode is blocked
-system.cpu.decode.DECODE:BranchMispred 93 # Number of times decode detected a branch misprediction
-system.cpu.decode.DECODE:BranchResolved 185 # Number of times decode resolved a branch
-system.cpu.decode.DECODE:DecodedInsts 12349 # Number of instructions handled by decode
-system.cpu.decode.DECODE:IdleCycles 3542 # Number of cycles decode is idle
-system.cpu.decode.DECODE:RunCycles 2158 # Number of cycles decode is running
-system.cpu.decode.DECODE:SquashCycles 754 # Number of cycles decode is squashing
-system.cpu.decode.DECODE:SquashedInsts 286 # Number of squashed instructions handled by decode
-system.cpu.decode.DECODE:UnblockCycles 30 # Number of cycles decode is unblocking
-system.cpu.fetch.Branches 2256 # Number of branches that fetch encountered
-system.cpu.fetch.CacheLines 1582 # Number of cache lines fetched
-system.cpu.fetch.Cycles 3905 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.IcacheSquashes 148 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.Insts 13707 # Number of instructions fetch has processed
-system.cpu.fetch.SquashCycles 456 # Number of cycles fetch has spent squashing
-system.cpu.fetch.branchRate 0.328336 # Number of branch fetches per cycle
-system.cpu.fetch.icacheStallCycles 1582 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.predictedBranches 833 # Number of branches that fetch has predicted taken
-system.cpu.fetch.rate 1.994906 # Number of inst fetches per cycle
-system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist.samples 6871
-system.cpu.fetch.rateDist.min_value 0
- 0 4549 6620.58%
- 1 174 253.24%
- 2 186 270.70%
- 3 157 228.50%
- 4 211 307.09%
- 5 153 222.68%
- 6 171 248.87%
- 7 105 152.82%
- 8 1165 1695.53%
-system.cpu.fetch.rateDist.max_value 8
-system.cpu.fetch.rateDist.end_dist
-
-system.cpu.icache.ReadReq_accesses 1582 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 2.960245 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 1.996885 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits 1255 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 968 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate 0.206700 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses 327 # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_hits 6 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_miss_latency 641 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.202908 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses 321 # number of ReadReq MSHR misses
-system.cpu.icache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles_no_targets no value # average number of cycles each access was blocked
-system.cpu.icache.avg_refs 3.909657 # Average number of references to valid blocks.
-system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.demand_accesses 1582 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 2.960245 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 1.996885 # average overall mshr miss latency
-system.cpu.icache.demand_hits 1255 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 968 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate 0.206700 # miss rate for demand accesses
-system.cpu.icache.demand_misses 327 # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_hits 6 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 641 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate 0.202908 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses 321 # number of demand (read+write) MSHR misses
-system.cpu.icache.fast_writes 0 # number of fast writes performed
-system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.overall_accesses 1582 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 2.960245 # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 1.996885 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits 1255 # number of overall hits
-system.cpu.icache.overall_miss_latency 968 # number of overall miss cycles
-system.cpu.icache.overall_miss_rate 0.206700 # miss rate for overall accesses
-system.cpu.icache.overall_misses 327 # number of overall misses
-system.cpu.icache.overall_mshr_hits 6 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 641 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate 0.202908 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses 321 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.icache.replacements 0 # number of replacements
-system.cpu.icache.sampled_refs 321 # Sample count of references to valid blocks.
-system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 176.393247 # Cycle average of tags in use
-system.cpu.icache.total_refs 1255 # Total number of references to valid blocks.
-system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.iew.EXEC:branches 1206 # Number of branches executed
-system.cpu.iew.EXEC:insts 7969 # Number of executed instructions
-system.cpu.iew.EXEC:loads 1610 # Number of load instructions executed
-system.cpu.iew.EXEC:nop 37 # number of nop insts executed
-system.cpu.iew.EXEC:rate 1.159802 # Inst execution rate
-system.cpu.iew.EXEC:refs 2599 # number of memory reference insts executed
-system.cpu.iew.EXEC:squashedInsts 419 # Number of squashed instructions skipped in execute
-system.cpu.iew.EXEC:stores 989 # Number of stores executed
-system.cpu.iew.EXEC:swp 0 # number of swp insts executed
-system.cpu.iew.WB:consumers 5438 # num instructions consuming a value
-system.cpu.iew.WB:count 7722 # cumulative count of insts written-back
-system.cpu.iew.WB:fanout 0.744575 # average fanout of values written-back
-system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.iew.WB:producers 4049 # num instructions producing a value
-system.cpu.iew.WB:rate 1.123854 # insts written-back per cycle
-system.cpu.iew.WB:sent 7762 # cumulative count of insts sent to commit
-system.cpu.iew.branchMispredicts 393 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewBlockCycles 4 # Number of cycles IEW is blocking
-system.cpu.iew.iewDispLoadInsts 2050 # Number of dispatched load instructions
-system.cpu.iew.iewDispNonSpecInsts 21 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewDispSquashedInsts 272 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispStoreInsts 1221 # Number of dispatched store instructions
-system.cpu.iew.iewDispatchedInsts 9990 # Number of instructions dispatched to IQ
-system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.iewSquashCycles 754 # Number of cycles IEW is squashing
-system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking
-system.cpu.iew.lsq.thread.0.blockedLoads 1 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread.0.cacheBlocked 5 # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.lsq.thread.0.forwLoads 55 # Number of loads that had data forwarded from stores
-system.cpu.iew.lsq.thread.0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
-system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread.0.squashedLoads 1071 # Number of loads squashed
-system.cpu.iew.lsq.thread.0.squashedStores 409 # Number of stores squashed
-system.cpu.iew.memOrderViolationEvents 41 # Number of memory order violations
-system.cpu.iew.predictedNotTakenIncorrect 296 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.predictedTakenIncorrect 97 # Number of branches that were predicted taken incorrectly
-system.cpu.ipc 0.818486 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.818486 # IPC: Total IPC of All Threads
-system.cpu.iq.IQ:residence:(null).start_dist # cycles from dispatch to issue
-system.cpu.iq.IQ:residence:(null).samples 0
-system.cpu.iq.IQ:residence:(null).min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
- 20 0
- 22 0
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- 94 0
- 96 0
- 98 0
-system.cpu.iq.IQ:residence:(null).max_value 0
-system.cpu.iq.IQ:residence:(null).end_dist
-
-system.cpu.iq.IQ:residence:IntAlu.start_dist # cycles from dispatch to issue
-system.cpu.iq.IQ:residence:IntAlu.samples 0
-system.cpu.iq.IQ:residence:IntAlu.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
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- 96 0
- 98 0
-system.cpu.iq.IQ:residence:IntAlu.max_value 0
-system.cpu.iq.IQ:residence:IntAlu.end_dist
-
-system.cpu.iq.IQ:residence:IntMult.start_dist # cycles from dispatch to issue
-system.cpu.iq.IQ:residence:IntMult.samples 0
-system.cpu.iq.IQ:residence:IntMult.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
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- 12 0
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- 94 0
- 96 0
- 98 0
-system.cpu.iq.IQ:residence:IntMult.max_value 0
-system.cpu.iq.IQ:residence:IntMult.end_dist
-
-system.cpu.iq.IQ:residence:IntDiv.start_dist # cycles from dispatch to issue
-system.cpu.iq.IQ:residence:IntDiv.samples 0
-system.cpu.iq.IQ:residence:IntDiv.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
- 20 0
- 22 0
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- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.IQ:residence:IntDiv.max_value 0
-system.cpu.iq.IQ:residence:IntDiv.end_dist
-
-system.cpu.iq.IQ:residence:FloatAdd.start_dist # cycles from dispatch to issue
-system.cpu.iq.IQ:residence:FloatAdd.samples 0
-system.cpu.iq.IQ:residence:FloatAdd.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
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- 86 0
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- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.IQ:residence:FloatAdd.max_value 0
-system.cpu.iq.IQ:residence:FloatAdd.end_dist
-
-system.cpu.iq.IQ:residence:FloatCmp.start_dist # cycles from dispatch to issue
-system.cpu.iq.IQ:residence:FloatCmp.samples 0
-system.cpu.iq.IQ:residence:FloatCmp.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
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- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.IQ:residence:FloatCmp.max_value 0
-system.cpu.iq.IQ:residence:FloatCmp.end_dist
-
-system.cpu.iq.IQ:residence:FloatCvt.start_dist # cycles from dispatch to issue
-system.cpu.iq.IQ:residence:FloatCvt.samples 0
-system.cpu.iq.IQ:residence:FloatCvt.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
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- 96 0
- 98 0
-system.cpu.iq.IQ:residence:FloatCvt.max_value 0
-system.cpu.iq.IQ:residence:FloatCvt.end_dist
-
-system.cpu.iq.IQ:residence:FloatMult.start_dist # cycles from dispatch to issue
-system.cpu.iq.IQ:residence:FloatMult.samples 0
-system.cpu.iq.IQ:residence:FloatMult.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
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- 94 0
- 96 0
- 98 0
-system.cpu.iq.IQ:residence:FloatMult.max_value 0
-system.cpu.iq.IQ:residence:FloatMult.end_dist
-
-system.cpu.iq.IQ:residence:FloatDiv.start_dist # cycles from dispatch to issue
-system.cpu.iq.IQ:residence:FloatDiv.samples 0
-system.cpu.iq.IQ:residence:FloatDiv.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
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- 96 0
- 98 0
-system.cpu.iq.IQ:residence:FloatDiv.max_value 0
-system.cpu.iq.IQ:residence:FloatDiv.end_dist
-
-system.cpu.iq.IQ:residence:FloatSqrt.start_dist # cycles from dispatch to issue
-system.cpu.iq.IQ:residence:FloatSqrt.samples 0
-system.cpu.iq.IQ:residence:FloatSqrt.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
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- 14 0
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- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.IQ:residence:FloatSqrt.max_value 0
-system.cpu.iq.IQ:residence:FloatSqrt.end_dist
-
-system.cpu.iq.IQ:residence:MemRead.start_dist # cycles from dispatch to issue
-system.cpu.iq.IQ:residence:MemRead.samples 0
-system.cpu.iq.IQ:residence:MemRead.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
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- 16 0
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- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.IQ:residence:MemRead.max_value 0
-system.cpu.iq.IQ:residence:MemRead.end_dist
-
-system.cpu.iq.IQ:residence:MemWrite.start_dist # cycles from dispatch to issue
-system.cpu.iq.IQ:residence:MemWrite.samples 0
-system.cpu.iq.IQ:residence:MemWrite.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
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- 92 0
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- 96 0
- 98 0
-system.cpu.iq.IQ:residence:MemWrite.max_value 0
-system.cpu.iq.IQ:residence:MemWrite.end_dist
-
-system.cpu.iq.IQ:residence:IprAccess.start_dist # cycles from dispatch to issue
-system.cpu.iq.IQ:residence:IprAccess.samples 0
-system.cpu.iq.IQ:residence:IprAccess.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
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- 94 0
- 96 0
- 98 0
-system.cpu.iq.IQ:residence:IprAccess.max_value 0
-system.cpu.iq.IQ:residence:IprAccess.end_dist
-
-system.cpu.iq.IQ:residence:InstPrefetch.start_dist # cycles from dispatch to issue
-system.cpu.iq.IQ:residence:InstPrefetch.samples 0
-system.cpu.iq.IQ:residence:InstPrefetch.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
- 20 0
- 22 0
- 24 0
- 26 0
- 28 0
- 30 0
- 32 0
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- 36 0
- 38 0
- 40 0
- 42 0
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- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.IQ:residence:InstPrefetch.max_value 0
-system.cpu.iq.IQ:residence:InstPrefetch.end_dist
-
-system.cpu.iq.ISSUE:(null)_delay.start_dist # cycles from operands ready to issue
-system.cpu.iq.ISSUE:(null)_delay.samples 0
-system.cpu.iq.ISSUE:(null)_delay.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
- 20 0
- 22 0
- 24 0
- 26 0
- 28 0
- 30 0
- 32 0
- 34 0
- 36 0
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- 78 0
- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.ISSUE:(null)_delay.max_value 0
-system.cpu.iq.ISSUE:(null)_delay.end_dist
-
-system.cpu.iq.ISSUE:IntAlu_delay.start_dist # cycles from operands ready to issue
-system.cpu.iq.ISSUE:IntAlu_delay.samples 0
-system.cpu.iq.ISSUE:IntAlu_delay.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
- 20 0
- 22 0
- 24 0
- 26 0
- 28 0
- 30 0
- 32 0
- 34 0
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- 78 0
- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.ISSUE:IntAlu_delay.max_value 0
-system.cpu.iq.ISSUE:IntAlu_delay.end_dist
-
-system.cpu.iq.ISSUE:IntMult_delay.start_dist # cycles from operands ready to issue
-system.cpu.iq.ISSUE:IntMult_delay.samples 0
-system.cpu.iq.ISSUE:IntMult_delay.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
- 20 0
- 22 0
- 24 0
- 26 0
- 28 0
- 30 0
- 32 0
- 34 0
- 36 0
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- 40 0
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- 50 0
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- 76 0
- 78 0
- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.ISSUE:IntMult_delay.max_value 0
-system.cpu.iq.ISSUE:IntMult_delay.end_dist
-
-system.cpu.iq.ISSUE:IntDiv_delay.start_dist # cycles from operands ready to issue
-system.cpu.iq.ISSUE:IntDiv_delay.samples 0
-system.cpu.iq.ISSUE:IntDiv_delay.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
- 20 0
- 22 0
- 24 0
- 26 0
- 28 0
- 30 0
- 32 0
- 34 0
- 36 0
- 38 0
- 40 0
- 42 0
- 44 0
- 46 0
- 48 0
- 50 0
- 52 0
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- 70 0
- 72 0
- 74 0
- 76 0
- 78 0
- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.ISSUE:IntDiv_delay.max_value 0
-system.cpu.iq.ISSUE:IntDiv_delay.end_dist
-
-system.cpu.iq.ISSUE:FloatAdd_delay.start_dist # cycles from operands ready to issue
-system.cpu.iq.ISSUE:FloatAdd_delay.samples 0
-system.cpu.iq.ISSUE:FloatAdd_delay.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
- 20 0
- 22 0
- 24 0
- 26 0
- 28 0
- 30 0
- 32 0
- 34 0
- 36 0
- 38 0
- 40 0
- 42 0
- 44 0
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- 50 0
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- 66 0
- 68 0
- 70 0
- 72 0
- 74 0
- 76 0
- 78 0
- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.ISSUE:FloatAdd_delay.max_value 0
-system.cpu.iq.ISSUE:FloatAdd_delay.end_dist
-
-system.cpu.iq.ISSUE:FloatCmp_delay.start_dist # cycles from operands ready to issue
-system.cpu.iq.ISSUE:FloatCmp_delay.samples 0
-system.cpu.iq.ISSUE:FloatCmp_delay.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
- 20 0
- 22 0
- 24 0
- 26 0
- 28 0
- 30 0
- 32 0
- 34 0
- 36 0
- 38 0
- 40 0
- 42 0
- 44 0
- 46 0
- 48 0
- 50 0
- 52 0
- 54 0
- 56 0
- 58 0
- 60 0
- 62 0
- 64 0
- 66 0
- 68 0
- 70 0
- 72 0
- 74 0
- 76 0
- 78 0
- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.ISSUE:FloatCmp_delay.max_value 0
-system.cpu.iq.ISSUE:FloatCmp_delay.end_dist
-
-system.cpu.iq.ISSUE:FloatCvt_delay.start_dist # cycles from operands ready to issue
-system.cpu.iq.ISSUE:FloatCvt_delay.samples 0
-system.cpu.iq.ISSUE:FloatCvt_delay.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
- 20 0
- 22 0
- 24 0
- 26 0
- 28 0
- 30 0
- 32 0
- 34 0
- 36 0
- 38 0
- 40 0
- 42 0
- 44 0
- 46 0
- 48 0
- 50 0
- 52 0
- 54 0
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- 60 0
- 62 0
- 64 0
- 66 0
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- 72 0
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- 76 0
- 78 0
- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.ISSUE:FloatCvt_delay.max_value 0
-system.cpu.iq.ISSUE:FloatCvt_delay.end_dist
-
-system.cpu.iq.ISSUE:FloatMult_delay.start_dist # cycles from operands ready to issue
-system.cpu.iq.ISSUE:FloatMult_delay.samples 0
-system.cpu.iq.ISSUE:FloatMult_delay.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
- 20 0
- 22 0
- 24 0
- 26 0
- 28 0
- 30 0
- 32 0
- 34 0
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- 40 0
- 42 0
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- 50 0
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- 72 0
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- 76 0
- 78 0
- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.ISSUE:FloatMult_delay.max_value 0
-system.cpu.iq.ISSUE:FloatMult_delay.end_dist
-
-system.cpu.iq.ISSUE:FloatDiv_delay.start_dist # cycles from operands ready to issue
-system.cpu.iq.ISSUE:FloatDiv_delay.samples 0
-system.cpu.iq.ISSUE:FloatDiv_delay.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
- 20 0
- 22 0
- 24 0
- 26 0
- 28 0
- 30 0
- 32 0
- 34 0
- 36 0
- 38 0
- 40 0
- 42 0
- 44 0
- 46 0
- 48 0
- 50 0
- 52 0
- 54 0
- 56 0
- 58 0
- 60 0
- 62 0
- 64 0
- 66 0
- 68 0
- 70 0
- 72 0
- 74 0
- 76 0
- 78 0
- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.ISSUE:FloatDiv_delay.max_value 0
-system.cpu.iq.ISSUE:FloatDiv_delay.end_dist
-
-system.cpu.iq.ISSUE:FloatSqrt_delay.start_dist # cycles from operands ready to issue
-system.cpu.iq.ISSUE:FloatSqrt_delay.samples 0
-system.cpu.iq.ISSUE:FloatSqrt_delay.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
- 20 0
- 22 0
- 24 0
- 26 0
- 28 0
- 30 0
- 32 0
- 34 0
- 36 0
- 38 0
- 40 0
- 42 0
- 44 0
- 46 0
- 48 0
- 50 0
- 52 0
- 54 0
- 56 0
- 58 0
- 60 0
- 62 0
- 64 0
- 66 0
- 68 0
- 70 0
- 72 0
- 74 0
- 76 0
- 78 0
- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.ISSUE:FloatSqrt_delay.max_value 0
-system.cpu.iq.ISSUE:FloatSqrt_delay.end_dist
-
-system.cpu.iq.ISSUE:MemRead_delay.start_dist # cycles from operands ready to issue
-system.cpu.iq.ISSUE:MemRead_delay.samples 0
-system.cpu.iq.ISSUE:MemRead_delay.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
- 20 0
- 22 0
- 24 0
- 26 0
- 28 0
- 30 0
- 32 0
- 34 0
- 36 0
- 38 0
- 40 0
- 42 0
- 44 0
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- 48 0
- 50 0
- 52 0
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- 60 0
- 62 0
- 64 0
- 66 0
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- 70 0
- 72 0
- 74 0
- 76 0
- 78 0
- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.ISSUE:MemRead_delay.max_value 0
-system.cpu.iq.ISSUE:MemRead_delay.end_dist
-
-system.cpu.iq.ISSUE:MemWrite_delay.start_dist # cycles from operands ready to issue
-system.cpu.iq.ISSUE:MemWrite_delay.samples 0
-system.cpu.iq.ISSUE:MemWrite_delay.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
- 20 0
- 22 0
- 24 0
- 26 0
- 28 0
- 30 0
- 32 0
- 34 0
- 36 0
- 38 0
- 40 0
- 42 0
- 44 0
- 46 0
- 48 0
- 50 0
- 52 0
- 54 0
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- 64 0
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- 72 0
- 74 0
- 76 0
- 78 0
- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.ISSUE:MemWrite_delay.max_value 0
-system.cpu.iq.ISSUE:MemWrite_delay.end_dist
-
-system.cpu.iq.ISSUE:IprAccess_delay.start_dist # cycles from operands ready to issue
-system.cpu.iq.ISSUE:IprAccess_delay.samples 0
-system.cpu.iq.ISSUE:IprAccess_delay.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
- 20 0
- 22 0
- 24 0
- 26 0
- 28 0
- 30 0
- 32 0
- 34 0
- 36 0
- 38 0
- 40 0
- 42 0
- 44 0
- 46 0
- 48 0
- 50 0
- 52 0
- 54 0
- 56 0
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- 60 0
- 62 0
- 64 0
- 66 0
- 68 0
- 70 0
- 72 0
- 74 0
- 76 0
- 78 0
- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.ISSUE:IprAccess_delay.max_value 0
-system.cpu.iq.ISSUE:IprAccess_delay.end_dist
-
-system.cpu.iq.ISSUE:InstPrefetch_delay.start_dist # cycles from operands ready to issue
-system.cpu.iq.ISSUE:InstPrefetch_delay.samples 0
-system.cpu.iq.ISSUE:InstPrefetch_delay.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
- 20 0
- 22 0
- 24 0
- 26 0
- 28 0
- 30 0
- 32 0
- 34 0
- 36 0
- 38 0
- 40 0
- 42 0
- 44 0
- 46 0
- 48 0
- 50 0
- 52 0
- 54 0
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- 62 0
- 64 0
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- 68 0
- 70 0
- 72 0
- 74 0
- 76 0
- 78 0
- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.ISSUE:InstPrefetch_delay.max_value 0
-system.cpu.iq.ISSUE:InstPrefetch_delay.end_dist
-
-system.cpu.iq.ISSUE:FU_type_0 8388 # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0.start_dist
- (null) 2 0.02% # Type of FU issued
- IntAlu 5594 66.69% # Type of FU issued
- IntMult 1 0.01% # Type of FU issued
- IntDiv 0 0.00% # Type of FU issued
- FloatAdd 2 0.02% # Type of FU issued
- FloatCmp 0 0.00% # Type of FU issued
- FloatCvt 0 0.00% # Type of FU issued
- FloatMult 0 0.00% # Type of FU issued
- FloatDiv 0 0.00% # Type of FU issued
- FloatSqrt 0 0.00% # Type of FU issued
- MemRead 1757 20.95% # Type of FU issued
- MemWrite 1032 12.30% # Type of FU issued
- IprAccess 0 0.00% # Type of FU issued
- InstPrefetch 0 0.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0.end_dist
-system.cpu.iq.ISSUE:fu_busy_cnt 115 # FU busy when requested
-system.cpu.iq.ISSUE:fu_busy_rate 0.013710 # FU busy rate (busy events/executed inst)
-system.cpu.iq.ISSUE:fu_full.start_dist
- (null) 0 0.00% # attempts to use FU when none available
- IntAlu 1 0.87% # attempts to use FU when none available
- IntMult 0 0.00% # attempts to use FU when none available
- IntDiv 0 0.00% # attempts to use FU when none available
- FloatAdd 0 0.00% # attempts to use FU when none available
- FloatCmp 0 0.00% # attempts to use FU when none available
- FloatCvt 0 0.00% # attempts to use FU when none available
- FloatMult 0 0.00% # attempts to use FU when none available
- FloatDiv 0 0.00% # attempts to use FU when none available
- FloatSqrt 0 0.00% # attempts to use FU when none available
- MemRead 76 66.09% # attempts to use FU when none available
- MemWrite 38 33.04% # attempts to use FU when none available
- IprAccess 0 0.00% # attempts to use FU when none available
- InstPrefetch 0 0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full.end_dist
-system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle.samples 6871
-system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
- 0 3753 5462.09%
- 1 894 1301.12%
- 2 723 1052.25%
- 3 614 893.61%
- 4 451 656.38%
- 5 279 406.05%
- 6 104 151.36%
- 7 41 59.67%
- 8 12 17.46%
-system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
-system.cpu.iq.ISSUE:issued_per_cycle.end_dist
-
-system.cpu.iq.ISSUE:rate 1.220783 # Inst issue rate
-system.cpu.iq.iqInstsAdded 9932 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqInstsIssued 8388 # Number of instructions issued
-system.cpu.iq.iqNonSpecInstsAdded 21 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqSquashedInstsExamined 3990 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedInstsIssued 21 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedNonSpecRemoved 4 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.iqSquashedOperandsExamined 2486 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.l2cache.ReadReq_accesses 499 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 2.042254 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency 1015 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate 0.995992 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses 497 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 490 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.981964 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses 490 # number of ReadReq MSHR misses
-system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs 0.004024 # Average number of references to valid blocks.
-system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.demand_accesses 499 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 2.042254 # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 1 # average overall mshr miss latency
-system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 1015 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate 0.995992 # miss rate for demand accesses
-system.cpu.l2cache.demand_misses 497 # number of demand (read+write) misses
-system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency 490 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate 0.981964 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses 490 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.fast_writes 0 # number of fast writes performed
-system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.overall_accesses 499 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 2.042254 # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 1 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits 2 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 1015 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate 0.995992 # miss rate for overall accesses
-system.cpu.l2cache.overall_misses 497 # number of overall misses
-system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 490 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate 0.981964 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses 490 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.l2cache.replacements 0 # number of replacements
-system.cpu.l2cache.sampled_refs 497 # Sample count of references to valid blocks.
-system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 295.773395 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks 0 # number of writebacks
-system.cpu.numCycles 6871 # number of cpu cycles simulated
-system.cpu.rename.RENAME:BlockCycles 4 # Number of cycles rename is blocking
-system.cpu.rename.RENAME:CommittedMaps 4051 # Number of HB maps that are committed
-system.cpu.rename.RENAME:IdleCycles 3758 # Number of cycles rename is idle
-system.cpu.rename.RENAME:LSQFullEvents 62 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RENAME:RenameLookups 14786 # Number of register rename lookups that rename has made
-system.cpu.rename.RENAME:RenamedInsts 11555 # Number of instructions processed by rename
-system.cpu.rename.RENAME:RenamedOperands 8634 # Number of destination operands rename has renamed
-system.cpu.rename.RENAME:RunCycles 1975 # Number of cycles rename is running
-system.cpu.rename.RENAME:SquashCycles 754 # Number of cycles rename is squashing
-system.cpu.rename.RENAME:UnblockCycles 111 # Number of cycles rename is unblocking
-system.cpu.rename.RENAME:UndoneMaps 4583 # Number of HB maps that are undone due to squashing
-system.cpu.rename.RENAME:serializeStallCycles 269 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RENAME:serializingInsts 26 # count of serializing insts renamed
-system.cpu.rename.RENAME:skidInsts 408 # count of insts added to the skid buffer
-system.cpu.rename.RENAME:tempSerializingInsts 21 # count of temporary serializing insts renamed
-system.cpu.workload.PROG:num_syscalls 17 # Number of system calls
+sim_insts 91900700 # Number of instructions simulated
+sim_seconds 0.000092 # Number of seconds simulated
+sim_ticks 91900699 # Number of ticks simulated
+system.cpu.idle_fraction 0 # Percentage of idle cycles
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.numCycles 91900700 # number of cpu cycles simulated
+system.cpu.num_insts 91900700 # Number of instructions executed
+system.cpu.num_refs 26536244 # Number of memory references
+system.cpu.workload.PROG:num_syscalls 387 # Number of system calls
---------- End Simulation Statistics ----------
diff --git a/tests/long/70.twolf/ref/alpha/linux/simple-atomic/smred.out b/tests/long/70.twolf/ref/alpha/linux/simple-atomic/smred.out
new file mode 100644
index 000000000..00387ae5c
--- /dev/null
+++ b/tests/long/70.twolf/ref/alpha/linux/simple-atomic/smred.out
@@ -0,0 +1,276 @@
+
+TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988
+Standard Cell Placement and Global Routing Program
+Authors: Carl Sechen, Bill Swartz
+ Yale University
+
+
+NOTE: Restart file .rs2 not used
+
+TimberWolf will perform a global route step
+rowSep: 1.000000
+feedThruWidth: 4
+
+******************
+BLOCK DATA
+block:1 desire:85
+block:2 desire:85
+Total Desired Length: 170
+total cell length: 168
+total block length: 168
+block x-span:84 block y-span:78
+implicit feed thru range: -84
+Using default value of bin.penalty.control:1.000000
+numBins automatically set to:5
+binWidth = average_cell_width + 0 sigma= 17
+average_cell_width is:16
+standard deviation of cell length is:23.6305
+TimberWolfSC starting from the beginning
+
+
+
+THIS IS THE ROUTE COST OF THE ORIGINAL PLACEMENT: 645
+The number of nets with 1 pin is 4
+The number of nets with 2 pin is 9
+The number of nets with 3 pin is 0
+The number of nets with 4 pin is 2
+The number of nets with 5 pin is 0
+The number of nets with 6 pin is 0
+The number of nets with 7 pin is 0
+The number of nets with 8 pin is 0
+The number of nets with 9 pin is 0
+The number of nets with 10 pin or more is 0
+
+New Cost Function: Initial Horizontal Cost:242
+New Cost Function: FEEDS:0 MISSING_ROWS:-46
+
+bdxlen:86 bdylen:78
+l:0 t:78 r:86 b:0
+
+
+
+THIS IS THE ROUTE COST OF THE CURRENT PLACEMENT: 645
+
+
+
+THIS IS THE PENALTY OF THE CURRENT PLACEMENT: 44
+
+The rand generator seed was at utemp() : 1
+
+
+ tempfile[0][0] = 0.982500 tempfile[0][1] = 90.000000
+ tempfile[1][0] = 0.915000 tempfile[1][1] = 20.000000
+ tempfile[2][0] = 0.700000 tempfile[2][1] = 10.000000
+ tempfile[3][0] = 0.100000 tempfile[3][1] = 0.000000
+
+ I T fds Wire Penalty P_lim Epct binC rowC acc s/p early FDs MRs
+ 1 500 0 929 592 160 30.0 1.0 3.0 84.2 34.7 0.0 0 40
+ 2 491 0 876 106 726 0.0 0.8 2.5 80.0 18.5 0.0 0 46
+ 3 482 0 822 273 372 0.0 0.5 1.5 80.8 21.2 0.0 0 46
+ 4 474 0 826 53 247 0.0 0.5 0.9 65.0 21.9 0.0 0 48
+ 5 465 8 987 73 190 0.0 0.5 0.5 50.0 38.3 0.0 0 46
+ 6 457 8 851 67 226 0.0 0.5 0.5 53.8 42.9 0.0 0 52
+ 7 449 8 1067 108 190 0.0 0.5 0.5 46.2 53.8 0.0 0 50
+ 8 441 8 918 106 171 0.0 0.5 0.5 47.1 40.4 0.0 0 48
+ 9 434 8 812 101 197 0.0 0.5 0.5 53.6 21.0 0.0 0 48
+ 10 426 8 1038 121 181 0.0 0.5 0.5 43.6 27.1 0.0 0 48
+ 11 419 8 898 93 187 0.0 0.5 0.5 45.3 47.8 0.0 0 50
+ 12 411 4 857 94 240 0.0 0.5 0.5 62.7 51.6 0.0 0 44
+ 13 404 8 1043 88 185 0.0 0.5 0.5 54.0 52.8 0.0 0 50
+ 14 397 8 767 94 154 0.0 0.5 0.5 33.8 35.0 0.0 0 50
+ 15 390 8 862 89 183 0.0 0.5 0.5 55.6 29.0 0.0 0 46
+ 16 383 4 798 79 173 0.0 0.5 0.5 57.5 35.3 0.0 0 52
+ 17 376 8 827 100 152 0.0 0.5 0.5 35.3 81.8 0.0 0 50
+ 18 370 8 878 101 208 0.0 0.5 0.5 44.7 46.2 0.0 0 48
+ 19 363 4 921 67 167 0.0 0.5 0.5 57.1 34.7 0.0 0 48
+ 20 357 8 933 93 154 0.0 0.5 0.5 46.5 43.6 0.0 0 52
+ 21 351 8 930 89 147 0.0 0.5 0.5 39.4 36.5 0.0 0 52
+ 22 345 8 951 79 142 0.0 0.5 0.5 32.8 51.3 0.0 0 50
+ 23 339 8 1046 87 207 0.0 0.5 0.5 52.8 61.0 0.0 0 48
+ 24 333 4 989 96 185 0.0 0.5 0.5 45.3 43.3 0.0 0 42
+ 25 327 4 577 86 157 0.0 0.5 0.5 31.1 55.3 0.0 0 52
+ 26 321 8 776 97 174 0.0 0.5 0.5 47.9 62.5 0.0 0 52
+ 27 315 8 850 81 188 0.0 0.5 0.5 45.0 55.2 0.0 0 50
+ 28 310 8 898 97 148 0.0 0.5 0.5 43.0 45.8 0.0 0 48
+ 29 304 8 889 65 173 0.0 0.5 0.5 32.5 41.3 0.0 0 50
+ 30 299 8 858 81 153 0.0 0.5 0.5 44.3 29.2 0.0 0 46
+ 31 294 8 871 82 187 0.0 0.5 0.5 45.7 47.7 0.0 0 48
+ 32 289 8 782 109 173 0.0 0.5 0.5 35.2 57.4 0.0 0 48
+ 33 284 8 743 98 189 0.0 0.6 0.5 41.8 64.3 0.0 0 52
+ 34 279 8 943 90 147 0.0 0.5 0.5 38.6 32.8 0.0 0 48
+ 35 274 8 907 57 166 0.0 0.5 0.5 33.6 51.0 0.0 0 48
+ 36 269 8 900 70 148 0.0 0.5 0.5 45.0 41.4 0.0 0 50
+ 37 264 4 875 106 133 0.0 0.5 0.5 31.7 55.3 0.0 0 52
+ 38 260 8 1023 145 149 0.0 0.6 0.5 28.7 65.0 0.0 0 52
+ 39 255 8 801 151 173 0.0 0.9 0.5 41.7 41.2 0.0 0 48
+ 40 251 8 741 104 159 0.0 0.8 0.5 36.2 47.5 0.0 0 48
+ 41 246 8 828 108 149 0.0 0.5 0.5 34.6 50.9 0.0 0 50
+ 42 242 8 947 128 132 0.0 0.7 0.5 34.2 39.0 0.0 0 50
+ 43 238 8 917 101 142 0.0 0.8 0.5 34.4 50.9 0.0 0 48
+ 44 234 8 761 86 129 0.0 0.5 0.5 42.0 36.4 0.0 0 52
+ 45 229 8 979 106 137 0.0 0.5 0.5 29.2 55.3 0.0 0 50
+ 46 225 8 806 74 130 0.0 0.7 0.5 33.1 65.4 0.0 0 52
+ 47 221 8 971 125 114 0.0 0.5 0.5 31.9 45.6 0.0 0 52
+ 48 218 8 869 125 104 0.0 0.9 0.5 30.0 56.0 0.0 0 48
+ 49 214 8 999 153 140 0.0 0.8 0.5 30.4 46.4 0.0 0 52
+ 50 210 8 798 192 139 0.0 1.0 0.5 28.9 50.0 0.0 0 52
+ 51 206 8 860 125 157 0.0 1.2 0.5 31.5 26.9 0.0 0 52
+ 52 203 8 893 186 127 5.9 0.9 0.5 26.4 42.3 0.0 0 46
+ 53 199 8 863 126 141 0.0 1.2 0.5 32.5 44.4 0.0 0 44
+ 54 196 8 788 97 133 0.0 0.9 0.5 37.5 40.0 0.0 0 50
+ 55 192 8 926 119 116 0.0 0.6 0.5 26.1 55.3 0.0 0 52
+ 56 189 8 789 162 107 0.0 0.8 0.5 25.2 40.4 0.0 0 48
+ 57 186 8 878 107 128 0.0 1.1 0.5 23.1 34.0 0.0 0 52
+ 58 182 8 775 105 122 0.0 0.8 0.5 25.5 57.4 0.0 0 50
+ 59 179 8 747 94 129 0.0 0.7 0.5 34.3 37.3 0.0 0 50
+ 60 176 8 845 96 138 0.0 0.6 0.5 28.3 41.7 0.0 0 52
+ 61 173 8 961 121 110 0.0 0.6 0.5 29.0 52.6 0.0 0 48
+ 62 170 4 911 110 109 0.0 0.9 0.5 33.5 33.3 0.0 0 48
+ 63 167 8 656 109 109 0.0 0.8 0.5 21.9 44.7 0.0 0 52
+ 64 164 8 934 117 105 0.0 0.8 0.5 15.5 50.0 0.0 0 52
+ 65 161 8 972 125 95 0.0 0.8 0.5 24.4 50.0 0.0 0 50
+ 66 158 8 894 125 101 0.0 0.9 0.5 27.2 35.9 0.0 0 52
+ 67 155 8 798 146 129 0.0 1.0 0.5 22.8 58.7 0.0 0 52
+ 68 153 8 901 183 92 0.0 1.1 0.5 23.6 34.5 0.0 0 52
+ 69 150 8 977 197 103 0.0 1.4 0.5 23.6 36.8 0.0 0 52
+ 70 147 8 905 262 93 0.0 1.5 0.5 20.3 63.4 0.0 0 52
+ 71 145 8 995 148 122 0.0 1.9 0.5 20.9 35.3 0.0 0 52
+ 72 142 8 934 230 99 0.0 1.6 0.5 20.0 65.9 0.0 0 52
+ 73 140 8 862 173 100 0.0 1.8 0.5 26.8 46.8 0.0 0 52
+ 74 137 8 924 139 90 0.0 1.7 0.5 16.8 42.5 0.0 0 52
+ 75 135 8 888 168 113 0.0 1.6 0.5 22.9 40.4 0.0 0 52
+ 76 133 8 712 212 84 0.0 1.6 0.5 13.4 46.9 0.0 0 52
+ 77 130 8 868 210 91 0.0 1.7 0.5 17.7 51.2 0.0 0 52
+ 78 128 8 952 307 92 0.0 1.9 0.5 19.7 44.9 0.0 0 50
+ 79 126 8 801 157 107 0.0 2.2 0.5 15.8 39.0 0.0 0 52
+ 80 123 8 849 147 93 0.0 2.1 0.5 15.6 51.4 0.0 0 52
+ 81 121 8 799 154 86 0.0 1.9 0.5 12.2 50.0 0.0 0 52
+ 82 119 8 941 213 82 0.0 1.8 0.5 19.5 41.2 0.0 0 50
+ 83 117 8 751 268 94 0.0 2.0 0.5 20.8 42.6 0.0 0 50
+ 84 115 8 828 198 102 0.0 2.2 0.5 15.5 59.5 0.0 0 52
+ 85 113 8 898 266 123 0.0 2.2 0.5 13.2 85.2 0.0 0 52
+ 86 111 8 943 190 93 0.0 2.4 0.5 19.5 45.1 0.0 0 52
+ 87 109 8 864 183 65 0.0 2.4 0.5 14.9 31.8 0.0 0 52
+ 88 107 8 793 203 93 0.0 2.4 0.5 11.8 35.3 0.0 0 52
+ 89 105 8 752 162 74 1.2 2.4 0.5 13.1 21.4 0.0 0 52
+ 90 103 8 801 149 77 0.0 2.3 0.5 9.7 58.3 0.0 0 52
+ 91 102 8 901 230 99 0.0 2.2 0.5 16.0 25.5 0.0 0 52
+ 92 100 8 826 201 87 0.0 2.4 0.5 12.8 45.7 0.0 0 52
+ 93 98 8 810 196 83 0.0 2.5 0.5 14.0 24.4 0.0 0 52
+ 94 96 8 857 209 68 1.0 2.5 0.5 11.5 27.0 5.1 0 52
+ 95 95 8 771 174 91 0.0 2.6 0.5 10.5 26.5 0.0 0 52
+ 96 93 8 955 210 59 0.0 2.6 0.5 10.0 36.7 0.7 0 52
+ 97 91 8 833 206 53 0.0 2.7 0.5 10.2 19.4 1.4 0 52
+ 98 90 8 888 229 86 0.0 2.8 0.5 8.1 36.0 0.0 0 52
+ 99 88 8 794 186 91 1.0 2.9 0.5 8.3 25.0 0.5 0 52
+100 81 8 756 170 72 1.0 2.9 0.5 6.0 23.8 7.0 0 52
+101 74 8 791 176 67 0.0 2.9 0.5 4.4 58.3 4.0 0 52
+102 67 8 813 213 43 0.0 3.0 0.5 7.0 150.0 4.2 0 52
+103 62 8 779 245 39 0.0 3.1 0.5 3.2 16.7 13.0 0 52
+104 56 8 767 303 63 0.0 3.2 0.5 4.1 20.0 0.7 0 52
+105 52 8 757 270 57 0.0 3.5 0.5 6.4 3.7 0.5 0 52
+106 47 8 763 283 41 0.0 3.7 0.5 4.5 0.0 0.0 0 52
+107 43 8 768 283 36 0.0 3.7 0.5 2.9 18.2 3.6 0 52
+108 39 8 804 283 25 0.0 3.7 0.5 3.1 0.0 6.2 0 52
+109 36 8 781 283 24 0.0 3.7 0.5 3.6 6.7 6.7 0 52
+110 33 8 738 298 42 0.0 3.7 0.5 3.3 15.4 3.5 0 52
+111 30 8 761 298 36 0.0 3.7 0.5 2.2 0.0 4.3 0 52
+112 27 8 769 298 37 0.0 3.7 0.5 0.9 0.0 2.2 0 52
+113 25 8 745 298 31 0.0 3.7 0.5 1.5 0.0 6.6 0 52
+114 23 8 753 298 16 0.0 3.7 0.5 1.3 0.0 2.8 0 52
+115 21 8 745 298 11 0.0 3.7 0.5 1.5 0.0 14.0 0 52
+116 19 8 747 298 21 0.0 3.7 0.5 2.1 0.0 5.8 0 52
+117 13 8 737 298 12 0.0 3.7 0.5 1.0 0.0 10.0 0 52
+118 9 8 736 298 4 0.0 3.7 0.5 1.5 0.0 18.5 0 52
+119 0 8 739 298 0 0.0 3.7 0.5 1.8 0.0 18.0 0 52
+120 0 8 732 298 0 0.0 3.7 0.5 1.2 0.0 21.8 0 52
+121 0 8 732 19 -1 0.0 0.0 0.5 0.0 100.0 54.8
+
+Initial Wiring Cost: 645 Final Wiring Cost: 732
+############## Percent Wire Cost Reduction: -13
+
+
+Initial Wire Length: 645 Final Wire Length: 732
+************** Percent Wire Length Reduction: -13
+
+
+Initial Horiz. Wire: 216 Final Horiz. Wire: 147
+$$$$$$$$$$$ Percent H-Wire Length Reduction: 32
+
+
+Initial Vert. Wire: 429 Final Vert. Wire: 585
+@@@@@@@@@@@ Percent V-Wire Length Reduction: -36
+
+Before Feeds are Added:
+BLOCK TOTAL CELL LENGTHS OVER/UNDER TARGET
+ 1 82 -20
+ 2 86 -16
+
+LONGEST Block is:2 Its length is:86
+BLOCK TOTAL CELL LENGTHS OVER/UNDER TARGET
+ 1 86 -16
+ 2 86 -16
+
+LONGEST Block is:1 Its length is:86
+Added: 1 feed-through cells
+
+Removed the cell overlaps --- Will do neighbor interchanges only now
+
+TOTAL INTERCONNECT LENGTH: 994
+OVERLAP PENALTY: 0
+
+initialRowControl: 1.650
+finalRowControl: 0.300
+iter T Wire accept
+ 122 0.001 976 16%
+ 123 0.001 971 0%
+ 124 0.001 971 0%
+Total Feed-Alignment Movement (Pass 1): 0
+Total Feed-Alignment Movement (Pass 2): 0
+Total Feed-Alignment Movement (Pass 3): 0
+Total Feed-Alignment Movement (Pass 4): 0
+Total Feed-Alignment Movement (Pass 5): 0
+Total Feed-Alignment Movement (Pass 6): 0
+Total Feed-Alignment Movement (Pass 7): 0
+Total Feed-Alignment Movement (Pass 8): 0
+
+The rand generator seed was at globroute() : 987654321
+
+
+Total Number of Net Segments: 9
+Number of Switchable Net Segments: 0
+
+Number of channels: 3
+
+
+
+THIS IS THE ORIGINAL NUMBER OF TRACKS: 5
+
+
+no. of accepted flips: 0
+no. of attempted flips: 0
+THIS IS THE NUMBER OF TRACKS: 5
+
+
+
+FINAL NUMBER OF ROUTING TRACKS: 5
+
+MAX OF CHANNEL: 1 is: 0
+MAX OF CHANNEL: 2 is: 4
+MAX OF CHANNEL: 3 is: 1
+FINAL TOTAL INTERCONNECT LENGTH: 978
+FINAL OVERLAP PENALTY: 0 FINAL VALUE OF TOTAL COST IS: 978
+MAX NUMBER OF ATTEMPTED FLIPS PER T: 55
+
+
+cost_scale_factor:3.90616
+
+Number of Feed Thrus: 0
+Number of Implicit Feed Thrus: 0
+
+Statistics:
+Number of Standard Cells: 10
+Number of Pads: 0
+Number of Nets: 15
+Number of Pins: 46
+Usage statistics not available
diff --git a/tests/long/70.twolf/ref/alpha/linux/simple-atomic/smred.pin b/tests/long/70.twolf/ref/alpha/linux/simple-atomic/smred.pin
new file mode 100644
index 000000000..62b922e4e
--- /dev/null
+++ b/tests/long/70.twolf/ref/alpha/linux/simple-atomic/smred.pin
@@ -0,0 +1,17 @@
+$COUNT_1/$AND2_1/$ND2_1$Z 1 $COUNT_1/$AND2_1/$ND2_1 00#Z 17 52 2 1 0
+$COUNT_1/$AND2_1/$ND2_1$Z 1 ACOUNT_1 00#A 15 26 2 -1 0
+B7 2 $COUNT_1/$FJK3_2 00#K 25 78 3 -1 0
+B7 2 $COUNT_1/$FJK3_2 00#J 23 78 3 -1 0
+B7 3 $COUNT_1/$AND2_2/$ND2_1 00#A 9 26 2 -1 0
+B7 3 ACOUNT_1 01#Z 17 26 2 -1 0
+B6 5 $COUNT_1/$FJK3_1 00#K 25 26 2 -1 0
+B6 5 $COUNT_1/$FJK3_1 00#J 23 26 2 -1 0
+B6 5 $COUNT_1/$AND2_3/$IV_1 01#Z 7 26 2 -1 0
+$COUNT_1/$FJK3_1$Q 6 $COUNT_1/$FJK3_1 01#Q 81 26 2 -1 0
+$COUNT_1/$FJK3_1$Q 6 $COUNT_1/$AND2_1/$ND2_1 00#B 19 52 2 1 0
+$COUNT_1/$FJK3_2$Q 7 $COUNT_1/$FJK3_2 00#Q 81 52 2 1 0
+$COUNT_1/$FJK3_2$Q 7 $COUNT_1/$AND2_2/$ND2_1 01#B 11 26 2 -1 0
+$COUNT_1/$AND2_3/$ND2_1$Z 8 $COUNT_1/$AND2_3/$ND2_1 00#Z 5 52 2 1 0
+$COUNT_1/$AND2_3/$ND2_1$Z 8 $COUNT_1/$AND2_3/$IV_1 00#A 5 26 2 -1 0
+$COUNT_1/$AND2_4/$ND2_1$Z 9 $COUNT_1/$AND2_4/$ND2_1 00#Z 7 52 2 1 0
+$COUNT_1/$AND2_4/$ND2_1$Z 9 $COUNT_1/$AND2_4/$IV_1 00#A 3 26 2 -1 0
diff --git a/tests/long/70.twolf/ref/alpha/linux/simple-atomic/smred.pl1 b/tests/long/70.twolf/ref/alpha/linux/simple-atomic/smred.pl1
new file mode 100644
index 000000000..bdc569e39
--- /dev/null
+++ b/tests/long/70.twolf/ref/alpha/linux/simple-atomic/smred.pl1
@@ -0,0 +1,11 @@
+$COUNT_1/$AND2_4/$IV_1 0 0 4 26 0 1
+$COUNT_1/$AND2_3/$IV_1 4 0 8 26 2 1
+$COUNT_1/$AND2_2/$ND2_1 8 0 14 26 0 1
+ACOUNT_1 14 0 18 26 2 1
+twfeed1 18 0 22 26 0 1
+$COUNT_1/$FJK3_1 22 0 86 26 0 1
+$COUNT_1/$AND2_3/$ND2_1 0 52 6 78 0 2
+$COUNT_1/$AND2_4/$ND2_1 6 52 12 78 2 2
+$COUNT_1/$AND2_2/$IV_1 12 52 16 78 2 2
+$COUNT_1/$AND2_1/$ND2_1 16 52 22 78 2 2
+$COUNT_1/$FJK3_2 22 52 86 78 0 2
diff --git a/tests/long/70.twolf/ref/alpha/linux/simple-atomic/smred.pl2 b/tests/long/70.twolf/ref/alpha/linux/simple-atomic/smred.pl2
new file mode 100644
index 000000000..6e2601e82
--- /dev/null
+++ b/tests/long/70.twolf/ref/alpha/linux/simple-atomic/smred.pl2
@@ -0,0 +1,2 @@
+1 0 0 86 26 0 0
+2 0 52 86 78 0 0
diff --git a/tests/long/70.twolf/ref/alpha/linux/simple-atomic/smred.sav b/tests/long/70.twolf/ref/alpha/linux/simple-atomic/smred.sav
new file mode 100644
index 000000000..04c8e9935
--- /dev/null
+++ b/tests/long/70.twolf/ref/alpha/linux/simple-atomic/smred.sav
@@ -0,0 +1,18 @@
+0.009592
+121
+0
+1
+0.000000
+0.500000
+3.906156
+1
+1 1 2 37 13
+2 2 0 34 65
+3 2 2 63 65
+4 1 0 59 13
+5 1 2 32 13
+6 2 0 23 65
+7 1 2 12 13
+8 2 0 6 65
+9 1 0 70 13
+10 2 0 70 65
diff --git a/tests/long/70.twolf/ref/alpha/linux/simple-atomic/smred.sv2 b/tests/long/70.twolf/ref/alpha/linux/simple-atomic/smred.sv2
new file mode 100644
index 000000000..9dd68ecdb
--- /dev/null
+++ b/tests/long/70.twolf/ref/alpha/linux/simple-atomic/smred.sv2
@@ -0,0 +1,19 @@
+0.001000
+123
+0
+2
+0.000000
+0.500000
+3.906156
+1
+1 1 2 16 13
+2 2 2 19 65
+3 2 2 14 65
+4 1 0 11 13
+5 1 2 6 13
+6 2 0 3 65
+7 1 0 2 13
+8 2 2 9 65
+9 1 0 50 13
+10 2 0 54 65
+11 1 0 84 13
diff --git a/tests/long/70.twolf/ref/alpha/linux/simple-atomic/smred.twf b/tests/long/70.twolf/ref/alpha/linux/simple-atomic/smred.twf
new file mode 100644
index 000000000..a4c2eac35
--- /dev/null
+++ b/tests/long/70.twolf/ref/alpha/linux/simple-atomic/smred.twf
@@ -0,0 +1,29 @@
+net 1
+segment channel 2
+ pin1 1 pin2 7 0 0
+net 2
+segment channel 3
+pin1 41 pin2 42 0 0
+segment channel 2
+pin1 12 pin2 3 0 0
+net 3
+segment channel 2
+pin1 35 pin2 36 0 0
+segment channel 2
+pin1 19 pin2 35 0 0
+net 4
+segment channel 2
+ pin1 5 pin2 38 0 0
+net 5
+net 7
+segment channel 2
+ pin1 14 pin2 43 0 0
+net 8
+segment channel 2
+ pin1 23 pin2 17 0 0
+net 9
+net 11
+segment channel 2
+ pin1 25 pin2 31 0 0
+net 14
+net 15
diff --git a/tests/long/70.twolf/ref/alpha/linux/simple-atomic/stderr b/tests/long/70.twolf/ref/alpha/linux/simple-atomic/stderr
index 8893caac8..87866a2a5 100644
--- a/tests/long/70.twolf/ref/alpha/linux/simple-atomic/stderr
+++ b/tests/long/70.twolf/ref/alpha/linux/simple-atomic/stderr
@@ -1,3 +1 @@
warn: Entering event queue @ 0. Starting simulation...
-warn: cycle 0: fault (page_table_fault) detected @ PC 0x000000
-warn: Increasing stack 0x11ff92000:0x11ff9b000 to 0x11ff90000:0x11ff9b000 because of access to 0x11ff91ff0
diff --git a/tests/long/70.twolf/ref/alpha/linux/simple-atomic/stdout b/tests/long/70.twolf/ref/alpha/linux/simple-atomic/stdout
index fbb329a2f..f32f0a972 100644
--- a/tests/long/70.twolf/ref/alpha/linux/simple-atomic/stdout
+++ b/tests/long/70.twolf/ref/alpha/linux/simple-atomic/stdout
@@ -1,13 +1,14 @@
-Hello world!
-M5 Simulator System
-Copyright (c) 2001-2006
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Sep 5 2006 15:28:48
-M5 started Tue Sep 5 15:42:12 2006
-M5 executing on zizzer.eecs.umich.edu
-command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/o3-timing tests/run.py quick/00.hello/alpha/linux/o3-timing
-Exiting @ tick 6870 because target called exit()
+TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988
+Standard Cell Placement and Global Routing Program
+Authors: Carl Sechen, Bill Swartz
+ Yale University
+ 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
+ 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
+ 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
+ 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
+ 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75
+ 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
+ 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
+106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
+122 123 124 \ No newline at end of file
diff --git a/tests/long/70.twolf/ref/alpha/linux/simple-timing/config.ini b/tests/long/70.twolf/ref/alpha/linux/simple-timing/config.ini
index c3a59fbce..9f6151e4d 100644
--- a/tests/long/70.twolf/ref/alpha/linux/simple-timing/config.ini
+++ b/tests/long/70.twolf/ref/alpha/linux/simple-timing/config.ini
@@ -7,11 +7,9 @@ max_tick=0
output_file=cout
progress_interval=0
-[debug]
-break_cycles=
-
[exetrace]
intel_format=false
+legion_lockstep=false
pc_symbol=true
print_cpseq=false
print_cycle=true
@@ -53,73 +51,20 @@ mem_mode=atomic
physmem=system.physmem
[system.cpu]
-type=DerivO3CPU
-children=dcache fuPool icache l2cache toL2Bus workload
-BTBEntries=4096
-BTBTagSize=16
-LFSTSize=1024
-LQEntries=32
-RASSize=16
-SQEntries=32
-SSITSize=1024
-activity=0
-backComSize=5
-choiceCtrBits=2
-choicePredictorSize=8192
+type=TimingSimpleCPU
+children=dcache icache l2cache toL2Bus workload
clock=1
-commitToDecodeDelay=1
-commitToFetchDelay=1
-commitToIEWDelay=1
-commitToRenameDelay=1
-commitWidth=8
-decodeToFetchDelay=1
-decodeToRenameDelay=1
-decodeWidth=8
+cpu_id=0
defer_registration=false
-dispatchWidth=8
-fetchToDecodeDelay=1
-fetchTrapLatency=1
-fetchWidth=8
-forwardComSize=5
-fuPool=system.cpu.fuPool
function_trace=false
function_trace_start=0
-globalCtrBits=2
-globalHistoryBits=13
-globalPredictorSize=8192
-iewToCommitDelay=1
-iewToDecodeDelay=1
-iewToFetchDelay=1
-iewToRenameDelay=1
-instShiftAmt=2
-issueToExecuteDelay=1
-issueWidth=8
-localCtrBits=2
-localHistoryBits=11
-localHistoryTableSize=2048
-localPredictorSize=2048
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
-mem=system.cpu.dcache
-numIQEntries=64
-numPhysFloatRegs=256
-numPhysIntRegs=256
-numROBEntries=192
-numRobs=1
-numThreads=1
-predType=tournament
-renameToDecodeDelay=1
-renameToFetchDelay=1
-renameToIEWDelay=2
-renameToROBDelay=1
-renameWidth=8
-squashWidth=8
+phase=0
+progress_interval=0
system=system
-trapLatency=13
-wbDepth=1
-wbWidth=8
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
@@ -131,7 +76,6 @@ assoc=2
block_size=64
compressed_bus=false
compression_latency=0
-do_copy=false
hash_delay=1
hit_latency=1
latency=1
@@ -164,143 +108,6 @@ write_buffers=8
cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.port[1]
-[system.cpu.fuPool]
-type=FUPool
-children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7
-FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7
-
-[system.cpu.fuPool.FUList0]
-type=FUDesc
-children=opList0
-count=6
-opList=system.cpu.fuPool.FUList0.opList0
-
-[system.cpu.fuPool.FUList0.opList0]
-type=OpDesc
-issueLat=1
-opClass=IntAlu
-opLat=1
-
-[system.cpu.fuPool.FUList1]
-type=FUDesc
-children=opList0 opList1
-count=2
-opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
-
-[system.cpu.fuPool.FUList1.opList0]
-type=OpDesc
-issueLat=1
-opClass=IntMult
-opLat=3
-
-[system.cpu.fuPool.FUList1.opList1]
-type=OpDesc
-issueLat=19
-opClass=IntDiv
-opLat=20
-
-[system.cpu.fuPool.FUList2]
-type=FUDesc
-children=opList0 opList1 opList2
-count=4
-opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
-
-[system.cpu.fuPool.FUList2.opList0]
-type=OpDesc
-issueLat=1
-opClass=FloatAdd
-opLat=2
-
-[system.cpu.fuPool.FUList2.opList1]
-type=OpDesc
-issueLat=1
-opClass=FloatCmp
-opLat=2
-
-[system.cpu.fuPool.FUList2.opList2]
-type=OpDesc
-issueLat=1
-opClass=FloatCvt
-opLat=2
-
-[system.cpu.fuPool.FUList3]
-type=FUDesc
-children=opList0 opList1 opList2
-count=2
-opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
-
-[system.cpu.fuPool.FUList3.opList0]
-type=OpDesc
-issueLat=1
-opClass=FloatMult
-opLat=4
-
-[system.cpu.fuPool.FUList3.opList1]
-type=OpDesc
-issueLat=12
-opClass=FloatDiv
-opLat=12
-
-[system.cpu.fuPool.FUList3.opList2]
-type=OpDesc
-issueLat=24
-opClass=FloatSqrt
-opLat=24
-
-[system.cpu.fuPool.FUList4]
-type=FUDesc
-children=opList0
-count=0
-opList=system.cpu.fuPool.FUList4.opList0
-
-[system.cpu.fuPool.FUList4.opList0]
-type=OpDesc
-issueLat=1
-opClass=MemRead
-opLat=1
-
-[system.cpu.fuPool.FUList5]
-type=FUDesc
-children=opList0
-count=0
-opList=system.cpu.fuPool.FUList5.opList0
-
-[system.cpu.fuPool.FUList5.opList0]
-type=OpDesc
-issueLat=1
-opClass=MemWrite
-opLat=1
-
-[system.cpu.fuPool.FUList6]
-type=FUDesc
-children=opList0 opList1
-count=4
-opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1
-
-[system.cpu.fuPool.FUList6.opList0]
-type=OpDesc
-issueLat=1
-opClass=MemRead
-opLat=1
-
-[system.cpu.fuPool.FUList6.opList1]
-type=OpDesc
-issueLat=1
-opClass=MemWrite
-opLat=1
-
-[system.cpu.fuPool.FUList7]
-type=FUDesc
-children=opList0
-count=1
-opList=system.cpu.fuPool.FUList7.opList0
-
-[system.cpu.fuPool.FUList7.opList0]
-type=OpDesc
-issueLat=3
-opClass=IprAccess
-opLat=3
-
[system.cpu.icache]
type=BaseCache
adaptive_compression=false
@@ -308,7 +115,6 @@ assoc=2
block_size=64
compressed_bus=false
compression_latency=0
-do_copy=false
hash_delay=1
hit_latency=1
latency=1
@@ -348,7 +154,6 @@ assoc=2
block_size=64
compressed_bus=false
compression_latency=0
-do_copy=false
hash_delay=1
hit_latency=1
latency=1
@@ -384,20 +189,33 @@ mem_side=system.membus.port[1]
[system.cpu.toL2Bus]
type=Bus
bus_id=0
+clock=1000
+responder_set=false
+width=64
port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
[system.cpu.workload]
type=LiveProcess
-cmd=hello
+cmd=twolf smred
+cwd=build/ALPHA_SE/tests/opt/long/70.twolf/alpha/linux/simple-timing
+egid=100
env=
-executable=tests/test-progs/hello/bin/alpha/linux/hello
+euid=100
+executable=/dist/m5/cpu2000/binaries/alpha/tru64/twolf
+gid=100
input=cin
output=cout
+pid=100
+ppid=99
system=system
+uid=100
[system.membus]
type=Bus
bus_id=0
+clock=1000
+responder_set=false
+width=64
port=system.physmem.port system.cpu.l2cache.mem_side
[system.physmem]
@@ -409,6 +227,7 @@ port=system.membus.port[0]
[trace]
bufsize=0
+cycle=0
dump_on_exit=false
file=cout
flags=
diff --git a/tests/long/70.twolf/ref/alpha/linux/simple-timing/config.out b/tests/long/70.twolf/ref/alpha/linux/simple-timing/config.out
index f491a3081..c27975bcb 100644
--- a/tests/long/70.twolf/ref/alpha/linux/simple-timing/config.out
+++ b/tests/long/70.twolf/ref/alpha/linux/simple-timing/config.out
@@ -19,19 +19,54 @@ mem_mode=atomic
[system.membus]
type=Bus
bus_id=0
+clock=1000
+width=64
+responder_set=false
[system.cpu.workload]
type=LiveProcess
-cmd=hello
-executable=tests/test-progs/hello/bin/alpha/linux/hello
+cmd=twolf smred
+executable=/dist/m5/cpu2000/binaries/alpha/tru64/twolf
input=cin
output=cout
env=
+cwd=build/ALPHA_SE/tests/opt/long/70.twolf/alpha/linux/simple-timing
system=system
+uid=100
+euid=100
+gid=100
+egid=100
+pid=100
+ppid=99
-[system.cpu.dcache]
+[system.cpu]
+type=TimingSimpleCPU
+max_insts_any_thread=0
+max_insts_all_threads=0
+max_loads_any_thread=0
+max_loads_all_threads=0
+progress_interval=0
+system=system
+cpu_id=0
+workload=system.cpu.workload
+clock=1
+phase=0
+defer_registration=false
+// width not specified
+function_trace=false
+function_trace_start=0
+// simulate_stalls not specified
+
+[system.cpu.toL2Bus]
+type=Bus
+bus_id=0
+clock=1000
+width=64
+responder_set=false
+
+[system.cpu.icache]
type=BaseCache
-size=262144
+size=131072
assoc=2
block_size=64
latency=1
@@ -39,7 +74,6 @@ mshrs=10
tgts_per_mshr=5
write_buffers=8
prioritizeRequests=false
-do_copy=false
protocol=null
trace_addr=0
hash_delay=1
@@ -68,214 +102,9 @@ prefetch_use_cpu_id=true
prefetch_data_accesses_only=false
hit_latency=1
-[system.cpu.fuPool.FUList0.opList0]
-type=OpDesc
-opClass=IntAlu
-opLat=1
-issueLat=1
-
-[system.cpu.fuPool.FUList0]
-type=FUDesc
-opList=system.cpu.fuPool.FUList0.opList0
-count=6
-
-[system.cpu.fuPool.FUList1.opList0]
-type=OpDesc
-opClass=IntMult
-opLat=3
-issueLat=1
-
-[system.cpu.fuPool.FUList1.opList1]
-type=OpDesc
-opClass=IntDiv
-opLat=20
-issueLat=19
-
-[system.cpu.fuPool.FUList1]
-type=FUDesc
-opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
-count=2
-
-[system.cpu.fuPool.FUList2.opList0]
-type=OpDesc
-opClass=FloatAdd
-opLat=2
-issueLat=1
-
-[system.cpu.fuPool.FUList2.opList1]
-type=OpDesc
-opClass=FloatCmp
-opLat=2
-issueLat=1
-
-[system.cpu.fuPool.FUList2.opList2]
-type=OpDesc
-opClass=FloatCvt
-opLat=2
-issueLat=1
-
-[system.cpu.fuPool.FUList2]
-type=FUDesc
-opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
-count=4
-
-[system.cpu.fuPool.FUList3.opList0]
-type=OpDesc
-opClass=FloatMult
-opLat=4
-issueLat=1
-
-[system.cpu.fuPool.FUList3.opList1]
-type=OpDesc
-opClass=FloatDiv
-opLat=12
-issueLat=12
-
-[system.cpu.fuPool.FUList3.opList2]
-type=OpDesc
-opClass=FloatSqrt
-opLat=24
-issueLat=24
-
-[system.cpu.fuPool.FUList3]
-type=FUDesc
-opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
-count=2
-
-[system.cpu.fuPool.FUList4.opList0]
-type=OpDesc
-opClass=MemRead
-opLat=1
-issueLat=1
-
-[system.cpu.fuPool.FUList4]
-type=FUDesc
-opList=system.cpu.fuPool.FUList4.opList0
-count=0
-
-[system.cpu.fuPool.FUList5.opList0]
-type=OpDesc
-opClass=MemWrite
-opLat=1
-issueLat=1
-
-[system.cpu.fuPool.FUList5]
-type=FUDesc
-opList=system.cpu.fuPool.FUList5.opList0
-count=0
-
-[system.cpu.fuPool.FUList6.opList0]
-type=OpDesc
-opClass=MemRead
-opLat=1
-issueLat=1
-
-[system.cpu.fuPool.FUList6.opList1]
-type=OpDesc
-opClass=MemWrite
-opLat=1
-issueLat=1
-
-[system.cpu.fuPool.FUList6]
-type=FUDesc
-opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1
-count=4
-
-[system.cpu.fuPool.FUList7.opList0]
-type=OpDesc
-opClass=IprAccess
-opLat=3
-issueLat=3
-
-[system.cpu.fuPool.FUList7]
-type=FUDesc
-opList=system.cpu.fuPool.FUList7.opList0
-count=1
-
-[system.cpu.fuPool]
-type=FUPool
-FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7
-
-[system.cpu]
-type=DerivO3CPU
-clock=1
-numThreads=1
-activity=0
-workload=system.cpu.workload
-mem=system.cpu.dcache
-checker=null
-max_insts_any_thread=0
-max_insts_all_threads=0
-max_loads_any_thread=0
-max_loads_all_threads=0
-cachePorts=200
-decodeToFetchDelay=1
-renameToFetchDelay=1
-iewToFetchDelay=1
-commitToFetchDelay=1
-fetchWidth=8
-renameToDecodeDelay=1
-iewToDecodeDelay=1
-commitToDecodeDelay=1
-fetchToDecodeDelay=1
-decodeWidth=8
-iewToRenameDelay=1
-commitToRenameDelay=1
-decodeToRenameDelay=1
-renameWidth=8
-commitToIEWDelay=1
-renameToIEWDelay=2
-issueToExecuteDelay=1
-dispatchWidth=8
-issueWidth=8
-wbWidth=8
-wbDepth=1
-fuPool=system.cpu.fuPool
-iewToCommitDelay=1
-renameToROBDelay=1
-commitWidth=8
-squashWidth=8
-trapLatency=13
-backComSize=5
-forwardComSize=5
-predType=tournament
-localPredictorSize=2048
-localCtrBits=2
-localHistoryTableSize=2048
-localHistoryBits=11
-globalPredictorSize=8192
-globalCtrBits=2
-globalHistoryBits=13
-choicePredictorSize=8192
-choiceCtrBits=2
-BTBEntries=4096
-BTBTagSize=16
-RASSize=16
-LQEntries=32
-SQEntries=32
-LFSTSize=1024
-SSITSize=1024
-numPhysIntRegs=256
-numPhysFloatRegs=256
-numIQEntries=64
-numROBEntries=192
-smtNumFetchingThreads=1
-smtFetchPolicy=SingleThread
-smtLSQPolicy=Partitioned
-smtLSQThreshold=100
-smtIQPolicy=Partitioned
-smtIQThreshold=100
-smtROBPolicy=Partitioned
-smtROBThreshold=100
-smtCommitPolicy=RoundRobin
-instShiftAmt=2
-defer_registration=false
-function_trace=false
-function_trace_start=0
-
-[system.cpu.icache]
+[system.cpu.dcache]
type=BaseCache
-size=131072
+size=262144
assoc=2
block_size=64
latency=1
@@ -283,7 +112,6 @@ mshrs=10
tgts_per_mshr=5
write_buffers=8
prioritizeRequests=false
-do_copy=false
protocol=null
trace_addr=0
hash_delay=1
@@ -322,7 +150,6 @@ mshrs=10
tgts_per_mshr=5
write_buffers=8
prioritizeRequests=false
-do_copy=false
protocol=null
trace_addr=0
hash_delay=1
@@ -351,13 +178,10 @@ prefetch_use_cpu_id=true
prefetch_data_accesses_only=false
hit_latency=1
-[system.cpu.toL2Bus]
-type=Bus
-bus_id=0
-
[trace]
flags=
start=0
+cycle=0
bufsize=0
file=cout
dump_on_exit=false
@@ -396,8 +220,9 @@ print_cpseq=false
print_reg_delta=false
pc_symbol=true
intel_format=false
+legion_lockstep=false
trace_system=client
-[debug]
-break_cycles=
+[statsreset]
+reset_cycle=0
diff --git a/tests/long/70.twolf/ref/alpha/linux/simple-timing/m5stats.txt b/tests/long/70.twolf/ref/alpha/linux/simple-timing/m5stats.txt
index 5d4f9235a..3926b2de9 100644
--- a/tests/long/70.twolf/ref/alpha/linux/simple-timing/m5stats.txt
+++ b/tests/long/70.twolf/ref/alpha/linux/simple-timing/m5stats.txt
@@ -1,112 +1,67 @@
---------- Begin Simulation Statistics ----------
-global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-global.BPredUnit.BTBHits 542 # Number of BTB hits
-global.BPredUnit.BTBLookups 1938 # Number of BTB lookups
-global.BPredUnit.RASInCorrect 48 # Number of incorrect RAS predictions.
-global.BPredUnit.condIncorrect 420 # Number of conditional branches incorrect
-global.BPredUnit.condPredicted 1304 # Number of conditional branches predicted
-global.BPredUnit.lookups 2256 # Number of BP lookups
-global.BPredUnit.usedRAS 291 # Number of times the RAS was used to get a target.
-host_inst_rate 41797 # Simulator instruction rate (inst/s)
-host_mem_usage 160344 # Number of bytes of host memory used
-host_seconds 0.13 # Real time elapsed on the host
-host_tick_rate 50948 # Simulator tick rate (ticks/s)
-memdepunit.memDep.conflictingLoads 12 # Number of conflicting loads.
-memdepunit.memDep.conflictingStores 259 # Number of conflicting stores.
-memdepunit.memDep.insertedLoads 2050 # Number of loads inserted to the mem dependence unit.
-memdepunit.memDep.insertedStores 1221 # Number of stores inserted to the mem dependence unit.
+host_inst_rate 460435 # Simulator instruction rate (inst/s)
+host_mem_usage 178124 # Number of bytes of host memory used
+host_seconds 199.60 # Real time elapsed on the host
+host_tick_rate 765898 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 5623 # Number of instructions simulated
-sim_seconds 0.000000 # Number of seconds simulated
-sim_ticks 6870 # Number of ticks simulated
-system.cpu.commit.COM:branches 862 # Number of branches committed
-system.cpu.commit.COM:bw_lim_events 74 # number cycles where commit BW limit reached
-system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle.samples 6116
-system.cpu.commit.COM:committed_per_cycle.min_value 0
- 0 3908 6389.80%
- 1 1064 1739.70%
- 2 389 636.04%
- 3 210 343.36%
- 4 153 250.16%
- 5 93 152.06%
- 6 76 124.26%
- 7 149 243.62%
- 8 74 120.99%
-system.cpu.commit.COM:committed_per_cycle.max_value 8
-system.cpu.commit.COM:committed_per_cycle.end_dist
-
-system.cpu.commit.COM:count 5640 # Number of instructions committed
-system.cpu.commit.COM:loads 979 # Number of loads committed
-system.cpu.commit.COM:membars 0 # Number of memory barriers committed
-system.cpu.commit.COM:refs 1791 # Number of memory references committed
-system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.branchMispredicts 337 # The number of times a branch was mispredicted
-system.cpu.commit.commitCommittedInsts 5640 # The number of committed instructions
-system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.commitSquashedInsts 4350 # The number of squashed insts skipped by commit
-system.cpu.committedInsts 5623 # Number of Instructions Simulated
-system.cpu.committedInsts_total 5623 # Number of Instructions Simulated
-system.cpu.cpi 1.221768 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 1.221768 # CPI: Total CPI of All Threads
-system.cpu.dcache.ReadReq_accesses 1538 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 3.072000 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2.240000 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits 1413 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 384 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate 0.081274 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses 125 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_hits 25 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_miss_latency 224 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate 0.065020 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses 100 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_accesses 821 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 2.467742 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2.140845 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 635 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 459 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.226553 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 186 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_hits 108 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_miss_latency 152 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.086480 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 71 # number of WriteReq MSHR misses
+sim_insts 91900700 # Number of instructions simulated
+sim_seconds 0.000153 # Number of seconds simulated
+sim_ticks 152870012 # Number of ticks simulated
+system.cpu.dcache.ReadReq_accesses 19995627 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 3765.212314 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2765.212314 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits 19995156 # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency 1773415 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate 0.000024 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses 471 # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_miss_latency 1302415 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate 0.000024 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_misses 471 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_accesses 6500813 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_avg_miss_latency 3867.178372 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2867.178372 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits 6499204 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 6222290 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate 0.000248 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses 1609 # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_miss_latency 4613290 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.000248 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses 1609 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles_no_targets 0.800000 # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 11.505618 # Average number of references to valid blocks.
+system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu.dcache.avg_refs 12737.673077 # Average number of references to valid blocks.
system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_no_targets 5 # number of cycles access was blocked
+system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles_no_targets 4 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.demand_accesses 2359 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 2.710611 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 2.198830 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 2048 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 843 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.131836 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 311 # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits 133 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 376 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate 0.072488 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 171 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_accesses 26496440 # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency 3844.088942 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 2844.088942 # average overall mshr miss latency
+system.cpu.dcache.demand_hits 26494360 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 7995705 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate 0.000079 # miss rate for demand accesses
+system.cpu.dcache.demand_misses 2080 # number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency 5915705 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate 0.000079 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses 2080 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.overall_accesses 2359 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 2.710611 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 2.198830 # average overall mshr miss latency
+system.cpu.dcache.overall_accesses 26496440 # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency 3844.088942 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 2844.088942 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 2048 # number of overall hits
-system.cpu.dcache.overall_miss_latency 843 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.131836 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 311 # number of overall misses
-system.cpu.dcache.overall_mshr_hits 133 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 376 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate 0.072488 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 171 # number of overall MSHR misses
+system.cpu.dcache.overall_hits 26494360 # number of overall hits
+system.cpu.dcache.overall_miss_latency 7995705 # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate 0.000079 # miss rate for overall accesses
+system.cpu.dcache.overall_misses 2080 # number of overall misses
+system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_miss_latency 5915705 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate 0.000079 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses 2080 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@@ -118,92 +73,57 @@ system.cpu.dcache.prefetcher.num_hwpf_issued 0
system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.dcache.replacements 0 # number of replacements
-system.cpu.dcache.sampled_refs 178 # Sample count of references to valid blocks.
+system.cpu.dcache.replacements 103 # number of replacements
+system.cpu.dcache.sampled_refs 2080 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 119.831029 # Cycle average of tags in use
-system.cpu.dcache.total_refs 2048 # Total number of references to valid blocks.
+system.cpu.dcache.tagsinuse 1399.324024 # Cycle average of tags in use
+system.cpu.dcache.total_refs 26494360 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks 0 # number of writebacks
-system.cpu.decode.DECODE:BlockedCycles 387 # Number of cycles decode is blocked
-system.cpu.decode.DECODE:BranchMispred 93 # Number of times decode detected a branch misprediction
-system.cpu.decode.DECODE:BranchResolved 185 # Number of times decode resolved a branch
-system.cpu.decode.DECODE:DecodedInsts 12349 # Number of instructions handled by decode
-system.cpu.decode.DECODE:IdleCycles 3542 # Number of cycles decode is idle
-system.cpu.decode.DECODE:RunCycles 2158 # Number of cycles decode is running
-system.cpu.decode.DECODE:SquashCycles 754 # Number of cycles decode is squashing
-system.cpu.decode.DECODE:SquashedInsts 286 # Number of squashed instructions handled by decode
-system.cpu.decode.DECODE:UnblockCycles 30 # Number of cycles decode is unblocking
-system.cpu.fetch.Branches 2256 # Number of branches that fetch encountered
-system.cpu.fetch.CacheLines 1582 # Number of cache lines fetched
-system.cpu.fetch.Cycles 3905 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.IcacheSquashes 148 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.Insts 13707 # Number of instructions fetch has processed
-system.cpu.fetch.SquashCycles 456 # Number of cycles fetch has spent squashing
-system.cpu.fetch.branchRate 0.328336 # Number of branch fetches per cycle
-system.cpu.fetch.icacheStallCycles 1582 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.predictedBranches 833 # Number of branches that fetch has predicted taken
-system.cpu.fetch.rate 1.994906 # Number of inst fetches per cycle
-system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist.samples 6871
-system.cpu.fetch.rateDist.min_value 0
- 0 4549 6620.58%
- 1 174 253.24%
- 2 186 270.70%
- 3 157 228.50%
- 4 211 307.09%
- 5 153 222.68%
- 6 171 248.87%
- 7 105 152.82%
- 8 1165 1695.53%
-system.cpu.fetch.rateDist.max_value 8
-system.cpu.fetch.rateDist.end_dist
-
-system.cpu.icache.ReadReq_accesses 1582 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 2.960245 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 1.996885 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits 1255 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 968 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate 0.206700 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses 327 # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_hits 6 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_miss_latency 641 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.202908 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses 321 # number of ReadReq MSHR misses
-system.cpu.icache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles_no_targets no value # average number of cycles each access was blocked
-system.cpu.icache.avg_refs 3.909657 # Average number of references to valid blocks.
+system.cpu.dcache.writebacks 74 # number of writebacks
+system.cpu.icache.ReadReq_accesses 91900701 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency 3116.205529 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 2116.205529 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits 91892201 # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency 26487747 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_rate 0.000092 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_misses 8500 # number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_miss_latency 17987747 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate 0.000092 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_misses 8500 # number of ReadReq MSHR misses
+system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu.icache.avg_refs 10810.847176 # Average number of references to valid blocks.
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.demand_accesses 1582 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 2.960245 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 1.996885 # average overall mshr miss latency
-system.cpu.icache.demand_hits 1255 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 968 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate 0.206700 # miss rate for demand accesses
-system.cpu.icache.demand_misses 327 # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_hits 6 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 641 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate 0.202908 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses 321 # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_accesses 91900701 # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency 3116.205529 # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 2116.205529 # average overall mshr miss latency
+system.cpu.icache.demand_hits 91892201 # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency 26487747 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_rate 0.000092 # miss rate for demand accesses
+system.cpu.icache.demand_misses 8500 # number of demand (read+write) misses
+system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_miss_latency 17987747 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_rate 0.000092 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_misses 8500 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.overall_accesses 1582 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 2.960245 # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 1.996885 # average overall mshr miss latency
+system.cpu.icache.overall_accesses 91900701 # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency 3116.205529 # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 2116.205529 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits 1255 # number of overall hits
-system.cpu.icache.overall_miss_latency 968 # number of overall miss cycles
-system.cpu.icache.overall_miss_rate 0.206700 # miss rate for overall accesses
-system.cpu.icache.overall_misses 327 # number of overall misses
-system.cpu.icache.overall_mshr_hits 6 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 641 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate 0.202908 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses 321 # number of overall MSHR misses
+system.cpu.icache.overall_hits 91892201 # number of overall hits
+system.cpu.icache.overall_miss_latency 26487747 # number of overall miss cycles
+system.cpu.icache.overall_miss_rate 0.000092 # miss rate for overall accesses
+system.cpu.icache.overall_misses 8500 # number of overall misses
+system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_miss_latency 17987747 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_rate 0.000092 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_misses 8500 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@@ -215,1726 +135,60 @@ system.cpu.icache.prefetcher.num_hwpf_issued 0
system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.icache.replacements 0 # number of replacements
-system.cpu.icache.sampled_refs 321 # Sample count of references to valid blocks.
+system.cpu.icache.replacements 6677 # number of replacements
+system.cpu.icache.sampled_refs 8500 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 176.393247 # Cycle average of tags in use
-system.cpu.icache.total_refs 1255 # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse 1370.015418 # Cycle average of tags in use
+system.cpu.icache.total_refs 91892201 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.iew.EXEC:branches 1206 # Number of branches executed
-system.cpu.iew.EXEC:insts 7969 # Number of executed instructions
-system.cpu.iew.EXEC:loads 1610 # Number of load instructions executed
-system.cpu.iew.EXEC:nop 37 # number of nop insts executed
-system.cpu.iew.EXEC:rate 1.159802 # Inst execution rate
-system.cpu.iew.EXEC:refs 2599 # number of memory reference insts executed
-system.cpu.iew.EXEC:squashedInsts 419 # Number of squashed instructions skipped in execute
-system.cpu.iew.EXEC:stores 989 # Number of stores executed
-system.cpu.iew.EXEC:swp 0 # number of swp insts executed
-system.cpu.iew.WB:consumers 5438 # num instructions consuming a value
-system.cpu.iew.WB:count 7722 # cumulative count of insts written-back
-system.cpu.iew.WB:fanout 0.744575 # average fanout of values written-back
-system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.iew.WB:producers 4049 # num instructions producing a value
-system.cpu.iew.WB:rate 1.123854 # insts written-back per cycle
-system.cpu.iew.WB:sent 7762 # cumulative count of insts sent to commit
-system.cpu.iew.branchMispredicts 393 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewBlockCycles 4 # Number of cycles IEW is blocking
-system.cpu.iew.iewDispLoadInsts 2050 # Number of dispatched load instructions
-system.cpu.iew.iewDispNonSpecInsts 21 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewDispSquashedInsts 272 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispStoreInsts 1221 # Number of dispatched store instructions
-system.cpu.iew.iewDispatchedInsts 9990 # Number of instructions dispatched to IQ
-system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.iewSquashCycles 754 # Number of cycles IEW is squashing
-system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking
-system.cpu.iew.lsq.thread.0.blockedLoads 1 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread.0.cacheBlocked 5 # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.lsq.thread.0.forwLoads 55 # Number of loads that had data forwarded from stores
-system.cpu.iew.lsq.thread.0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
-system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread.0.squashedLoads 1071 # Number of loads squashed
-system.cpu.iew.lsq.thread.0.squashedStores 409 # Number of stores squashed
-system.cpu.iew.memOrderViolationEvents 41 # Number of memory order violations
-system.cpu.iew.predictedNotTakenIncorrect 296 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.predictedTakenIncorrect 97 # Number of branches that were predicted taken incorrectly
-system.cpu.ipc 0.818486 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.818486 # IPC: Total IPC of All Threads
-system.cpu.iq.IQ:residence:(null).start_dist # cycles from dispatch to issue
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- 70 0
- 72 0
- 74 0
- 76 0
- 78 0
- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.ISSUE:FloatDiv_delay.max_value 0
-system.cpu.iq.ISSUE:FloatDiv_delay.end_dist
-
-system.cpu.iq.ISSUE:FloatSqrt_delay.start_dist # cycles from operands ready to issue
-system.cpu.iq.ISSUE:FloatSqrt_delay.samples 0
-system.cpu.iq.ISSUE:FloatSqrt_delay.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
- 20 0
- 22 0
- 24 0
- 26 0
- 28 0
- 30 0
- 32 0
- 34 0
- 36 0
- 38 0
- 40 0
- 42 0
- 44 0
- 46 0
- 48 0
- 50 0
- 52 0
- 54 0
- 56 0
- 58 0
- 60 0
- 62 0
- 64 0
- 66 0
- 68 0
- 70 0
- 72 0
- 74 0
- 76 0
- 78 0
- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.ISSUE:FloatSqrt_delay.max_value 0
-system.cpu.iq.ISSUE:FloatSqrt_delay.end_dist
-
-system.cpu.iq.ISSUE:MemRead_delay.start_dist # cycles from operands ready to issue
-system.cpu.iq.ISSUE:MemRead_delay.samples 0
-system.cpu.iq.ISSUE:MemRead_delay.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
- 20 0
- 22 0
- 24 0
- 26 0
- 28 0
- 30 0
- 32 0
- 34 0
- 36 0
- 38 0
- 40 0
- 42 0
- 44 0
- 46 0
- 48 0
- 50 0
- 52 0
- 54 0
- 56 0
- 58 0
- 60 0
- 62 0
- 64 0
- 66 0
- 68 0
- 70 0
- 72 0
- 74 0
- 76 0
- 78 0
- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.ISSUE:MemRead_delay.max_value 0
-system.cpu.iq.ISSUE:MemRead_delay.end_dist
-
-system.cpu.iq.ISSUE:MemWrite_delay.start_dist # cycles from operands ready to issue
-system.cpu.iq.ISSUE:MemWrite_delay.samples 0
-system.cpu.iq.ISSUE:MemWrite_delay.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
- 20 0
- 22 0
- 24 0
- 26 0
- 28 0
- 30 0
- 32 0
- 34 0
- 36 0
- 38 0
- 40 0
- 42 0
- 44 0
- 46 0
- 48 0
- 50 0
- 52 0
- 54 0
- 56 0
- 58 0
- 60 0
- 62 0
- 64 0
- 66 0
- 68 0
- 70 0
- 72 0
- 74 0
- 76 0
- 78 0
- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.ISSUE:MemWrite_delay.max_value 0
-system.cpu.iq.ISSUE:MemWrite_delay.end_dist
-
-system.cpu.iq.ISSUE:IprAccess_delay.start_dist # cycles from operands ready to issue
-system.cpu.iq.ISSUE:IprAccess_delay.samples 0
-system.cpu.iq.ISSUE:IprAccess_delay.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
- 20 0
- 22 0
- 24 0
- 26 0
- 28 0
- 30 0
- 32 0
- 34 0
- 36 0
- 38 0
- 40 0
- 42 0
- 44 0
- 46 0
- 48 0
- 50 0
- 52 0
- 54 0
- 56 0
- 58 0
- 60 0
- 62 0
- 64 0
- 66 0
- 68 0
- 70 0
- 72 0
- 74 0
- 76 0
- 78 0
- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.ISSUE:IprAccess_delay.max_value 0
-system.cpu.iq.ISSUE:IprAccess_delay.end_dist
-
-system.cpu.iq.ISSUE:InstPrefetch_delay.start_dist # cycles from operands ready to issue
-system.cpu.iq.ISSUE:InstPrefetch_delay.samples 0
-system.cpu.iq.ISSUE:InstPrefetch_delay.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
- 20 0
- 22 0
- 24 0
- 26 0
- 28 0
- 30 0
- 32 0
- 34 0
- 36 0
- 38 0
- 40 0
- 42 0
- 44 0
- 46 0
- 48 0
- 50 0
- 52 0
- 54 0
- 56 0
- 58 0
- 60 0
- 62 0
- 64 0
- 66 0
- 68 0
- 70 0
- 72 0
- 74 0
- 76 0
- 78 0
- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.ISSUE:InstPrefetch_delay.max_value 0
-system.cpu.iq.ISSUE:InstPrefetch_delay.end_dist
-
-system.cpu.iq.ISSUE:FU_type_0 8388 # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0.start_dist
- (null) 2 0.02% # Type of FU issued
- IntAlu 5594 66.69% # Type of FU issued
- IntMult 1 0.01% # Type of FU issued
- IntDiv 0 0.00% # Type of FU issued
- FloatAdd 2 0.02% # Type of FU issued
- FloatCmp 0 0.00% # Type of FU issued
- FloatCvt 0 0.00% # Type of FU issued
- FloatMult 0 0.00% # Type of FU issued
- FloatDiv 0 0.00% # Type of FU issued
- FloatSqrt 0 0.00% # Type of FU issued
- MemRead 1757 20.95% # Type of FU issued
- MemWrite 1032 12.30% # Type of FU issued
- IprAccess 0 0.00% # Type of FU issued
- InstPrefetch 0 0.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0.end_dist
-system.cpu.iq.ISSUE:fu_busy_cnt 115 # FU busy when requested
-system.cpu.iq.ISSUE:fu_busy_rate 0.013710 # FU busy rate (busy events/executed inst)
-system.cpu.iq.ISSUE:fu_full.start_dist
- (null) 0 0.00% # attempts to use FU when none available
- IntAlu 1 0.87% # attempts to use FU when none available
- IntMult 0 0.00% # attempts to use FU when none available
- IntDiv 0 0.00% # attempts to use FU when none available
- FloatAdd 0 0.00% # attempts to use FU when none available
- FloatCmp 0 0.00% # attempts to use FU when none available
- FloatCvt 0 0.00% # attempts to use FU when none available
- FloatMult 0 0.00% # attempts to use FU when none available
- FloatDiv 0 0.00% # attempts to use FU when none available
- FloatSqrt 0 0.00% # attempts to use FU when none available
- MemRead 76 66.09% # attempts to use FU when none available
- MemWrite 38 33.04% # attempts to use FU when none available
- IprAccess 0 0.00% # attempts to use FU when none available
- InstPrefetch 0 0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full.end_dist
-system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle.samples 6871
-system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
- 0 3753 5462.09%
- 1 894 1301.12%
- 2 723 1052.25%
- 3 614 893.61%
- 4 451 656.38%
- 5 279 406.05%
- 6 104 151.36%
- 7 41 59.67%
- 8 12 17.46%
-system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
-system.cpu.iq.ISSUE:issued_per_cycle.end_dist
-
-system.cpu.iq.ISSUE:rate 1.220783 # Inst issue rate
-system.cpu.iq.iqInstsAdded 9932 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqInstsIssued 8388 # Number of instructions issued
-system.cpu.iq.iqNonSpecInstsAdded 21 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqSquashedInstsExamined 3990 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedInstsIssued 21 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedNonSpecRemoved 4 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.iqSquashedOperandsExamined 2486 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.l2cache.ReadReq_accesses 499 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 2.042254 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency 1015 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate 0.995992 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses 497 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 490 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.981964 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses 490 # number of ReadReq MSHR misses
+system.cpu.idle_fraction 0 # Percentage of idle cycles
+system.cpu.l2cache.ReadReq_accesses 10580 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_avg_miss_latency 2883.751500 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1878.799057 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_hits 5912 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_miss_latency 13461352 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate 0.441210 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses 4668 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency 8770234 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.441210 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses 4668 # number of ReadReq MSHR misses
+system.cpu.l2cache.WriteReqNoAck|Writeback_accesses 74 # number of WriteReqNoAck|Writeback accesses(hits+misses)
+system.cpu.l2cache.WriteReqNoAck|Writeback_hits 74 # number of WriteReqNoAck|Writeback hits
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs 0.004024 # Average number of references to valid blocks.
+system.cpu.l2cache.avg_refs 1.282348 # Average number of references to valid blocks.
system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.demand_accesses 499 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 2.042254 # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 1 # average overall mshr miss latency
-system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 1015 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate 0.995992 # miss rate for demand accesses
-system.cpu.l2cache.demand_misses 497 # number of demand (read+write) misses
+system.cpu.l2cache.demand_accesses 10580 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_avg_miss_latency 2883.751500 # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 1878.799057 # average overall mshr miss latency
+system.cpu.l2cache.demand_hits 5912 # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency 13461352 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate 0.441210 # miss rate for demand accesses
+system.cpu.l2cache.demand_misses 4668 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency 490 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate 0.981964 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses 490 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_miss_latency 8770234 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate 0.441210 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses 4668 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.overall_accesses 499 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 2.042254 # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 1 # average overall mshr miss latency
+system.cpu.l2cache.overall_accesses 10654 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_avg_miss_latency 2883.751500 # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 1878.799057 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits 2 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 1015 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate 0.995992 # miss rate for overall accesses
-system.cpu.l2cache.overall_misses 497 # number of overall misses
+system.cpu.l2cache.overall_hits 5986 # number of overall hits
+system.cpu.l2cache.overall_miss_latency 13461352 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate 0.438145 # miss rate for overall accesses
+system.cpu.l2cache.overall_misses 4668 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 490 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate 0.981964 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses 490 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_miss_latency 8770234 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate 0.438145 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses 4668 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@@ -1947,28 +201,16 @@ system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.l2cache.replacements 0 # number of replacements
-system.cpu.l2cache.sampled_refs 497 # Sample count of references to valid blocks.
+system.cpu.l2cache.sampled_refs 4668 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 295.773395 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks.
+system.cpu.l2cache.tagsinuse 3056.777484 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 5986 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks
-system.cpu.numCycles 6871 # number of cpu cycles simulated
-system.cpu.rename.RENAME:BlockCycles 4 # Number of cycles rename is blocking
-system.cpu.rename.RENAME:CommittedMaps 4051 # Number of HB maps that are committed
-system.cpu.rename.RENAME:IdleCycles 3758 # Number of cycles rename is idle
-system.cpu.rename.RENAME:LSQFullEvents 62 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RENAME:RenameLookups 14786 # Number of register rename lookups that rename has made
-system.cpu.rename.RENAME:RenamedInsts 11555 # Number of instructions processed by rename
-system.cpu.rename.RENAME:RenamedOperands 8634 # Number of destination operands rename has renamed
-system.cpu.rename.RENAME:RunCycles 1975 # Number of cycles rename is running
-system.cpu.rename.RENAME:SquashCycles 754 # Number of cycles rename is squashing
-system.cpu.rename.RENAME:UnblockCycles 111 # Number of cycles rename is unblocking
-system.cpu.rename.RENAME:UndoneMaps 4583 # Number of HB maps that are undone due to squashing
-system.cpu.rename.RENAME:serializeStallCycles 269 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RENAME:serializingInsts 26 # count of serializing insts renamed
-system.cpu.rename.RENAME:skidInsts 408 # count of insts added to the skid buffer
-system.cpu.rename.RENAME:tempSerializingInsts 21 # count of temporary serializing insts renamed
-system.cpu.workload.PROG:num_syscalls 17 # Number of system calls
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.numCycles 152870012 # number of cpu cycles simulated
+system.cpu.num_insts 91900700 # Number of instructions executed
+system.cpu.num_refs 26536244 # Number of memory references
+system.cpu.workload.PROG:num_syscalls 387 # Number of system calls
---------- End Simulation Statistics ----------
diff --git a/tests/long/70.twolf/ref/alpha/linux/simple-timing/smred.out b/tests/long/70.twolf/ref/alpha/linux/simple-timing/smred.out
new file mode 100644
index 000000000..00387ae5c
--- /dev/null
+++ b/tests/long/70.twolf/ref/alpha/linux/simple-timing/smred.out
@@ -0,0 +1,276 @@
+
+TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988
+Standard Cell Placement and Global Routing Program
+Authors: Carl Sechen, Bill Swartz
+ Yale University
+
+
+NOTE: Restart file .rs2 not used
+
+TimberWolf will perform a global route step
+rowSep: 1.000000
+feedThruWidth: 4
+
+******************
+BLOCK DATA
+block:1 desire:85
+block:2 desire:85
+Total Desired Length: 170
+total cell length: 168
+total block length: 168
+block x-span:84 block y-span:78
+implicit feed thru range: -84
+Using default value of bin.penalty.control:1.000000
+numBins automatically set to:5
+binWidth = average_cell_width + 0 sigma= 17
+average_cell_width is:16
+standard deviation of cell length is:23.6305
+TimberWolfSC starting from the beginning
+
+
+
+THIS IS THE ROUTE COST OF THE ORIGINAL PLACEMENT: 645
+The number of nets with 1 pin is 4
+The number of nets with 2 pin is 9
+The number of nets with 3 pin is 0
+The number of nets with 4 pin is 2
+The number of nets with 5 pin is 0
+The number of nets with 6 pin is 0
+The number of nets with 7 pin is 0
+The number of nets with 8 pin is 0
+The number of nets with 9 pin is 0
+The number of nets with 10 pin or more is 0
+
+New Cost Function: Initial Horizontal Cost:242
+New Cost Function: FEEDS:0 MISSING_ROWS:-46
+
+bdxlen:86 bdylen:78
+l:0 t:78 r:86 b:0
+
+
+
+THIS IS THE ROUTE COST OF THE CURRENT PLACEMENT: 645
+
+
+
+THIS IS THE PENALTY OF THE CURRENT PLACEMENT: 44
+
+The rand generator seed was at utemp() : 1
+
+
+ tempfile[0][0] = 0.982500 tempfile[0][1] = 90.000000
+ tempfile[1][0] = 0.915000 tempfile[1][1] = 20.000000
+ tempfile[2][0] = 0.700000 tempfile[2][1] = 10.000000
+ tempfile[3][0] = 0.100000 tempfile[3][1] = 0.000000
+
+ I T fds Wire Penalty P_lim Epct binC rowC acc s/p early FDs MRs
+ 1 500 0 929 592 160 30.0 1.0 3.0 84.2 34.7 0.0 0 40
+ 2 491 0 876 106 726 0.0 0.8 2.5 80.0 18.5 0.0 0 46
+ 3 482 0 822 273 372 0.0 0.5 1.5 80.8 21.2 0.0 0 46
+ 4 474 0 826 53 247 0.0 0.5 0.9 65.0 21.9 0.0 0 48
+ 5 465 8 987 73 190 0.0 0.5 0.5 50.0 38.3 0.0 0 46
+ 6 457 8 851 67 226 0.0 0.5 0.5 53.8 42.9 0.0 0 52
+ 7 449 8 1067 108 190 0.0 0.5 0.5 46.2 53.8 0.0 0 50
+ 8 441 8 918 106 171 0.0 0.5 0.5 47.1 40.4 0.0 0 48
+ 9 434 8 812 101 197 0.0 0.5 0.5 53.6 21.0 0.0 0 48
+ 10 426 8 1038 121 181 0.0 0.5 0.5 43.6 27.1 0.0 0 48
+ 11 419 8 898 93 187 0.0 0.5 0.5 45.3 47.8 0.0 0 50
+ 12 411 4 857 94 240 0.0 0.5 0.5 62.7 51.6 0.0 0 44
+ 13 404 8 1043 88 185 0.0 0.5 0.5 54.0 52.8 0.0 0 50
+ 14 397 8 767 94 154 0.0 0.5 0.5 33.8 35.0 0.0 0 50
+ 15 390 8 862 89 183 0.0 0.5 0.5 55.6 29.0 0.0 0 46
+ 16 383 4 798 79 173 0.0 0.5 0.5 57.5 35.3 0.0 0 52
+ 17 376 8 827 100 152 0.0 0.5 0.5 35.3 81.8 0.0 0 50
+ 18 370 8 878 101 208 0.0 0.5 0.5 44.7 46.2 0.0 0 48
+ 19 363 4 921 67 167 0.0 0.5 0.5 57.1 34.7 0.0 0 48
+ 20 357 8 933 93 154 0.0 0.5 0.5 46.5 43.6 0.0 0 52
+ 21 351 8 930 89 147 0.0 0.5 0.5 39.4 36.5 0.0 0 52
+ 22 345 8 951 79 142 0.0 0.5 0.5 32.8 51.3 0.0 0 50
+ 23 339 8 1046 87 207 0.0 0.5 0.5 52.8 61.0 0.0 0 48
+ 24 333 4 989 96 185 0.0 0.5 0.5 45.3 43.3 0.0 0 42
+ 25 327 4 577 86 157 0.0 0.5 0.5 31.1 55.3 0.0 0 52
+ 26 321 8 776 97 174 0.0 0.5 0.5 47.9 62.5 0.0 0 52
+ 27 315 8 850 81 188 0.0 0.5 0.5 45.0 55.2 0.0 0 50
+ 28 310 8 898 97 148 0.0 0.5 0.5 43.0 45.8 0.0 0 48
+ 29 304 8 889 65 173 0.0 0.5 0.5 32.5 41.3 0.0 0 50
+ 30 299 8 858 81 153 0.0 0.5 0.5 44.3 29.2 0.0 0 46
+ 31 294 8 871 82 187 0.0 0.5 0.5 45.7 47.7 0.0 0 48
+ 32 289 8 782 109 173 0.0 0.5 0.5 35.2 57.4 0.0 0 48
+ 33 284 8 743 98 189 0.0 0.6 0.5 41.8 64.3 0.0 0 52
+ 34 279 8 943 90 147 0.0 0.5 0.5 38.6 32.8 0.0 0 48
+ 35 274 8 907 57 166 0.0 0.5 0.5 33.6 51.0 0.0 0 48
+ 36 269 8 900 70 148 0.0 0.5 0.5 45.0 41.4 0.0 0 50
+ 37 264 4 875 106 133 0.0 0.5 0.5 31.7 55.3 0.0 0 52
+ 38 260 8 1023 145 149 0.0 0.6 0.5 28.7 65.0 0.0 0 52
+ 39 255 8 801 151 173 0.0 0.9 0.5 41.7 41.2 0.0 0 48
+ 40 251 8 741 104 159 0.0 0.8 0.5 36.2 47.5 0.0 0 48
+ 41 246 8 828 108 149 0.0 0.5 0.5 34.6 50.9 0.0 0 50
+ 42 242 8 947 128 132 0.0 0.7 0.5 34.2 39.0 0.0 0 50
+ 43 238 8 917 101 142 0.0 0.8 0.5 34.4 50.9 0.0 0 48
+ 44 234 8 761 86 129 0.0 0.5 0.5 42.0 36.4 0.0 0 52
+ 45 229 8 979 106 137 0.0 0.5 0.5 29.2 55.3 0.0 0 50
+ 46 225 8 806 74 130 0.0 0.7 0.5 33.1 65.4 0.0 0 52
+ 47 221 8 971 125 114 0.0 0.5 0.5 31.9 45.6 0.0 0 52
+ 48 218 8 869 125 104 0.0 0.9 0.5 30.0 56.0 0.0 0 48
+ 49 214 8 999 153 140 0.0 0.8 0.5 30.4 46.4 0.0 0 52
+ 50 210 8 798 192 139 0.0 1.0 0.5 28.9 50.0 0.0 0 52
+ 51 206 8 860 125 157 0.0 1.2 0.5 31.5 26.9 0.0 0 52
+ 52 203 8 893 186 127 5.9 0.9 0.5 26.4 42.3 0.0 0 46
+ 53 199 8 863 126 141 0.0 1.2 0.5 32.5 44.4 0.0 0 44
+ 54 196 8 788 97 133 0.0 0.9 0.5 37.5 40.0 0.0 0 50
+ 55 192 8 926 119 116 0.0 0.6 0.5 26.1 55.3 0.0 0 52
+ 56 189 8 789 162 107 0.0 0.8 0.5 25.2 40.4 0.0 0 48
+ 57 186 8 878 107 128 0.0 1.1 0.5 23.1 34.0 0.0 0 52
+ 58 182 8 775 105 122 0.0 0.8 0.5 25.5 57.4 0.0 0 50
+ 59 179 8 747 94 129 0.0 0.7 0.5 34.3 37.3 0.0 0 50
+ 60 176 8 845 96 138 0.0 0.6 0.5 28.3 41.7 0.0 0 52
+ 61 173 8 961 121 110 0.0 0.6 0.5 29.0 52.6 0.0 0 48
+ 62 170 4 911 110 109 0.0 0.9 0.5 33.5 33.3 0.0 0 48
+ 63 167 8 656 109 109 0.0 0.8 0.5 21.9 44.7 0.0 0 52
+ 64 164 8 934 117 105 0.0 0.8 0.5 15.5 50.0 0.0 0 52
+ 65 161 8 972 125 95 0.0 0.8 0.5 24.4 50.0 0.0 0 50
+ 66 158 8 894 125 101 0.0 0.9 0.5 27.2 35.9 0.0 0 52
+ 67 155 8 798 146 129 0.0 1.0 0.5 22.8 58.7 0.0 0 52
+ 68 153 8 901 183 92 0.0 1.1 0.5 23.6 34.5 0.0 0 52
+ 69 150 8 977 197 103 0.0 1.4 0.5 23.6 36.8 0.0 0 52
+ 70 147 8 905 262 93 0.0 1.5 0.5 20.3 63.4 0.0 0 52
+ 71 145 8 995 148 122 0.0 1.9 0.5 20.9 35.3 0.0 0 52
+ 72 142 8 934 230 99 0.0 1.6 0.5 20.0 65.9 0.0 0 52
+ 73 140 8 862 173 100 0.0 1.8 0.5 26.8 46.8 0.0 0 52
+ 74 137 8 924 139 90 0.0 1.7 0.5 16.8 42.5 0.0 0 52
+ 75 135 8 888 168 113 0.0 1.6 0.5 22.9 40.4 0.0 0 52
+ 76 133 8 712 212 84 0.0 1.6 0.5 13.4 46.9 0.0 0 52
+ 77 130 8 868 210 91 0.0 1.7 0.5 17.7 51.2 0.0 0 52
+ 78 128 8 952 307 92 0.0 1.9 0.5 19.7 44.9 0.0 0 50
+ 79 126 8 801 157 107 0.0 2.2 0.5 15.8 39.0 0.0 0 52
+ 80 123 8 849 147 93 0.0 2.1 0.5 15.6 51.4 0.0 0 52
+ 81 121 8 799 154 86 0.0 1.9 0.5 12.2 50.0 0.0 0 52
+ 82 119 8 941 213 82 0.0 1.8 0.5 19.5 41.2 0.0 0 50
+ 83 117 8 751 268 94 0.0 2.0 0.5 20.8 42.6 0.0 0 50
+ 84 115 8 828 198 102 0.0 2.2 0.5 15.5 59.5 0.0 0 52
+ 85 113 8 898 266 123 0.0 2.2 0.5 13.2 85.2 0.0 0 52
+ 86 111 8 943 190 93 0.0 2.4 0.5 19.5 45.1 0.0 0 52
+ 87 109 8 864 183 65 0.0 2.4 0.5 14.9 31.8 0.0 0 52
+ 88 107 8 793 203 93 0.0 2.4 0.5 11.8 35.3 0.0 0 52
+ 89 105 8 752 162 74 1.2 2.4 0.5 13.1 21.4 0.0 0 52
+ 90 103 8 801 149 77 0.0 2.3 0.5 9.7 58.3 0.0 0 52
+ 91 102 8 901 230 99 0.0 2.2 0.5 16.0 25.5 0.0 0 52
+ 92 100 8 826 201 87 0.0 2.4 0.5 12.8 45.7 0.0 0 52
+ 93 98 8 810 196 83 0.0 2.5 0.5 14.0 24.4 0.0 0 52
+ 94 96 8 857 209 68 1.0 2.5 0.5 11.5 27.0 5.1 0 52
+ 95 95 8 771 174 91 0.0 2.6 0.5 10.5 26.5 0.0 0 52
+ 96 93 8 955 210 59 0.0 2.6 0.5 10.0 36.7 0.7 0 52
+ 97 91 8 833 206 53 0.0 2.7 0.5 10.2 19.4 1.4 0 52
+ 98 90 8 888 229 86 0.0 2.8 0.5 8.1 36.0 0.0 0 52
+ 99 88 8 794 186 91 1.0 2.9 0.5 8.3 25.0 0.5 0 52
+100 81 8 756 170 72 1.0 2.9 0.5 6.0 23.8 7.0 0 52
+101 74 8 791 176 67 0.0 2.9 0.5 4.4 58.3 4.0 0 52
+102 67 8 813 213 43 0.0 3.0 0.5 7.0 150.0 4.2 0 52
+103 62 8 779 245 39 0.0 3.1 0.5 3.2 16.7 13.0 0 52
+104 56 8 767 303 63 0.0 3.2 0.5 4.1 20.0 0.7 0 52
+105 52 8 757 270 57 0.0 3.5 0.5 6.4 3.7 0.5 0 52
+106 47 8 763 283 41 0.0 3.7 0.5 4.5 0.0 0.0 0 52
+107 43 8 768 283 36 0.0 3.7 0.5 2.9 18.2 3.6 0 52
+108 39 8 804 283 25 0.0 3.7 0.5 3.1 0.0 6.2 0 52
+109 36 8 781 283 24 0.0 3.7 0.5 3.6 6.7 6.7 0 52
+110 33 8 738 298 42 0.0 3.7 0.5 3.3 15.4 3.5 0 52
+111 30 8 761 298 36 0.0 3.7 0.5 2.2 0.0 4.3 0 52
+112 27 8 769 298 37 0.0 3.7 0.5 0.9 0.0 2.2 0 52
+113 25 8 745 298 31 0.0 3.7 0.5 1.5 0.0 6.6 0 52
+114 23 8 753 298 16 0.0 3.7 0.5 1.3 0.0 2.8 0 52
+115 21 8 745 298 11 0.0 3.7 0.5 1.5 0.0 14.0 0 52
+116 19 8 747 298 21 0.0 3.7 0.5 2.1 0.0 5.8 0 52
+117 13 8 737 298 12 0.0 3.7 0.5 1.0 0.0 10.0 0 52
+118 9 8 736 298 4 0.0 3.7 0.5 1.5 0.0 18.5 0 52
+119 0 8 739 298 0 0.0 3.7 0.5 1.8 0.0 18.0 0 52
+120 0 8 732 298 0 0.0 3.7 0.5 1.2 0.0 21.8 0 52
+121 0 8 732 19 -1 0.0 0.0 0.5 0.0 100.0 54.8
+
+Initial Wiring Cost: 645 Final Wiring Cost: 732
+############## Percent Wire Cost Reduction: -13
+
+
+Initial Wire Length: 645 Final Wire Length: 732
+************** Percent Wire Length Reduction: -13
+
+
+Initial Horiz. Wire: 216 Final Horiz. Wire: 147
+$$$$$$$$$$$ Percent H-Wire Length Reduction: 32
+
+
+Initial Vert. Wire: 429 Final Vert. Wire: 585
+@@@@@@@@@@@ Percent V-Wire Length Reduction: -36
+
+Before Feeds are Added:
+BLOCK TOTAL CELL LENGTHS OVER/UNDER TARGET
+ 1 82 -20
+ 2 86 -16
+
+LONGEST Block is:2 Its length is:86
+BLOCK TOTAL CELL LENGTHS OVER/UNDER TARGET
+ 1 86 -16
+ 2 86 -16
+
+LONGEST Block is:1 Its length is:86
+Added: 1 feed-through cells
+
+Removed the cell overlaps --- Will do neighbor interchanges only now
+
+TOTAL INTERCONNECT LENGTH: 994
+OVERLAP PENALTY: 0
+
+initialRowControl: 1.650
+finalRowControl: 0.300
+iter T Wire accept
+ 122 0.001 976 16%
+ 123 0.001 971 0%
+ 124 0.001 971 0%
+Total Feed-Alignment Movement (Pass 1): 0
+Total Feed-Alignment Movement (Pass 2): 0
+Total Feed-Alignment Movement (Pass 3): 0
+Total Feed-Alignment Movement (Pass 4): 0
+Total Feed-Alignment Movement (Pass 5): 0
+Total Feed-Alignment Movement (Pass 6): 0
+Total Feed-Alignment Movement (Pass 7): 0
+Total Feed-Alignment Movement (Pass 8): 0
+
+The rand generator seed was at globroute() : 987654321
+
+
+Total Number of Net Segments: 9
+Number of Switchable Net Segments: 0
+
+Number of channels: 3
+
+
+
+THIS IS THE ORIGINAL NUMBER OF TRACKS: 5
+
+
+no. of accepted flips: 0
+no. of attempted flips: 0
+THIS IS THE NUMBER OF TRACKS: 5
+
+
+
+FINAL NUMBER OF ROUTING TRACKS: 5
+
+MAX OF CHANNEL: 1 is: 0
+MAX OF CHANNEL: 2 is: 4
+MAX OF CHANNEL: 3 is: 1
+FINAL TOTAL INTERCONNECT LENGTH: 978
+FINAL OVERLAP PENALTY: 0 FINAL VALUE OF TOTAL COST IS: 978
+MAX NUMBER OF ATTEMPTED FLIPS PER T: 55
+
+
+cost_scale_factor:3.90616
+
+Number of Feed Thrus: 0
+Number of Implicit Feed Thrus: 0
+
+Statistics:
+Number of Standard Cells: 10
+Number of Pads: 0
+Number of Nets: 15
+Number of Pins: 46
+Usage statistics not available
diff --git a/tests/long/70.twolf/ref/alpha/linux/simple-timing/smred.pin b/tests/long/70.twolf/ref/alpha/linux/simple-timing/smred.pin
new file mode 100644
index 000000000..62b922e4e
--- /dev/null
+++ b/tests/long/70.twolf/ref/alpha/linux/simple-timing/smred.pin
@@ -0,0 +1,17 @@
+$COUNT_1/$AND2_1/$ND2_1$Z 1 $COUNT_1/$AND2_1/$ND2_1 00#Z 17 52 2 1 0
+$COUNT_1/$AND2_1/$ND2_1$Z 1 ACOUNT_1 00#A 15 26 2 -1 0
+B7 2 $COUNT_1/$FJK3_2 00#K 25 78 3 -1 0
+B7 2 $COUNT_1/$FJK3_2 00#J 23 78 3 -1 0
+B7 3 $COUNT_1/$AND2_2/$ND2_1 00#A 9 26 2 -1 0
+B7 3 ACOUNT_1 01#Z 17 26 2 -1 0
+B6 5 $COUNT_1/$FJK3_1 00#K 25 26 2 -1 0
+B6 5 $COUNT_1/$FJK3_1 00#J 23 26 2 -1 0
+B6 5 $COUNT_1/$AND2_3/$IV_1 01#Z 7 26 2 -1 0
+$COUNT_1/$FJK3_1$Q 6 $COUNT_1/$FJK3_1 01#Q 81 26 2 -1 0
+$COUNT_1/$FJK3_1$Q 6 $COUNT_1/$AND2_1/$ND2_1 00#B 19 52 2 1 0
+$COUNT_1/$FJK3_2$Q 7 $COUNT_1/$FJK3_2 00#Q 81 52 2 1 0
+$COUNT_1/$FJK3_2$Q 7 $COUNT_1/$AND2_2/$ND2_1 01#B 11 26 2 -1 0
+$COUNT_1/$AND2_3/$ND2_1$Z 8 $COUNT_1/$AND2_3/$ND2_1 00#Z 5 52 2 1 0
+$COUNT_1/$AND2_3/$ND2_1$Z 8 $COUNT_1/$AND2_3/$IV_1 00#A 5 26 2 -1 0
+$COUNT_1/$AND2_4/$ND2_1$Z 9 $COUNT_1/$AND2_4/$ND2_1 00#Z 7 52 2 1 0
+$COUNT_1/$AND2_4/$ND2_1$Z 9 $COUNT_1/$AND2_4/$IV_1 00#A 3 26 2 -1 0
diff --git a/tests/long/70.twolf/ref/alpha/linux/simple-timing/smred.pl1 b/tests/long/70.twolf/ref/alpha/linux/simple-timing/smred.pl1
new file mode 100644
index 000000000..bdc569e39
--- /dev/null
+++ b/tests/long/70.twolf/ref/alpha/linux/simple-timing/smred.pl1
@@ -0,0 +1,11 @@
+$COUNT_1/$AND2_4/$IV_1 0 0 4 26 0 1
+$COUNT_1/$AND2_3/$IV_1 4 0 8 26 2 1
+$COUNT_1/$AND2_2/$ND2_1 8 0 14 26 0 1
+ACOUNT_1 14 0 18 26 2 1
+twfeed1 18 0 22 26 0 1
+$COUNT_1/$FJK3_1 22 0 86 26 0 1
+$COUNT_1/$AND2_3/$ND2_1 0 52 6 78 0 2
+$COUNT_1/$AND2_4/$ND2_1 6 52 12 78 2 2
+$COUNT_1/$AND2_2/$IV_1 12 52 16 78 2 2
+$COUNT_1/$AND2_1/$ND2_1 16 52 22 78 2 2
+$COUNT_1/$FJK3_2 22 52 86 78 0 2
diff --git a/tests/long/70.twolf/ref/alpha/linux/simple-timing/smred.pl2 b/tests/long/70.twolf/ref/alpha/linux/simple-timing/smred.pl2
new file mode 100644
index 000000000..6e2601e82
--- /dev/null
+++ b/tests/long/70.twolf/ref/alpha/linux/simple-timing/smred.pl2
@@ -0,0 +1,2 @@
+1 0 0 86 26 0 0
+2 0 52 86 78 0 0
diff --git a/tests/long/70.twolf/ref/alpha/linux/simple-timing/smred.sav b/tests/long/70.twolf/ref/alpha/linux/simple-timing/smred.sav
new file mode 100644
index 000000000..04c8e9935
--- /dev/null
+++ b/tests/long/70.twolf/ref/alpha/linux/simple-timing/smred.sav
@@ -0,0 +1,18 @@
+0.009592
+121
+0
+1
+0.000000
+0.500000
+3.906156
+1
+1 1 2 37 13
+2 2 0 34 65
+3 2 2 63 65
+4 1 0 59 13
+5 1 2 32 13
+6 2 0 23 65
+7 1 2 12 13
+8 2 0 6 65
+9 1 0 70 13
+10 2 0 70 65
diff --git a/tests/long/70.twolf/ref/alpha/linux/simple-timing/smred.sv2 b/tests/long/70.twolf/ref/alpha/linux/simple-timing/smred.sv2
new file mode 100644
index 000000000..9dd68ecdb
--- /dev/null
+++ b/tests/long/70.twolf/ref/alpha/linux/simple-timing/smred.sv2
@@ -0,0 +1,19 @@
+0.001000
+123
+0
+2
+0.000000
+0.500000
+3.906156
+1
+1 1 2 16 13
+2 2 2 19 65
+3 2 2 14 65
+4 1 0 11 13
+5 1 2 6 13
+6 2 0 3 65
+7 1 0 2 13
+8 2 2 9 65
+9 1 0 50 13
+10 2 0 54 65
+11 1 0 84 13
diff --git a/tests/long/70.twolf/ref/alpha/linux/simple-timing/smred.twf b/tests/long/70.twolf/ref/alpha/linux/simple-timing/smred.twf
new file mode 100644
index 000000000..a4c2eac35
--- /dev/null
+++ b/tests/long/70.twolf/ref/alpha/linux/simple-timing/smred.twf
@@ -0,0 +1,29 @@
+net 1
+segment channel 2
+ pin1 1 pin2 7 0 0
+net 2
+segment channel 3
+pin1 41 pin2 42 0 0
+segment channel 2
+pin1 12 pin2 3 0 0
+net 3
+segment channel 2
+pin1 35 pin2 36 0 0
+segment channel 2
+pin1 19 pin2 35 0 0
+net 4
+segment channel 2
+ pin1 5 pin2 38 0 0
+net 5
+net 7
+segment channel 2
+ pin1 14 pin2 43 0 0
+net 8
+segment channel 2
+ pin1 23 pin2 17 0 0
+net 9
+net 11
+segment channel 2
+ pin1 25 pin2 31 0 0
+net 14
+net 15
diff --git a/tests/long/70.twolf/ref/alpha/linux/simple-timing/stderr b/tests/long/70.twolf/ref/alpha/linux/simple-timing/stderr
index 8893caac8..87866a2a5 100644
--- a/tests/long/70.twolf/ref/alpha/linux/simple-timing/stderr
+++ b/tests/long/70.twolf/ref/alpha/linux/simple-timing/stderr
@@ -1,3 +1 @@
warn: Entering event queue @ 0. Starting simulation...
-warn: cycle 0: fault (page_table_fault) detected @ PC 0x000000
-warn: Increasing stack 0x11ff92000:0x11ff9b000 to 0x11ff90000:0x11ff9b000 because of access to 0x11ff91ff0
diff --git a/tests/long/70.twolf/ref/alpha/linux/simple-timing/stdout b/tests/long/70.twolf/ref/alpha/linux/simple-timing/stdout
index fbb329a2f..f32f0a972 100644
--- a/tests/long/70.twolf/ref/alpha/linux/simple-timing/stdout
+++ b/tests/long/70.twolf/ref/alpha/linux/simple-timing/stdout
@@ -1,13 +1,14 @@
-Hello world!
-M5 Simulator System
-Copyright (c) 2001-2006
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Sep 5 2006 15:28:48
-M5 started Tue Sep 5 15:42:12 2006
-M5 executing on zizzer.eecs.umich.edu
-command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/o3-timing tests/run.py quick/00.hello/alpha/linux/o3-timing
-Exiting @ tick 6870 because target called exit()
+TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988
+Standard Cell Placement and Global Routing Program
+Authors: Carl Sechen, Bill Swartz
+ Yale University
+ 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
+ 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
+ 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
+ 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
+ 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75
+ 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
+ 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
+106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
+122 123 124 \ No newline at end of file
diff --git a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini
index dff95e358..791395981 100644
--- a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini
+++ b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini
@@ -82,7 +82,7 @@ table_size=65536
[drivesys.disk0.image.child]
type=RawDiskImage
-image_file=/dist/m5/system/disks/myimg.img
+image_file=/dist/m5/system/disks/linux-latest.img
read_only=true
[drivesys.disk2]
@@ -166,7 +166,7 @@ system=drivesys
[drivesys.simple_disk.disk]
type=RawDiskImage
-image_file=/dist/m5/system/disks/myimg.img
+image_file=/dist/m5/system/disks/linux-latest.img
read_only=true
[drivesys.tsunami]
@@ -701,7 +701,7 @@ table_size=65536
[testsys.disk0.image.child]
type=RawDiskImage
-image_file=/dist/m5/system/disks/myimg.img
+image_file=/dist/m5/system/disks/linux-latest.img
read_only=true
[testsys.disk2]
@@ -785,7 +785,7 @@ system=testsys
[testsys.simple_disk.disk]
type=RawDiskImage
-image_file=/dist/m5/system/disks/myimg.img
+image_file=/dist/m5/system/disks/linux-latest.img
read_only=true
[testsys.tsunami]
diff --git a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.out b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.out
index 19bb5af44..21b542b9b 100644
--- a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.out
+++ b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.out
@@ -305,7 +305,7 @@ write_ack=false
[testsys.disk0.image.child]
type=RawDiskImage
-image_file=/dist/m5/system/disks/myimg.img
+image_file=/dist/m5/system/disks/linux-latest.img
read_only=true
[testsys.disk0.image]
@@ -341,7 +341,7 @@ delay=1000000
[testsys.simple_disk.disk]
type=RawDiskImage
-image_file=/dist/m5/system/disks/myimg.img
+image_file=/dist/m5/system/disks/linux-latest.img
read_only=true
[testsys.simple_disk]
@@ -691,7 +691,7 @@ write_ack=false
[drivesys.disk0.image.child]
type=RawDiskImage
-image_file=/dist/m5/system/disks/myimg.img
+image_file=/dist/m5/system/disks/linux-latest.img
read_only=true
[drivesys.disk0.image]
@@ -727,7 +727,7 @@ delay=1000000
[drivesys.simple_disk.disk]
type=RawDiskImage
-image_file=/dist/m5/system/disks/myimg.img
+image_file=/dist/m5/system/disks/linux-latest.img
read_only=true
[drivesys.simple_disk]
diff --git a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/console.drivesys.sim_console b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/console.drivesys.sim_console
index 931411c03..aa129d6a7 100644
--- a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/console.drivesys.sim_console
+++ b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/console.drivesys.sim_console
@@ -72,7 +72,7 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
hdb: M5 IDE Disk, ATA DISK drive
ide0 at 0x8410-0x8417,0x8422 on irq 31
hda: max request size: 128KiB
- hda: 409248 sectors (209 MB), CHS=406/16/63, UDMA(33)
+ hda: 511056 sectors (261 MB), CHS=507/16/63, UDMA(33)
hda: cache flushes not supported
hda: hda1
hdb: max request size: 128KiB
@@ -99,7 +99,7 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
All bugs added by David S. Miller <davem@redhat.com>
VFS: Mounted root (ext2 filesystem) readonly.
Freeing unused kernel memory: 224k freed
- init started: BusyBox v1.1.0 (2006.10.31-01:25+0000) multi-call binary
+ init started: BusyBox v1.1.0 (2006.08.17-02:54+0000) multi-call binary
mounting filesystems...
loading script...
setting up network...
diff --git a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/console.testsys.sim_console b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/console.testsys.sim_console
index aea9af01d..b8f1a6cae 100644
--- a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/console.testsys.sim_console
+++ b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/console.testsys.sim_console
@@ -72,7 +72,7 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
hdb: M5 IDE Disk, ATA DISK drive
ide0 at 0x8410-0x8417,0x8422 on irq 31
hda: max request size: 128KiB
- hda: 409248 sectors (209 MB), CHS=406/16/63, UDMA(33)
+ hda: 511056 sectors (261 MB), CHS=507/16/63, UDMA(33)
hda: cache flushes not supported
hda: hda1
hdb: max request size: 128KiB
@@ -99,7 +99,7 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
All bugs added by David S. Miller <davem@redhat.com>
VFS: Mounted root (ext2 filesystem) readonly.
Freeing unused kernel memory: 224k freed
- init started: BusyBox v1.1.0 (2006.10.31-01:25+0000) multi-call binary
+ init started: BusyBox v1.1.0 (2006.08.17-02:54+0000) multi-call binary
mounting filesystems...
loading script...
setting up network...
diff --git a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/m5stats.txt b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/m5stats.txt
index 328846907..dc4ea4a17 100644
--- a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/m5stats.txt
+++ b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/m5stats.txt
@@ -39,8 +39,8 @@ drivesys.cpu.kern.ipl_good_0 1189 45.85% 45.85% # nu
drivesys.cpu.kern.ipl_good_21 10 0.39% 46.24% # number of times we switched to this ipl from a different ipl
drivesys.cpu.kern.ipl_good_22 205 7.91% 54.15% # number of times we switched to this ipl from a different ipl
drivesys.cpu.kern.ipl_good_31 1189 45.85% 100.00% # number of times we switched to this ipl from a different ipl
-drivesys.cpu.kern.ipl_ticks 199572064366 # number of cycles we spent at this ipl
-drivesys.cpu.kern.ipl_ticks_0 199571744403 100.00% 100.00% # number of cycles we spent at this ipl
+drivesys.cpu.kern.ipl_ticks 199572064367 # number of cycles we spent at this ipl
+drivesys.cpu.kern.ipl_ticks_0 199571744404 100.00% 100.00% # number of cycles we spent at this ipl
drivesys.cpu.kern.ipl_ticks_21 1620 0.00% 100.00% # number of cycles we spent at this ipl
drivesys.cpu.kern.ipl_ticks_22 17630 0.00% 100.00% # number of cycles we spent at this ipl
drivesys.cpu.kern.ipl_ticks_31 300713 0.00% 100.00% # number of cycles we spent at this ipl
@@ -61,7 +61,7 @@ drivesys.cpu.kern.mode_switch_good_user 1 # fr
drivesys.cpu.kern.mode_switch_good_idle 0.013761 # fraction of useful protection mode switches
drivesys.cpu.kern.mode_ticks_kernel 263475 0.24% 0.24% # number of ticks spent at the given mode
drivesys.cpu.kern.mode_ticks_user 1278343 1.18% 1.43% # number of ticks spent at the given mode
-drivesys.cpu.kern.mode_ticks_idle 106483912 98.57% 100.00% # number of ticks spent at the given mode
+drivesys.cpu.kern.mode_ticks_idle 106485234 98.57% 100.00% # number of ticks spent at the given mode
drivesys.cpu.kern.swap_context 70 # number of times the context was actually changed
drivesys.cpu.kern.syscall 22 # number of syscalls executed
drivesys.cpu.kern.syscall_2 1 4.55% 4.55% # number of syscalls executed
@@ -140,12 +140,12 @@ drivesys.tsunami.ethernet.txPPS 25 # Pa
drivesys.tsunami.ethernet.txPackets 5 # Number of Packets Transmitted
drivesys.tsunami.ethernet.txTcpChecksums 2 # Number of tx TCP Checksums done by device
drivesys.tsunami.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device
-host_inst_rate 38374803 # Simulator instruction rate (inst/s)
-host_mem_usage 411180 # Number of bytes of host memory used
-host_seconds 7.20 # Real time elapsed on the host
-host_tick_rate 27794359444 # Simulator tick rate (ticks/s)
+host_inst_rate 38710250 # Simulator instruction rate (inst/s)
+host_mem_usage 411152 # Number of bytes of host memory used
+host_seconds 7.14 # Real time elapsed on the host
+host_tick_rate 28030590990 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 276122825 # Number of instructions simulated
+sim_insts 276189231 # Number of instructions simulated
sim_seconds 0.200001 # Number of seconds simulated
sim_ticks 200000789468 # Number of ticks simulated
testsys.cpu.dtb.accesses 335402 # DTB accesses
@@ -188,8 +188,8 @@ testsys.cpu.kern.ipl_good_0 5055 48.15% 48.15% # nu
testsys.cpu.kern.ipl_good_21 183 1.74% 49.90% # number of times we switched to this ipl from a different ipl
testsys.cpu.kern.ipl_good_22 205 1.95% 51.85% # number of times we switched to this ipl from a different ipl
testsys.cpu.kern.ipl_good_31 5055 48.15% 100.00% # number of times we switched to this ipl from a different ipl
-testsys.cpu.kern.ipl_ticks 199569923608 # number of cycles we spent at this ipl
-testsys.cpu.kern.ipl_ticks_0 199569308038 100.00% 100.00% # number of cycles we spent at this ipl
+testsys.cpu.kern.ipl_ticks 199569923603 # number of cycles we spent at this ipl
+testsys.cpu.kern.ipl_ticks_0 199569308033 100.00% 100.00% # number of cycles we spent at this ipl
testsys.cpu.kern.ipl_ticks_21 30857 0.00% 100.00% # number of cycles we spent at this ipl
testsys.cpu.kern.ipl_ticks_22 17630 0.00% 100.00% # number of cycles we spent at this ipl
testsys.cpu.kern.ipl_ticks_31 567083 0.00% 100.00% # number of cycles we spent at this ipl
@@ -210,7 +210,7 @@ testsys.cpu.kern.mode_switch_good_user 1 # fr
testsys.cpu.kern.mode_switch_good_idle 0.013123 # fraction of useful protection mode switches
testsys.cpu.kern.mode_ticks_kernel 1821232 2.16% 2.16% # number of ticks spent at the given mode
testsys.cpu.kern.mode_ticks_user 1065606 1.26% 3.42% # number of ticks spent at the given mode
-testsys.cpu.kern.mode_ticks_idle 81402474 96.58% 100.00% # number of ticks spent at the given mode
+testsys.cpu.kern.mode_ticks_idle 81403567 96.58% 100.00% # number of ticks spent at the given mode
testsys.cpu.kern.swap_context 440 # number of times the context was actually changed
testsys.cpu.kern.syscall 83 # number of syscalls executed
testsys.cpu.kern.syscall_2 3 3.61% 3.61% # number of syscalls executed
@@ -383,12 +383,12 @@ drivesys.tsunami.ethernet.totalSwi 0 # to
drivesys.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
drivesys.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
drivesys.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
-host_inst_rate 76361400719 # Simulator instruction rate (inst/s)
-host_mem_usage 411180 # Number of bytes of host memory used
+host_inst_rate 75502796884 # Simulator instruction rate (inst/s)
+host_mem_usage 411152 # Number of bytes of host memory used
host_seconds 0.00 # Real time elapsed on the host
-host_tick_rate 203621244 # Simulator tick rate (ticks/s)
+host_tick_rate 201377914 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 276122825 # Number of instructions simulated
+sim_insts 276189231 # Number of instructions simulated
sim_seconds 0.000001 # Number of seconds simulated
sim_ticks 785978 # Number of ticks simulated
testsys.cpu.dtb.accesses 0 # DTB accesses
@@ -417,10 +417,10 @@ testsys.cpu.kern.mode_good_idle 0
testsys.cpu.kern.mode_switch_kernel 0 # number of protection mode switches
testsys.cpu.kern.mode_switch_user 0 # number of protection mode switches
testsys.cpu.kern.mode_switch_idle 0 # number of protection mode switches
-testsys.cpu.kern.mode_switch_good <err: div-0> # fraction of useful protection mode switches
-testsys.cpu.kern.mode_switch_good_kernel <err: div-0> # fraction of useful protection mode switches
-testsys.cpu.kern.mode_switch_good_user <err: div-0> # fraction of useful protection mode switches
-testsys.cpu.kern.mode_switch_good_idle <err: div-0> # fraction of useful protection mode switches
+testsys.cpu.kern.mode_switch_good no value # fraction of useful protection mode switches
+testsys.cpu.kern.mode_switch_good_kernel no value # fraction of useful protection mode switches
+testsys.cpu.kern.mode_switch_good_user no value # fraction of useful protection mode switches
+testsys.cpu.kern.mode_switch_good_idle no value # fraction of useful protection mode switches
testsys.cpu.kern.mode_ticks_kernel 0 # number of ticks spent at the given mode
testsys.cpu.kern.mode_ticks_user 0 # number of ticks spent at the given mode
testsys.cpu.kern.mode_ticks_idle 0 # number of ticks spent at the given mode
diff --git a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stdout b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stdout
index 765e59472..183b4bb4e 100644
--- a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stdout
+++ b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stdout
@@ -6,12 +6,9 @@ All Rights Reserved
M5 compiled Nov 29 2006 16:48:25
-M5 started Fri Dec 1 01:07:49 2006
+M5 started Sat Dec 2 11:01:31 2006
M5 executing on zed.eecs.umich.edu
-command line: build/ALPHA_FS/m5.opt -d build/ALPHA_FS/tests/opt/long/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic tests/run.py long/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic
-WTF
-9685900: testsys.sim_console: attach console 0
-3327958029: drivesys.sim_console: attach console 0
-Resetting stats at cycle 4100234765800!
-Resetting stats at cycle 4300235555268!
-Exiting @ tick 4300236341246 because checkpoint
+command line: build/ALPHA_FS/m5.opt -d build/ALPHA_FS/tests/opt/quick/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic tests/run.py quick/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic
+Resetting stats at cycle 4093398828306!
+Resetting stats at cycle 4293399617774!
+Exiting @ tick 4293400403752 because checkpoint
diff --git a/util/cscope-find.py b/util/cscope-find.py
deleted file mode 100755
index 1775f1864..000000000
--- a/util/cscope-find.py
+++ /dev/null
@@ -1,38 +0,0 @@
-#! /usr/bin/python
-
-# Generate list of files to index with cscope.
-
-# From the m5 directory, run:
-# util/cscope-find.py > cscope.files
-# cscope -b
-
-import os
-
-# absolute paths to skip
-skipdirs = [ 'src/unittest', 'src/doxygen' ]
-
-# suffixes of files to index
-suffixes = [ '.cc', '.hh', '.c', '.h' ]
-
-def oksuffix(f):
- for s in suffixes:
- if f.endswith(s):
- return True
- return False
-
-for dirpath,subdirs,files in os.walk('src'):
- # filter out undesirable subdirectories
- for i,dir in enumerate(subdirs):
- if dir == 'SCCS':
- del subdirs[i]
- break
-
- # filter out undesriable absolute paths
- if dirpath in skipdirs:
- del subdirs[:]
- continue
-
- # find C/C++ sources
- okfiles = [f for f in files if oksuffix(f)]
- if okfiles:
- print '\n'.join([os.path.join(dirpath, f) for f in okfiles])
diff --git a/util/cscope-index.py b/util/cscope-index.py
new file mode 100755
index 000000000..1e653235f
--- /dev/null
+++ b/util/cscope-index.py
@@ -0,0 +1,71 @@
+#! /usr/bin/python
+# Copyright (c) 2006 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Steve Reinhardt
+
+# Generate list of files to index with cscope and then generate cscope index.
+
+# Should be run from root of m5 tree (i.e. as 'util/cscope-index.py').
+
+import os
+
+# absolute paths to skip
+skipdirs = [ 'src/unittest', 'src/doxygen' ]
+
+# suffixes of files to index
+suffixes = [ '.cc', '.hh', '.c', '.h' ]
+
+def oksuffix(f):
+ for s in suffixes:
+ if f.endswith(s):
+ return True
+ return False
+
+file_list = file('cscope.files', 'w')
+
+for dirpath,subdirs,files in os.walk('src'):
+ # filter out undesirable subdirectories
+ for i,dir in enumerate(subdirs):
+ if dir == 'SCCS':
+ del subdirs[i]
+ break
+
+ # filter out undesirable absolute paths
+ if dirpath in skipdirs:
+ del subdirs[:]
+ continue
+
+ # find C/C++ sources
+ okfiles = [f for f in files if oksuffix(f)]
+ if okfiles:
+ print >> file_list, \
+ '\n'.join([os.path.join(dirpath, f) for f in okfiles])
+
+file_list.close()
+
+# run cscope to generate index
+os.system("cscope -b")
diff --git a/util/make_release.py b/util/make_release.py
index d1161166d..f07bafe3b 100755
--- a/util/make_release.py
+++ b/util/make_release.py
@@ -80,18 +80,31 @@ if len(sys.argv) != 3:
destdir = sys.argv[1]
releasename = sys.argv[2]
+release_dest = joinpath(destdir, 'release')
+encumbered_dest = joinpath(destdir, 'encumbered')
+release_dir = joinpath(release_dest, releasename)
+encumbered_dir = joinpath(encumbered_dest, releasename)
if exists(destdir):
if not isdir(destdir):
raise AttributeError, '%s exists, but is not a directory' % destdir
- rmtree(destdir)
-
-release_dir = joinpath(destdir, 'release', releasename)
-encumbered_dir = joinpath(destdir, 'encumbered', releasename)
-
-mkdir(destdir)
-mkdir(destdir, 'release')
-mkdir(destdir, 'encumbered')
+else:
+ mkdir(destdir)
+
+if exists(release_dest):
+ if not isdir(release_dest):
+ raise AttributeError, \
+ '%s exists, but is not a directory' % release_dest
+ rmtree(release_dest)
+
+if exists(encumbered_dest):
+ if not isdir(encumbered_dest):
+ raise AttributeError, \
+ '%s exists, but is not a directory' % encumbered_dest
+ rmtree(encumbered_dest)
+
+mkdir(release_dest)
+mkdir(encumbered_dest)
mkdir(release_dir)
mkdir(encumbered_dir)
@@ -109,7 +122,6 @@ rmtree(release_dir, 'src/mem/cache/prefetch/ghb_*.cc')
rmtree(release_dir, 'src/mem/cache/prefetch/ghb_*.hh')
rmtree(release_dir, 'src/mem/cache/prefetch/stride_*.cc')
rmtree(release_dir, 'src/mem/cache/prefetch/stride_*.hh')
-rmtree(release_dir, 'src/oldmem')
rmtree(release_dir, 'configs/fullsys')
rmtree(release_dir, 'configs/test')
rmtree(release_dir, 'configs/splash2')
diff --git a/util/regress b/util/regress
index 8e60b6fee..5d6f321f2 100755
--- a/util/regress
+++ b/util/regress
@@ -43,11 +43,13 @@ optparser.add_option('--builds', dest='builds',
help='comma-separated list of build targets to test '
" (default: '%default')" )
optparser.add_option('--variants', dest='variants',
- default='opt',
+ default='fast',
help='comma-separated list of build variants to test '
" (default: '%default')" )
optparser.add_option('--scons-opts', dest='scons_opts', default='',
help='scons options', metavar='OPTS')
+optparser.add_option('-j', '--jobs', type='int', default=1,
+ help='number of parallel jobs to use')
(options, tests) = optparser.parse_args()
@@ -75,10 +77,11 @@ def shellquote(s):
try:
if not tests:
- print "No tests specified."
- sys.exit(1)
-
- if 'all' in tests:
+ print "No tests specified, just building binaries."
+ targets = ['build/%s/m5.%s' % (build, variant)
+ for build in builds
+ for variant in variants]
+ elif 'all' in tests:
targets = ['build/%s/tests/%s' % (build, variant)
for build in builds
for variant in variants]
@@ -88,7 +91,11 @@ try:
for variant in variants
for test in tests]
- system('scons %s %s' % (options.scons_opts, ' '.join(targets)))
+ scons_opts = options.scons_opts
+ if options.jobs != 1:
+ scons_opts += ' -j %d' % options.jobs
+
+ system('scons %s %s' % (scons_opts, ' '.join(targets)))
sys.exit(0)