diff options
author | Kevin Lim <ktlim@umich.edu> | 2006-11-07 14:25:54 -0500 |
---|---|---|
committer | Kevin Lim <ktlim@umich.edu> | 2006-11-07 14:25:54 -0500 |
commit | 8ba73da056ae8b34713dc5b927d4ceb238db969a (patch) | |
tree | d374baa289829a81a33f2e6c0f8de840cce27f8b | |
parent | 244e0c884c60c141ea1bc63bb93e0aee25d6a854 (diff) | |
download | gem5-8ba73da056ae8b34713dc5b927d4ceb238db969a.tar.xz |
Fix up bus draining and add draining to the caches.
src/mem/bus.cc:
Fix up draining to work properly.
src/mem/bus.hh:
Initialize drainEvent to NULL.
src/mem/cache/base_cache.cc:
src/mem/cache/base_cache.hh:
Add draining to the caches.
--HG--
extra : convert_revision : 3082220a75d50876f10909f9f99bec535889f818
-rw-r--r-- | src/mem/bus.cc | 10 | ||||
-rw-r--r-- | src/mem/bus.hh | 4 | ||||
-rw-r--r-- | src/mem/cache/base_cache.cc | 22 | ||||
-rw-r--r-- | src/mem/cache/base_cache.hh | 33 |
4 files changed, 61 insertions, 8 deletions
diff --git a/src/mem/bus.cc b/src/mem/bus.cc index 28ee3476b..7b65d252b 100644 --- a/src/mem/bus.cc +++ b/src/mem/bus.cc @@ -240,10 +240,10 @@ Bus::recvRetry(int id) busIdle.reschedule(tickNextIdle); } } - //If we weren't able to drain before, we might be able to now. - if (drainEvent && retryList.size() == 0 && curTick >= tickNextIdle) - drainEvent->process(); } + //If we weren't able to drain before, we might be able to now. + if (drainEvent && retryList.size() == 0 && curTick >= tickNextIdle) + drainEvent->process(); } Port * @@ -521,10 +521,10 @@ Bus::drain(Event * de) //waiting. We might be idle but have someone waiting if the device we //contacted for a retry didn't actually retry. if (curTick >= tickNextIdle && retryList.size() == 0) { + return 0; + } else { drainEvent = de; return 1; - } else { - return 0; } } diff --git a/src/mem/bus.hh b/src/mem/bus.hh index 1d1cfde89..ff1d2545d 100644 --- a/src/mem/bus.hh +++ b/src/mem/bus.hh @@ -257,8 +257,8 @@ class Bus : public MemObject Bus(const std::string &n, int bus_id, int _clock, int _width, bool responder_set) : MemObject(n), busId(bus_id), clock(_clock), width(_width), - tickNextIdle(0), busIdle(this), inRetry(false), defaultPort(NULL), - responderSet(responder_set) + tickNextIdle(0), drainEvent(NULL), busIdle(this), inRetry(false), + defaultPort(NULL), responderSet(responder_set) { //Both the width and clock period must be positive if (width <= 0) diff --git a/src/mem/cache/base_cache.cc b/src/mem/cache/base_cache.cc index 1c519fb86..c26d7782b 100644 --- a/src/mem/cache/base_cache.cc +++ b/src/mem/cache/base_cache.cc @@ -140,6 +140,9 @@ BaseCache::CachePort::recvRetry() } waitingOnRetry = false; } + // Check if we're done draining once this list is empty + if (drainList.empty()) + cache->checkDrain(); } else if (!isCpuSide) { @@ -338,6 +341,10 @@ BaseCache::CacheEvent::process() cachePort->drainList.push_back(pkt); cachePort->waitingOnRetry = true; } + + // Check if we're done draining once this list is empty + if (cachePort->drainList.empty()) + cachePort->cache->checkDrain(); } const char * @@ -599,3 +606,18 @@ BaseCache::regStats() ; } + +unsigned int +BaseCache::drain(Event *de) +{ + // Set status + if (!canDrain()) { + drainEvent = de; + + changeState(SimObject::Draining); + return 1; + } + + changeState(SimObject::Drained); + return 0; +} diff --git a/src/mem/cache/base_cache.hh b/src/mem/cache/base_cache.hh index 565280aef..ea7544fbb 100644 --- a/src/mem/cache/base_cache.hh +++ b/src/mem/cache/base_cache.hh @@ -105,6 +105,8 @@ class BaseCache : public MemObject void clearBlocked(); + bool canDrain() { return drainList.empty(); } + bool blocked; bool mustSendRetry; @@ -227,6 +229,9 @@ class BaseCache : public MemObject /** The number of misses to trigger an exit event. */ Counter missCount; + /** The drain event. */ + Event *drainEvent; + public: // Statistics /** @@ -340,7 +345,7 @@ class BaseCache : public MemObject BaseCache(const std::string &name, Params ¶ms) : MemObject(name), blocked(0), blockedSnoop(0), masterRequests(0), slaveRequests(0), blkSize(params.blkSize), - missCount(params.maxMisses) + missCount(params.maxMisses), drainEvent(NULL) { //Start ports at null if more than one is created we should panic cpuSidePort = NULL; @@ -477,6 +482,7 @@ class BaseCache : public MemObject { uint8_t flag = 1<<cause; masterRequests &= ~flag; + checkDrain(); } /** @@ -512,6 +518,7 @@ class BaseCache : public MemObject { uint8_t flag = 1<<cause; slaveRequests &= ~flag; + checkDrain(); } /** @@ -589,6 +596,30 @@ class BaseCache : public MemObject return; } } + + virtual unsigned int drain(Event *de); + + void checkDrain() + { + if (drainEvent && canDrain()) { + drainEvent->process(); + changeState(SimObject::Drained); + // Clear the drain event + drainEvent = NULL; + } + } + + bool canDrain() + { + if (doMasterRequest() || doSlaveRequest()) { + return false; + } else if (memSidePort && !memSidePort->canDrain()) { + return false; + } else if (cpuSidePort && !cpuSidePort->canDrain()) { + return false; + } + return true; + } }; #endif //__BASE_CACHE_HH__ |