diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2014-11-24 09:03:39 -0500 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2014-11-24 09:03:39 -0500 |
| commit | b0aa5a326da8489583d055b4876f534b6fc23626 (patch) | |
| tree | 54beca1c0dcaa197ec03588aee704510931aa5d9 | |
| parent | d66b14ca61bec95a4049e5aae468904395055efd (diff) | |
| download | gem5-b0aa5a326da8489583d055b4876f534b6fc23626.tar.xz | |
stats: Bump stats after static analysis fixes
Fixing up the uninitialised values changes two of the x86 Linux boot
regressions slightly.
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/stats.txt | 660 | ||||
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt | 130 |
2 files changed, 395 insertions, 395 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/stats.txt index 0478e90e4..b728ac0c9 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/stats.txt @@ -4,11 +4,11 @@ sim_seconds 5.300742 # Nu sim_ticks 5300741898500 # Number of ticks simulated final_tick 5300741898500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 150557 # Simulator instruction rate (inst/s) -host_op_rate 288657 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 7473061965 # Simulator tick rate (ticks/s) -host_mem_usage 840444 # Number of bytes of host memory used -host_seconds 709.31 # Real time elapsed on the host +host_inst_rate 268181 # Simulator instruction rate (inst/s) +host_op_rate 514172 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 13311463323 # Simulator tick rate (ticks/s) +host_mem_usage 800056 # Number of bytes of host memory used +host_seconds 398.21 # Real time elapsed on the host sim_insts 106792132 # Number of instructions simulated sim_ops 204747982 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -290,6 +290,273 @@ system.mem_ctrls.totalEnergy::0 3546444264855 # T system.mem_ctrls.totalEnergy::1 3546550064145 # Total energy per rank (pJ) system.mem_ctrls.averagePower::0 669.047128 # Core power per rank (mW) system.mem_ctrls.averagePower::1 669.067087 # Core power per rank (mW) +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu0.apic_clk_domain.clock 8000 # Clock period in ticks +system.cpu0.numCycles 10600620667 # number of cpu cycles simulated +system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu0.committedInsts 58326751 # Number of instructions committed +system.cpu0.committedOps 112208544 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 105142610 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses +system.cpu0.num_func_calls 999393 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 9968022 # number of instructions that are conditional controls +system.cpu0.num_int_insts 105142610 # number of integer instructions +system.cpu0.num_fp_insts 0 # number of float instructions +system.cpu0.num_int_register_reads 198014063 # number of times the integer registers were read +system.cpu0.num_int_register_writes 89363011 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu0.num_cc_register_reads 60260543 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 43624365 # number of times the CC registers were written +system.cpu0.num_mem_refs 12030075 # number of memory refs +system.cpu0.num_load_insts 7288332 # Number of load instructions +system.cpu0.num_store_insts 4741743 # Number of store instructions +system.cpu0.num_idle_cycles 10084773874.270475 # Number of idle cycles +system.cpu0.num_busy_cycles 515846792.729524 # Number of busy cycles +system.cpu0.not_idle_fraction 0.048662 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.951338 # Percentage of idle cycles +system.cpu0.Branches 11302630 # Number of branches fetched +system.cpu0.op_class::No_OpClass 132692 0.12% 0.12% # Class of executed instruction +system.cpu0.op_class::IntAlu 99906926 89.04% 89.15% # Class of executed instruction +system.cpu0.op_class::IntMult 87661 0.08% 89.23% # Class of executed instruction +system.cpu0.op_class::IntDiv 51849 0.05% 89.28% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 89.28% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 89.28% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 89.28% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 89.28% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 89.28% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 89.28% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 89.28% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 89.28% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 89.28% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 89.28% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 89.28% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 89.28% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 89.28% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 89.28% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 89.28% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 89.28% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 89.28% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 89.28% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 89.28% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 89.28% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 89.28% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 89.28% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 0 0.00% 89.28% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 89.28% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 89.28% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 89.28% # Class of executed instruction +system.cpu0.op_class::MemRead 7288332 6.50% 95.77% # Class of executed instruction +system.cpu0.op_class::MemWrite 4741743 4.23% 100.00% # Class of executed instruction +system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu0.op_class::total 112209203 # Class of executed instruction +system.cpu0.kern.inst.arm 0 # number of arm instructions executed +system.cpu0.kern.inst.quiesce 0 # number of quiesce instructions executed +system.cpu1.apic_clk_domain.clock 8000 # Clock period in ticks +system.cpu1.numCycles 10601483797 # number of cpu cycles simulated +system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu1.committedInsts 48465381 # Number of instructions committed +system.cpu1.committedOps 92539438 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 88910462 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses +system.cpu1.num_func_calls 1744945 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 8275238 # number of instructions that are conditional controls +system.cpu1.num_int_insts 88910462 # number of integer instructions +system.cpu1.num_fp_insts 0 # number of float instructions +system.cpu1.num_int_register_reads 172623141 # number of times the integer registers were read +system.cpu1.num_int_register_writes 73500216 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu1.num_cc_register_reads 51257305 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 33029139 # number of times the CC registers were written +system.cpu1.num_mem_refs 14403882 # number of memory refs +system.cpu1.num_load_insts 9271822 # Number of load instructions +system.cpu1.num_store_insts 5132060 # Number of store instructions +system.cpu1.num_idle_cycles 10262330670.974064 # Number of idle cycles +system.cpu1.num_busy_cycles 339153126.025936 # Number of busy cycles +system.cpu1.not_idle_fraction 0.031991 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.968009 # Percentage of idle cycles +system.cpu1.Branches 10623766 # Number of branches fetched +system.cpu1.op_class::No_OpClass 173936 0.19% 0.19% # Class of executed instruction +system.cpu1.op_class::IntAlu 77788975 84.06% 84.25% # Class of executed instruction +system.cpu1.op_class::IntMult 96916 0.10% 84.35% # Class of executed instruction +system.cpu1.op_class::IntDiv 76680 0.08% 84.44% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 84.44% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 84.44% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 84.44% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 84.44% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 84.44% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 84.44% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 84.44% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 84.44% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 84.44% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 84.44% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 84.44% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 84.44% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 84.44% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 84.44% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 84.44% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 84.44% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 84.44% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 84.44% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 84.44% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 84.44% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 84.44% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 84.44% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 0 0.00% 84.44% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 84.44% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 84.44% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 84.44% # Class of executed instruction +system.cpu1.op_class::MemRead 9271822 10.02% 94.45% # Class of executed instruction +system.cpu1.op_class::MemWrite 5132060 5.55% 100.00% # Class of executed instruction +system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu1.op_class::total 92540389 # Class of executed instruction +system.cpu1.kern.inst.arm 0 # number of arm instructions executed +system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed +system.iobus.trans_dist::ReadReq 857926 # Transaction distribution +system.iobus.trans_dist::ReadResp 857926 # Transaction distribution +system.iobus.trans_dist::WriteReq 36569 # Transaction distribution +system.iobus.trans_dist::WriteResp 36569 # Transaction distribution +system.iobus.trans_dist::MessageReq 1919 # Transaction distribution +system.iobus.trans_dist::MessageResp 1919 # Transaction distribution +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl0.sequencer.pio-slave-port 1700 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl1.sequencer.pio-slave-port 1642 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3342 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.cmos.pio 36 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.ide.pio 4780 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.ide-pciconf 88 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.keyboard.pio 1048 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio 82 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic2.pio 42 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.speaker.pio 934582 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio 990 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.i_dont_exist1.pio 90 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.com_1.pio 16892 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port 743276 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port 296 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.pciconfig.pio 2126 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::total 1704360 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.cmos.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.ide.pio 6262 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.ide-pciconf 92 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.keyboard.pio 316 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio 12 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic2.pio 12 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pit.pio 31164 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio 364 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.i_dont_exist1.pio 31252 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.com_1.pio 10236 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port 200 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port 5148 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::total 85126 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 1792828 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl0.sequencer.pio-slave-port 3400 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl1.sequencer.pio-slave-port 3284 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6684 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.cmos.pio 18 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.ide.pio 2696 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.ide-pciconf 149 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.keyboard.pio 524 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio 41 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic2.pio 21 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.speaker.pio 467291 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio 1980 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.i_dont_exist1.pio 45 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.com_1.pio 8446 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port 1486546 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port 592 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.pciconfig.pio 4252 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::total 1972617 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.cmos.pio 8 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.ide.pio 3964 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.ide-pciconf 72 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.keyboard.pio 158 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio 6 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic2.pio 6 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pit.pio 15582 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio 728 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.i_dont_exist1.pio 15626 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.com_1.pio 5118 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port 400 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port 10293 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::total 51987 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2031288 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 51000 # Layer occupancy (ticks) +system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer1.occupancy 6500 # Layer occupancy (ticks) +system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer2.occupancy 10161500 # Layer occupancy (ticks) +system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer3.occupancy 144000 # Layer occupancy (ticks) +system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer4.occupancy 1080000 # Layer occupancy (ticks) +system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer5.occupancy 94000 # Layer occupancy (ticks) +system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer6.occupancy 59500 # Layer occupancy (ticks) +system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer7.occupancy 20808000 # Layer occupancy (ticks) +system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer8.occupancy 700937500 # Layer occupancy (ticks) +system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer9.occupancy 1385500 # Layer occupancy (ticks) +system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer10.occupancy 31365000 # Layer occupancy (ticks) +system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer12.occupancy 2500 # Layer occupancy (ticks) +system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer13.occupancy 23203000 # Layer occupancy (ticks) +system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer14.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer15.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer16.occupancy 12000 # Layer occupancy (ticks) +system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer17.occupancy 11000 # Layer occupancy (ticks) +system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer18.occupancy 469007612 # Layer occupancy (ticks) +system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer19.occupancy 8240496 # Layer occupancy (ticks) +system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer21.occupancy 1330000 # Layer occupancy (ticks) +system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer0.occupancy 2404108 # Layer occupancy (ticks) +system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer2.occupancy 2025089500 # Layer occupancy (ticks) +system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer4.occupancy 59993000 # Layer occupancy (ticks) +system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) +system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). +system.pc.south_bridge.ide.disks0.dma_read_bytes 32768 # Number of bytes transfered via DMA reads (not PRD). +system.pc.south_bridge.ide.disks0.dma_read_txs 30 # Number of DMA read transactions (not PRD). +system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes. +system.pc.south_bridge.ide.disks0.dma_write_bytes 2987008 # Number of bytes transfered via DMA writes. +system.pc.south_bridge.ide.disks0.dma_write_txs 813 # Number of DMA write transactions. +system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). +system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). +system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD). +system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. +system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. +system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. system.ruby.clk_domain.clock 500 # Clock period in ticks system.ruby.delayHist::bucket_size 4 # delay histogram for all message system.ruby.delayHist::max_bucket 39 # delay histogram for all message @@ -335,7 +602,6 @@ system.ruby.l1_cntrl0.L1Dcache.demand_accesses 11203338 system.ruby.l1_cntrl0.L1Icache.demand_hits 67461431 # Number of cache demand hits system.ruby.l1_cntrl0.L1Icache.demand_misses 317291 # Number of cache demand misses system.ruby.l1_cntrl0.L1Icache.demand_accesses 67778722 # Number of cache demand accesses -system.cpu_clk_domain.clock 500 # Clock period in ticks system.ruby.l1_cntrl0.prefetcher.miss_observed 0 # number of misses observed system.ruby.l1_cntrl0.prefetcher.allocated_streams 0 # number of streams allocated for prefetching system.ruby.l1_cntrl0.prefetcher.prefetches_requested 0 # number of prefetch requests made @@ -346,6 +612,26 @@ system.ruby.l1_cntrl0.prefetcher.partial_hits 0 system.ruby.l1_cntrl0.prefetcher.pages_crossed 0 # number of prefetches across pages system.ruby.l1_cntrl0.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed system.ruby.l1_cntrl0.fully_busy_cycles 12 # cycles for which number of transistions == max transitions +system.ruby.l1_cntrl1.L1Dcache.demand_hits 13058053 # Number of cache demand hits +system.ruby.l1_cntrl1.L1Dcache.demand_misses 1328322 # Number of cache demand misses +system.ruby.l1_cntrl1.L1Dcache.demand_accesses 14386375 # Number of cache demand accesses +system.ruby.l1_cntrl1.L1Icache.demand_hits 58259753 # Number of cache demand hits +system.ruby.l1_cntrl1.L1Icache.demand_misses 500441 # Number of cache demand misses +system.ruby.l1_cntrl1.L1Icache.demand_accesses 58760194 # Number of cache demand accesses +system.ruby.l1_cntrl1.prefetcher.miss_observed 0 # number of misses observed +system.ruby.l1_cntrl1.prefetcher.allocated_streams 0 # number of streams allocated for prefetching +system.ruby.l1_cntrl1.prefetcher.prefetches_requested 0 # number of prefetch requests made +system.ruby.l1_cntrl1.prefetcher.prefetches_accepted 0 # number of prefetch requests accepted +system.ruby.l1_cntrl1.prefetcher.dropped_prefetches 0 # number of prefetch requests dropped +system.ruby.l1_cntrl1.prefetcher.hits 0 # number of prefetched blocks accessed +system.ruby.l1_cntrl1.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched +system.ruby.l1_cntrl1.prefetcher.pages_crossed 0 # number of prefetches across pages +system.ruby.l1_cntrl1.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed +system.ruby.l1_cntrl1.fully_busy_cycles 12 # cycles for which number of transistions == max transitions +system.ruby.l2_cntrl0.L2cache.demand_hits 2436707 # Number of cache demand hits +system.ruby.l2_cntrl0.L2cache.demand_misses 227883 # Number of cache demand misses +system.ruby.l2_cntrl0.L2cache.demand_accesses 2664590 # Number of cache demand accesses +system.ruby.memctrl_clk_domain.clock 1500 # Clock period in ticks system.ruby.network.routers0.percent_links_utilized 0.029331 system.ruby.network.routers0.msg_count.Control::0 835827 system.ruby.network.routers0.msg_count.Request_Control::2 42905 @@ -363,22 +649,6 @@ system.ruby.network.routers0.msg_bytes.Response_Control::2 3940352 system.ruby.network.routers0.msg_bytes.Writeback_Data::0 21055680 system.ruby.network.routers0.msg_bytes.Writeback_Data::1 12024 system.ruby.network.routers0.msg_bytes.Writeback_Control::0 1296352 -system.ruby.l1_cntrl1.L1Dcache.demand_hits 13058053 # Number of cache demand hits -system.ruby.l1_cntrl1.L1Dcache.demand_misses 1328322 # Number of cache demand misses -system.ruby.l1_cntrl1.L1Dcache.demand_accesses 14386375 # Number of cache demand accesses -system.ruby.l1_cntrl1.L1Icache.demand_hits 58259753 # Number of cache demand hits -system.ruby.l1_cntrl1.L1Icache.demand_misses 500441 # Number of cache demand misses -system.ruby.l1_cntrl1.L1Icache.demand_accesses 58760194 # Number of cache demand accesses -system.ruby.l1_cntrl1.prefetcher.miss_observed 0 # number of misses observed -system.ruby.l1_cntrl1.prefetcher.allocated_streams 0 # number of streams allocated for prefetching -system.ruby.l1_cntrl1.prefetcher.prefetches_requested 0 # number of prefetch requests made -system.ruby.l1_cntrl1.prefetcher.prefetches_accepted 0 # number of prefetch requests accepted -system.ruby.l1_cntrl1.prefetcher.dropped_prefetches 0 # number of prefetch requests dropped -system.ruby.l1_cntrl1.prefetcher.hits 0 # number of prefetched blocks accessed -system.ruby.l1_cntrl1.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched -system.ruby.l1_cntrl1.prefetcher.pages_crossed 0 # number of prefetches across pages -system.ruby.l1_cntrl1.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed -system.ruby.l1_cntrl1.fully_busy_cycles 12 # cycles for which number of transistions == max transitions system.ruby.network.routers1.percent_links_utilized 0.057975 system.ruby.network.routers1.msg_count.Control::0 1828763 system.ruby.network.routers1.msg_count.Request_Control::2 40586 @@ -396,9 +666,6 @@ system.ruby.network.routers1.msg_bytes.Response_Control::2 10157488 system.ruby.network.routers1.msg_bytes.Writeback_Data::0 20369808 system.ruby.network.routers1.msg_bytes.Writeback_Data::1 14976 system.ruby.network.routers1.msg_bytes.Writeback_Control::0 7591088 -system.ruby.l2_cntrl0.L2cache.demand_hits 2436707 # Number of cache demand hits -system.ruby.l2_cntrl0.L2cache.demand_misses 227883 # Number of cache demand misses -system.ruby.l2_cntrl0.L2cache.demand_accesses 2664590 # Number of cache demand accesses system.ruby.network.routers2.percent_links_utilized 0.091680 system.ruby.network.routers2.msg_count.Control::0 2843003 system.ruby.network.routers2.msg_count.Request_Control::2 81677 @@ -466,273 +733,6 @@ system.ruby.network.msg_byte.Response_Data 636023880 system.ruby.network.msg_byte.Response_Control 87260712 system.ruby.network.msg_byte.Writeback_Data 124357464 system.ruby.network.msg_byte.Writeback_Control 28925184 -system.ruby.memctrl_clk_domain.clock 1500 # Clock period in ticks -system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). -system.pc.south_bridge.ide.disks0.dma_read_bytes 32768 # Number of bytes transfered via DMA reads (not PRD). -system.pc.south_bridge.ide.disks0.dma_read_txs 30 # Number of DMA read transactions (not PRD). -system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes. -system.pc.south_bridge.ide.disks0.dma_write_bytes 2987008 # Number of bytes transfered via DMA writes. -system.pc.south_bridge.ide.disks0.dma_write_txs 813 # Number of DMA write transactions. -system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). -system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). -system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD). -system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. -system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. -system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. -system.iobus.trans_dist::ReadReq 857926 # Transaction distribution -system.iobus.trans_dist::ReadResp 857926 # Transaction distribution -system.iobus.trans_dist::WriteReq 36569 # Transaction distribution -system.iobus.trans_dist::WriteResp 36569 # Transaction distribution -system.iobus.trans_dist::MessageReq 1919 # Transaction distribution -system.iobus.trans_dist::MessageResp 1919 # Transaction distribution -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl0.sequencer.pio-slave-port 1700 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl1.sequencer.pio-slave-port 1642 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3342 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.cmos.pio 36 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.ide.pio 4780 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.ide-pciconf 88 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.keyboard.pio 1048 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio 82 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic2.pio 42 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.speaker.pio 934582 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio 990 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.i_dont_exist.pio 90 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.com_1.pio 16892 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port 743276 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port 296 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.pciconfig.pio 2126 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::total 1704360 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.cmos.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.ide.pio 6262 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.ide-pciconf 92 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.keyboard.pio 316 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio 12 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic2.pio 12 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pit.pio 31164 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio 364 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.i_dont_exist.pio 31252 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.com_1.pio 10236 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port 200 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port 5148 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::total 85126 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 1792828 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl0.sequencer.pio-slave-port 3400 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl1.sequencer.pio-slave-port 3284 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6684 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.cmos.pio 18 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.ide.pio 2696 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.ide-pciconf 149 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.keyboard.pio 524 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio 41 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic2.pio 21 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.speaker.pio 467291 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio 1980 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.i_dont_exist.pio 45 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.com_1.pio 8446 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port 1486546 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port 592 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.pciconfig.pio 4252 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::total 1972617 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.cmos.pio 8 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.ide.pio 3964 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.ide-pciconf 72 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.keyboard.pio 158 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio 6 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic2.pio 6 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pit.pio 15582 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio 728 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.i_dont_exist.pio 15626 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.com_1.pio 5118 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port 400 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port 10293 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::total 51987 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2031288 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 51000 # Layer occupancy (ticks) -system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 6500 # Layer occupancy (ticks) -system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 10161500 # Layer occupancy (ticks) -system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 144000 # Layer occupancy (ticks) -system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer4.occupancy 1080000 # Layer occupancy (ticks) -system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer5.occupancy 94000 # Layer occupancy (ticks) -system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer6.occupancy 59500 # Layer occupancy (ticks) -system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 20808000 # Layer occupancy (ticks) -system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer8.occupancy 700937500 # Layer occupancy (ticks) -system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer9.occupancy 1385500 # Layer occupancy (ticks) -system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 31365000 # Layer occupancy (ticks) -system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer11.occupancy 2500 # Layer occupancy (ticks) -system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer12.occupancy 23203000 # Layer occupancy (ticks) -system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer13.occupancy 9000 # Layer occupancy (ticks) -system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer14.occupancy 9000 # Layer occupancy (ticks) -system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer15.occupancy 12000 # Layer occupancy (ticks) -system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer16.occupancy 11000 # Layer occupancy (ticks) -system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer17.occupancy 469007612 # Layer occupancy (ticks) -system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer18.occupancy 8240496 # Layer occupancy (ticks) -system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer20.occupancy 1330000 # Layer occupancy (ticks) -system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 2404108 # Layer occupancy (ticks) -system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer2.occupancy 2025089500 # Layer occupancy (ticks) -system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer4.occupancy 59993000 # Layer occupancy (ticks) -system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.cpu0.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu0.numCycles 10600620667 # number of cpu cycles simulated -system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 58326751 # Number of instructions committed -system.cpu0.committedOps 112208544 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 105142610 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu0.num_func_calls 999393 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 9968022 # number of instructions that are conditional controls -system.cpu0.num_int_insts 105142610 # number of integer instructions -system.cpu0.num_fp_insts 0 # number of float instructions -system.cpu0.num_int_register_reads 198014063 # number of times the integer registers were read -system.cpu0.num_int_register_writes 89363011 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 60260543 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 43624365 # number of times the CC registers were written -system.cpu0.num_mem_refs 12030075 # number of memory refs -system.cpu0.num_load_insts 7288332 # Number of load instructions -system.cpu0.num_store_insts 4741743 # Number of store instructions -system.cpu0.num_idle_cycles 10084773874.270475 # Number of idle cycles -system.cpu0.num_busy_cycles 515846792.729524 # Number of busy cycles -system.cpu0.not_idle_fraction 0.048662 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.951338 # Percentage of idle cycles -system.cpu0.Branches 11302630 # Number of branches fetched -system.cpu0.op_class::No_OpClass 132692 0.12% 0.12% # Class of executed instruction -system.cpu0.op_class::IntAlu 99906926 89.04% 89.15% # Class of executed instruction -system.cpu0.op_class::IntMult 87661 0.08% 89.23% # Class of executed instruction -system.cpu0.op_class::IntDiv 51849 0.05% 89.28% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 89.28% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 89.28% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 89.28% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 89.28% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 89.28% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 89.28% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 89.28% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 89.28% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 89.28% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 89.28% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 89.28% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 89.28% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 89.28% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 89.28% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 89.28% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 89.28% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 89.28% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 89.28% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 89.28% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 89.28% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 89.28% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 89.28% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 0 0.00% 89.28% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 89.28% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 89.28% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 89.28% # Class of executed instruction -system.cpu0.op_class::MemRead 7288332 6.50% 95.77% # Class of executed instruction -system.cpu0.op_class::MemWrite 4741743 4.23% 100.00% # Class of executed instruction -system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 112209203 # Class of executed instruction -system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu1.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu1.numCycles 10601483797 # number of cpu cycles simulated -system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 48465381 # Number of instructions committed -system.cpu1.committedOps 92539438 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 88910462 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu1.num_func_calls 1744945 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 8275238 # number of instructions that are conditional controls -system.cpu1.num_int_insts 88910462 # number of integer instructions -system.cpu1.num_fp_insts 0 # number of float instructions -system.cpu1.num_int_register_reads 172623141 # number of times the integer registers were read -system.cpu1.num_int_register_writes 73500216 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 51257305 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 33029139 # number of times the CC registers were written -system.cpu1.num_mem_refs 14403882 # number of memory refs -system.cpu1.num_load_insts 9271822 # Number of load instructions -system.cpu1.num_store_insts 5132060 # Number of store instructions -system.cpu1.num_idle_cycles 10262330670.974064 # Number of idle cycles -system.cpu1.num_busy_cycles 339153126.025936 # Number of busy cycles -system.cpu1.not_idle_fraction 0.031991 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.968009 # Percentage of idle cycles -system.cpu1.Branches 10623766 # Number of branches fetched -system.cpu1.op_class::No_OpClass 173936 0.19% 0.19% # Class of executed instruction -system.cpu1.op_class::IntAlu 77788975 84.06% 84.25% # Class of executed instruction -system.cpu1.op_class::IntMult 96916 0.10% 84.35% # Class of executed instruction -system.cpu1.op_class::IntDiv 76680 0.08% 84.44% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 84.44% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 84.44% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 84.44% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 84.44% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 84.44% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 84.44% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 84.44% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 84.44% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 84.44% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 84.44% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 84.44% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 84.44% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 84.44% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 84.44% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 84.44% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 84.44% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 84.44% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 84.44% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 84.44% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 84.44% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 84.44% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 84.44% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 0 0.00% 84.44% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 84.44% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 84.44% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 84.44% # Class of executed instruction -system.cpu1.op_class::MemRead 9271822 10.02% 94.45% # Class of executed instruction -system.cpu1.op_class::MemWrite 5132060 5.55% 100.00% # Class of executed instruction -system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 92540389 # Class of executed instruction -system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed system.ruby.network.routers0.throttle0.link_utilization 0.037422 system.ruby.network.routers0.throttle0.msg_count.Request_Control::2 42905 system.ruby.network.routers0.throttle0.msg_count.Response_Data::1 823544 @@ -1021,6 +1021,44 @@ system.ruby.Locked_RMW_Write.hit_latency_hist::mean 3 system.ruby.Locked_RMW_Write.hit_latency_hist::gmean 3.000000 system.ruby.Locked_RMW_Write.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 339542 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.Locked_RMW_Write.hit_latency_hist::total 339542 +system.ruby.Directory_Controller.Fetch 178413 0.00% 0.00% +system.ruby.Directory_Controller.Data 97701 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Data 178865 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Ack 142859 0.00% 0.00% +system.ruby.Directory_Controller.DMA_READ 814 0.00% 0.00% +system.ruby.Directory_Controller.DMA_WRITE 46736 0.00% 0.00% +system.ruby.Directory_Controller.CleanReplacement 15947 0.00% 0.00% +system.ruby.Directory_Controller.I.Fetch 178413 0.00% 0.00% +system.ruby.Directory_Controller.I.DMA_READ 452 0.00% 0.00% +system.ruby.Directory_Controller.I.DMA_WRITE 45158 0.00% 0.00% +system.ruby.Directory_Controller.ID.Memory_Data 452 0.00% 0.00% +system.ruby.Directory_Controller.ID_W.Memory_Ack 45158 0.00% 0.00% +system.ruby.Directory_Controller.M.Data 95761 0.00% 0.00% +system.ruby.Directory_Controller.M.DMA_READ 362 0.00% 0.00% +system.ruby.Directory_Controller.M.DMA_WRITE 1578 0.00% 0.00% +system.ruby.Directory_Controller.M.CleanReplacement 15947 0.00% 0.00% +system.ruby.Directory_Controller.IM.Memory_Data 178413 0.00% 0.00% +system.ruby.Directory_Controller.MI.Memory_Ack 95761 0.00% 0.00% +system.ruby.Directory_Controller.M_DRD.Data 362 0.00% 0.00% +system.ruby.Directory_Controller.M_DRDI.Memory_Ack 362 0.00% 0.00% +system.ruby.Directory_Controller.M_DWR.Data 1578 0.00% 0.00% +system.ruby.Directory_Controller.M_DWRI.Memory_Ack 1578 0.00% 0.00% +system.ruby.DMA_Controller.ReadRequest | 814 100.00% 100.00% | 0 0.00% 100.00% +system.ruby.DMA_Controller.ReadRequest::total 814 +system.ruby.DMA_Controller.WriteRequest | 46736 100.00% 100.00% | 0 0.00% 100.00% +system.ruby.DMA_Controller.WriteRequest::total 46736 +system.ruby.DMA_Controller.Data | 814 100.00% 100.00% | 0 0.00% 100.00% +system.ruby.DMA_Controller.Data::total 814 +system.ruby.DMA_Controller.Ack | 46736 100.00% 100.00% | 0 0.00% 100.00% +system.ruby.DMA_Controller.Ack::total 46736 +system.ruby.DMA_Controller.READY.ReadRequest | 814 100.00% 100.00% | 0 0.00% 100.00% +system.ruby.DMA_Controller.READY.ReadRequest::total 814 +system.ruby.DMA_Controller.READY.WriteRequest | 46736 100.00% 100.00% | 0 0.00% 100.00% +system.ruby.DMA_Controller.READY.WriteRequest::total 46736 +system.ruby.DMA_Controller.BUSY_RD.Data | 814 100.00% 100.00% | 0 0.00% 100.00% +system.ruby.DMA_Controller.BUSY_RD.Data::total 814 +system.ruby.DMA_Controller.BUSY_WR.Ack | 46736 100.00% 100.00% | 0 0.00% 100.00% +system.ruby.DMA_Controller.BUSY_WR.Ack::total 46736 system.ruby.L1Cache_Controller.Load | 6037097 40.47% 40.47% | 8881067 59.53% 100.00% system.ruby.L1Cache_Controller.Load::total 14918164 system.ruby.L1Cache_Controller.Ifetch | 67778726 53.56% 53.56% | 58760197 46.44% 100.00% @@ -1185,43 +1223,5 @@ system.ruby.L2Cache_Controller.MT_IIB.WB_Data_clean 2231 0.00% system.ruby.L2Cache_Controller.MT_IIB.Unblock 5 0.00% 0.00% system.ruby.L2Cache_Controller.MT_IB.WB_Data 5 0.00% 0.00% system.ruby.L2Cache_Controller.MT_SB.Unblock 25200 0.00% 0.00% -system.ruby.DMA_Controller.ReadRequest | 814 100.00% 100.00% | 0 0.00% 100.00% -system.ruby.DMA_Controller.ReadRequest::total 814 -system.ruby.DMA_Controller.WriteRequest | 46736 100.00% 100.00% | 0 0.00% 100.00% -system.ruby.DMA_Controller.WriteRequest::total 46736 -system.ruby.DMA_Controller.Data | 814 100.00% 100.00% | 0 0.00% 100.00% -system.ruby.DMA_Controller.Data::total 814 -system.ruby.DMA_Controller.Ack | 46736 100.00% 100.00% | 0 0.00% 100.00% -system.ruby.DMA_Controller.Ack::total 46736 -system.ruby.DMA_Controller.READY.ReadRequest | 814 100.00% 100.00% | 0 0.00% 100.00% -system.ruby.DMA_Controller.READY.ReadRequest::total 814 -system.ruby.DMA_Controller.READY.WriteRequest | 46736 100.00% 100.00% | 0 0.00% 100.00% -system.ruby.DMA_Controller.READY.WriteRequest::total 46736 -system.ruby.DMA_Controller.BUSY_RD.Data | 814 100.00% 100.00% | 0 0.00% 100.00% -system.ruby.DMA_Controller.BUSY_RD.Data::total 814 -system.ruby.DMA_Controller.BUSY_WR.Ack | 46736 100.00% 100.00% | 0 0.00% 100.00% -system.ruby.DMA_Controller.BUSY_WR.Ack::total 46736 -system.ruby.Directory_Controller.Fetch 178413 0.00% 0.00% -system.ruby.Directory_Controller.Data 97701 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Data 178865 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Ack 142859 0.00% 0.00% -system.ruby.Directory_Controller.DMA_READ 814 0.00% 0.00% -system.ruby.Directory_Controller.DMA_WRITE 46736 0.00% 0.00% -system.ruby.Directory_Controller.CleanReplacement 15947 0.00% 0.00% -system.ruby.Directory_Controller.I.Fetch 178413 0.00% 0.00% -system.ruby.Directory_Controller.I.DMA_READ 452 0.00% 0.00% -system.ruby.Directory_Controller.I.DMA_WRITE 45158 0.00% 0.00% -system.ruby.Directory_Controller.ID.Memory_Data 452 0.00% 0.00% -system.ruby.Directory_Controller.ID_W.Memory_Ack 45158 0.00% 0.00% -system.ruby.Directory_Controller.M.Data 95761 0.00% 0.00% -system.ruby.Directory_Controller.M.DMA_READ 362 0.00% 0.00% -system.ruby.Directory_Controller.M.DMA_WRITE 1578 0.00% 0.00% -system.ruby.Directory_Controller.M.CleanReplacement 15947 0.00% 0.00% -system.ruby.Directory_Controller.IM.Memory_Data 178413 0.00% 0.00% -system.ruby.Directory_Controller.MI.Memory_Ack 95761 0.00% 0.00% -system.ruby.Directory_Controller.M_DRD.Data 362 0.00% 0.00% -system.ruby.Directory_Controller.M_DRDI.Memory_Ack 362 0.00% 0.00% -system.ruby.Directory_Controller.M_DWR.Data 1578 0.00% 0.00% -system.ruby.Directory_Controller.M_DWRI.Memory_Ack 1578 0.00% 0.00% ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt index 33c10e980..443c7ed9f 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt @@ -4,13 +4,13 @@ sim_seconds 5.137752 # Nu sim_ticks 5137751757500 # Number of ticks simulated final_tick 5137751757500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 356493 # Simulator instruction rate (inst/s) -host_op_rate 708752 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 7521667943 # Simulator tick rate (ticks/s) -host_mem_usage 932888 # Number of bytes of host memory used -host_seconds 683.06 # Real time elapsed on the host -sim_insts 243506024 # Number of instructions simulated -sim_ops 484120523 # Number of ops (including micro ops) simulated +host_inst_rate 338442 # Simulator instruction rate (inst/s) +host_op_rate 672864 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 7140802707 # Simulator tick rate (ticks/s) +host_mem_usage 935656 # Number of bytes of host memory used +host_seconds 719.49 # Real time elapsed on the host +sim_insts 243506025 # Number of instructions simulated +sim_ops 484120527 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu0.itb.walker 256 # Number of bytes read from this memory @@ -306,10 +306,10 @@ system.physmem.readRowHitRate 79.65 # Ro system.physmem.writeRowHitRate 73.04 # Row buffer hit rate for writes system.physmem.avgGap 32320761.47 # Average gap between requests system.physmem.pageHitRate 76.54 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 4942660459000 # Time in different power states +system.physmem.memoryStateTime::IDLE 4942660463000 # Time in different power states system.physmem.memoryStateTime::REF 171560740000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 23528337250 # Time in different power states +system.physmem.memoryStateTime::ACT 23528333250 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states system.physmem.actEnergy::0 135618840 # Energy for activate commands per rank (pJ) system.physmem.actEnergy::1 145892880 # Energy for activate commands per rank (pJ) @@ -321,11 +321,11 @@ system.physmem.writeEnergy::0 231893280 # En system.physmem.writeEnergy::1 252266400 # Energy for write commands per rank (pJ) system.physmem.refreshEnergy::0 335572807440 # Energy for refresh commands per rank (pJ) system.physmem.refreshEnergy::1 335572807440 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 122729526630 # Energy for active background per rank (pJ) +system.physmem.actBackEnergy::0 122729524065 # Energy for active background per rank (pJ) system.physmem.actBackEnergy::1 123386936985 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 2974992234000 # Energy for precharge background per rank (pJ) +system.physmem.preBackEnergy::0 2974992236250 # Energy for precharge background per rank (pJ) system.physmem.preBackEnergy::1 2974415558250 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 3434046565365 # Total energy per rank (pJ) +system.physmem.totalEnergy::0 3434046565050 # Total energy per rank (pJ) system.physmem.totalEnergy::1 3434197896405 # Total energy per rank (pJ) system.physmem.averagePower::0 668.395092 # Core power per rank (mW) system.physmem.averagePower::1 668.424547 # Core power per rank (mW) @@ -395,9 +395,9 @@ system.cpu0.kern.inst.arm 0 # nu system.cpu0.kern.inst.quiesce 0 # number of quiesce instructions executed system.cpu0.dcache.tags.replacements 1637866 # number of replacements system.cpu0.dcache.tags.tagsinuse 511.999423 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 19673583 # Total number of references to valid blocks. +system.cpu0.dcache.tags.total_refs 19673585 # Total number of references to valid blocks. system.cpu0.dcache.tags.sampled_refs 1638378 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 12.007963 # Average number of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 12.007965 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 7549500 # Cycle when the warmup percentage was hit. system.cpu0.dcache.tags.occ_blocks::cpu0.data 126.297276 # Average occupied blocks per requestor system.cpu0.dcache.tags.occ_blocks::cpu1.data 280.648639 # Average occupied blocks per requestor @@ -411,28 +411,28 @@ system.cpu0.dcache.tags.age_task_id_blocks_1024::0 270 system.cpu0.dcache.tags.age_task_id_blocks_1024::1 221 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::2 21 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 88453869 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 88453869 # Number of data accesses +system.cpu0.dcache.tags.tag_accesses 88453877 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 88453877 # Number of data accesses system.cpu0.dcache.ReadReq_hits::cpu0.data 5010669 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 2623261 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 2623262 # number of ReadReq hits system.cpu0.dcache.ReadReq_hits::cpu2.data 3898583 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 11532513 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 11532514 # number of ReadReq hits system.cpu0.dcache.WriteReq_hits::cpu0.data 3480346 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 1810736 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 1810737 # number of WriteReq hits system.cpu0.dcache.WriteReq_hits::cpu2.data 2788314 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 8079396 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 8079397 # number of WriteReq hits system.cpu0.dcache.SoftPFReq_hits::cpu0.data 20263 # number of SoftPFReq hits system.cpu0.dcache.SoftPFReq_hits::cpu1.data 10587 # number of SoftPFReq hits system.cpu0.dcache.SoftPFReq_hits::cpu2.data 29029 # number of SoftPFReq hits system.cpu0.dcache.SoftPFReq_hits::total 59879 # number of SoftPFReq hits system.cpu0.dcache.demand_hits::cpu0.data 8491015 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 4433997 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu1.data 4433999 # number of demand (read+write) hits system.cpu0.dcache.demand_hits::cpu2.data 6686897 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 19611909 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 19611911 # number of demand (read+write) hits system.cpu0.dcache.overall_hits::cpu0.data 8511278 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 4444584 # number of overall hits +system.cpu0.dcache.overall_hits::cpu1.data 4444586 # number of overall hits system.cpu0.dcache.overall_hits::cpu2.data 6715926 # number of overall hits -system.cpu0.dcache.overall_hits::total 19671788 # number of overall hits +system.cpu0.dcache.overall_hits::total 19671790 # number of overall hits system.cpu0.dcache.ReadReq_misses::cpu0.data 362952 # number of ReadReq misses system.cpu0.dcache.ReadReq_misses::cpu1.data 164891 # number of ReadReq misses system.cpu0.dcache.ReadReq_misses::cpu2.data 772037 # number of ReadReq misses @@ -466,25 +466,25 @@ system.cpu0.dcache.overall_miss_latency::cpu1.data 4877372572 system.cpu0.dcache.overall_miss_latency::cpu2.data 15775545755 # number of overall miss cycles system.cpu0.dcache.overall_miss_latency::total 20652918327 # number of overall miss cycles system.cpu0.dcache.ReadReq_accesses::cpu0.data 5373621 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 2788152 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu1.data 2788153 # number of ReadReq accesses(hits+misses) system.cpu0.dcache.ReadReq_accesses::cpu2.data 4670620 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 12832393 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 12832394 # number of ReadReq accesses(hits+misses) system.cpu0.dcache.WriteReq_accesses::cpu0.data 3614306 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 1875865 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu1.data 1875866 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.WriteReq_accesses::cpu2.data 2914829 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 8405000 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 8405001 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 172200 # number of SoftPFReq accesses(hits+misses) system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 74881 # number of SoftPFReq accesses(hits+misses) system.cpu0.dcache.SoftPFReq_accesses::cpu2.data 219392 # number of SoftPFReq accesses(hits+misses) system.cpu0.dcache.SoftPFReq_accesses::total 466473 # number of SoftPFReq accesses(hits+misses) system.cpu0.dcache.demand_accesses::cpu0.data 8987927 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 4664017 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu1.data 4664019 # number of demand (read+write) accesses system.cpu0.dcache.demand_accesses::cpu2.data 7585449 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 21237393 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 21237395 # number of demand (read+write) accesses system.cpu0.dcache.overall_accesses::cpu0.data 9160127 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 4738898 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu1.data 4738900 # number of overall (read+write) accesses system.cpu0.dcache.overall_accesses::cpu2.data 7804841 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 21703866 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 21703868 # number of overall (read+write) accesses system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.067543 # miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.059140 # miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.165296 # miss rate for ReadReq accesses @@ -620,9 +620,9 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.icache.tags.replacements 866413 # number of replacements system.cpu0.icache.tags.tagsinuse 510.840210 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 130156157 # Total number of references to valid blocks. +system.cpu0.icache.tags.total_refs 130156159 # Total number of references to valid blocks. system.cpu0.icache.tags.sampled_refs 866925 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 150.135429 # Average number of references to valid blocks. +system.cpu0.icache.tags.avg_refs 150.135432 # Average number of references to valid blocks. system.cpu0.icache.tags.warmup_cycle 149014386250 # Cycle when the warmup percentage was hit. system.cpu0.icache.tags.occ_blocks::cpu0.inst 138.994027 # Average occupied blocks per requestor system.cpu0.icache.tags.occ_blocks::cpu1.inst 266.522548 # Average occupied blocks per requestor @@ -636,20 +636,20 @@ system.cpu0.icache.tags.age_task_id_blocks_1024::0 84 system.cpu0.icache.tags.age_task_id_blocks_1024::1 133 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::2 295 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 131912502 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 131912502 # Number of data accesses +system.cpu0.icache.tags.tag_accesses 131912504 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 131912504 # Number of data accesses system.cpu0.icache.ReadReq_hits::cpu0.inst 87639896 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 39531785 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 39531787 # number of ReadReq hits system.cpu0.icache.ReadReq_hits::cpu2.inst 2984476 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 130156157 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 130156159 # number of ReadReq hits system.cpu0.icache.demand_hits::cpu0.inst 87639896 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 39531785 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 39531787 # number of demand (read+write) hits system.cpu0.icache.demand_hits::cpu2.inst 2984476 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 130156157 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 130156159 # number of demand (read+write) hits system.cpu0.icache.overall_hits::cpu0.inst 87639896 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 39531785 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 39531787 # number of overall hits system.cpu0.icache.overall_hits::cpu2.inst 2984476 # number of overall hits -system.cpu0.icache.overall_hits::total 130156157 # number of overall hits +system.cpu0.icache.overall_hits::total 130156159 # number of overall hits system.cpu0.icache.ReadReq_misses::cpu0.inst 328528 # number of ReadReq misses system.cpu0.icache.ReadReq_misses::cpu1.inst 162109 # number of ReadReq misses system.cpu0.icache.ReadReq_misses::cpu2.inst 398768 # number of ReadReq misses @@ -672,17 +672,17 @@ system.cpu0.icache.overall_miss_latency::cpu1.inst 2245844750 system.cpu0.icache.overall_miss_latency::cpu2.inst 5606326194 # number of overall miss cycles system.cpu0.icache.overall_miss_latency::total 7852170944 # number of overall miss cycles system.cpu0.icache.ReadReq_accesses::cpu0.inst 87968424 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 39693894 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu1.inst 39693896 # number of ReadReq accesses(hits+misses) system.cpu0.icache.ReadReq_accesses::cpu2.inst 3383244 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 131045562 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 131045564 # number of ReadReq accesses(hits+misses) system.cpu0.icache.demand_accesses::cpu0.inst 87968424 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 39693894 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 39693896 # number of demand (read+write) accesses system.cpu0.icache.demand_accesses::cpu2.inst 3383244 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 131045562 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 131045564 # number of demand (read+write) accesses system.cpu0.icache.overall_accesses::cpu0.inst 87968424 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 39693894 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 39693896 # number of overall (read+write) accesses system.cpu0.icache.overall_accesses::cpu2.inst 3383244 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 131045562 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 131045564 # number of overall (read+write) accesses system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.003735 # miss rate for ReadReq accesses system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.004084 # miss rate for ReadReq accesses system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.117866 # miss rate for ReadReq accesses @@ -758,30 +758,30 @@ system.cpu0.icache.no_allocate_misses 0 # Nu system.cpu1.numCycles 2606022983 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 35939338 # Number of instructions committed -system.cpu1.committedOps 69774919 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 64844479 # Number of integer alu accesses +system.cpu1.committedInsts 35939339 # Number of instructions committed +system.cpu1.committedOps 69774923 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 64844483 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu1.num_func_calls 499287 # number of times a function call or return occured system.cpu1.num_conditional_control_insts 6580388 # number of instructions that are conditional controls -system.cpu1.num_int_insts 64844479 # number of integer instructions +system.cpu1.num_int_insts 64844483 # number of integer instructions system.cpu1.num_fp_insts 0 # number of float instructions -system.cpu1.num_int_register_reads 120226215 # number of times the integer registers were read -system.cpu1.num_int_register_writes 55826195 # number of times the integer registers were written +system.cpu1.num_int_register_reads 120226227 # number of times the integer registers were read +system.cpu1.num_int_register_writes 55826198 # number of times the integer registers were written system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 36586823 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 27309789 # number of times the CC registers were written -system.cpu1.num_mem_refs 4927871 # number of memory refs -system.cpu1.num_load_insts 3050338 # Number of load instructions -system.cpu1.num_store_insts 1877533 # Number of store instructions -system.cpu1.num_idle_cycles 2477290988.277639 # Number of idle cycles -system.cpu1.num_busy_cycles 128731994.722361 # Number of busy cycles +system.cpu1.num_cc_register_reads 36586824 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 27309791 # number of times the CC registers were written +system.cpu1.num_mem_refs 4927873 # number of memory refs +system.cpu1.num_load_insts 3050339 # Number of load instructions +system.cpu1.num_store_insts 1877534 # Number of store instructions +system.cpu1.num_idle_cycles 2477290986.248718 # Number of idle cycles +system.cpu1.num_busy_cycles 128731996.751282 # Number of busy cycles system.cpu1.not_idle_fraction 0.049398 # Percentage of non-idle cycles system.cpu1.idle_fraction 0.950602 # Percentage of idle cycles system.cpu1.Branches 7259898 # Number of branches fetched system.cpu1.op_class::No_OpClass 35461 0.05% 0.05% # Class of executed instruction -system.cpu1.op_class::IntAlu 64754695 92.80% 92.86% # Class of executed instruction +system.cpu1.op_class::IntAlu 64754697 92.80% 92.86% # Class of executed instruction system.cpu1.op_class::IntMult 31756 0.05% 92.90% # Class of executed instruction system.cpu1.op_class::IntDiv 25505 0.04% 92.94% # Class of executed instruction system.cpu1.op_class::FloatAdd 0 0.00% 92.94% # Class of executed instruction @@ -810,11 +810,11 @@ system.cpu1.op_class::SimdFloatMisc 0 0.00% 92.94% # Cl system.cpu1.op_class::SimdFloatMult 0 0.00% 92.94% # Class of executed instruction system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 92.94% # Class of executed instruction system.cpu1.op_class::SimdFloatSqrt 0 0.00% 92.94% # Class of executed instruction -system.cpu1.op_class::MemRead 3050338 4.37% 97.31% # Class of executed instruction -system.cpu1.op_class::MemWrite 1877533 2.69% 100.00% # Class of executed instruction +system.cpu1.op_class::MemRead 3050339 4.37% 97.31% # Class of executed instruction +system.cpu1.op_class::MemWrite 1877534 2.69% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 69775288 # Class of executed instruction +system.cpu1.op_class::total 69775292 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed system.cpu2.branchPred.lookups 29000272 # Number of BP lookups |