x86: Fix switching of CPUs

This patch prevents creation of interrupt controller for
cpus that will be switched in later

4 files changed, 28 insertions, 8 deletions

diff --git a/configs/common/CacheConfig.py b/configs/common/CacheConfig.py
index b9192fcbf..009cb1bf6 100644
--- a/configs/common/CacheConfig.py
+++ b/configs/common/CacheConfig.py
@@ -70,6 +70,7 @@ def config_cache(options, system):
                                                       PageTableWalkerCache())
             else:
                 system.cpu[i].addPrivateSplitL1Caches(icache, dcache)
+        system.cpu[i].createInterruptController()
         if options.l2cache:
             system.cpu[i].connectAllPorts(system.tol2bus, system.membus)
         else:
diff --git a/configs/example/fs.py b/configs/example/fs.py
index 4c2aeeefe..41b4a75ae 100644
--- a/configs/example/fs.py
+++ b/configs/example/fs.py
@@ -188,6 +188,7 @@ if len(bm) == 2:
         drive_sys = makeArmSystem(drive_mem_mode, options.machine_type, bm[1])
 
     drive_sys.cpu = DriveCPUClass(cpu_id=0)
+    drive_sys.cpu.createInterruptController()
     drive_sys.cpu.connectAllPorts(drive_sys.membus)
     if options.fastmem:
         drive_sys.cpu.physmem_port = drive_sys.physmem.port
diff --git a/src/cpu/BaseCPU.py b/src/cpu/BaseCPU.py
index 0bb2090ad..63f454968 100644
--- a/src/cpu/BaseCPU.py
+++ b/src/cpu/BaseCPU.py
@@ -100,33 +100,32 @@ class BaseCPU(MemObject):
         dtb = Param.SparcTLB(SparcTLB(), "Data TLB")
         itb = Param.SparcTLB(SparcTLB(), "Instruction TLB")
         interrupts = Param.SparcInterrupts(
-                SparcInterrupts(), "Interrupt Controller")
+                NULL, "Interrupt Controller")
     elif buildEnv['TARGET_ISA'] == 'alpha':
         dtb = Param.AlphaTLB(AlphaDTB(), "Data TLB")
         itb = Param.AlphaTLB(AlphaITB(), "Instruction TLB")
         interrupts = Param.AlphaInterrupts(
-                AlphaInterrupts(), "Interrupt Controller")
+                NULL, "Interrupt Controller")
     elif buildEnv['TARGET_ISA'] == 'x86':
         dtb = Param.X86TLB(X86TLB(), "Data TLB")
         itb = Param.X86TLB(X86TLB(), "Instruction TLB")
-        _localApic = X86LocalApic(pio_addr=0x2000000000000000)
-        interrupts = Param.X86LocalApic(_localApic, "Interrupt Controller")
+        interrupts = Param.X86LocalApic(NULL, "Interrupt Controller")
     elif buildEnv['TARGET_ISA'] == 'mips':
         dtb = Param.MipsTLB(MipsTLB(), "Data TLB")
         itb = Param.MipsTLB(MipsTLB(), "Instruction TLB")
         interrupts = Param.MipsInterrupts(
-                MipsInterrupts(), "Interrupt Controller")
+                NULL, "Interrupt Controller")
     elif buildEnv['TARGET_ISA'] == 'arm':
         dtb = Param.ArmTLB(ArmTLB(), "Data TLB")
         itb = Param.ArmTLB(ArmTLB(), "Instruction TLB")
         interrupts = Param.ArmInterrupts(
-                ArmInterrupts(), "Interrupt Controller")
+                NULL, "Interrupt Controller")
     elif buildEnv['TARGET_ISA'] == 'power':
         UnifiedTLB = Param.Bool(True, "Is this a Unified TLB?")
         dtb = Param.PowerTLB(PowerTLB(), "Data TLB")
         itb = Param.PowerTLB(PowerTLB(), "Instruction TLB")
         interrupts = Param.PowerInterrupts(
-                PowerInterrupts(), "Interrupt Controller")
+                NULL, "Interrupt Controller")
     else:
         print "Don't know what TLB to use for ISA %s" % \
             buildEnv['TARGET_ISA']
@@ -164,6 +163,25 @@ class BaseCPU(MemObject):
         _uncached_slave_ports += ["interrupts.pio", "interrupts.int_slave"]
         _uncached_master_ports += ["interrupts.int_master"]
 
+    def createInterruptController(self):
+        if buildEnv['TARGET_ISA'] == 'sparc':
+            self.interrupts = SparcInterrupts()
+        elif buildEnv['TARGET_ISA'] == 'alpha':
+            self.interrupts = AlphaInterrupts()
+        elif buildEnv['TARGET_ISA'] == 'x86':
+            _localApic = X86LocalApic(pio_addr=0x2000000000000000)
+            self.interrupts = _localApic
+        elif buildEnv['TARGET_ISA'] == 'mips':
+            self.interrupts = MipsInterrupts()
+        elif buildEnv['TARGET_ISA'] == 'arm':
+            self.interrupts = ArmInterrupts()
+        elif buildEnv['TARGET_ISA'] == 'power':
+            self.interrupts = PowerInterrupts()
+        else:
+            print "Don't know what Interrupt Controller to use for ISA %s" % \
+                buildEnv['TARGET_ISA']
+            sys.exit(1)
+
     def connectCachedPorts(self, bus):
         for p in self._cached_ports:
             exec('self.%s = bus.slave' % p)
diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index 7f24ee988..5dd2c3f3c 100644
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -653,7 +653,7 @@ FullO3CPU<Impl>::init()
     if (icachePort.isConnected())
         fetch.setIcache();
 
-    if (FullSystem) {
+    if (FullSystem && !params()->defer_registration) {
         for (ThreadID tid = 0; tid < numThreads; tid++) {
             ThreadContext *src_tc = threadContexts[tid];
             TheISA::initCPU(src_tc, src_tc->contextId());