diff options
| author | Kevin Lim <ktlim@umich.edu> | 2007-04-22 15:31:33 -0400 |
|---|---|---|
| committer | Kevin Lim <ktlim@umich.edu> | 2007-04-22 15:31:33 -0400 |
| commit | dbc1edd23deed386c952a77488a70f20485da711 (patch) | |
| tree | 9b220cc95d94064a5e001b2d65db5b064d8bc7cb | |
| parent | 088a0565836fc678fabef3c8662de79595bf20c2 (diff) | |
| parent | 67a37e83f3b69f832ae05c4612979c2c31bb4d3e (diff) | |
| download | gem5-dbc1edd23deed386c952a77488a70f20485da711.tar.xz | |
Merge ktlim@zizzer:/bk/newmem
into zamp.eecs.umich.edu:/z/ktlim2/clean/tmp/head
--HG--
extra : convert_revision : 05f738ab6cf1e8bd2940f4ce20602f1e8ad1af48
53 files changed, 1186 insertions, 1891 deletions
diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc index 2e6a43f9c..a775b66d5 100644 --- a/src/cpu/o3/cpu.cc +++ b/src/cpu/o3/cpu.cc @@ -384,25 +384,25 @@ FullO3CPU<Impl>::fullCPURegStats() .name(name() + ".cpi") .desc("CPI: Cycles Per Instruction") .precision(6); - cpi = simTicks / committedInsts; + cpi = numCycles / committedInsts; totalCpi .name(name() + ".cpi_total") .desc("CPI: Total CPI of All Threads") .precision(6); - totalCpi = simTicks / totalCommittedInsts; + totalCpi = numCycles / totalCommittedInsts; ipc .name(name() + ".ipc") .desc("IPC: Instructions Per Cycle") .precision(6); - ipc = committedInsts / simTicks; + ipc = committedInsts / numCycles; totalIpc .name(name() + ".ipc_total") .desc("IPC: Total IPC of All Threads") .precision(6); - totalIpc = totalCommittedInsts / simTicks; + totalIpc = totalCommittedInsts / numCycles; } diff --git a/tests/configs/o3-timing-mp.py b/tests/configs/o3-timing-mp.py index 331e2c569..1e414294c 100644 --- a/tests/configs/o3-timing-mp.py +++ b/tests/configs/o3-timing-mp.py @@ -1,4 +1,4 @@ -# Copyright (c) 2006 The Regents of The University of Michigan +# Copyright (c) 2006-2007 The Regents of The University of Michigan # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -73,6 +73,7 @@ for cpu in cpus: L1(size = '32kB', assoc = 4)) # connect cpu level-1 caches to shared level-2 cache cpu.connectMemPorts(system.toL2Bus) + cpu.clock = '2GHz' # connect memory to membus system.physmem.port = system.membus.port diff --git a/tests/configs/o3-timing.py b/tests/configs/o3-timing.py index 5600d9f22..d20a7e0c8 100644 --- a/tests/configs/o3-timing.py +++ b/tests/configs/o3-timing.py @@ -40,6 +40,7 @@ class MyCache(BaseCache): cpu = DerivO3CPU(cpu_id=0) cpu.addTwoLevelCacheHierarchy(MyCache(size = '128kB'), MyCache(size = '256kB'), MyCache(size = '2MB')) +cpu.clock = '2GHz' system = System(cpu = cpu, physmem = PhysicalMemory(), diff --git a/tests/configs/simple-atomic-mp.py b/tests/configs/simple-atomic-mp.py index f9e4e2767..e8000cd0a 100644 --- a/tests/configs/simple-atomic-mp.py +++ b/tests/configs/simple-atomic-mp.py @@ -1,4 +1,4 @@ -# Copyright (c) 2006 The Regents of The University of Michigan +# Copyright (c) 2006-2007 The Regents of The University of Michigan # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -72,6 +72,7 @@ for cpu in cpus: L1(size = '32kB', assoc = 4)) # connect cpu level-1 caches to shared level-2 cache cpu.connectMemPorts(system.toL2Bus) + cpu.clock = '2GHz' # connect memory to membus system.physmem.port = system.membus.port diff --git a/tests/configs/simple-atomic.py b/tests/configs/simple-atomic.py index a8a876994..cc303886b 100644 --- a/tests/configs/simple-atomic.py +++ b/tests/configs/simple-atomic.py @@ -1,4 +1,4 @@ -# Copyright (c) 2006 The Regents of The University of Michigan +# Copyright (c) 2006-2007 The Regents of The University of Michigan # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -34,5 +34,6 @@ system = System(cpu = AtomicSimpleCPU(cpu_id=0), membus = Bus()) system.physmem.port = system.membus.port system.cpu.connectMemPorts(system.membus) +system.cpu.clock = '2GHz' root = Root(system = system) diff --git a/tests/configs/simple-timing-mp.py b/tests/configs/simple-timing-mp.py index 0d99d8714..a263bcf57 100644 --- a/tests/configs/simple-timing-mp.py +++ b/tests/configs/simple-timing-mp.py @@ -1,4 +1,4 @@ -# Copyright (c) 2006 The Regents of The University of Michigan +# Copyright (c) 2006-2007 The Regents of The University of Michigan # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -72,6 +72,7 @@ for cpu in cpus: L1(size = '32kB', assoc = 4)) # connect cpu level-1 caches to shared level-2 cache cpu.connectMemPorts(system.toL2Bus) + cpu.clock = '2GHz' # connect memory to membus system.physmem.port = system.membus.port diff --git a/tests/configs/simple-timing.py b/tests/configs/simple-timing.py index d7d505a5a..6c4b8232f 100644 --- a/tests/configs/simple-timing.py +++ b/tests/configs/simple-timing.py @@ -1,4 +1,4 @@ -# Copyright (c) 2006 The Regents of The University of Michigan +# Copyright (c) 2006-2007 The Regents of The University of Michigan # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -44,5 +44,6 @@ system = System(cpu = cpu, membus = Bus()) system.physmem.port = system.membus.port cpu.connectMemPorts(system.membus) +cpu.clock = '2GHz' root = Root(system = system) diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini b/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini index 4d44e14fe..2a139492e 100644 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini @@ -23,7 +23,7 @@ activity=0 backComSize=5 choiceCtrBits=2 choicePredictorSize=8192 -clock=1 +clock=500 commitToDecodeDelay=1 commitToFetchDelay=1 commitToIEWDelay=1 diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.out b/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.out index 686c3b2f6..8155faf63 100644 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.out +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.out @@ -167,7 +167,7 @@ FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUL [system.cpu] type=DerivO3CPU -clock=1 +clock=500 phase=0 numThreads=1 cpu_id=0 diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt b/tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt index 988584966..86aa4129f 100644 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt @@ -1,40 +1,40 @@ ---------- Begin Simulation Statistics ---------- global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 615 # Number of BTB hits -global.BPredUnit.BTBLookups 1663 # Number of BTB lookups -global.BPredUnit.RASInCorrect 78 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 439 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 1180 # Number of conditional branches predicted -global.BPredUnit.lookups 2032 # Number of BP lookups -global.BPredUnit.usedRAS 304 # Number of times the RAS was used to get a target. -host_inst_rate 15105 # Simulator instruction rate (inst/s) -host_mem_usage 154056 # Number of bytes of host memory used -host_seconds 0.37 # Real time elapsed on the host -host_tick_rate 3572881 # Simulator tick rate (ticks/s) -memdepunit.memDep.conflictingLoads 24 # Number of conflicting loads. -memdepunit.memDep.conflictingStores 13 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 2144 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 1221 # Number of stores inserted to the mem dependence unit. +global.BPredUnit.BTBHits 606 # Number of BTB hits +global.BPredUnit.BTBLookups 1858 # Number of BTB lookups +global.BPredUnit.RASInCorrect 54 # Number of incorrect RAS predictions. +global.BPredUnit.condIncorrect 415 # Number of conditional branches incorrect +global.BPredUnit.condPredicted 1270 # Number of conditional branches predicted +global.BPredUnit.lookups 2195 # Number of BP lookups +global.BPredUnit.usedRAS 306 # Number of times the RAS was used to get a target. +host_inst_rate 22780 # Simulator instruction rate (inst/s) +host_mem_usage 154084 # Number of bytes of host memory used +host_seconds 0.25 # Real time elapsed on the host +host_tick_rate 14337041 # Simulator tick rate (ticks/s) +memdepunit.memDep.conflictingLoads 31 # Number of conflicting loads. +memdepunit.memDep.conflictingStores 138 # Number of conflicting stores. +memdepunit.memDep.insertedLoads 2061 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 1230 # Number of stores inserted to the mem dependence unit. sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5623 # Number of instructions simulated -sim_seconds 0.000001 # Number of seconds simulated -sim_ticks 1331134 # Number of ticks simulated +sim_seconds 0.000004 # Number of seconds simulated +sim_ticks 3543500 # Number of ticks simulated system.cpu.commit.COM:branches 862 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 101 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 121 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 30311 +system.cpu.commit.COM:committed_per_cycle.samples 6315 system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 27595 9103.96% - 1 1579 520.93% - 2 482 159.02% - 3 232 76.54% - 4 131 43.22% - 5 104 34.31% - 6 60 19.79% - 7 27 8.91% - 8 101 33.32% + 0 4255 6737.93% + 1 915 1448.93% + 2 408 646.08% + 3 162 256.53% + 4 140 221.69% + 5 91 144.10% + 6 121 191.61% + 7 102 161.52% + 8 121 191.61% system.cpu.commit.COM:committed_per_cycle.max_value 8 system.cpu.commit.COM:committed_per_cycle.end_dist @@ -43,69 +43,69 @@ system.cpu.commit.COM:loads 979 # Nu system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 1791 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 370 # The number of times a branch was mispredicted +system.cpu.commit.branchMispredicts 341 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 5640 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 4834 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 4458 # The number of squashed insts skipped by commit system.cpu.committedInsts 5623 # Number of Instructions Simulated system.cpu.committedInsts_total 5623 # Number of Instructions Simulated -system.cpu.cpi 236.730215 # CPI: Cycles Per Instruction -system.cpu.cpi_total 236.730215 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 1606 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 7256.076023 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7095.200000 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 1435 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 1240789 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.106476 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 171 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 71 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 709520 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.062267 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 100 # number of ReadReq MSHR misses +system.cpu.cpi 1.260537 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.260537 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 1516 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 4941.176471 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 4361.386139 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 1380 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 672000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.089710 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 136 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 35 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 440500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.066623 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 101 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 812 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 8026.070225 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 7200.452055 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 456 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 2857281 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.438424 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 356 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 283 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 525633 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.089901 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 73 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_avg_miss_latency 3265.671642 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 3819.444444 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 477 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 1094000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.412562 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 335 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 263 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 275000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.088670 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 72 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 10.930636 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 10.734104 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 2418 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 7776.223909 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 7139.612717 # average overall mshr miss latency -system.cpu.dcache.demand_hits 1891 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 4098070 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.217949 # miss rate for demand accesses -system.cpu.dcache.demand_misses 527 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 354 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 1235153 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.071547 # mshr miss rate for demand accesses +system.cpu.dcache.demand_accesses 2328 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 3749.469214 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 4135.838150 # average overall mshr miss latency +system.cpu.dcache.demand_hits 1857 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 1766000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.202320 # miss rate for demand accesses +system.cpu.dcache.demand_misses 471 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 298 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 715500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.074313 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 173 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 2418 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 7776.223909 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 7139.612717 # average overall mshr miss latency +system.cpu.dcache.overall_accesses 2328 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 3749.469214 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 4135.838150 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 1891 # number of overall hits -system.cpu.dcache.overall_miss_latency 4098070 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.217949 # miss rate for overall accesses -system.cpu.dcache.overall_misses 527 # number of overall misses -system.cpu.dcache.overall_mshr_hits 354 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 1235153 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.071547 # mshr miss rate for overall accesses +system.cpu.dcache.overall_hits 1857 # number of overall hits +system.cpu.dcache.overall_miss_latency 1766000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.202320 # miss rate for overall accesses +system.cpu.dcache.overall_misses 471 # number of overall misses +system.cpu.dcache.overall_mshr_hits 298 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 715500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.074313 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 173 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses @@ -121,89 +121,89 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 173 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 102.478227 # Cycle average of tags in use -system.cpu.dcache.total_refs 1891 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 111.557376 # Cycle average of tags in use +system.cpu.dcache.total_refs 1857 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 17469 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 70 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 169 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 11765 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 10684 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 2098 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 907 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 200 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 61 # Number of cycles decode is unblocking -system.cpu.fetch.Branches 2032 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 1710 # Number of cache lines fetched -system.cpu.fetch.Cycles 3962 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 268 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 12603 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 472 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.065089 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 1710 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 919 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 0.403696 # Number of inst fetches per cycle +system.cpu.decode.DECODE:BlockedCycles 381 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 81 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 172 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 12164 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 3741 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 2151 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 772 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 244 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 43 # Number of cycles decode is unblocking +system.cpu.fetch.Branches 2195 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 1616 # Number of cache lines fetched +system.cpu.fetch.Cycles 3951 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 151 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 13452 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 448 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.309678 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 1616 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 912 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.897856 # Number of inst fetches per cycle system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 31219 +system.cpu.fetch.rateDist.samples 7088 system.cpu.fetch.rateDist.min_value 0 - 0 28979 9282.49% - 1 197 63.10% - 2 198 63.42% - 3 167 53.49% - 4 197 63.10% - 5 187 59.90% - 6 222 71.11% - 7 122 39.08% - 8 950 304.30% + 0 4755 6708.52% + 1 197 277.93% + 2 177 249.72% + 3 163 229.97% + 4 234 330.14% + 5 170 239.84% + 6 198 279.35% + 7 114 160.84% + 8 1080 1523.70% system.cpu.fetch.rateDist.max_value 8 system.cpu.fetch.rateDist.end_dist -system.cpu.icache.ReadReq_accesses 1710 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 5139.251163 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 4349.151613 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 1280 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 2209878 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.251462 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 430 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 120 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 1348237 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.181287 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 310 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_accesses 1616 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 4068.597561 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 3148.089172 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 1288 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 1334500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.202970 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 328 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 14 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 988500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.194307 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 314 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_refs 4.129032 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 4.101911 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 1710 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 5139.251163 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 4349.151613 # average overall mshr miss latency -system.cpu.icache.demand_hits 1280 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 2209878 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.251462 # miss rate for demand accesses -system.cpu.icache.demand_misses 430 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 120 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 1348237 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.181287 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 310 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_accesses 1616 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 4068.597561 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 3148.089172 # average overall mshr miss latency +system.cpu.icache.demand_hits 1288 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 1334500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.202970 # miss rate for demand accesses +system.cpu.icache.demand_misses 328 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 14 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 988500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.194307 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 314 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 1710 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 5139.251163 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 4349.151613 # average overall mshr miss latency +system.cpu.icache.overall_accesses 1616 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 4068.597561 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 3148.089172 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 1280 # number of overall hits -system.cpu.icache.overall_miss_latency 2209878 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.251462 # miss rate for overall accesses -system.cpu.icache.overall_misses 430 # number of overall misses -system.cpu.icache.overall_mshr_hits 120 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 1348237 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.181287 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 310 # number of overall MSHR misses +system.cpu.icache.overall_hits 1288 # number of overall hits +system.cpu.icache.overall_miss_latency 1334500 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.202970 # miss rate for overall accesses +system.cpu.icache.overall_misses 328 # number of overall misses +system.cpu.icache.overall_mshr_hits 14 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 988500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.194307 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 314 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -216,61 +216,60 @@ system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.sampled_refs 310 # Sample count of references to valid blocks. +system.cpu.icache.sampled_refs 314 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 148.421347 # Cycle average of tags in use -system.cpu.icache.total_refs 1280 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 166.037293 # Cycle average of tags in use +system.cpu.icache.total_refs 1288 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 1299916 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 1267 # Number of branches executed -system.cpu.iew.EXEC:nop 48 # number of nop insts executed -system.cpu.iew.EXEC:rate 0.270476 # Inst execution rate -system.cpu.iew.EXEC:refs 2748 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 1031 # Number of stores executed +system.cpu.iew.EXEC:branches 1203 # Number of branches executed +system.cpu.iew.EXEC:nop 41 # number of nop insts executed +system.cpu.iew.EXEC:rate 1.125423 # Inst execution rate +system.cpu.iew.EXEC:refs 2585 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 989 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 5354 # num instructions consuming a value -system.cpu.iew.WB:count 8160 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.757378 # average fanout of values written-back +system.cpu.iew.WB:consumers 5598 # num instructions consuming a value +system.cpu.iew.WB:count 7767 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.741872 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 4055 # num instructions producing a value -system.cpu.iew.WB:rate 0.261379 # insts written-back per cycle -system.cpu.iew.WB:sent 8228 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 404 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 7230 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 2144 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 24 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 179 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 1221 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 10469 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 1717 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 299 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 8444 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 10 # Number of times the IQ has become full, causing a stall +system.cpu.iew.WB:producers 4153 # num instructions producing a value +system.cpu.iew.WB:rate 1.095796 # insts written-back per cycle +system.cpu.iew.WB:sent 7849 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 393 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 3 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 2061 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 23 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 240 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 1230 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 10115 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 1596 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 554 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 7977 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 1 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 907 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 39 # Number of cycles IEW is unblocking +system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 772 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 81 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.forwLoads 57 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 60 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.memOrderViolation 68 # Number of memory ordering violations system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 1165 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 409 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 60 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 279 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 125 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 0.004224 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.004224 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0 8743 # Type of FU issued +system.cpu.iew.lsq.thread.0.squashedLoads 1082 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 418 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 68 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 284 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 109 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 0.793313 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.793313 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0 8531 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist (null) 2 0.02% # Type of FU issued - IntAlu 5868 67.12% # Type of FU issued + IntAlu 5713 66.97% # Type of FU issued IntMult 1 0.01% # Type of FU issued IntDiv 0 0.00% # Type of FU issued FloatAdd 2 0.02% # Type of FU issued @@ -279,16 +278,16 @@ system.cpu.iq.ISSUE:FU_type_0.start_dist FloatMult 0 0.00% # Type of FU issued FloatDiv 0 0.00% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued - MemRead 1809 20.69% # Type of FU issued - MemWrite 1061 12.14% # Type of FU issued + MemRead 1773 20.78% # Type of FU issued + MemWrite 1040 12.19% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.end_dist -system.cpu.iq.ISSUE:fu_busy_cnt 87 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.009951 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_cnt 128 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.015004 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full.start_dist (null) 0 0.00% # attempts to use FU when none available - IntAlu 1 1.15% # attempts to use FU when none available + IntAlu 7 5.47% # attempts to use FU when none available IntMult 0 0.00% # attempts to use FU when none available IntDiv 0 0.00% # attempts to use FU when none available FloatAdd 0 0.00% # attempts to use FU when none available @@ -297,43 +296,43 @@ system.cpu.iq.ISSUE:fu_full.start_dist FloatMult 0 0.00% # attempts to use FU when none available FloatDiv 0 0.00% # attempts to use FU when none available FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 54 62.07% # attempts to use FU when none available - MemWrite 32 36.78% # attempts to use FU when none available + MemRead 78 60.94% # attempts to use FU when none available + MemWrite 43 33.59% # attempts to use FU when none available IprAccess 0 0.00% # attempts to use FU when none available InstPrefetch 0 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full.end_dist system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 31219 +system.cpu.iq.ISSUE:issued_per_cycle.samples 7088 system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 27042 8662.03% - 1 1845 590.99% - 2 1151 368.69% - 3 572 183.22% - 4 318 101.86% - 5 182 58.30% - 6 76 24.34% - 7 22 7.05% - 8 11 3.52% + 0 4068 5739.28% + 1 771 1087.75% + 2 763 1076.47% + 3 485 684.26% + 4 504 711.06% + 5 295 416.20% + 6 144 203.16% + 7 40 56.43% + 8 18 25.40% system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 system.cpu.iq.ISSUE:issued_per_cycle.end_dist -system.cpu.iq.ISSUE:rate 0.280054 # Inst issue rate -system.cpu.iq.iqInstsAdded 10397 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 8743 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 24 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 4378 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 68 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 7 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 2580 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.l2cache.ReadReq_accesses 481 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 4807.594595 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2390.114345 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_miss_latency 2312453 # number of ReadReq miss cycles +system.cpu.iq.ISSUE:rate 1.203584 # Inst issue rate +system.cpu.iq.iqInstsAdded 10051 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 8531 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 23 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 4086 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 39 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 6 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 2494 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.l2cache.ReadReq_accesses 485 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 3318.556701 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1934.377320 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_miss_latency 1609500 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 481 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1149645 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_misses 485 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 938173 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 481 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses 485 # number of ReadReq MSHR misses system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks. @@ -342,32 +341,32 @@ system.cpu.l2cache.blocked_no_targets 0 # nu system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 481 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 4807.594595 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 2390.114345 # average overall mshr miss latency +system.cpu.l2cache.demand_accesses 485 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 3318.556701 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 1934.377320 # average overall mshr miss latency system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 2312453 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 1609500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 481 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses 485 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 1149645 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 938173 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 481 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses 485 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 481 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 4807.594595 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 2390.114345 # average overall mshr miss latency +system.cpu.l2cache.overall_accesses 485 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 3318.556701 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 1934.377320 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 0 # number of overall hits -system.cpu.l2cache.overall_miss_latency 2312453 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 1609500 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 481 # number of overall misses +system.cpu.l2cache.overall_misses 485 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 1149645 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 938173 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 481 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses 485 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -380,31 +379,28 @@ system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 481 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 485 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 250.999286 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 277.255174 # Cycle average of tags in use system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.numCycles 31219 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 7810 # Number of cycles rename is blocking +system.cpu.numCycles 7088 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 3 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 4051 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 2 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 10837 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 465 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:ROBFullEvents 6 # Number of times rename has blocked due to ROB full -system.cpu.rename.RENAME:RenameLookups 14384 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 11306 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 8499 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 2010 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 907 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 491 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 4448 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 9164 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:IdleCycles 3933 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 65 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:RenameLookups 14798 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 11577 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 8671 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 2005 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 772 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 115 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 4620 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 260 # count of cycles rename stalled for serializing inst system.cpu.rename.RENAME:serializingInsts 27 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 825 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 21 # count of temporary serializing insts renamed -system.cpu.timesIdled 365 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.rename.RENAME:skidInsts 396 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 22 # count of temporary serializing insts renamed system.cpu.workload.PROG:num_syscalls 17 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stderr b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stderr index 8053728f7..f33d007a7 100644 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stderr +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stderr @@ -1,3 +1,2 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7001 warn: Entering event queue @ 0. Starting simulation... warn: Increasing stack size by one page. diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout index ef47b0265..eeba3846f 100644 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout @@ -6,9 +6,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Mar 30 2007 13:12:55 -M5 started Fri Mar 30 13:13:02 2007 +M5 compiled Apr 21 2007 21:50:58 +M5 started Sat Apr 21 21:51:06 2007 M5 executing on zamp.eecs.umich.edu command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/o3-timing tests/run.py quick/00.hello/alpha/linux/o3-timing Global frequency set at 1000000000000 ticks per second -Exiting @ tick 1331134 because target called exit() +Exiting @ tick 3543500 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini index 79673d775..26009ca4f 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini +++ b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini @@ -1,51 +1,7 @@ [root] type=Root children=system -checkpoint= -clock=1000000000000 -max_tick=0 -output_file=cout -progress_interval=0 - -[debug] -break_cycles= - -[exetrace] -intel_format=false -legion_lockstep=false -pc_symbol=true -print_cpseq=false -print_cycle=true -print_data=true -print_effaddr=true -print_fetchseq=false -print_iregs=false -print_opclass=true -print_thread=true -speculative=true -trace_system=client - -[serialize] -count=10 -cycle=0 -dir=cpt.%012d -period=0 - -[stats] -descriptions=true -dump_cycle=0 -dump_period=0 -dump_reset=false -ignore_events= -mysql_db= -mysql_host= -mysql_password= -mysql_user= -project_name=test -simulation_name=test -simulation_sample=0 -text_compat=true -text_file=m5stats.txt +dummy=0 [system] type=System @@ -56,7 +12,7 @@ physmem=system.physmem [system.cpu] type=AtomicSimpleCPU children=workload -clock=1 +clock=500 cpu_id=0 defer_registration=false function_trace=false @@ -65,6 +21,7 @@ max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 +phase=0 progress_interval=0 simulate_stalls=false system=system @@ -76,6 +33,7 @@ icache_port=system.membus.port[1] [system.cpu.workload] type=LiveProcess cmd=hello +cwd= egid=100 env= euid=100 @@ -101,14 +59,6 @@ type=PhysicalMemory file= latency=1 range=0:134217727 +zero=false port=system.membus.port[0] -[trace] -bufsize=0 -cycle=0 -dump_on_exit=false -file=cout -flags= -ignore= -start=0 - diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.out b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.out index 31870d5f3..f8e40871a 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.out +++ b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.out @@ -1,15 +1,13 @@ [root] type=Root -clock=1000000000000 -max_tick=0 -progress_interval=0 -output_file=cout +dummy=0 [system.physmem] type=PhysicalMemory file= range=[0,134217727] latency=1 +zero=false [system] type=System @@ -30,6 +28,7 @@ executable=tests/test-progs/hello/bin/alpha/linux/hello input=cin output=cout env= +cwd= system=system uid=100 euid=100 @@ -48,61 +47,11 @@ progress_interval=0 system=system cpu_id=0 workload=system.cpu.workload -clock=1 +clock=500 +phase=0 defer_registration=false width=1 function_trace=false function_trace_start=0 simulate_stalls=false -[trace] -flags= -start=0 -cycle=0 -bufsize=0 -file=cout -dump_on_exit=false -ignore= - -[stats] -descriptions=true -project_name=test -simulation_name=test -simulation_sample=0 -text_file=m5stats.txt -text_compat=true -mysql_db= -mysql_user= -mysql_password= -mysql_host= -events_start=-1 -dump_reset=false -dump_cycle=0 -dump_period=0 -ignore_events= - -[random] -seed=1 - -[exetrace] -speculative=true -print_cycle=true -print_opclass=true -print_thread=true -print_effaddr=true -print_data=true -print_iregs=false -print_fetchseq=false -print_cpseq=false -print_reg_delta=false -pc_symbol=true -intel_format=false -legion_lockstep=false -trace_system=client - -[debug] -break_cycles= - -[statsreset] -reset_cycle=0 - diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/m5stats.txt b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/m5stats.txt index 96973fa46..0f64469e9 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/m5stats.txt +++ b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/m5stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 684709 # Simulator instruction rate (inst/s) -host_mem_usage 148256 # Number of bytes of host memory used -host_seconds 0.01 # Real time elapsed on the host -host_tick_rate 650634 # Simulator tick rate (ticks/s) +host_inst_rate 357156 # Simulator instruction rate (inst/s) +host_mem_usage 148180 # Number of bytes of host memory used +host_seconds 0.02 # Real time elapsed on the host +host_tick_rate 171417285 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5642 # Number of instructions simulated -sim_seconds 0.000000 # Number of seconds simulated -sim_ticks 5641 # Number of ticks simulated +sim_seconds 0.000003 # Number of seconds simulated +sim_ticks 2820500 # Number of ticks simulated system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 5642 # number of cpu cycles simulated diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stderr b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stderr index 87866a2a5..f33d007a7 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stderr +++ b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stderr @@ -1 +1,2 @@ warn: Entering event queue @ 0. Starting simulation... +warn: Increasing stack size by one page. diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stdout b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stdout index c451577a3..5acc408a3 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stdout +++ b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stdout @@ -6,8 +6,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 3 2006 17:10:27 -M5 started Fri Nov 3 17:10:43 2006 -M5 executing on zizzer.eecs.umich.edu -command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/simple-atomic tests/run.py quick/00.hello/alpha/linux/simple-atomic -Exiting @ tick 5641 because target called exit() +M5 compiled Apr 21 2007 21:50:58 +M5 started Sat Apr 21 21:51:08 2007 +M5 executing on zamp.eecs.umich.edu +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-atomic tests/run.py quick/00.hello/alpha/linux/simple-atomic +Global frequency set at 1000000000000 ticks per second +Exiting @ tick 2820500 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini index 13004a42a..025531062 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini @@ -1,51 +1,7 @@ [root] type=Root children=system -checkpoint= -clock=1000000000000 -max_tick=0 -output_file=cout -progress_interval=0 - -[debug] -break_cycles= - -[exetrace] -intel_format=false -legion_lockstep=false -pc_symbol=true -print_cpseq=false -print_cycle=true -print_data=true -print_effaddr=true -print_fetchseq=false -print_iregs=false -print_opclass=true -print_thread=true -speculative=true -trace_system=client - -[serialize] -count=10 -cycle=0 -dir=cpt.%012d -period=0 - -[stats] -descriptions=true -dump_cycle=0 -dump_period=0 -dump_reset=false -ignore_events= -mysql_db= -mysql_host= -mysql_password= -mysql_user= -project_name=test -simulation_name=test -simulation_sample=0 -text_compat=true -text_file=m5stats.txt +dummy=0 [system] type=System @@ -56,7 +12,7 @@ physmem=system.physmem [system.cpu] type=TimingSimpleCPU children=dcache icache l2cache toL2Bus workload -clock=1 +clock=500 cpu_id=0 defer_registration=false function_trace=false @@ -65,6 +21,7 @@ max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 +phase=0 progress_interval=0 system=system workload=system.cpu.workload @@ -199,6 +156,7 @@ port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cp [system.cpu.workload] type=LiveProcess cmd=hello +cwd= egid=100 env= euid=100 @@ -224,14 +182,6 @@ type=PhysicalMemory file= latency=1 range=0:134217727 +zero=false port=system.membus.port[0] -[trace] -bufsize=0 -cycle=0 -dump_on_exit=false -file=cout -flags= -ignore= -start=0 - diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.out b/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.out index 58b3f5296..fa1054e9e 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.out +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.out @@ -1,15 +1,13 @@ [root] type=Root -clock=1000000000000 -max_tick=0 -progress_interval=0 -output_file=cout +dummy=0 [system.physmem] type=PhysicalMemory file= range=[0,134217727] latency=1 +zero=false [system] type=System @@ -30,6 +28,7 @@ executable=tests/test-progs/hello/bin/alpha/linux/hello input=cin output=cout env= +cwd= system=system uid=100 euid=100 @@ -48,7 +47,8 @@ progress_interval=0 system=system cpu_id=0 workload=system.cpu.workload -clock=1 +clock=500 +phase=0 defer_registration=false // width not specified function_trace=false @@ -176,54 +176,3 @@ prefetch_use_cpu_id=true prefetch_data_accesses_only=false hit_latency=1 -[trace] -flags= -start=0 -cycle=0 -bufsize=0 -file=cout -dump_on_exit=false -ignore= - -[stats] -descriptions=true -project_name=test -simulation_name=test -simulation_sample=0 -text_file=m5stats.txt -text_compat=true -mysql_db= -mysql_user= -mysql_password= -mysql_host= -events_start=-1 -dump_reset=false -dump_cycle=0 -dump_period=0 -ignore_events= - -[random] -seed=1 - -[exetrace] -speculative=true -print_cycle=true -print_opclass=true -print_thread=true -print_effaddr=true -print_data=true -print_iregs=false -print_fetchseq=false -print_cpseq=false -print_reg_delta=false -pc_symbol=true -intel_format=false -legion_lockstep=false -trace_system=client - -[debug] -break_cycles= - -[statsreset] -reset_cycle=0 - diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt b/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt index 68f6bcca4..afdac247d 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt @@ -1,31 +1,31 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 167195 # Simulator instruction rate (inst/s) -host_mem_usage 179768 # Number of bytes of host memory used +host_inst_rate 215467 # Simulator instruction rate (inst/s) +host_mem_usage 153656 # Number of bytes of host memory used host_seconds 0.03 # Real time elapsed on the host -host_tick_rate 51710933 # Simulator tick rate (ticks/s) +host_tick_rate 193088667 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5642 # Number of instructions simulated -sim_seconds 0.000002 # Number of seconds simulated -sim_ticks 1767066 # Number of ticks simulated +sim_seconds 0.000005 # Number of seconds simulated +sim_ticks 5135000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 979 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 3990.760870 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2990.760870 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 3750 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2750 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 887 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 367150 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 345000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.093973 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 92 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 275150 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 253000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.093973 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 92 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 812 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 3977.109589 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2977.109589 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 3582.191781 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2582.191781 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 739 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 290329 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 261500 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.089901 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 73 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 217329 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 188500 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.089901 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 73 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -37,29 +37,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 1791 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 3984.721212 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 2984.721212 # average overall mshr miss latency +system.cpu.dcache.demand_avg_miss_latency 3675.757576 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 2675.757576 # average overall mshr miss latency system.cpu.dcache.demand_hits 1626 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 657479 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency 606500 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.092127 # miss rate for demand accesses system.cpu.dcache.demand_misses 165 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 492479 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 441500 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.092127 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 165 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.overall_accesses 1791 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 3984.721212 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 2984.721212 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 3675.757576 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 2675.757576 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 1626 # number of overall hits -system.cpu.dcache.overall_miss_latency 657479 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency 606500 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.092127 # miss rate for overall accesses system.cpu.dcache.overall_misses 165 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 492479 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 441500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.092127 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 165 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -76,18 +76,18 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 165 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 97.858233 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 105.359700 # Cycle average of tags in use system.cpu.dcache.total_refs 1626 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks system.cpu.icache.ReadReq_accesses 5643 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 3980.490975 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 2980.490975 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_miss_latency 3729.241877 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 2729.241877 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_hits 5366 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 1102596 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency 1033000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.049087 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 277 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 825596 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 756000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.049087 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 277 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -99,29 +99,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 5643 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 3980.490975 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 2980.490975 # average overall mshr miss latency +system.cpu.icache.demand_avg_miss_latency 3729.241877 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 2729.241877 # average overall mshr miss latency system.cpu.icache.demand_hits 5366 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 1102596 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency 1033000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.049087 # miss rate for demand accesses system.cpu.icache.demand_misses 277 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 825596 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 756000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.049087 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 277 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.overall_accesses 5643 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 3980.490975 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 2980.490975 # average overall mshr miss latency +system.cpu.icache.overall_avg_miss_latency 3729.241877 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 2729.241877 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.icache.overall_hits 5366 # number of overall hits -system.cpu.icache.overall_miss_latency 1102596 # number of overall miss cycles +system.cpu.icache.overall_miss_latency 1033000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.049087 # miss rate for overall accesses system.cpu.icache.overall_misses 277 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 825596 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 756000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.049087 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 277 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -138,18 +138,18 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 0 # number of replacements system.cpu.icache.sampled_refs 277 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 122.802112 # Cycle average of tags in use +system.cpu.icache.tagsinuse 131.245403 # Cycle average of tags in use system.cpu.icache.total_refs 5366 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.l2cache.ReadReq_accesses 441 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 2984.340136 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1983.340136 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_miss_latency 1316094 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_avg_miss_latency 2712.018141 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1711.018141 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_miss_latency 1196000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 441 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 874653 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 754559 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 441 # number of ReadReq MSHR misses system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -161,29 +161,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 # system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 441 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 2984.340136 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 1983.340136 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_miss_latency 2712.018141 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 1711.018141 # average overall mshr miss latency system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 1316094 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 1196000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses system.cpu.l2cache.demand_misses 441 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 874653 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 754559 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 441 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.overall_accesses 441 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 2984.340136 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 1983.340136 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_miss_latency 2712.018141 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 1711.018141 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 0 # number of overall hits -system.cpu.l2cache.overall_miss_latency 1316094 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 1196000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses system.cpu.l2cache.overall_misses 441 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 874653 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 754559 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 441 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -200,12 +200,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.sampled_refs 441 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 220.802916 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 236.577060 # Cycle average of tags in use system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 1767066 # number of cpu cycles simulated +system.cpu.numCycles 5135000 # number of cpu cycles simulated system.cpu.num_insts 5642 # Number of instructions executed system.cpu.num_refs 1792 # Number of memory references system.cpu.workload.PROG:num_syscalls 17 # Number of system calls diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/stderr b/tests/quick/00.hello/ref/alpha/linux/simple-timing/stderr index 87866a2a5..f33d007a7 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/stderr +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/stderr @@ -1 +1,2 @@ warn: Entering event queue @ 0. Starting simulation... +warn: Increasing stack size by one page. diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout b/tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout index 61f79d88f..a79e87c66 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout @@ -6,8 +6,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 3 2006 17:10:27 -M5 started Fri Nov 3 17:10:44 2006 -M5 executing on zizzer.eecs.umich.edu -command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/simple-timing tests/run.py quick/00.hello/alpha/linux/simple-timing -Exiting @ tick 1767066 because target called exit() +M5 compiled Apr 21 2007 21:50:58 +M5 started Sat Apr 21 21:51:09 2007 +M5 executing on zamp.eecs.umich.edu +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-timing tests/run.py quick/00.hello/alpha/linux/simple-timing +Global frequency set at 1000000000000 ticks per second +Exiting @ tick 5135000 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini index bd6b9bcdc..1e3b2746e 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini @@ -23,7 +23,7 @@ activity=0 backComSize=5 choiceCtrBits=2 choicePredictorSize=8192 -clock=1 +clock=500 commitToDecodeDelay=1 commitToFetchDelay=1 commitToIEWDelay=1 diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.out b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.out index 58df46dcb..5df02e4ff 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.out +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.out @@ -167,7 +167,7 @@ FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUL [system.cpu] type=DerivO3CPU -clock=1 +clock=500 phase=0 numThreads=1 cpu_id=0 diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt index 1919ca3fe..d3074bcf9 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt @@ -1,40 +1,40 @@ ---------- Begin Simulation Statistics ---------- global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 187 # Number of BTB hits -global.BPredUnit.BTBLookups 653 # Number of BTB lookups -global.BPredUnit.RASInCorrect 41 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 217 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 426 # Number of conditional branches predicted -global.BPredUnit.lookups 832 # Number of BP lookups -global.BPredUnit.usedRAS 170 # Number of times the RAS was used to get a target. -host_inst_rate 19984 # Simulator instruction rate (inst/s) -host_mem_usage 153584 # Number of bytes of host memory used -host_seconds 0.12 # Real time elapsed on the host -host_tick_rate 6228839 # Simulator tick rate (ticks/s) +global.BPredUnit.BTBHits 162 # Number of BTB hits +global.BPredUnit.BTBLookups 671 # Number of BTB lookups +global.BPredUnit.RASInCorrect 36 # Number of incorrect RAS predictions. +global.BPredUnit.condIncorrect 220 # Number of conditional branches incorrect +global.BPredUnit.condPredicted 427 # Number of conditional branches predicted +global.BPredUnit.lookups 860 # Number of BP lookups +global.BPredUnit.usedRAS 174 # Number of times the RAS was used to get a target. +host_inst_rate 31252 # Simulator instruction rate (inst/s) +host_mem_usage 153592 # Number of bytes of host memory used +host_seconds 0.08 # Real time elapsed on the host +host_tick_rate 21107113 # Simulator tick rate (ticks/s) memdepunit.memDep.conflictingLoads 9 # Number of conflicting loads. -memdepunit.memDep.conflictingStores 8 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 701 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 382 # Number of stores inserted to the mem dependence unit. +memdepunit.memDep.conflictingStores 7 # Number of conflicting stores. +memdepunit.memDep.insertedLoads 692 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 385 # Number of stores inserted to the mem dependence unit. sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 2387 # Number of instructions simulated -sim_seconds 0.000001 # Number of seconds simulated -sim_ticks 746028 # Number of ticks simulated +sim_seconds 0.000002 # Number of seconds simulated +sim_ticks 1619000 # Number of ticks simulated system.cpu.commit.COM:branches 396 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 52 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 59 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 29809 +system.cpu.commit.COM:committed_per_cycle.samples 2977 system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 28885 9690.03% - 1 239 80.18% - 2 325 109.03% - 3 129 43.28% - 4 78 26.17% - 5 53 17.78% - 6 29 9.73% - 7 19 6.37% - 8 52 17.44% + 0 2102 7060.80% + 1 212 712.13% + 2 297 997.65% + 3 114 382.94% + 4 83 278.80% + 5 58 194.83% + 6 30 100.77% + 7 22 73.90% + 8 59 198.19% system.cpu.commit.COM:committed_per_cycle.max_value 8 system.cpu.commit.COM:committed_per_cycle.end_dist @@ -43,69 +43,69 @@ system.cpu.commit.COM:loads 415 # Nu system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 709 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 140 # The number of times a branch was mispredicted +system.cpu.commit.branchMispredicts 138 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 2576 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 4 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 1536 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 1420 # The number of squashed insts skipped by commit system.cpu.committedInsts 2387 # Number of Instructions Simulated system.cpu.committedInsts_total 2387 # Number of Instructions Simulated -system.cpu.cpi 312.537914 # CPI: Cycles Per Instruction -system.cpu.cpi_total 312.537914 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 565 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 7055.843750 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7158.016393 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 469 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 677361 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.169912 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 96 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 35 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 436639 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.107965 # mshr miss rate for ReadReq accesses +system.cpu.cpi 1.356933 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.356933 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 537 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 4625 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 3811.475410 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 465 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 333000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.134078 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 72 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 11 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 232500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.113594 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 61 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 294 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 7089.086420 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 6946.208333 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 213 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 574216 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.275510 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 81 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 57 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 166709 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_avg_miss_latency 5013.888889 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 4520.833333 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 222 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 361000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.244898 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 72 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 48 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 108500 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.081633 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 24 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 8.023529 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 8.082353 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 859 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 7071.056497 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 7098.211765 # average overall mshr miss latency -system.cpu.dcache.demand_hits 682 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 1251577 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.206054 # miss rate for demand accesses -system.cpu.dcache.demand_misses 177 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 92 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 603348 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.098952 # mshr miss rate for demand accesses +system.cpu.dcache.demand_accesses 831 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 4819.444444 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 4011.764706 # average overall mshr miss latency +system.cpu.dcache.demand_hits 687 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 694000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.173285 # miss rate for demand accesses +system.cpu.dcache.demand_misses 144 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 59 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 341000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.102286 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 85 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 859 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 7071.056497 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 7098.211765 # average overall mshr miss latency +system.cpu.dcache.overall_accesses 831 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 4819.444444 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 4011.764706 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 682 # number of overall hits -system.cpu.dcache.overall_miss_latency 1251577 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.206054 # miss rate for overall accesses -system.cpu.dcache.overall_misses 177 # number of overall misses -system.cpu.dcache.overall_mshr_hits 92 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 603348 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.098952 # mshr miss rate for overall accesses +system.cpu.dcache.overall_hits 687 # number of overall hits +system.cpu.dcache.overall_miss_latency 694000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.173285 # miss rate for overall accesses +system.cpu.dcache.overall_misses 144 # number of overall misses +system.cpu.dcache.overall_mshr_hits 59 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 341000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.102286 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 85 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses @@ -121,89 +121,89 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 85 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 46.650284 # Cycle average of tags in use -system.cpu.dcache.total_refs 682 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 50.824604 # Cycle average of tags in use +system.cpu.dcache.total_refs 687 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 23701 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 79 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 129 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 4617 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 5228 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 877 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 297 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 286 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 4 # Number of cycles decode is unblocking -system.cpu.fetch.Branches 832 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 760 # Number of cache lines fetched -system.cpu.fetch.Cycles 1674 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 131 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 5310 # Number of instructions fetch has processed +system.cpu.decode.DECODE:BlockedCycles 83 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 83 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 138 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 4642 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 2009 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 884 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 261 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 313 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 2 # Number of cycles decode is unblocking +system.cpu.fetch.Branches 860 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 736 # Number of cache lines fetched +system.cpu.fetch.Cycles 1668 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 78 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 5463 # Number of instructions fetch has processed system.cpu.fetch.SquashCycles 230 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.027635 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 760 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 357 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 0.176371 # Number of inst fetches per cycle +system.cpu.fetch.branchRate 0.265514 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 736 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 336 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.686632 # Number of inst fetches per cycle system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 30107 +system.cpu.fetch.rateDist.samples 3239 system.cpu.fetch.rateDist.min_value 0 - 0 29196 9697.41% - 1 37 12.29% - 2 87 28.90% - 3 73 24.25% - 4 125 41.52% - 5 66 21.92% - 6 42 13.95% - 7 50 16.61% - 8 431 143.16% + 0 2309 7128.74% + 1 47 145.11% + 2 82 253.16% + 3 70 216.12% + 4 128 395.18% + 5 58 179.07% + 6 37 114.23% + 7 46 142.02% + 8 462 1426.37% system.cpu.fetch.rateDist.max_value 8 system.cpu.fetch.rateDist.end_dist -system.cpu.icache.ReadReq_accesses 760 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 4979.783333 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 4157.255435 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 520 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 1195148 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.315789 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 240 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 56 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 764935 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.242105 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 184 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_accesses 736 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 4129.533679 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 3209.677419 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 543 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 797000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.262228 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 193 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 7 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 597000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.252717 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 186 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_refs 2.826087 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 2.919355 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 760 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 4979.783333 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 4157.255435 # average overall mshr miss latency -system.cpu.icache.demand_hits 520 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 1195148 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.315789 # miss rate for demand accesses -system.cpu.icache.demand_misses 240 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 56 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 764935 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.242105 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 184 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_accesses 736 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 4129.533679 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 3209.677419 # average overall mshr miss latency +system.cpu.icache.demand_hits 543 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 797000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.262228 # miss rate for demand accesses +system.cpu.icache.demand_misses 193 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 7 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 597000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.252717 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 186 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 760 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 4979.783333 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 4157.255435 # average overall mshr miss latency +system.cpu.icache.overall_accesses 736 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 4129.533679 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 3209.677419 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 520 # number of overall hits -system.cpu.icache.overall_miss_latency 1195148 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.315789 # miss rate for overall accesses -system.cpu.icache.overall_misses 240 # number of overall misses -system.cpu.icache.overall_mshr_hits 56 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 764935 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.242105 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 184 # number of overall MSHR misses +system.cpu.icache.overall_hits 543 # number of overall hits +system.cpu.icache.overall_miss_latency 797000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.262228 # miss rate for overall accesses +system.cpu.icache.overall_misses 193 # number of overall misses +system.cpu.icache.overall_mshr_hits 7 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 597000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.252717 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 186 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -216,61 +216,60 @@ system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.sampled_refs 184 # Sample count of references to valid blocks. +system.cpu.icache.sampled_refs 186 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 91.559894 # Cycle average of tags in use -system.cpu.icache.total_refs 520 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 104.079729 # Cycle average of tags in use +system.cpu.icache.total_refs 543 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 715922 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 547 # Number of branches executed -system.cpu.iew.EXEC:nop 269 # number of nop insts executed -system.cpu.iew.EXEC:rate 0.108081 # Inst execution rate -system.cpu.iew.EXEC:refs 940 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 340 # Number of stores executed +system.cpu.iew.EXEC:branches 535 # Number of branches executed +system.cpu.iew.EXEC:nop 256 # number of nop insts executed +system.cpu.iew.EXEC:rate 0.978388 # Inst execution rate +system.cpu.iew.EXEC:refs 913 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 339 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 1841 # num instructions consuming a value -system.cpu.iew.WB:count 3178 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.788702 # average fanout of values written-back +system.cpu.iew.WB:consumers 1857 # num instructions consuming a value +system.cpu.iew.WB:count 3126 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.787291 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 1452 # num instructions producing a value -system.cpu.iew.WB:rate 0.105557 # insts written-back per cycle -system.cpu.iew.WB:sent 3194 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 151 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 16588 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 701 # Number of dispatched load instructions +system.cpu.iew.WB:producers 1462 # num instructions producing a value +system.cpu.iew.WB:rate 0.965113 # insts written-back per cycle +system.cpu.iew.WB:sent 3139 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 156 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 0 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 692 # Number of dispatched load instructions system.cpu.iew.iewDispNonSpecInsts 6 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 62 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 382 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 4113 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 600 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 110 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 3254 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 9 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewDispSquashedInsts 99 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 385 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 4013 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 574 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 208 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 3169 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 297 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 12 # Number of cycles IEW is unblocking +system.cpu.iew.iewSquashCycles 261 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 29 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.forwLoads 27 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread.0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 15 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.memOrderViolation 10 # Number of memory ordering violations system.cpu.iew.lsq.thread.0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 286 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 88 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 15 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 96 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 55 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 0.003200 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.003200 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0 3364 # Type of FU issued +system.cpu.iew.lsq.thread.0.squashedLoads 277 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 91 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 10 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 103 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 53 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 0.736956 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.736956 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0 3377 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist (null) 0 0.00% # Type of FU issued - IntAlu 2398 71.28% # Type of FU issued + IntAlu 2413 71.45% # Type of FU issued IntMult 1 0.03% # Type of FU issued IntDiv 0 0.00% # Type of FU issued FloatAdd 0 0.00% # Type of FU issued @@ -279,16 +278,16 @@ system.cpu.iq.ISSUE:FU_type_0.start_dist FloatMult 0 0.00% # Type of FU issued FloatDiv 0 0.00% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued - MemRead 618 18.37% # Type of FU issued - MemWrite 347 10.32% # Type of FU issued + MemRead 617 18.27% # Type of FU issued + MemWrite 346 10.25% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.end_dist -system.cpu.iq.ISSUE:fu_busy_cnt 34 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.010107 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_cnt 37 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.010956 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full.start_dist (null) 0 0.00% # attempts to use FU when none available - IntAlu 1 2.94% # attempts to use FU when none available + IntAlu 1 2.70% # attempts to use FU when none available IntMult 0 0.00% # attempts to use FU when none available IntDiv 0 0.00% # attempts to use FU when none available FloatAdd 0 0.00% # attempts to use FU when none available @@ -297,43 +296,43 @@ system.cpu.iq.ISSUE:fu_full.start_dist FloatMult 0 0.00% # attempts to use FU when none available FloatDiv 0 0.00% # attempts to use FU when none available FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 11 32.35% # attempts to use FU when none available - MemWrite 22 64.71% # attempts to use FU when none available + MemRead 14 37.84% # attempts to use FU when none available + MemWrite 22 59.46% # attempts to use FU when none available IprAccess 0 0.00% # attempts to use FU when none available InstPrefetch 0 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full.end_dist system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 30107 +system.cpu.iq.ISSUE:issued_per_cycle.samples 3239 system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 28628 9508.75% - 1 616 204.60% - 2 335 111.27% - 3 225 74.73% - 4 177 58.79% - 5 80 26.57% - 6 31 10.30% - 7 11 3.65% - 8 4 1.33% + 0 2006 6193.27% + 1 362 1117.63% + 2 258 796.54% + 3 236 728.62% + 4 193 595.86% + 5 111 342.70% + 6 53 163.63% + 7 14 43.22% + 8 6 18.52% system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 system.cpu.iq.ISSUE:issued_per_cycle.end_dist -system.cpu.iq.ISSUE:rate 0.111735 # Inst issue rate -system.cpu.iq.iqInstsAdded 3838 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 3364 # Number of instructions issued +system.cpu.iq.ISSUE:rate 1.042606 # Inst issue rate +system.cpu.iq.iqInstsAdded 3751 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 3377 # Number of instructions issued system.cpu.iq.iqNonSpecInstsAdded 6 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 1301 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 35 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 1220 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 4 # Number of squashed instructions issued system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 682 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.l2cache.ReadReq_accesses 269 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 4610.717472 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2315.289963 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_miss_latency 1240283 # number of ReadReq miss cycles +system.cpu.iq.iqSquashedOperandsExamined 564 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.l2cache.ReadReq_accesses 271 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 3298.892989 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1993.811808 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_miss_latency 894000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 269 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 622813 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_misses 271 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 540323 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 269 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses 271 # number of ReadReq MSHR misses system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks. @@ -342,32 +341,32 @@ system.cpu.l2cache.blocked_no_targets 0 # nu system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 269 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 4610.717472 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 2315.289963 # average overall mshr miss latency +system.cpu.l2cache.demand_accesses 271 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 3298.892989 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 1993.811808 # average overall mshr miss latency system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 1240283 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 894000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 269 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses 271 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 622813 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 540323 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 269 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses 271 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 269 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 4610.717472 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 2315.289963 # average overall mshr miss latency +system.cpu.l2cache.overall_accesses 271 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 3298.892989 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 1993.811808 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 0 # number of overall hits -system.cpu.l2cache.overall_miss_latency 1240283 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 894000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 269 # number of overall misses +system.cpu.l2cache.overall_misses 271 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 622813 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 540323 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 269 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses 271 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -380,30 +379,27 @@ system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 269 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 271 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 138.742329 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 155.098898 # Cycle average of tags in use system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.numCycles 30107 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 16613 # Number of cycles rename is blocking +system.cpu.numCycles 3239 # number of cpu cycles simulated system.cpu.rename.RENAME:CommittedMaps 1768 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 14 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 5311 # Number of cycles rename is idle +system.cpu.rename.RENAME:IdleCycles 2100 # Number of cycles rename is idle system.cpu.rename.RENAME:LSQFullEvents 1 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:RenameLookups 5020 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 4436 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 3192 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 802 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 297 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 23 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 1424 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 7061 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:RenameLookups 5014 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 4443 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 3193 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 795 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 261 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 7 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 1425 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 76 # count of cycles rename stalled for serializing inst system.cpu.rename.RENAME:serializingInsts 8 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 78 # count of insts added to the skid buffer +system.cpu.rename.RENAME:skidInsts 52 # count of insts added to the skid buffer system.cpu.rename.RENAME:tempSerializingInsts 6 # count of temporary serializing insts renamed -system.cpu.timesIdled 207 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 4 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout index 25e5ec43b..835f03aa2 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout @@ -6,9 +6,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Mar 30 2007 13:12:55 -M5 started Fri Mar 30 13:13:05 2007 +M5 compiled Apr 21 2007 21:50:58 +M5 started Sat Apr 21 21:51:10 2007 M5 executing on zamp.eecs.umich.edu command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/o3-timing tests/run.py quick/00.hello/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second -Exiting @ tick 746028 because target called exit() +Exiting @ tick 1619000 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini index 41c8029a3..3e6a662e6 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini @@ -1,51 +1,7 @@ [root] type=Root children=system -checkpoint= -clock=1000000000000 -max_tick=0 -output_file=cout -progress_interval=0 - -[debug] -break_cycles= - -[exetrace] -intel_format=false -legion_lockstep=false -pc_symbol=true -print_cpseq=false -print_cycle=true -print_data=true -print_effaddr=true -print_fetchseq=false -print_iregs=false -print_opclass=true -print_thread=true -speculative=true -trace_system=client - -[serialize] -count=10 -cycle=0 -dir=cpt.%012d -period=0 - -[stats] -descriptions=true -dump_cycle=0 -dump_period=0 -dump_reset=false -ignore_events= -mysql_db= -mysql_host= -mysql_password= -mysql_user= -project_name=test -simulation_name=test -simulation_sample=0 -text_compat=true -text_file=m5stats.txt +dummy=0 [system] type=System @@ -56,7 +12,7 @@ physmem=system.physmem [system.cpu] type=AtomicSimpleCPU children=workload -clock=1 +clock=500 cpu_id=0 defer_registration=false function_trace=false @@ -65,6 +21,7 @@ max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 +phase=0 progress_interval=0 simulate_stalls=false system=system @@ -76,6 +33,7 @@ icache_port=system.membus.port[1] [system.cpu.workload] type=LiveProcess cmd=hello +cwd= egid=100 env= euid=100 @@ -101,14 +59,6 @@ type=PhysicalMemory file= latency=1 range=0:134217727 +zero=false port=system.membus.port[0] -[trace] -bufsize=0 -cycle=0 -dump_on_exit=false -file=cout -flags= -ignore= -start=0 - diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.out b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.out index 88d1a9a45..a2be80e9b 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.out +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.out @@ -1,15 +1,13 @@ [root] type=Root -clock=1000000000000 -max_tick=0 -progress_interval=0 -output_file=cout +dummy=0 [system.physmem] type=PhysicalMemory file= range=[0,134217727] latency=1 +zero=false [system] type=System @@ -30,6 +28,7 @@ executable=tests/test-progs/hello/bin/alpha/tru64/hello input=cin output=cout env= +cwd= system=system uid=100 euid=100 @@ -48,61 +47,11 @@ progress_interval=0 system=system cpu_id=0 workload=system.cpu.workload -clock=1 +clock=500 +phase=0 defer_registration=false width=1 function_trace=false function_trace_start=0 simulate_stalls=false -[trace] -flags= -start=0 -cycle=0 -bufsize=0 -file=cout -dump_on_exit=false -ignore= - -[stats] -descriptions=true -project_name=test -simulation_name=test -simulation_sample=0 -text_file=m5stats.txt -text_compat=true -mysql_db= -mysql_user= -mysql_password= -mysql_host= -events_start=-1 -dump_reset=false -dump_cycle=0 -dump_period=0 -ignore_events= - -[random] -seed=1 - -[exetrace] -speculative=true -print_cycle=true -print_opclass=true -print_thread=true -print_effaddr=true -print_data=true -print_iregs=false -print_fetchseq=false -print_cpseq=false -print_reg_delta=false -pc_symbol=true -intel_format=false -legion_lockstep=false -trace_system=client - -[debug] -break_cycles= - -[statsreset] -reset_cycle=0 - diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/m5stats.txt b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/m5stats.txt index 25dace389..16257c237 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/m5stats.txt +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/m5stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 480164 # Simulator instruction rate (inst/s) -host_mem_usage 147928 # Number of bytes of host memory used +host_inst_rate 254768 # Simulator instruction rate (inst/s) +host_mem_usage 147764 # Number of bytes of host memory used host_seconds 0.01 # Real time elapsed on the host -host_tick_rate 437596 # Simulator tick rate (ticks/s) +host_tick_rate 121316260 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 2578 # Number of instructions simulated -sim_seconds 0.000000 # Number of seconds simulated -sim_ticks 2577 # Number of ticks simulated +sim_seconds 0.000001 # Number of seconds simulated +sim_ticks 1288500 # Number of ticks simulated system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 2578 # number of cpu cycles simulated diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stderr b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stderr index b3cdfe967..9f8e7c2e9 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stderr +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stderr @@ -1,2 +1,3 @@ warn: Entering event queue @ 0. Starting simulation... +warn: Increasing stack size by one page. warn: ignoring syscall sigprocmask(1, 18446744073709547831, ...) diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stdout b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stdout index 099a6d041..ddbbe3d32 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stdout +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stdout @@ -6,8 +6,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 3 2006 17:10:27 -M5 started Fri Nov 3 17:10:50 2006 -M5 executing on zizzer.eecs.umich.edu -command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/simple-atomic tests/run.py quick/00.hello/alpha/tru64/simple-atomic -Exiting @ tick 2577 because target called exit() +M5 compiled Apr 21 2007 21:50:58 +M5 started Sat Apr 21 21:51:10 2007 +M5 executing on zamp.eecs.umich.edu +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-atomic tests/run.py quick/00.hello/alpha/tru64/simple-atomic +Global frequency set at 1000000000000 ticks per second +Exiting @ tick 1288500 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini index 62041169c..52183bdb1 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini @@ -1,51 +1,7 @@ [root] type=Root children=system -checkpoint= -clock=1000000000000 -max_tick=0 -output_file=cout -progress_interval=0 - -[debug] -break_cycles= - -[exetrace] -intel_format=false -legion_lockstep=false -pc_symbol=true -print_cpseq=false -print_cycle=true -print_data=true -print_effaddr=true -print_fetchseq=false -print_iregs=false -print_opclass=true -print_thread=true -speculative=true -trace_system=client - -[serialize] -count=10 -cycle=0 -dir=cpt.%012d -period=0 - -[stats] -descriptions=true -dump_cycle=0 -dump_period=0 -dump_reset=false -ignore_events= -mysql_db= -mysql_host= -mysql_password= -mysql_user= -project_name=test -simulation_name=test -simulation_sample=0 -text_compat=true -text_file=m5stats.txt +dummy=0 [system] type=System @@ -56,7 +12,7 @@ physmem=system.physmem [system.cpu] type=TimingSimpleCPU children=dcache icache l2cache toL2Bus workload -clock=1 +clock=500 cpu_id=0 defer_registration=false function_trace=false @@ -65,6 +21,7 @@ max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 +phase=0 progress_interval=0 system=system workload=system.cpu.workload @@ -199,6 +156,7 @@ port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cp [system.cpu.workload] type=LiveProcess cmd=hello +cwd= egid=100 env= euid=100 @@ -224,14 +182,6 @@ type=PhysicalMemory file= latency=1 range=0:134217727 +zero=false port=system.membus.port[0] -[trace] -bufsize=0 -cycle=0 -dump_on_exit=false -file=cout -flags= -ignore= -start=0 - diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.out b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.out index 85dfbaa94..05d289a63 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.out +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.out @@ -1,15 +1,13 @@ [root] type=Root -clock=1000000000000 -max_tick=0 -progress_interval=0 -output_file=cout +dummy=0 [system.physmem] type=PhysicalMemory file= range=[0,134217727] latency=1 +zero=false [system] type=System @@ -30,6 +28,7 @@ executable=tests/test-progs/hello/bin/alpha/tru64/hello input=cin output=cout env= +cwd= system=system uid=100 euid=100 @@ -48,7 +47,8 @@ progress_interval=0 system=system cpu_id=0 workload=system.cpu.workload -clock=1 +clock=500 +phase=0 defer_registration=false // width not specified function_trace=false @@ -176,54 +176,3 @@ prefetch_use_cpu_id=true prefetch_data_accesses_only=false hit_latency=1 -[trace] -flags= -start=0 -cycle=0 -bufsize=0 -file=cout -dump_on_exit=false -ignore= - -[stats] -descriptions=true -project_name=test -simulation_name=test -simulation_sample=0 -text_file=m5stats.txt -text_compat=true -mysql_db= -mysql_user= -mysql_password= -mysql_host= -events_start=-1 -dump_reset=false -dump_cycle=0 -dump_period=0 -ignore_events= - -[random] -seed=1 - -[exetrace] -speculative=true -print_cycle=true -print_opclass=true -print_thread=true -print_effaddr=true -print_data=true -print_iregs=false -print_fetchseq=false -print_cpseq=false -print_reg_delta=false -pc_symbol=true -intel_format=false -legion_lockstep=false -trace_system=client - -[debug] -break_cycles= - -[statsreset] -reset_cycle=0 - diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt index 010da4162..8671d784f 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt @@ -1,31 +1,31 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 153015 # Simulator instruction rate (inst/s) -host_mem_usage 179088 # Number of bytes of host memory used +host_inst_rate 125225 # Simulator instruction rate (inst/s) +host_mem_usage 153176 # Number of bytes of host memory used host_seconds 0.02 # Real time elapsed on the host -host_tick_rate 56749783 # Simulator tick rate (ticks/s) +host_tick_rate 116347710 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 2578 # Number of instructions simulated -sim_seconds 0.000001 # Number of seconds simulated -sim_ticks 980012 # Number of ticks simulated +sim_seconds 0.000002 # Number of seconds simulated +sim_ticks 2444000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 415 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 3988.472727 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2988.472727 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 3890.909091 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2890.909091 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 360 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 219366 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 214000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.132530 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 55 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 164366 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 159000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.132530 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 55 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 294 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 3991.518519 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2991.518519 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 3722.222222 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2722.222222 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 267 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 107771 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 100500 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.091837 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 27 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 80771 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 73500 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.091837 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 27 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -37,29 +37,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 709 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 3989.475610 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 2989.475610 # average overall mshr miss latency +system.cpu.dcache.demand_avg_miss_latency 3835.365854 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 2835.365854 # average overall mshr miss latency system.cpu.dcache.demand_hits 627 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 327137 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency 314500 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.115656 # miss rate for demand accesses system.cpu.dcache.demand_misses 82 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 245137 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 232500 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.115656 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 82 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.overall_accesses 709 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 3989.475610 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 2989.475610 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 3835.365854 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 2835.365854 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 627 # number of overall hits -system.cpu.dcache.overall_miss_latency 327137 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency 314500 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.115656 # miss rate for overall accesses system.cpu.dcache.overall_misses 82 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 245137 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 232500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.115656 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 82 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -76,18 +76,18 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 82 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 45.884153 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 51.430454 # Cycle average of tags in use system.cpu.dcache.total_refs 627 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks system.cpu.icache.ReadReq_accesses 2579 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 3986.705521 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 2986.705521 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_miss_latency 3733.128834 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 2733.128834 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_hits 2416 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 649833 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency 608500 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.063203 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 163 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 486833 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 445500 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.063203 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 163 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -99,29 +99,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 2579 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 3986.705521 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 2986.705521 # average overall mshr miss latency +system.cpu.icache.demand_avg_miss_latency 3733.128834 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 2733.128834 # average overall mshr miss latency system.cpu.icache.demand_hits 2416 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 649833 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency 608500 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.063203 # miss rate for demand accesses system.cpu.icache.demand_misses 163 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 486833 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 445500 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.063203 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 163 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.overall_accesses 2579 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 3986.705521 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 2986.705521 # average overall mshr miss latency +system.cpu.icache.overall_avg_miss_latency 3733.128834 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 2733.128834 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.icache.overall_hits 2416 # number of overall hits -system.cpu.icache.overall_miss_latency 649833 # number of overall miss cycles +system.cpu.icache.overall_miss_latency 608500 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.063203 # miss rate for overall accesses system.cpu.icache.overall_misses 163 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 486833 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 445500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.063203 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 163 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -138,18 +138,18 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 0 # number of replacements system.cpu.icache.sampled_refs 163 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 76.367476 # Cycle average of tags in use +system.cpu.icache.tagsinuse 89.421061 # Cycle average of tags in use system.cpu.icache.total_refs 2416 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.l2cache.ReadReq_accesses 245 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 2987.632653 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1986.632653 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_miss_latency 731970 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_avg_miss_latency 2767.346939 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1766.346939 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_miss_latency 678000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 245 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 486725 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 432755 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 245 # number of ReadReq MSHR misses system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -161,29 +161,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 # system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 245 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 2987.632653 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 1986.632653 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_miss_latency 2767.346939 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 1766.346939 # average overall mshr miss latency system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 731970 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 678000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses system.cpu.l2cache.demand_misses 245 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 486725 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 432755 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 245 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.overall_accesses 245 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 2987.632653 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 1986.632653 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_miss_latency 2767.346939 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 1766.346939 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 0 # number of overall hits -system.cpu.l2cache.overall_miss_latency 731970 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 678000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses system.cpu.l2cache.overall_misses 245 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 486725 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 432755 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 245 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -200,12 +200,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.sampled_refs 245 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 122.501625 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 140.951761 # Cycle average of tags in use system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 980012 # number of cpu cycles simulated +system.cpu.numCycles 2444000 # number of cpu cycles simulated system.cpu.num_insts 2578 # Number of instructions executed system.cpu.num_refs 710 # Number of memory references system.cpu.workload.PROG:num_syscalls 4 # Number of system calls diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stderr b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stderr index b3cdfe967..9f8e7c2e9 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stderr +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stderr @@ -1,2 +1,3 @@ warn: Entering event queue @ 0. Starting simulation... +warn: Increasing stack size by one page. warn: ignoring syscall sigprocmask(1, 18446744073709547831, ...) diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout index cf7a58ef1..d2bc8bfb7 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout @@ -6,8 +6,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 3 2006 17:10:27 -M5 started Fri Nov 3 17:10:51 2006 -M5 executing on zizzer.eecs.umich.edu -command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/simple-timing tests/run.py quick/00.hello/alpha/tru64/simple-timing -Exiting @ tick 980012 because target called exit() +M5 compiled Apr 21 2007 21:50:58 +M5 started Sat Apr 21 21:51:11 2007 +M5 executing on zamp.eecs.umich.edu +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-timing tests/run.py quick/00.hello/alpha/tru64/simple-timing +Global frequency set at 1000000000000 ticks per second +Exiting @ tick 2444000 because target called exit() diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini index e11ca74dd..5e1ced152 100644 --- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini +++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini @@ -23,7 +23,7 @@ activity=0 backComSize=5 choiceCtrBits=2 choicePredictorSize=8192 -clock=1 +clock=500 commitToDecodeDelay=1 commitToFetchDelay=1 commitToIEWDelay=1 diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.out b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.out index 0d9c5215b..f04ad4ffd 100644 --- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.out +++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.out @@ -183,7 +183,7 @@ FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUL [system.cpu] type=DerivO3CPU -clock=1 +clock=500 phase=0 numThreads=1 cpu_id=0 diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt index 684314d31..b44194dff 100644 --- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt +++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt @@ -1,48 +1,48 @@ ---------- Begin Simulation Statistics ---------- global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 827 # Number of BTB hits -global.BPredUnit.BTBLookups 3697 # Number of BTB lookups -global.BPredUnit.RASInCorrect 179 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 1207 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 2534 # Number of conditional branches predicted -global.BPredUnit.lookups 4455 # Number of BP lookups -global.BPredUnit.usedRAS 640 # Number of times the RAS was used to get a target. -host_inst_rate 15344 # Simulator instruction rate (inst/s) -host_mem_usage 154676 # Number of bytes of host memory used -host_seconds 0.73 # Real time elapsed on the host -host_tick_rate 2857242 # Simulator tick rate (ticks/s) -memdepunit.memDep.conflictingLoads 24 # Number of conflicting loads. -memdepunit.memDep.conflictingLoads 26 # Number of conflicting loads. -memdepunit.memDep.conflictingStores 4 # Number of conflicting stores. -memdepunit.memDep.conflictingStores 5 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 2132 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedLoads 2142 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 1150 # Number of stores inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 1138 # Number of stores inserted to the mem dependence unit. +global.BPredUnit.BTBHits 687 # Number of BTB hits +global.BPredUnit.BTBLookups 3480 # Number of BTB lookups +global.BPredUnit.RASInCorrect 113 # Number of incorrect RAS predictions. +global.BPredUnit.condIncorrect 1086 # Number of conditional branches incorrect +global.BPredUnit.condPredicted 2328 # Number of conditional branches predicted +global.BPredUnit.lookups 4062 # Number of BP lookups +global.BPredUnit.usedRAS 562 # Number of times the RAS was used to get a target. +host_inst_rate 49679 # Simulator instruction rate (inst/s) +host_mem_usage 154724 # Number of bytes of host memory used +host_seconds 0.23 # Real time elapsed on the host +host_tick_rate 20293608 # Simulator tick rate (ticks/s) +memdepunit.memDep.conflictingLoads 15 # Number of conflicting loads. +memdepunit.memDep.conflictingLoads 21 # Number of conflicting loads. +memdepunit.memDep.conflictingStores 59 # Number of conflicting stores. +memdepunit.memDep.conflictingStores 54 # Number of conflicting stores. +memdepunit.memDep.insertedLoads 1911 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedLoads 1833 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 1079 # Number of stores inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 1058 # Number of stores inserted to the mem dependence unit. sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 11247 # Number of instructions simulated -sim_seconds 0.000002 # Number of seconds simulated -sim_ticks 2095164 # Number of ticks simulated +sim_seconds 0.000005 # Number of seconds simulated +sim_ticks 4600500 # Number of ticks simulated system.cpu.commit.COM:branches 1724 # Number of branches committed system.cpu.commit.COM:branches_0 862 # Number of branches committed system.cpu.commit.COM:branches_1 862 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 123 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 179 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.COM:bw_limited_0 0 # number of insts not committed due to BW limits system.cpu.commit.COM:bw_limited_1 0 # number of insts not committed due to BW limits system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 165684 +system.cpu.commit.COM:committed_per_cycle.samples 9158 system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 159919 9652.05% - 1 3333 201.17% - 2 1165 70.31% - 3 515 31.08% - 4 270 16.30% - 5 201 12.13% - 6 102 6.16% - 7 56 3.38% - 8 123 7.42% + 0 4902 5352.70% + 1 1725 1883.60% + 2 937 1023.15% + 3 472 515.40% + 4 355 387.64% + 5 234 255.51% + 6 234 255.51% + 7 120 131.03% + 8 179 195.46% system.cpu.commit.COM:committed_per_cycle.max_value 8 system.cpu.commit.COM:committed_per_cycle.end_dist @@ -61,141 +61,141 @@ system.cpu.commit.COM:refs_1 1791 # Nu system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed system.cpu.commit.COM:swp_count_0 0 # Number of s/w prefetches committed system.cpu.commit.COM:swp_count_1 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 947 # The number of times a branch was mispredicted +system.cpu.commit.branchMispredicts 843 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 11281 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 34 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 9432 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 7371 # The number of squashed insts skipped by commit system.cpu.committedInsts_0 5623 # Number of Instructions Simulated system.cpu.committedInsts_1 5624 # Number of Instructions Simulated system.cpu.committedInsts_total 11247 # Number of Instructions Simulated -system.cpu.cpi_0 372.606082 # CPI: Cycles Per Instruction -system.cpu.cpi_1 372.539829 # CPI: Cycles Per Instruction -system.cpu.cpi_total 186.286476 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 3234 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses_0 3234 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 10308.511696 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency_0 10308.511696 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 10789.975000 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency_0 10789.975000 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 2892 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits_0 2892 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 3525511 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency_0 3525511 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.105751 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate_0 0.105751 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 342 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses_0 342 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 142 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits_0 142 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 2157995 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency_0 2157995 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.061843 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate_0 0.061843 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 200 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses_0 200 # number of ReadReq MSHR misses +system.cpu.cpi_0 1.636671 # CPI: Cycles Per Instruction +system.cpu.cpi_1 1.636380 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.818263 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 2909 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses_0 2909 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 6520.912548 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency_0 6520.912548 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 6121.212121 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency_0 6121.212121 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 2646 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits_0 2646 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 1715000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency_0 1715000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.090409 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate_0 0.090409 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 263 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses_0 263 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 65 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits_0 65 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 1212000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency_0 1212000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.068065 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate_0 0.068065 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 198 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses_0 198 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 1624 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses_0 1624 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 8945.050491 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency_0 8945.050491 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 9931.897260 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency_0 9931.897260 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 911 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits_0 911 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 6377821 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency_0 6377821 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.439039 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate_0 0.439039 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 713 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses_0 713 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 567 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits_0 567 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 1450057 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency_0 1450057 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_avg_miss_latency 4509.846827 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency_0 4509.846827 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 4681.506849 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency_0 4681.506849 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 1167 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits_0 1167 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 2061000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency_0 2061000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.281404 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate_0 0.281404 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 457 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses_0 457 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 311 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits_0 311 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 683500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency_0 683500 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.089901 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate_0 0.089901 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 146 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses_0 146 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles_no_mshrs 994 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 10.991329 # Average number of references to valid blocks. -system.cpu.dcache.blocked_no_mshrs 1 # number of cycles access was blocked +system.cpu.dcache.avg_refs 11.084302 # Average number of references to valid blocks. +system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_mshrs 994 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 4858 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses_0 4858 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses 4533 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses_0 4533 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses_1 0 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 9387.044550 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency_0 9387.044550 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency 5244.444444 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency_0 5244.444444 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency_1 <err: div-0> # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 10427.895954 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency_0 10427.895954 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 5510.174419 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency_0 5510.174419 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency_1 <err: div-0> # average overall mshr miss latency -system.cpu.dcache.demand_hits 3803 # number of demand (read+write) hits -system.cpu.dcache.demand_hits_0 3803 # number of demand (read+write) hits +system.cpu.dcache.demand_hits 3813 # number of demand (read+write) hits +system.cpu.dcache.demand_hits_0 3813 # number of demand (read+write) hits system.cpu.dcache.demand_hits_1 0 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 9903332 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency_0 9903332 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency 3776000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency_0 3776000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency_1 0 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.217168 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate_0 0.217168 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate 0.158835 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate_0 0.158835 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate_1 <err: div-0> # miss rate for demand accesses -system.cpu.dcache.demand_misses 1055 # number of demand (read+write) misses -system.cpu.dcache.demand_misses_0 1055 # number of demand (read+write) misses +system.cpu.dcache.demand_misses 720 # number of demand (read+write) misses +system.cpu.dcache.demand_misses_0 720 # number of demand (read+write) misses system.cpu.dcache.demand_misses_1 0 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 709 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits_0 709 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits 376 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits_0 376 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_hits_1 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 3608052 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency_0 3608052 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 1895500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency_0 1895500 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency_1 0 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.071223 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate_0 0.071223 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate 0.075888 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate_0 0.075888 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate_1 <err: div-0> # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 346 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses_0 346 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses 344 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses_0 344 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses_1 0 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.mshr_cap_events_0 0 # number of times MSHR cap was activated system.cpu.dcache.mshr_cap_events_1 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 4858 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses_0 4858 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses 4533 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses_0 4533 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses_1 0 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 9387.044550 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency_0 9387.044550 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 5244.444444 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency_0 5244.444444 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency_1 <err: div-0> # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 10427.895954 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency_0 10427.895954 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 5510.174419 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency_0 5510.174419 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency_1 <err: div-0> # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency_0 <err: div-0> # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency_1 <err: div-0> # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 3803 # number of overall hits -system.cpu.dcache.overall_hits_0 3803 # number of overall hits +system.cpu.dcache.overall_hits 3813 # number of overall hits +system.cpu.dcache.overall_hits_0 3813 # number of overall hits system.cpu.dcache.overall_hits_1 0 # number of overall hits -system.cpu.dcache.overall_miss_latency 9903332 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency_0 9903332 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency 3776000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency_0 3776000 # number of overall miss cycles system.cpu.dcache.overall_miss_latency_1 0 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.217168 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate_0 0.217168 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate 0.158835 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate_0 0.158835 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate_1 <err: div-0> # miss rate for overall accesses -system.cpu.dcache.overall_misses 1055 # number of overall misses -system.cpu.dcache.overall_misses_0 1055 # number of overall misses +system.cpu.dcache.overall_misses 720 # number of overall misses +system.cpu.dcache.overall_misses_0 720 # number of overall misses system.cpu.dcache.overall_misses_1 0 # number of overall misses -system.cpu.dcache.overall_mshr_hits 709 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits_0 709 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits 376 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits_0 376 # number of overall MSHR hits system.cpu.dcache.overall_mshr_hits_1 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 3608052 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency_0 3608052 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 1895500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency_0 1895500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency_1 0 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.071223 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate_0 0.071223 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate 0.075888 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate_0 0.075888 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate_1 <err: div-0> # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 346 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses_0 346 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses 344 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses_0 344 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses_1 0 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_latency_0 0 # number of overall MSHR uncacheable cycles @@ -215,153 +215,153 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.replacements_0 0 # number of replacements system.cpu.dcache.replacements_1 0 # number of replacements -system.cpu.dcache.sampled_refs 346 # Sample count of references to valid blocks. +system.cpu.dcache.sampled_refs 344 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.soft_prefetch_mshr_full_0 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.soft_prefetch_mshr_full_1 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 200.098842 # Cycle average of tags in use -system.cpu.dcache.total_refs 3803 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 218.590181 # Cycle average of tags in use +system.cpu.dcache.total_refs 3813 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks system.cpu.dcache.writebacks_0 0 # number of writebacks system.cpu.dcache.writebacks_1 0 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 112235 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 273 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 396 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 24032 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 212833 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 4096 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 1856 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 672 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 181 # Number of cycles decode is unblocking -system.cpu.fetch.Branches 4455 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 3542 # Number of cache lines fetched -system.cpu.fetch.Cycles 8000 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 608 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 26459 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 1268 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.026888 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 3542 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 1467 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 0.159692 # Number of inst fetches per cycle +system.cpu.decode.DECODE:BlockedCycles 1876 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 260 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 354 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 22033 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 11054 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 3598 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 1407 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 337 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 284 # Number of cycles decode is unblocking +system.cpu.fetch.Branches 4062 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 2946 # Number of cache lines fetched +system.cpu.fetch.Cycles 6973 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 278 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 24430 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 1145 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.441378 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 2946 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 1249 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 2.654569 # Number of inst fetches per cycle system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 165688 +system.cpu.fetch.rateDist.samples 9203 system.cpu.fetch.rateDist.min_value 0 - 0 161234 9731.18% - 1 342 20.64% - 2 283 17.08% - 3 285 17.20% - 4 390 23.54% - 5 369 22.27% - 6 367 22.15% - 7 255 15.39% - 8 2163 130.55% + 0 5177 5625.34% + 1 291 316.20% + 2 234 254.26% + 3 263 285.78% + 4 314 341.19% + 5 294 319.46% + 6 311 337.93% + 7 262 284.69% + 8 2057 2235.14% system.cpu.fetch.rateDist.max_value 8 system.cpu.fetch.rateDist.end_dist -system.cpu.icache.ReadReq_accesses 3542 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses_0 3542 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 7880.839306 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency_0 7880.839306 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 7272.060897 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency_0 7272.060897 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 2677 # number of ReadReq hits -system.cpu.icache.ReadReq_hits_0 2677 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 6816926 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency_0 6816926 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.244212 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate_0 0.244212 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 865 # number of ReadReq misses -system.cpu.icache.ReadReq_misses_0 865 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 241 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits_0 241 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 4537766 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency_0 4537766 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.176172 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate_0 0.176172 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 624 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses_0 624 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_accesses 2946 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses_0 2946 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 4950.682853 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency_0 4950.682853 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 4079.838710 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency_0 4079.838710 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 2287 # number of ReadReq hits +system.cpu.icache.ReadReq_hits_0 2287 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 3262500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency_0 3262500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.223693 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate_0 0.223693 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 659 # number of ReadReq misses +system.cpu.icache.ReadReq_misses_0 659 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 39 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits_0 39 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 2529500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency_0 2529500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.210455 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate_0 0.210455 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 620 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses_0 620 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_refs 4.290064 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 3.688710 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 3542 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses_0 3542 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses 2946 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses_0 2946 # number of demand (read+write) accesses system.cpu.icache.demand_accesses_1 0 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 7880.839306 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency_0 7880.839306 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency 4950.682853 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency_0 4950.682853 # average overall miss latency system.cpu.icache.demand_avg_miss_latency_1 <err: div-0> # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 7272.060897 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency_0 7272.060897 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 4079.838710 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency_0 4079.838710 # average overall mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency_1 <err: div-0> # average overall mshr miss latency -system.cpu.icache.demand_hits 2677 # number of demand (read+write) hits -system.cpu.icache.demand_hits_0 2677 # number of demand (read+write) hits +system.cpu.icache.demand_hits 2287 # number of demand (read+write) hits +system.cpu.icache.demand_hits_0 2287 # number of demand (read+write) hits system.cpu.icache.demand_hits_1 0 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 6816926 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency_0 6816926 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency 3262500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency_0 3262500 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_latency_1 0 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.244212 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate_0 0.244212 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate 0.223693 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate_0 0.223693 # miss rate for demand accesses system.cpu.icache.demand_miss_rate_1 <err: div-0> # miss rate for demand accesses -system.cpu.icache.demand_misses 865 # number of demand (read+write) misses -system.cpu.icache.demand_misses_0 865 # number of demand (read+write) misses +system.cpu.icache.demand_misses 659 # number of demand (read+write) misses +system.cpu.icache.demand_misses_0 659 # number of demand (read+write) misses system.cpu.icache.demand_misses_1 0 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 241 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits_0 241 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits 39 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits_0 39 # number of demand (read+write) MSHR hits system.cpu.icache.demand_mshr_hits_1 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 4537766 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency_0 4537766 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 2529500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency_0 2529500 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency_1 0 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.176172 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate_0 0.176172 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate 0.210455 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate_0 0.210455 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate_1 <err: div-0> # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 624 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses_0 624 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses 620 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses_0 620 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses_1 0 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.mshr_cap_events_0 0 # number of times MSHR cap was activated system.cpu.icache.mshr_cap_events_1 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 3542 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses_0 3542 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses 2946 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses_0 2946 # number of overall (read+write) accesses system.cpu.icache.overall_accesses_1 0 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 7880.839306 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency_0 7880.839306 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 4950.682853 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency_0 4950.682853 # average overall miss latency system.cpu.icache.overall_avg_miss_latency_1 <err: div-0> # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 7272.060897 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency_0 7272.060897 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 4079.838710 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency_0 4079.838710 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency_1 <err: div-0> # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency_0 <err: div-0> # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency_1 <err: div-0> # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 2677 # number of overall hits -system.cpu.icache.overall_hits_0 2677 # number of overall hits +system.cpu.icache.overall_hits 2287 # number of overall hits +system.cpu.icache.overall_hits_0 2287 # number of overall hits system.cpu.icache.overall_hits_1 0 # number of overall hits -system.cpu.icache.overall_miss_latency 6816926 # number of overall miss cycles -system.cpu.icache.overall_miss_latency_0 6816926 # number of overall miss cycles +system.cpu.icache.overall_miss_latency 3262500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency_0 3262500 # number of overall miss cycles system.cpu.icache.overall_miss_latency_1 0 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.244212 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate_0 0.244212 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate 0.223693 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate_0 0.223693 # miss rate for overall accesses system.cpu.icache.overall_miss_rate_1 <err: div-0> # miss rate for overall accesses -system.cpu.icache.overall_misses 865 # number of overall misses -system.cpu.icache.overall_misses_0 865 # number of overall misses +system.cpu.icache.overall_misses 659 # number of overall misses +system.cpu.icache.overall_misses_0 659 # number of overall misses system.cpu.icache.overall_misses_1 0 # number of overall misses -system.cpu.icache.overall_mshr_hits 241 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits_0 241 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits 39 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits_0 39 # number of overall MSHR hits system.cpu.icache.overall_mshr_hits_1 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 4537766 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency_0 4537766 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 2529500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency_0 2529500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency_1 0 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.176172 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate_0 0.176172 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate 0.210455 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate_0 0.210455 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate_1 <err: div-0> # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 624 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses_0 624 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses 620 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses_0 620 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses_1 0 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency_0 0 # number of overall MSHR uncacheable cycles @@ -378,107 +378,107 @@ system.cpu.icache.prefetcher.num_hwpf_issued 0 system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.icache.replacements 6 # number of replacements -system.cpu.icache.replacements_0 6 # number of replacements +system.cpu.icache.replacements 9 # number of replacements +system.cpu.icache.replacements_0 9 # number of replacements system.cpu.icache.replacements_1 0 # number of replacements -system.cpu.icache.sampled_refs 624 # Sample count of references to valid blocks. +system.cpu.icache.sampled_refs 620 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.soft_prefetch_mshr_full_0 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.soft_prefetch_mshr_full_1 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 289.929418 # Cycle average of tags in use -system.cpu.icache.total_refs 2677 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 315.428279 # Cycle average of tags in use +system.cpu.icache.total_refs 2287 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.icache.writebacks_0 0 # number of writebacks system.cpu.icache.writebacks_1 0 # number of writebacks -system.cpu.idleCycles 1929477 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 2535 # Number of branches executed -system.cpu.iew.EXEC:branches_0 1269 # Number of branches executed -system.cpu.iew.EXEC:branches_1 1266 # Number of branches executed -system.cpu.iew.EXEC:nop 84 # number of nop insts executed -system.cpu.iew.EXEC:nop_0 42 # number of nop insts executed -system.cpu.iew.EXEC:nop_1 42 # number of nop insts executed -system.cpu.iew.EXEC:rate 0.100864 # Inst execution rate -system.cpu.iew.EXEC:refs 5422 # number of memory reference insts executed -system.cpu.iew.EXEC:refs_0 2727 # number of memory reference insts executed -system.cpu.iew.EXEC:refs_1 2695 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 1997 # Number of stores executed -system.cpu.iew.EXEC:stores_0 1003 # Number of stores executed -system.cpu.iew.EXEC:stores_1 994 # Number of stores executed +system.cpu.idleCycles -1 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 2339 # Number of branches executed +system.cpu.iew.EXEC:branches_0 1175 # Number of branches executed +system.cpu.iew.EXEC:branches_1 1164 # Number of branches executed +system.cpu.iew.EXEC:nop 72 # number of nop insts executed +system.cpu.iew.EXEC:nop_0 36 # number of nop insts executed +system.cpu.iew.EXEC:nop_1 36 # number of nop insts executed +system.cpu.iew.EXEC:rate 1.666196 # Inst execution rate +system.cpu.iew.EXEC:refs 4928 # number of memory reference insts executed +system.cpu.iew.EXEC:refs_0 2490 # number of memory reference insts executed +system.cpu.iew.EXEC:refs_1 2438 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 1865 # Number of stores executed +system.cpu.iew.EXEC:stores_0 938 # Number of stores executed +system.cpu.iew.EXEC:stores_1 927 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed system.cpu.iew.EXEC:swp_0 0 # number of swp insts executed system.cpu.iew.EXEC:swp_1 0 # number of swp insts executed -system.cpu.iew.WB:consumers 10258 # num instructions consuming a value -system.cpu.iew.WB:consumers_0 5162 # num instructions consuming a value -system.cpu.iew.WB:consumers_1 5096 # num instructions consuming a value -system.cpu.iew.WB:count 16101 # cumulative count of insts written-back -system.cpu.iew.WB:count_0 8089 # cumulative count of insts written-back -system.cpu.iew.WB:count_1 8012 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.770326 # average fanout of values written-back -system.cpu.iew.WB:fanout_0 0.768888 # average fanout of values written-back -system.cpu.iew.WB:fanout_1 0.771782 # average fanout of values written-back +system.cpu.iew.WB:consumers 10157 # num instructions consuming a value +system.cpu.iew.WB:consumers_0 5143 # num instructions consuming a value +system.cpu.iew.WB:consumers_1 5014 # num instructions consuming a value +system.cpu.iew.WB:count 14949 # cumulative count of insts written-back +system.cpu.iew.WB:count_0 7544 # cumulative count of insts written-back +system.cpu.iew.WB:count_1 7405 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.769912 # average fanout of values written-back +system.cpu.iew.WB:fanout_0 0.768229 # average fanout of values written-back +system.cpu.iew.WB:fanout_1 0.771639 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_0 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_1 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.iew.WB:penalized_rate_0 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.iew.WB:penalized_rate_1 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 7902 # num instructions producing a value -system.cpu.iew.WB:producers_0 3969 # num instructions producing a value -system.cpu.iew.WB:producers_1 3933 # num instructions producing a value -system.cpu.iew.WB:rate 0.097177 # insts written-back per cycle -system.cpu.iew.WB:rate_0 0.048821 # insts written-back per cycle -system.cpu.iew.WB:rate_1 0.048356 # insts written-back per cycle -system.cpu.iew.WB:sent 16249 # cumulative count of insts sent to commit -system.cpu.iew.WB:sent_0 8166 # cumulative count of insts sent to commit -system.cpu.iew.WB:sent_1 8083 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 1031 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 84087 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 4274 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 41 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 468 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 2288 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 20693 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 3425 # Number of load instructions executed -system.cpu.iew.iewExecLoadInsts_0 1724 # Number of load instructions executed -system.cpu.iew.iewExecLoadInsts_1 1701 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 741 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 16712 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 57 # Number of times the IQ has become full, causing a stall +system.cpu.iew.WB:producers 7820 # num instructions producing a value +system.cpu.iew.WB:producers_0 3951 # num instructions producing a value +system.cpu.iew.WB:producers_1 3869 # num instructions producing a value +system.cpu.iew.WB:rate 1.624362 # insts written-back per cycle +system.cpu.iew.WB:rate_0 0.819733 # insts written-back per cycle +system.cpu.iew.WB:rate_1 0.804629 # insts written-back per cycle +system.cpu.iew.WB:sent 15070 # cumulative count of insts sent to commit +system.cpu.iew.WB:sent_0 7606 # cumulative count of insts sent to commit +system.cpu.iew.WB:sent_1 7464 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 927 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 6 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 3744 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 40 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 587 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 2137 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 18669 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 3063 # Number of load instructions executed +system.cpu.iew.iewExecLoadInsts_0 1552 # Number of load instructions executed +system.cpu.iew.iewExecLoadInsts_1 1511 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1008 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 15334 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 1 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 4 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 1856 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 131 # Number of cycles IEW is unblocking +system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 1407 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 1 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 70 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 10 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.forwLoads 42 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 6 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 60 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.memOrderViolation 56 # Number of memory ordering violations system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 1153 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 338 # Number of stores squashed +system.cpu.iew.lsq.thread.0.squashedLoads 932 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 267 # Number of stores squashed system.cpu.iew.lsq.thread.1.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.1.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.1.forwLoads 65 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.1.ignoredResponses 12 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.1.forwLoads 49 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.1.ignoredResponses 11 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.1.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.1.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.1.memOrderViolation 59 # Number of memory ordering violations +system.cpu.iew.lsq.thread.1.memOrderViolation 57 # Number of memory ordering violations system.cpu.iew.lsq.thread.1.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.1.squashedLoads 1163 # Number of loads squashed -system.cpu.iew.lsq.thread.1.squashedStores 326 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 119 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 791 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 240 # Number of branches that were predicted taken incorrectly -system.cpu.ipc_0 0.002684 # IPC: Instructions Per Cycle -system.cpu.ipc_1 0.002684 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.005368 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0 8768 # Type of FU issued +system.cpu.iew.lsq.thread.1.squashedLoads 854 # Number of loads squashed +system.cpu.iew.lsq.thread.1.squashedStores 246 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 113 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 753 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 174 # Number of branches that were predicted taken incorrectly +system.cpu.ipc_0 0.610996 # IPC: Instructions Per Cycle +system.cpu.ipc_1 0.611105 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.222101 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0 8271 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist (null) 2 0.02% # Type of FU issued - IntAlu 5895 67.23% # Type of FU issued + IntAlu 5600 67.71% # Type of FU issued IntMult 1 0.01% # Type of FU issued IntDiv 0 0.00% # Type of FU issued FloatAdd 2 0.02% # Type of FU issued @@ -487,15 +487,15 @@ system.cpu.iq.ISSUE:FU_type_0.start_dist FloatMult 0 0.00% # Type of FU issued FloatDiv 0 0.00% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued - MemRead 1838 20.96% # Type of FU issued - MemWrite 1030 11.75% # Type of FU issued + MemRead 1701 20.57% # Type of FU issued + MemWrite 965 11.67% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.end_dist -system.cpu.iq.ISSUE:FU_type_1 8685 # Type of FU issued +system.cpu.iq.ISSUE:FU_type_1 8071 # Type of FU issued system.cpu.iq.ISSUE:FU_type_1.start_dist (null) 2 0.02% # Type of FU issued - IntAlu 5859 67.46% # Type of FU issued + IntAlu 5485 67.96% # Type of FU issued IntMult 1 0.01% # Type of FU issued IntDiv 0 0.00% # Type of FU issued FloatAdd 2 0.02% # Type of FU issued @@ -504,15 +504,15 @@ system.cpu.iq.ISSUE:FU_type_1.start_dist FloatMult 0 0.00% # Type of FU issued FloatDiv 0 0.00% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued - MemRead 1800 20.73% # Type of FU issued - MemWrite 1021 11.76% # Type of FU issued + MemRead 1640 20.32% # Type of FU issued + MemWrite 941 11.66% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_1.end_dist -system.cpu.iq.ISSUE:FU_type 17453 # Type of FU issued +system.cpu.iq.ISSUE:FU_type 16342 # Type of FU issued system.cpu.iq.ISSUE:FU_type.start_dist (null) 4 0.02% # Type of FU issued - IntAlu 11754 67.35% # Type of FU issued + IntAlu 11085 67.83% # Type of FU issued IntMult 2 0.01% # Type of FU issued IntDiv 0 0.00% # Type of FU issued FloatAdd 4 0.02% # Type of FU issued @@ -521,20 +521,20 @@ system.cpu.iq.ISSUE:FU_type.start_dist FloatMult 0 0.00% # Type of FU issued FloatDiv 0 0.00% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued - MemRead 3638 20.84% # Type of FU issued - MemWrite 2051 11.75% # Type of FU issued + MemRead 3341 20.44% # Type of FU issued + MemWrite 1906 11.66% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type.end_dist -system.cpu.iq.ISSUE:fu_busy_cnt 133 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_cnt_0 69 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_cnt_1 64 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.007620 # FU busy rate (busy events/executed inst) -system.cpu.iq.ISSUE:fu_busy_rate_0 0.003953 # FU busy rate (busy events/executed inst) -system.cpu.iq.ISSUE:fu_busy_rate_1 0.003667 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_cnt 184 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_cnt_0 95 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_cnt_1 89 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.011259 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_rate_0 0.005813 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_rate_1 0.005446 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full.start_dist (null) 0 0.00% # attempts to use FU when none available - IntAlu 0 0.00% # attempts to use FU when none available + IntAlu 11 5.98% # attempts to use FU when none available IntMult 0 0.00% # attempts to use FU when none available IntDiv 0 0.00% # attempts to use FU when none available FloatAdd 0 0.00% # attempts to use FU when none available @@ -543,133 +543,135 @@ system.cpu.iq.ISSUE:fu_full.start_dist FloatMult 0 0.00% # attempts to use FU when none available FloatDiv 0 0.00% # attempts to use FU when none available FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 79 59.40% # attempts to use FU when none available - MemWrite 54 40.60% # attempts to use FU when none available + MemRead 108 58.70% # attempts to use FU when none available + MemWrite 65 35.33% # attempts to use FU when none available IprAccess 0 0.00% # attempts to use FU when none available InstPrefetch 0 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full.end_dist system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 165688 +system.cpu.iq.ISSUE:issued_per_cycle.samples 9203 system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 156701 9457.59% - 1 4387 264.77% - 2 2473 149.26% - 3 1076 64.94% - 4 569 34.34% - 5 325 19.62% - 6 120 7.24% - 7 25 1.51% - 8 12 0.72% + 0 3452 3750.95% + 1 1399 1520.16% + 2 1479 1607.08% + 3 1070 1162.66% + 4 845 918.18% + 5 528 573.73% + 6 290 315.11% + 7 105 114.09% + 8 35 38.03% system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 system.cpu.iq.ISSUE:issued_per_cycle.end_dist -system.cpu.iq.ISSUE:rate 0.105337 # Inst issue rate -system.cpu.iq.iqInstsAdded 20568 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 17453 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 41 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 8303 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 214 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 7 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 4870 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.l2cache.ReadReq_accesses 968 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses_0 968 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 7151.675620 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency_0 7151.675620 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 3855.918388 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency_0 3855.918388 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_miss_latency 6922822 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency_0 6922822 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate_0 1 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 968 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses_0 968 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 3732529 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency_0 3732529 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate_0 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 968 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses_0 968 # number of ReadReq MSHR misses +system.cpu.iq.ISSUE:rate 1.775725 # Inst issue rate +system.cpu.iq.iqInstsAdded 18557 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 16342 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 40 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 6288 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 37 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 6 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 3616 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.l2cache.ReadReq_accesses 960 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses_0 960 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 4143.899896 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency_0 4143.899896 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2323.820647 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency_0 2323.820647 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 1 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits_0 1 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 3974000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency_0 3974000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.998958 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate_0 0.998958 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 959 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses_0 959 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 2228544 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency_0 2228544 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.998958 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate_0 0.998958 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 959 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses_0 959 # number of ReadReq MSHR misses system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 0.001043 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 968 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses_0 968 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses 960 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses_0 960 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses_1 0 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 7151.675620 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency_0 7151.675620 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency 4143.899896 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency_0 4143.899896 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency_1 <err: div-0> # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 3855.918388 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency_0 3855.918388 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 2323.820647 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency_0 2323.820647 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency_1 <err: div-0> # average overall mshr miss latency -system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits_0 0 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits 1 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits_0 1 # number of demand (read+write) hits system.cpu.l2cache.demand_hits_1 0 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 6922822 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency_0 6922822 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 3974000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency_0 3974000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency_1 0 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate_0 1 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate 0.998958 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate_0 0.998958 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate_1 <err: div-0> # miss rate for demand accesses -system.cpu.l2cache.demand_misses 968 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses_0 968 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses 959 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses_0 959 # number of demand (read+write) misses system.cpu.l2cache.demand_misses_1 0 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits_0 0 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits_1 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 3732529 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency_0 3732529 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 2228544 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency_0 2228544 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency_1 0 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate_0 1 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate 0.998958 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate_0 0.998958 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate_1 <err: div-0> # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 968 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses_0 968 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses 959 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses_0 959 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses_1 0 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.mshr_cap_events_0 0 # number of times MSHR cap was activated system.cpu.l2cache.mshr_cap_events_1 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 968 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses_0 968 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses 960 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses_0 960 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses_1 0 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 7151.675620 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency_0 7151.675620 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 4143.899896 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency_0 4143.899896 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency_1 <err: div-0> # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 3855.918388 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency_0 3855.918388 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 2323.820647 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency_0 2323.820647 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency_1 <err: div-0> # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency_0 <err: div-0> # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency_1 <err: div-0> # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 0 # number of overall hits -system.cpu.l2cache.overall_hits_0 0 # number of overall hits +system.cpu.l2cache.overall_hits 1 # number of overall hits +system.cpu.l2cache.overall_hits_0 1 # number of overall hits system.cpu.l2cache.overall_hits_1 0 # number of overall hits -system.cpu.l2cache.overall_miss_latency 6922822 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency_0 6922822 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 3974000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency_0 3974000 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency_1 0 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate_0 1 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate 0.998958 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate_0 0.998958 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate_1 <err: div-0> # miss rate for overall accesses -system.cpu.l2cache.overall_misses 968 # number of overall misses -system.cpu.l2cache.overall_misses_0 968 # number of overall misses +system.cpu.l2cache.overall_misses 959 # number of overall misses +system.cpu.l2cache.overall_misses_0 959 # number of overall misses system.cpu.l2cache.overall_misses_1 0 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits_0 0 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits_1 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 3732529 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency_0 3732529 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 2228544 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency_0 2228544 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency_1 0 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate_0 1 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.998958 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate_0 0.998958 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate_1 <err: div-0> # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 968 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses_0 968 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses 959 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses_0 959 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses_1 0 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_latency_0 0 # number of overall MSHR uncacheable cycles @@ -689,35 +691,33 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.replacements_0 0 # number of replacements system.cpu.l2cache.replacements_1 0 # number of replacements -system.cpu.l2cache.sampled_refs 968 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 959 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.l2cache.soft_prefetch_mshr_full_0 0 # number of mshr full events for SW prefetching instrutions system.cpu.l2cache.soft_prefetch_mshr_full_1 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 491.189820 # Cycle average of tags in use -system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 534.228654 # Cycle average of tags in use +system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.l2cache.writebacks_0 0 # number of writebacks system.cpu.l2cache.writebacks_1 0 # number of writebacks -system.cpu.numCycles 165688 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 87802 # Number of cycles rename is blocking +system.cpu.numCycles 9203 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 514 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 8102 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 24 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 213369 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 2127 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:ROBFullEvents 18 # Number of times rename has blocked due to ROB full -system.cpu.rename.RENAME:RenameLookups 28570 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 22635 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 17117 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 3694 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 1856 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 2143 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 9015 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 22337 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 51 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 4330 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 37 # count of temporary serializing insts renamed -system.cpu.timesIdled 688 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.rename.RENAME:IdleCycles 11467 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 762 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:RenameLookups 26335 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 20742 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 15622 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 3447 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 1407 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 876 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 7520 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 508 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 48 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 2622 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 38 # count of temporary serializing insts renamed +system.cpu.timesIdled 1 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload0.PROG:num_syscalls 17 # Number of system calls system.cpu.workload1.PROG:num_syscalls 17 # Number of system calls diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stderr b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stderr index 54505c240..d0a887867 100644 --- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stderr +++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stderr @@ -1,5 +1,3 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7001 -0: system.remote_gdb.listener: listening for remote gdb on port 7002 warn: Entering event queue @ 0. Starting simulation... warn: Increasing stack size by one page. warn: Increasing stack size by one page. diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout index b4ae56cae..ea08dc448 100644 --- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout +++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout @@ -7,9 +7,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Mar 30 2007 13:12:55 -M5 started Fri Mar 30 13:13:07 2007 +M5 compiled Apr 21 2007 21:50:58 +M5 started Sat Apr 21 21:51:11 2007 M5 executing on zamp.eecs.umich.edu command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/01.hello-2T-smt/alpha/linux/o3-timing tests/run.py quick/01.hello-2T-smt/alpha/linux/o3-timing Global frequency set at 1000000000000 ticks per second -Exiting @ tick 2095164 because target called exit() +Exiting @ tick 4600500 because target called exit() diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.ini b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.ini index 71c721b07..0c1dbb0ba 100644 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.ini +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.ini @@ -1,51 +1,7 @@ [root] type=Root children=system -checkpoint= -clock=1000000000000 -max_tick=0 -output_file=cout -progress_interval=0 - -[debug] -break_cycles= - -[exetrace] -intel_format=false -legion_lockstep=false -pc_symbol=true -print_cpseq=false -print_cycle=true -print_data=true -print_effaddr=true -print_fetchseq=false -print_iregs=false -print_opclass=true -print_thread=true -speculative=true -trace_system=client - -[serialize] -count=10 -cycle=0 -dir=cpt.%012d -period=0 - -[stats] -descriptions=true -dump_cycle=0 -dump_period=0 -dump_reset=false -ignore_events= -mysql_db= -mysql_host= -mysql_password= -mysql_user= -project_name=test -simulation_name=test -simulation_sample=0 -text_compat=true -text_file=m5stats.txt +dummy=0 [system] type=System @@ -56,7 +12,7 @@ physmem=system.physmem [system.cpu] type=AtomicSimpleCPU children=workload -clock=1 +clock=500 cpu_id=0 defer_registration=false function_trace=false @@ -65,6 +21,7 @@ max_insts_all_threads=0 max_insts_any_thread=500000 max_loads_all_threads=0 max_loads_any_thread=0 +phase=0 progress_interval=0 simulate_stalls=false system=system @@ -93,14 +50,6 @@ type=PhysicalMemory file= latency=1 range=0:134217727 +zero=false port=system.membus.port[0] -[trace] -bufsize=0 -cycle=0 -dump_on_exit=false -file=cout -flags= -ignore= -start=0 - diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.out b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.out index 95a0614c9..5e988f3f9 100644 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.out +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.out @@ -1,15 +1,13 @@ [root] type=Root -clock=1000000000000 -max_tick=0 -progress_interval=0 -output_file=cout +dummy=0 [system.physmem] type=PhysicalMemory file= range=[0,134217727] latency=1 +zero=false [system] type=System @@ -40,61 +38,11 @@ progress_interval=0 system=system cpu_id=0 workload=system.cpu.workload -clock=1 +clock=500 +phase=0 defer_registration=false width=1 function_trace=false function_trace_start=0 simulate_stalls=false -[trace] -flags= -start=0 -cycle=0 -bufsize=0 -file=cout -dump_on_exit=false -ignore= - -[stats] -descriptions=true -project_name=test -simulation_name=test -simulation_sample=0 -text_file=m5stats.txt -text_compat=true -mysql_db= -mysql_user= -mysql_password= -mysql_host= -events_start=-1 -dump_reset=false -dump_cycle=0 -dump_period=0 -ignore_events= - -[random] -seed=1 - -[exetrace] -speculative=true -print_cycle=true -print_opclass=true -print_thread=true -print_effaddr=true -print_data=true -print_iregs=false -print_fetchseq=false -print_cpseq=false -print_reg_delta=false -pc_symbol=true -intel_format=false -legion_lockstep=false -trace_system=client - -[debug] -break_cycles= - -[statsreset] -reset_cycle=0 - diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/m5stats.txt b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/m5stats.txt index 50d3a76c7..bc0a96087 100644 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/m5stats.txt +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/m5stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1281059 # Simulator instruction rate (inst/s) -host_mem_usage 147756 # Number of bytes of host memory used -host_seconds 0.39 # Real time elapsed on the host -host_tick_rate 1279755 # Simulator tick rate (ticks/s) +host_inst_rate 689098 # Simulator instruction rate (inst/s) +host_mem_usage 147724 # Number of bytes of host memory used +host_seconds 0.73 # Real time elapsed on the host +host_tick_rate 344128671 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 500000 # Number of instructions simulated -sim_seconds 0.000000 # Number of seconds simulated -sim_ticks 499999 # Number of ticks simulated +sim_seconds 0.000250 # Number of seconds simulated +sim_ticks 249999500 # Number of ticks simulated system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 500000 # number of cpu cycles simulated diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stdout b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stdout index 18a78c936..47ee09274 100644 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stdout +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stdout @@ -7,8 +7,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 3 2006 17:10:27 -M5 started Fri Nov 3 17:10:57 2006 -M5 executing on zizzer.eecs.umich.edu -command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/20.eio-short/alpha/eio/simple-atomic tests/run.py quick/20.eio-short/alpha/eio/simple-atomic -Exiting @ tick 499999 because a thread reached the max instruction count +M5 compiled Apr 21 2007 21:50:58 +M5 started Sat Apr 21 21:51:12 2007 +M5 executing on zamp.eecs.umich.edu +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-atomic tests/run.py quick/20.eio-short/alpha/eio/simple-atomic +Global frequency set at 1000000000000 ticks per second +Exiting @ tick 249999500 because a thread reached the max instruction count diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini index 2be814794..eef4c0a1a 100644 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini @@ -1,51 +1,7 @@ [root] type=Root children=system -checkpoint= -clock=1000000000000 -max_tick=0 -output_file=cout -progress_interval=0 - -[debug] -break_cycles= - -[exetrace] -intel_format=false -legion_lockstep=false -pc_symbol=true -print_cpseq=false -print_cycle=true -print_data=true -print_effaddr=true -print_fetchseq=false -print_iregs=false -print_opclass=true -print_thread=true -speculative=true -trace_system=client - -[serialize] -count=10 -cycle=0 -dir=cpt.%012d -period=0 - -[stats] -descriptions=true -dump_cycle=0 -dump_period=0 -dump_reset=false -ignore_events= -mysql_db= -mysql_host= -mysql_password= -mysql_user= -project_name=test -simulation_name=test -simulation_sample=0 -text_compat=true -text_file=m5stats.txt +dummy=0 [system] type=System @@ -56,7 +12,7 @@ physmem=system.physmem [system.cpu] type=TimingSimpleCPU children=dcache icache l2cache toL2Bus workload -clock=1 +clock=500 cpu_id=0 defer_registration=false function_trace=false @@ -65,6 +21,7 @@ max_insts_all_threads=0 max_insts_any_thread=500000 max_loads_all_threads=0 max_loads_any_thread=0 +phase=0 progress_interval=0 system=system workload=system.cpu.workload @@ -216,14 +173,6 @@ type=PhysicalMemory file= latency=1 range=0:134217727 +zero=false port=system.membus.port[0] -[trace] -bufsize=0 -cycle=0 -dump_on_exit=false -file=cout -flags= -ignore= -start=0 - diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.out b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.out index bd0dbfad0..e897b733f 100644 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.out +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.out @@ -1,15 +1,13 @@ [root] type=Root -clock=1000000000000 -max_tick=0 -progress_interval=0 -output_file=cout +dummy=0 [system.physmem] type=PhysicalMemory file= range=[0,134217727] latency=1 +zero=false [system] type=System @@ -40,7 +38,8 @@ progress_interval=0 system=system cpu_id=0 workload=system.cpu.workload -clock=1 +clock=500 +phase=0 defer_registration=false // width not specified function_trace=false @@ -168,54 +167,3 @@ prefetch_use_cpu_id=true prefetch_data_accesses_only=false hit_latency=1 -[trace] -flags= -start=0 -cycle=0 -bufsize=0 -file=cout -dump_on_exit=false -ignore= - -[stats] -descriptions=true -project_name=test -simulation_name=test -simulation_sample=0 -text_file=m5stats.txt -text_compat=true -mysql_db= -mysql_user= -mysql_password= -mysql_host= -events_start=-1 -dump_reset=false -dump_cycle=0 -dump_period=0 -ignore_events= - -[random] -seed=1 - -[exetrace] -speculative=true -print_cycle=true -print_opclass=true -print_thread=true -print_effaddr=true -print_data=true -print_iregs=false -print_fetchseq=false -print_cpseq=false -print_reg_delta=false -pc_symbol=true -intel_format=false -legion_lockstep=false -trace_system=client - -[debug] -break_cycles= - -[statsreset] -reset_cycle=0 - diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt index d8d06877e..a6caa5891 100644 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt @@ -1,31 +1,31 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 542626 # Simulator instruction rate (inst/s) -host_mem_usage 178896 # Number of bytes of host memory used -host_seconds 0.92 # Real time elapsed on the host -host_tick_rate 4319791 # Simulator tick rate (ticks/s) +host_inst_rate 518674 # Simulator instruction rate (inst/s) +host_mem_usage 153108 # Number of bytes of host memory used +host_seconds 0.96 # Real time elapsed on the host +host_tick_rate 355827019 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 500000 # Number of instructions simulated -sim_seconds 0.000004 # Number of seconds simulated -sim_ticks 3982316 # Number of ticks simulated +sim_seconds 0.000343 # Number of seconds simulated +sim_ticks 343161000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 124435 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 3670.641270 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2670.641270 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 3793.650794 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2793.650794 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 124120 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 1156252 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 1195000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.002531 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 315 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 841252 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 880000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.002531 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 315 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 56340 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 3907.374101 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2907.374101 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 3600.719424 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2600.719424 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 56201 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 543125 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 500500 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.002467 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 139 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 404125 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 361500 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.002467 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 139 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -37,29 +37,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 180775 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 3743.121145 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 2743.121145 # average overall mshr miss latency +system.cpu.dcache.demand_avg_miss_latency 3734.581498 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 2734.581498 # average overall mshr miss latency system.cpu.dcache.demand_hits 180321 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 1699377 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency 1695500 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.002511 # miss rate for demand accesses system.cpu.dcache.demand_misses 454 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 1245377 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 1241500 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.002511 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 454 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.overall_accesses 180775 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 3743.121145 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 2743.121145 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 3734.581498 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 2734.581498 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 180321 # number of overall hits -system.cpu.dcache.overall_miss_latency 1699377 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency 1695500 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.002511 # miss rate for overall accesses system.cpu.dcache.overall_misses 454 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 1245377 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 1241500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.002511 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 454 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -76,18 +76,18 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 454 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 227.376906 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 291.533202 # Cycle average of tags in use system.cpu.dcache.total_refs 180321 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks system.cpu.icache.ReadReq_accesses 500000 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 3977.722084 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 2977.722084 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_miss_latency 3739.454094 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 2739.454094 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_hits 499597 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 1603022 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency 1507000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000806 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 403 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 1200022 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 1104000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000806 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 403 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -99,29 +99,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 500000 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 3977.722084 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 2977.722084 # average overall mshr miss latency +system.cpu.icache.demand_avg_miss_latency 3739.454094 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 2739.454094 # average overall mshr miss latency system.cpu.icache.demand_hits 499597 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 1603022 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency 1507000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000806 # miss rate for demand accesses system.cpu.icache.demand_misses 403 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 1200022 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 1104000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.000806 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 403 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.overall_accesses 500000 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 3977.722084 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 2977.722084 # average overall mshr miss latency +system.cpu.icache.overall_avg_miss_latency 3739.454094 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 2739.454094 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.icache.overall_hits 499597 # number of overall hits -system.cpu.icache.overall_miss_latency 1603022 # number of overall miss cycles +system.cpu.icache.overall_miss_latency 1507000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000806 # miss rate for overall accesses system.cpu.icache.overall_misses 403 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 1200022 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 1104000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.000806 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 403 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -138,18 +138,18 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 0 # number of replacements system.cpu.icache.sampled_refs 403 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 221.721362 # Cycle average of tags in use +system.cpu.icache.tagsinuse 268.106513 # Cycle average of tags in use system.cpu.icache.total_refs 499597 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.l2cache.ReadReq_accesses 857 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 2853.441074 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1852.441074 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_miss_latency 2445399 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_avg_miss_latency 2736.872812 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1735.872812 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_miss_latency 2345500 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 857 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1587542 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 1487643 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 857 # number of ReadReq MSHR misses system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -161,29 +161,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 # system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 857 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 2853.441074 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 1852.441074 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_miss_latency 2736.872812 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 1735.872812 # average overall mshr miss latency system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 2445399 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 2345500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses system.cpu.l2cache.demand_misses 857 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 1587542 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 1487643 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 857 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.overall_accesses 857 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 2853.441074 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 1852.441074 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_miss_latency 2736.872812 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 1735.872812 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 0 # number of overall hits -system.cpu.l2cache.overall_miss_latency 2445399 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 2345500 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses system.cpu.l2cache.overall_misses 857 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 1587542 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 1487643 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 857 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -200,12 +200,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.sampled_refs 857 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 449.313470 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 559.642213 # Cycle average of tags in use system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 3982316 # number of cpu cycles simulated +system.cpu.numCycles 343161000 # number of cpu cycles simulated system.cpu.num_insts 500000 # Number of instructions executed system.cpu.num_refs 182203 # Number of memory references system.cpu.workload.PROG:num_syscalls 18 # Number of system calls diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stdout b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stdout index 787ea041d..8126fb0fb 100644 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stdout +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stdout @@ -7,8 +7,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 3 2006 17:10:27 -M5 started Fri Nov 3 17:10:58 2006 -M5 executing on zizzer.eecs.umich.edu -command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/20.eio-short/alpha/eio/simple-timing tests/run.py quick/20.eio-short/alpha/eio/simple-timing -Exiting @ tick 3982316 because a thread reached the max instruction count +M5 compiled Apr 21 2007 21:50:58 +M5 started Sat Apr 21 21:51:14 2007 +M5 executing on zamp.eecs.umich.edu +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-timing tests/run.py quick/20.eio-short/alpha/eio/simple-timing +Global frequency set at 1000000000000 ticks per second +Exiting @ tick 343161000 because a thread reached the max instruction count diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest/config.ini b/tests/quick/50.memtest/ref/alpha/linux/memtest/config.ini index 05eb91461..363cb64d4 100644 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest/config.ini +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest/config.ini @@ -1,48 +1,7 @@ [root] type=Root children=system -checkpoint= -clock=1000000000000 -max_tick=0 -output_file=cout -progress_interval=0 - -[exetrace] -intel_format=false -legion_lockstep=false -pc_symbol=true -print_cpseq=false -print_cycle=true -print_data=true -print_effaddr=true -print_fetchseq=false -print_iregs=false -print_opclass=true -print_thread=true -speculative=true -trace_system=client - -[serialize] -count=10 -cycle=0 -dir=cpt.%012d -period=0 - -[stats] -descriptions=true -dump_cycle=0 -dump_period=0 -dump_reset=false -ignore_events= -mysql_db= -mysql_host= -mysql_password= -mysql_user= -project_name=test -simulation_name=test -simulation_sample=0 -text_compat=true -text_file=m5stats.txt +dummy=0 [system] type=System @@ -610,12 +569,3 @@ responder_set=false width=16 port=system.l2c.cpu_side system.cpu0.l1c.mem_side system.cpu1.l1c.mem_side system.cpu2.l1c.mem_side system.cpu3.l1c.mem_side system.cpu4.l1c.mem_side system.cpu5.l1c.mem_side system.cpu6.l1c.mem_side system.cpu7.l1c.mem_side -[trace] -bufsize=0 -cycle=0 -dump_on_exit=false -file=cout -flags= -ignore= -start=0 - diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest/config.out b/tests/quick/50.memtest/ref/alpha/linux/memtest/config.out index b8ae04bc0..b3f4ec871 100644 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest/config.out +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest/config.out @@ -1,9 +1,6 @@ [root] type=Root -clock=1000000000000 -max_tick=0 -progress_interval=0 -output_file=cout +dummy=0 [system.physmem] type=PhysicalMemory @@ -524,51 +521,3 @@ clock=2 width=16 responder_set=false -[trace] -flags= -start=0 -cycle=0 -bufsize=0 -file=cout -dump_on_exit=false -ignore= - -[stats] -descriptions=true -project_name=test -simulation_name=test -simulation_sample=0 -text_file=m5stats.txt -text_compat=true -mysql_db= -mysql_user= -mysql_password= -mysql_host= -events_start=-1 -dump_reset=false -dump_cycle=0 -dump_period=0 -ignore_events= - -[random] -seed=1 - -[exetrace] -speculative=true -print_cycle=true -print_opclass=true -print_thread=true -print_effaddr=true -print_data=true -print_iregs=false -print_fetchseq=false -print_cpseq=false -print_reg_delta=false -pc_symbol=true -intel_format=false -legion_lockstep=false -trace_system=client - -[statsreset] -reset_cycle=0 - diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest/m5stats.txt b/tests/quick/50.memtest/ref/alpha/linux/memtest/m5stats.txt index a65b235b0..285ab3702 100644 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest/m5stats.txt +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest/m5stats.txt @@ -1,8 +1,8 @@ ---------- Begin Simulation Statistics ---------- -host_mem_usage 435124 # Number of bytes of host memory used -host_seconds 28.46 # Real time elapsed on the host -host_tick_rate 202211 # Simulator tick rate (ticks/s) +host_mem_usage 303680 # Number of bytes of host memory used +host_seconds 32.50 # Real time elapsed on the host +host_tick_rate 177110 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_seconds 0.000006 # Number of seconds simulated sim_ticks 5755736 # Number of ticks simulated @@ -887,15 +887,15 @@ system.l2c.ReadReq_mshr_misses 66414 # nu system.l2c.ReadReq_mshr_uncacheable 78703 # number of ReadReq MSHR uncacheable system.l2c.ReadResp_avg_mshr_uncacheable_latency inf # average ReadResp mshr uncacheable latency system.l2c.ReadResp_mshr_uncacheable_latency 420484 # number of ReadResp MSHR uncacheable cycles -system.l2c.WriteReqNoAck|Writeback_accesses 86614 # number of WriteReqNoAck|Writeback accesses(hits+misses) -system.l2c.WriteReqNoAck|Writeback_hits 18299 # number of WriteReqNoAck|Writeback hits -system.l2c.WriteReqNoAck|Writeback_miss_rate 0.788729 # miss rate for WriteReqNoAck|Writeback accesses -system.l2c.WriteReqNoAck|Writeback_misses 68315 # number of WriteReqNoAck|Writeback misses -system.l2c.WriteReqNoAck|Writeback_mshr_miss_rate 0.788729 # mshr miss rate for WriteReqNoAck|Writeback accesses -system.l2c.WriteReqNoAck|Writeback_mshr_misses 68315 # number of WriteReqNoAck|Writeback MSHR misses system.l2c.WriteReq_mshr_uncacheable 42661 # number of WriteReq MSHR uncacheable system.l2c.WriteResp_avg_mshr_uncacheable_latency inf # average WriteResp mshr uncacheable latency system.l2c.WriteResp_mshr_uncacheable_latency 298282 # number of WriteResp MSHR uncacheable cycles +system.l2c.Writeback_accesses 86614 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_hits 18299 # number of Writeback hits +system.l2c.Writeback_miss_rate 0.788729 # miss rate for Writeback accesses +system.l2c.Writeback_misses 68315 # number of Writeback misses +system.l2c.Writeback_mshr_miss_rate 0.788729 # mshr miss rate for Writeback accesses +system.l2c.Writeback_mshr_misses 68315 # number of Writeback MSHR misses system.l2c.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.l2c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked system.l2c.avg_refs 1.277186 # Average number of references to valid blocks. diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest/stdout b/tests/quick/50.memtest/ref/alpha/linux/memtest/stdout index 3d3289d71..ea4812a6d 100644 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest/stdout +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest/stdout @@ -5,9 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 6 2007 20:30:01 -M5 started Tue Feb 6 21:04:07 2007 -M5 executing on vm1 +M5 compiled Apr 21 2007 21:50:58 +M5 started Sat Apr 21 21:51:15 2007 +M5 executing on zamp.eecs.umich.edu command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/50.memtest/alpha/linux/memtest tests/run.py quick/50.memtest/alpha/linux/memtest warning: overwriting port funcmem.functional value cpu1.functional with cpu2.functional warning: overwriting port funcmem.functional value cpu2.functional with cpu3.functional @@ -15,4 +15,5 @@ warning: overwriting port funcmem.functional value cpu3.functional with cpu4.fun warning: overwriting port funcmem.functional value cpu4.functional with cpu5.functional warning: overwriting port funcmem.functional value cpu5.functional with cpu6.functional warning: overwriting port funcmem.functional value cpu6.functional with cpu7.functional +Global frequency set at 1000000000000 ticks per second Exiting @ tick 5755736 because Maximum number of loads reached! |