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authorAli Saidi <saidi@eecs.umich.edu>2007-11-08 10:46:41 -0500
committerAli Saidi <saidi@eecs.umich.edu>2007-11-08 10:46:41 -0500
commite41197a3f8e93a1c67dddccc96a54e6f560386b2 (patch)
treeedad4e900baa21dfa8c95fb2ae6586911e2c8447
parent17e83e7f8346a25a313e4fc58ed7008b46fd818f (diff)
downloadgem5-e41197a3f8e93a1c67dddccc96a54e6f560386b2.tar.xz
CPU: Add function to explictly compare thread contexts after copying.
--HG-- extra : convert_revision : 9b7af59a11202a91409aad7c427b7749cd1d2f12
-rw-r--r--src/arch/alpha/SConscript2
-rw-r--r--src/cpu/SConscript2
-rw-r--r--src/cpu/base.cc3
-rw-r--r--src/cpu/thread_context.cc81
-rw-r--r--src/cpu/thread_context.hh3
5 files changed, 88 insertions, 3 deletions
diff --git a/src/arch/alpha/SConscript b/src/arch/alpha/SConscript
index ca20cf585..04bac3996 100644
--- a/src/arch/alpha/SConscript
+++ b/src/arch/alpha/SConscript
@@ -75,5 +75,3 @@ if env['TARGET_ISA'] == 'alpha':
for f in isa_desc_files:
if not f.path.endswith('.hh'):
Source(f)
-
- TraceFlag('Context')
diff --git a/src/cpu/SConscript b/src/cpu/SConscript
index 6b43c6c16..c7d0c33bd 100644
--- a/src/cpu/SConscript
+++ b/src/cpu/SConscript
@@ -118,6 +118,7 @@ Source('pc_event.cc')
Source('quiesce_event.cc')
Source('static_inst.cc')
Source('simple_thread.cc')
+Source('thread_context.cc')
Source('thread_state.cc')
if env['FULL_SYSTEM']:
@@ -150,6 +151,7 @@ if env['USE_CHECKER']:
TraceFlag('Activity')
TraceFlag('Commit')
+TraceFlag('Context')
TraceFlag('Decode')
TraceFlag('DynInst')
TraceFlag('ExecEnable')
diff --git a/src/cpu/base.cc b/src/cpu/base.cc
index 25bd3f893..7b04f5a90 100644
--- a/src/cpu/base.cc
+++ b/src/cpu/base.cc
@@ -334,7 +334,8 @@ BaseCPU::takeOverFrom(BaseCPU *oldCPU, Port *ic, Port *dc)
newTC->getProcessPtr()->replaceThreadContext(newTC, newTC->readCpuId());
#endif
-// TheISA::compareXCs(oldXC, newXC);
+ if (DTRACE(Context))
+ ThreadContext::compare(oldTC, newTC);
}
#if FULL_SYSTEM
diff --git a/src/cpu/thread_context.cc b/src/cpu/thread_context.cc
new file mode 100644
index 000000000..10c94027d
--- /dev/null
+++ b/src/cpu/thread_context.cc
@@ -0,0 +1,81 @@
+/*
+ * Copyright (c) 2006 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Kevin Lim
+ */
+
+#include "base/misc.hh"
+#include "base/trace.hh"
+#include "cpu/thread_context.hh"
+
+void
+ThreadContext::compare(ThreadContext *one, ThreadContext *two)
+{
+ DPRINTF(Context, "Comparing thread contexts\n");
+
+ // First loop through the integer registers.
+ for (int i = 0; i < TheISA::NumIntRegs; ++i) {
+ TheISA::IntReg t1 = one->readIntReg(i);
+ TheISA::IntReg t2 = two->readIntReg(i);
+ if (t1 != t2)
+ panic("Int reg idx %d doesn't match, one: %#x, two: %#x",
+ i, t1, t2);
+ }
+
+ // Then loop through the floating point registers.
+ for (int i = 0; i < TheISA::NumFloatRegs; ++i) {
+ TheISA::FloatRegBits t1 = one->readFloatRegBits(i);
+ TheISA::FloatRegBits t2 = two->readFloatRegBits(i);
+ if (t1 != t2)
+ panic("Float reg idx %d doesn't match, one: %#x, two: %#x",
+ i, t1, t2);
+ }
+#if FULL_SYSTEM
+ for (int i = 0; i < TheISA::NumMiscRegs; ++i) {
+ TheISA::MiscReg t1 = one->readMiscRegNoEffect(i);
+ TheISA::MiscReg t2 = two->readMiscRegNoEffect(i);
+ if (t1 != t2)
+ panic("Misc reg idx %d doesn't match, one: %#x, two: %#x",
+ i, t1, t2);
+ }
+#endif
+
+ Addr pc1 = one->readPC();
+ Addr pc2 = two->readPC();
+ if (pc1 != pc2)
+ panic("PCs doesn't match, one: %#x, two: %#x", pc1, pc2);
+
+ Addr npc1 = one->readNextPC();
+ Addr npc2 = two->readNextPC();
+ if (npc1 != npc2)
+ panic("NPCs doesn't match, one: %#x, two: %#x", npc1, npc2);
+
+ int id1 = one->readCpuId();
+ int id2 = two->readCpuId();
+ if (id1 != id2)
+ panic("CPU ids don't match, one: %d, two: %d", id1, id2);
+}
diff --git a/src/cpu/thread_context.hh b/src/cpu/thread_context.hh
index 1af029093..31fdb42c2 100644
--- a/src/cpu/thread_context.hh
+++ b/src/cpu/thread_context.hh
@@ -268,6 +268,9 @@ class ThreadContext
virtual void changeRegFileContext(TheISA::RegContextParam param,
TheISA::RegContextVal val) = 0;
+
+ /** function to compare two thread contexts (for debugging) */
+ static void compare(ThreadContext *one, ThreadContext *two);
};
/**