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| author | Nilay Vaish <nilay@cs.wisc.edu> | 2015-07-21 10:08:25 -0500 |
|---|---|---|
| committer | Nilay Vaish <nilay@cs.wisc.edu> | 2015-07-21 10:08:25 -0500 |
| commit | 0b163ea7078058a837c6df801420555b63c6f665 (patch) | |
| tree | c0bff56fe736b3eecb54820f0876be8af4b47c0b | |
| parent | c47001de8c242e2335243dadd0a49956d7036c8f (diff) | |
| download | gem5-0b163ea7078058a837c6df801420555b63c6f665.tar.xz | |
configs: network test: remove redundant physical memory
| -rw-r--r-- | configs/example/ruby_network_test.py | 5 |
1 files changed, 2 insertions, 3 deletions
diff --git a/configs/example/ruby_network_test.py b/configs/example/ruby_network_test.py index 6e9a88431..f0e075055 100644 --- a/configs/example/ruby_network_test.py +++ b/configs/example/ruby_network_test.py @@ -103,8 +103,7 @@ cpus = [ NetworkTest(fixed_pkts=options.fixed_pkts, for i in xrange(options.num_cpus) ] # create the desired simulated system -system = System(cpu = cpus, physmem = SimpleMemory(), - mem_ranges = [AddrRange(options.mem_size)]) +system = System(cpu = cpus, mem_ranges = [AddrRange(options.mem_size)]) # Create a top-level voltage domain and clock domain @@ -131,7 +130,7 @@ for ruby_port in system.ruby._cpu_ports: # run simulation # ----------------------- -root = Root( full_system = False, system = system ) +root = Root(full_system = False, system = system) root.system.mem_mode = 'timing' # Not much point in this being higher than the L1 latency |