cpu: rename *_DepTag constants to *_Reg_Base

Make these names more meaningful.

Specifically, made these substitutions:

s/FP_Base_DepTag/FP_Reg_Base/g;
s/Ctrl_Base_DepTag/Misc_Reg_Base/g;
s/Max_DepTag/Max_Reg_Index/g;

24 files changed, 104 insertions, 104 deletions

diff --git a/src/arch/alpha/isa/fp.isa b/src/arch/alpha/isa/fp.isa
index 5821ebcc5..e4b4c66c6 100644
--- a/src/arch/alpha/isa/fp.isa
+++ b/src/arch/alpha/isa/fp.isa
@@ -149,7 +149,7 @@ output decoder {{
 
 #ifndef SS_COMPATIBLE_DISASSEMBLY
         std::string suffix("");
-        suffix += ((_destRegIdx[0] >= FP_Base_DepTag)
+        suffix += ((_destRegIdx[0] >= FP_Reg_Base)
                    ? fpTrappingModeSuffix[trappingMode]
                    : intTrappingModeSuffix[trappingMode]);
         suffix += roundingModeSuffix[roundingMode];
diff --git a/src/arch/alpha/isa/main.isa b/src/arch/alpha/isa/main.isa
index cb43c1357..4d7dccb15 100644
--- a/src/arch/alpha/isa/main.isa
+++ b/src/arch/alpha/isa/main.isa
@@ -224,7 +224,7 @@ output header {{
         /// this class and derived classes.  Maybe these should really
         /// live here and not in the AlphaISA namespace.
         enum DependenceTags {
-            FP_Base_DepTag = AlphaISA::FP_Base_DepTag
+            FP_Reg_Base = AlphaISA::FP_Reg_Base
         };
 
         /// Constructor.
@@ -253,11 +253,11 @@ output decoder {{
     void
     AlphaStaticInst::printReg(std::ostream &os, int reg) const
     {
-        if (reg < FP_Base_DepTag) {
+        if (reg < FP_Reg_Base) {
             ccprintf(os, "r%d", reg);
         }
         else {
-            ccprintf(os, "f%d", reg - FP_Base_DepTag);
+            ccprintf(os, "f%d", reg - FP_Reg_Base);
         }
     }
 
diff --git a/src/arch/alpha/registers.hh b/src/arch/alpha/registers.hh
index 6f0b02c7f..92ba22ee8 100644
--- a/src/arch/alpha/registers.hh
+++ b/src/arch/alpha/registers.hh
@@ -99,10 +99,10 @@ const int TotalNumRegs =
 // These enumerate all the registers for dependence tracking.
 enum DependenceTags {
     // 0..31 are the integer regs 0..31
-    // 32..63 are the FP regs 0..31, i.e. use (reg + FP_Base_DepTag)
-    FP_Base_DepTag = NumIntRegs,
-    Ctrl_Base_DepTag = FP_Base_DepTag + NumFloatRegs,
-    Max_DepTag = Ctrl_Base_DepTag + NumMiscRegs + NumInternalProcRegs
+    // 32..63 are the FP regs 0..31, i.e. use (reg + FP_Reg_Base)
+    FP_Reg_Base = NumIntRegs,
+    Misc_Reg_Base = FP_Reg_Base + NumFloatRegs,
+    Max_Reg_Index = Misc_Reg_Base + NumMiscRegs + NumInternalProcRegs
 };
 
 } // namespace AlphaISA
diff --git a/src/arch/arm/insts/misc.cc b/src/arch/arm/insts/misc.cc
index c40b6711f..6320bb6da 100644
--- a/src/arch/arm/insts/misc.cc
+++ b/src/arch/arm/insts/misc.cc
@@ -80,10 +80,10 @@ MsrBase::printMsrBase(std::ostream &os) const
     bool foundPsr = false;
     for (unsigned i = 0; i < numDestRegs(); i++) {
         int idx = destRegIdx(i);
-        if (idx < Ctrl_Base_DepTag) {
+        if (idx < Misc_Reg_Base) {
             continue;
         }
-        idx -= Ctrl_Base_DepTag;
+        idx -= Misc_Reg_Base;
         if (idx == MISCREG_CPSR) {
             os << "cpsr_";
             foundPsr = true;
diff --git a/src/arch/arm/insts/vfp.cc b/src/arch/arm/insts/vfp.cc
index 015247d68..ca0f58226 100644
--- a/src/arch/arm/insts/vfp.cc
+++ b/src/arch/arm/insts/vfp.cc
@@ -50,9 +50,9 @@ FpRegRegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss);
-    printReg(ss, dest + FP_Base_DepTag);
+    printReg(ss, dest + FP_Reg_Base);
     ss << ", ";
-    printReg(ss, op1 + FP_Base_DepTag);
+    printReg(ss, op1 + FP_Reg_Base);
     return ss.str();
 }
 
@@ -61,7 +61,7 @@ FpRegImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss);
-    printReg(ss, dest + FP_Base_DepTag);
+    printReg(ss, dest + FP_Reg_Base);
     ccprintf(ss, ", #%d", imm);
     return ss.str();
 }
@@ -71,9 +71,9 @@ FpRegRegImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss);
-    printReg(ss, dest + FP_Base_DepTag);
+    printReg(ss, dest + FP_Reg_Base);
     ss << ", ";
-    printReg(ss, op1 + FP_Base_DepTag);
+    printReg(ss, op1 + FP_Reg_Base);
     ccprintf(ss, ", #%d", imm);
     return ss.str();
 }
@@ -83,11 +83,11 @@ FpRegRegRegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss);
-    printReg(ss, dest + FP_Base_DepTag);
+    printReg(ss, dest + FP_Reg_Base);
     ss << ", ";
-    printReg(ss, op1 + FP_Base_DepTag);
+    printReg(ss, op1 + FP_Reg_Base);
     ss << ", ";
-    printReg(ss, op2 + FP_Base_DepTag);
+    printReg(ss, op2 + FP_Reg_Base);
     return ss.str();
 }
 
@@ -96,11 +96,11 @@ FpRegRegRegImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss);
-    printReg(ss, dest + FP_Base_DepTag);
+    printReg(ss, dest + FP_Reg_Base);
     ss << ", ";
-    printReg(ss, op1 + FP_Base_DepTag);
+    printReg(ss, op1 + FP_Reg_Base);
     ss << ", ";
-    printReg(ss, op2 + FP_Base_DepTag);
+    printReg(ss, op2 + FP_Reg_Base);
     ccprintf(ss, ", #%d", imm);
     return ss.str();
 }
diff --git a/src/arch/arm/registers.hh b/src/arch/arm/registers.hh
index cd2f1f9b8..cc4fac824 100644
--- a/src/arch/arm/registers.hh
+++ b/src/arch/arm/registers.hh
@@ -101,9 +101,9 @@ const int SyscallPseudoReturnReg = ReturnValueReg;
 const int SyscallSuccessReg = ReturnValueReg;
 
 // These help enumerate all the registers for dependence tracking.
-const int FP_Base_DepTag = NumIntRegs * (MODE_MAXMODE + 1);
-const int Ctrl_Base_DepTag = FP_Base_DepTag + NumFloatRegs;
-const int Max_DepTag = Ctrl_Base_DepTag + NumMiscRegs;
+const int FP_Reg_Base = NumIntRegs * (MODE_MAXMODE + 1);
+const int Misc_Reg_Base = FP_Reg_Base + NumFloatRegs;
+const int Max_Reg_Index = Misc_Reg_Base + NumMiscRegs;
 
 typedef union {
     IntReg   intreg;
diff --git a/src/arch/isa_parser.py b/src/arch/isa_parser.py
index ec0efe5e6..e4f81c173 100755
--- a/src/arch/isa_parser.py
+++ b/src/arch/isa_parser.py
@@ -610,12 +610,12 @@ class FloatRegOperand(Operand):
         c_dest = ''
 
         if self.is_src:
-            c_src = '\n\t_srcRegIdx[_numSrcRegs++] = %s + FP_Base_DepTag;' % \
+            c_src = '\n\t_srcRegIdx[_numSrcRegs++] = %s + FP_Reg_Base;' % \
                     (self.reg_spec)
 
         if self.is_dest:
             c_dest = \
-              '\n\t_destRegIdx[_numDestRegs++] = %s + FP_Base_DepTag;' % \
+              '\n\t_destRegIdx[_numDestRegs++] = %s + FP_Reg_Base;' % \
               (self.reg_spec)
             c_dest += '\n\t_numFPDestRegs++;'
 
@@ -673,12 +673,12 @@ class ControlRegOperand(Operand):
 
         if self.is_src:
             c_src = \
-              '\n\t_srcRegIdx[_numSrcRegs++] = %s + Ctrl_Base_DepTag;' % \
+              '\n\t_srcRegIdx[_numSrcRegs++] = %s + Misc_Reg_Base;' % \
               (self.reg_spec)
 
         if self.is_dest:
             c_dest = \
-              '\n\t_destRegIdx[_numDestRegs++] = %s + Ctrl_Base_DepTag;' % \
+              '\n\t_destRegIdx[_numDestRegs++] = %s + Misc_Reg_Base;' % \
               (self.reg_spec)
 
         return c_src + c_dest
diff --git a/src/arch/mips/isa/base.isa b/src/arch/mips/isa/base.isa
index cd6faf0f3..455ed70e7 100644
--- a/src/arch/mips/isa/base.isa
+++ b/src/arch/mips/isa/base.isa
@@ -72,11 +72,11 @@ output decoder {{
 
     void MipsStaticInst::printReg(std::ostream &os, int reg) const
     {
-        if (reg < FP_Base_DepTag) {
+        if (reg < FP_Reg_Base) {
             ccprintf(os, "r%d", reg);
         }
         else {
-            ccprintf(os, "f%d", reg - FP_Base_DepTag);
+            ccprintf(os, "f%d", reg - FP_Reg_Base);
         }
     }
 
diff --git a/src/arch/mips/isa/decoder.isa b/src/arch/mips/isa/decoder.isa
index 1091e67a0..5ff23ca5e 100644
--- a/src/arch/mips/isa/decoder.isa
+++ b/src/arch/mips/isa/decoder.isa
@@ -385,7 +385,7 @@ decode OPCODE_HI default Unknown::unknown() {
                     0x8: decode MT_U {
                         0x0: mftc0({{
                             data = xc->readRegOtherThread((RT << 3 | SEL) +
-                                                          Ctrl_Base_DepTag);
+                                                          Misc_Reg_Base);
                         }});
                         0x1: decode SEL {
                             0x0: mftgpr({{
@@ -409,19 +409,19 @@ decode OPCODE_HI default Unknown::unknown() {
                             }
                             0x2: decode MT_H {
                                 0x0: mftc1({{ data = xc->readRegOtherThread(RT +
-                                                                            FP_Base_DepTag);
+                                                                            FP_Reg_Base);
                                 }});
                                 0x1: mfthc1({{ data = xc->readRegOtherThread(RT +
-                                                                             FP_Base_DepTag);
+                                                                             FP_Reg_Base);
                                 }});
                             }
                             0x3: cftc1({{
                                 uint32_t fcsr_val = xc->readRegOtherThread(FLOATREG_FCSR +
-                                                                            FP_Base_DepTag);
+                                                                            FP_Reg_Base);
                                 switch (RT) {
                                   case 0:
                                     data = xc->readRegOtherThread(FLOATREG_FIR +
-                                                                  Ctrl_Base_DepTag);
+                                                                  Misc_Reg_Base);
                                     break;
                                   case 25:
                                     data = (fcsr_val & 0xFE000000 >> 24) |
@@ -450,7 +450,7 @@ decode OPCODE_HI default Unknown::unknown() {
                 format MT_MTTR {
                     // Decode MIPS MT MTTR instruction into sub-instructions
                     0xC: decode MT_U {
-                        0x0: mttc0({{ xc->setRegOtherThread((RD << 3 | SEL) + Ctrl_Base_DepTag,
+                        0x0: mttc0({{ xc->setRegOtherThread((RD << 3 | SEL) + Misc_Reg_Base,
                                                             Rt);
                                    }});
                         0x1: decode SEL {
@@ -496,10 +496,10 @@ decode OPCODE_HI default Unknown::unknown() {
                             }
                             0x2: mttc1({{
                                 uint64_t data = xc->readRegOtherThread(RD +
-                                                                       FP_Base_DepTag);
+                                                                       FP_Reg_Base);
                                 data = insertBits(data, MT_H ? 63 : 31,
                                                   MT_H ? 32 : 0, Rt);
-                                xc->setRegOtherThread(RD + FP_Base_DepTag,
+                                xc->setRegOtherThread(RD + FP_Reg_Base,
                                                       data);
                             }});
                             0x3: cttc1({{
@@ -534,7 +534,7 @@ decode OPCODE_HI default Unknown::unknown() {
                                             "Access to Floating Control "
                                             "S""tatus Register", FS);
                                 }
-                                xc->setRegOtherThread(FLOATREG_FCSR + FP_Base_DepTag, data);
+                                xc->setRegOtherThread(FLOATREG_FCSR + FP_Reg_Base, data);
                             }});
                             default: CP0Unimpl::unknown();
                         }
diff --git a/src/arch/mips/isa/formats/mt.isa b/src/arch/mips/isa/formats/mt.isa
index b4d00454e..74163eebf 100644
--- a/src/arch/mips/isa/formats/mt.isa
+++ b/src/arch/mips/isa/formats/mt.isa
@@ -102,7 +102,7 @@ output exec {{
             MVPConf0Reg &mvp_conf0)
     {
         vpe_conf0 = xc->readMiscReg(MISCREG_VPE_CONF0);
-        tc_bind_mt = xc->readRegOtherThread(MISCREG_TC_BIND + Ctrl_Base_DepTag);
+        tc_bind_mt = xc->readRegOtherThread(MISCREG_TC_BIND + Misc_Reg_Base);
         tc_bind = xc->readMiscReg(MISCREG_TC_BIND);
         vpe_control = xc->readMiscReg(MISCREG_VPE_CONTROL);
         mvp_conf0 = xc->readMiscReg(MISCREG_MVP_CONF0);
diff --git a/src/arch/mips/mt.hh b/src/arch/mips/mt.hh
index 02e98a170..64c765f19 100755
--- a/src/arch/mips/mt.hh
+++ b/src/arch/mips/mt.hh
@@ -113,23 +113,23 @@ forkThread(TC *tc, Fault &fault, int Rd_bits, int Rs, int Rt)
     int success = 0;
     for (ThreadID tid = 0; tid < num_threads && success == 0; tid++) {
         TCBindReg tidTCBind =
-            tc->readRegOtherThread(MISCREG_TC_BIND + Ctrl_Base_DepTag, tid);
+            tc->readRegOtherThread(MISCREG_TC_BIND + Misc_Reg_Base, tid);
         TCBindReg tcBind = tc->readMiscRegNoEffect(MISCREG_TC_BIND);
 
         if (tidTCBind.curVPE == tcBind.curVPE) {
 
             TCStatusReg tidTCStatus =
                 tc->readRegOtherThread(MISCREG_TC_STATUS +
-                                       Ctrl_Base_DepTag,tid);
+                                       Misc_Reg_Base,tid);
 
             TCHaltReg tidTCHalt =
-                tc->readRegOtherThread(MISCREG_TC_HALT + Ctrl_Base_DepTag,tid);
+                tc->readRegOtherThread(MISCREG_TC_HALT + Misc_Reg_Base,tid);
 
             if (tidTCStatus.da == 1 && tidTCHalt.h == 0 &&
                 tidTCStatus.a == 0 && success == 0) {
 
                 tc->setRegOtherThread(MISCREG_TC_RESTART +
-                                      Ctrl_Base_DepTag, Rs, tid);
+                                      Misc_Reg_Base, Rs, tid);
                 tc->setRegOtherThread(Rd_bits, Rt, tid);
 
                 StatusReg status = tc->readMiscReg(MISCREG_STATUS);
@@ -149,7 +149,7 @@ forkThread(TC *tc, Fault &fault, int Rd_bits, int Rs, int Rt)
                 tidTCStatus.asid = tcStatus.asid;
 
                 // Write Status Register
-                tc->setRegOtherThread(MISCREG_TC_STATUS + Ctrl_Base_DepTag,
+                tc->setRegOtherThread(MISCREG_TC_STATUS + Misc_Reg_Base,
                                       tidTCStatus, tid);
 
                 // Mark As Successful Fork
@@ -185,13 +185,13 @@ yieldThread(TC *tc, Fault &fault, int src_reg, uint32_t yield_mask)
 
         for (ThreadID tid = 0; tid < num_threads; tid++) {
             TCStatusReg tidTCStatus =
-                tc->readRegOtherThread(MISCREG_TC_STATUS + Ctrl_Base_DepTag,
+                tc->readRegOtherThread(MISCREG_TC_STATUS + Misc_Reg_Base,
                                        tid);
             TCHaltReg tidTCHalt =
-                tc->readRegOtherThread(MISCREG_TC_HALT + Ctrl_Base_DepTag,
+                tc->readRegOtherThread(MISCREG_TC_HALT + Misc_Reg_Base,
                                        tid);
             TCBindReg tidTCBind =
-                tc->readRegOtherThread(MISCREG_TC_BIND + Ctrl_Base_DepTag,
+                tc->readRegOtherThread(MISCREG_TC_BIND + Misc_Reg_Base,
                                        tid);
 
             if (tidTCBind.curVPE == tcBind.curVPE &&
diff --git a/src/arch/mips/registers.hh b/src/arch/mips/registers.hh
index 911e09d41..d9d94e47b 100644
--- a/src/arch/mips/registers.hh
+++ b/src/arch/mips/registers.hh
@@ -275,9 +275,9 @@ enum MiscRegIndex{
 const int NumMiscRegs = MISCREG_NUMREGS;
 
 // These help enumerate all the registers for dependence tracking.
-const int FP_Base_DepTag = NumIntRegs;
-const int Ctrl_Base_DepTag = FP_Base_DepTag + NumFloatRegs;
-const int Max_DepTag = Ctrl_Base_DepTag + NumMiscRegs;
+const int FP_Reg_Base = NumIntRegs;
+const int Misc_Reg_Base = FP_Reg_Base + NumFloatRegs;
+const int Max_Reg_Index = Misc_Reg_Base + NumMiscRegs;
 
 const int TotalNumRegs = NumIntRegs + NumFloatRegs + NumMiscRegs;
 
diff --git a/src/arch/power/registers.hh b/src/arch/power/registers.hh
index 723d664d2..89de3719c 100644
--- a/src/arch/power/registers.hh
+++ b/src/arch/power/registers.hh
@@ -84,9 +84,9 @@ const int SyscallPseudoReturnReg = 3;
 const int SyscallSuccessReg = 3;
 
 // These help enumerate all the registers for dependence tracking.
-const int FP_Base_DepTag = NumIntRegs;
-const int Ctrl_Base_DepTag = FP_Base_DepTag + NumFloatRegs;
-const int Max_DepTag = Ctrl_Base_DepTag + NumMiscRegs;
+const int FP_Reg_Base = NumIntRegs;
+const int Misc_Reg_Base = FP_Reg_Base + NumFloatRegs;
+const int Max_Reg_Index = Misc_Reg_Base + NumMiscRegs;
 
 typedef union {
     IntReg   intreg;
diff --git a/src/arch/sparc/isa/base.isa b/src/arch/sparc/isa/base.isa
index 3b3974cbf..3ff1d22b0 100644
--- a/src/arch/sparc/isa/base.isa
+++ b/src/arch/sparc/isa/base.isa
@@ -290,7 +290,7 @@ output decoder {{
             const int MaxLocal = 24;
             const int MaxInput = 32;
             const int MaxMicroReg = 40;
-            if (reg < FP_Base_DepTag) {
+            if (reg < FP_Reg_Base) {
                 // If we used a register from the next or previous window,
                 // take out the offset.
                 while (reg >= MaxMicroReg)
@@ -335,10 +335,10 @@ output decoder {{
                         break;
                     }
                 }
-            } else if (reg < Ctrl_Base_DepTag) {
-                ccprintf(os, "%%f%d", reg - FP_Base_DepTag);
+            } else if (reg < Misc_Reg_Base) {
+                ccprintf(os, "%%f%d", reg - FP_Reg_Base);
             } else {
-                switch (reg - Ctrl_Base_DepTag) {
+                switch (reg - Misc_Reg_Base) {
                   case MISCREG_ASI:
                     ccprintf(os, "%%asi");
                     break;
@@ -430,7 +430,7 @@ output decoder {{
                     ccprintf(os, "%%fsr");
                     break;
                   default:
-                    ccprintf(os, "%%ctrl%d", reg - Ctrl_Base_DepTag);
+                    ccprintf(os, "%%ctrl%d", reg - Misc_Reg_Base);
                 }
             }
         }
diff --git a/src/arch/sparc/registers.hh b/src/arch/sparc/registers.hh
index ffcfafcba..0e774b69e 100644
--- a/src/arch/sparc/registers.hh
+++ b/src/arch/sparc/registers.hh
@@ -75,9 +75,9 @@ const int TotalNumRegs = NumIntRegs + NumFloatRegs + NumMiscRegs;
 
 // These enumerate all the registers for dependence tracking.
 enum DependenceTags {
-    FP_Base_DepTag = NumIntRegs,
-    Ctrl_Base_DepTag = FP_Base_DepTag + NumFloatRegs,
-    Max_DepTag = Ctrl_Base_DepTag + NumMiscRegs
+    FP_Reg_Base = NumIntRegs,
+    Misc_Reg_Base = FP_Reg_Base + NumFloatRegs,
+    Max_Reg_Index = Misc_Reg_Base + NumMiscRegs
 };
 
 } // namespace SparcISA
diff --git a/src/arch/x86/registers.hh b/src/arch/x86/registers.hh
index e811ed2d3..bb9f5f7b1 100644
--- a/src/arch/x86/registers.hh
+++ b/src/arch/x86/registers.hh
@@ -65,12 +65,12 @@ const int NumFloatRegs =
 
 // These enumerate all the registers for dependence tracking.
 enum DependenceTags {
-    // FP_Base_DepTag must be large enough to be bigger than any integer
+    // FP_Reg_Base must be large enough to be bigger than any integer
     // register index which has the IntFoldBit (1 << 6) set.  To be safe
     // we just start at (1 << 7) == 128.
-    FP_Base_DepTag = 128,
-    Ctrl_Base_DepTag = FP_Base_DepTag + NumFloatRegs,
-    Max_DepTag = Ctrl_Base_DepTag + NumMiscRegs
+    FP_Reg_Base = 128,
+    Misc_Reg_Base = FP_Reg_Base + NumFloatRegs,
+    Max_Reg_Index = Misc_Reg_Base + NumMiscRegs
 };
 
 // semantically meaningful register indices
diff --git a/src/cpu/checker/cpu.hh b/src/cpu/checker/cpu.hh
index 19d3420ec..637481706 100644
--- a/src/cpu/checker/cpu.hh
+++ b/src/cpu/checker/cpu.hh
@@ -213,13 +213,13 @@ class CheckerCPU : public BaseCPU
 
     FloatReg readFloatRegOperand(const StaticInst *si, int idx)
     {
-        int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
+        int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Reg_Base;
         return thread->readFloatReg(reg_idx);
     }
 
     FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx)
     {
-        int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
+        int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Reg_Base;
         return thread->readFloatRegBits(reg_idx);
     }
 
@@ -239,7 +239,7 @@ class CheckerCPU : public BaseCPU
 
     void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val)
     {
-        int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
+        int reg_idx = si->destRegIdx(idx) - TheISA::FP_Reg_Base;
         thread->setFloatReg(reg_idx, val);
         setResult<double>(val);
     }
@@ -247,7 +247,7 @@ class CheckerCPU : public BaseCPU
     void setFloatRegOperandBits(const StaticInst *si, int idx,
                                 FloatRegBits val)
     {
-        int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
+        int reg_idx = si->destRegIdx(idx) - TheISA::FP_Reg_Base;
         thread->setFloatRegBits(reg_idx, val);
         setResult<uint64_t>(val);
     }
@@ -294,14 +294,14 @@ class CheckerCPU : public BaseCPU
 
     MiscReg readMiscRegOperand(const StaticInst *si, int idx)
     {
-        int reg_idx = si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag;
+        int reg_idx = si->srcRegIdx(idx) - TheISA::Misc_Reg_Base;
         return thread->readMiscReg(reg_idx);
     }
 
     void setMiscRegOperand(
             const StaticInst *si, int idx, const MiscReg &val)
     {
-        int reg_idx = si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag;
+        int reg_idx = si->destRegIdx(idx) - TheISA::Misc_Reg_Base;
         return thread->setMiscReg(reg_idx, val);
     }
 
diff --git a/src/cpu/checker/cpu_impl.hh b/src/cpu/checker/cpu_impl.hh
index 1967e02f3..185fed88e 100644
--- a/src/cpu/checker/cpu_impl.hh
+++ b/src/cpu/checker/cpu_impl.hh
@@ -607,7 +607,7 @@ Checker<Impl>::copyResult(DynInstPtr &inst, uint64_t mismatch_val,
             thread->setFloatRegBits(idx, mismatch_val);
             break;
           case MiscRegClass:
-            thread->setMiscReg(idx - TheISA::Ctrl_Base_DepTag,
+            thread->setMiscReg(idx - TheISA::Misc_Reg_Base,
                                mismatch_val);
             break;
         }
@@ -626,7 +626,7 @@ Checker<Impl>::copyResult(DynInstPtr &inst, uint64_t mismatch_val,
             break;
           case MiscRegClass:
             // Try to get the proper misc register index for ARM here...
-            thread->setMiscReg(idx - TheISA::Ctrl_Base_DepTag, res);
+            thread->setMiscReg(idx - TheISA::Misc_Reg_Base, res);
             break;
             // else Register is out of range...
         }
diff --git a/src/cpu/inorder/resources/use_def.cc b/src/cpu/inorder/resources/use_def.cc
index d7863095d..d25925b9b 100644
--- a/src/cpu/inorder/resources/use_def.cc
+++ b/src/cpu/inorder/resources/use_def.cc
@@ -247,7 +247,7 @@ UseDefUnit::execute(int slot_idx)
                         DPRINTF(InOrderUseDef, "[tid:%i]: [sn:%i]: Reading Float Reg %i"
                                 " (%i) from Register File:%x (%08f).\n",
                                 tid, seq_num,
-                                reg_idx - FP_Base_DepTag, flat_idx,
+                                reg_idx - FP_Reg_Base, flat_idx,
                                 cpu->readFloatRegBits(flat_idx,
                                                       inst->readTid()),
                                 cpu->readFloatReg(flat_idx,
@@ -269,7 +269,7 @@ UseDefUnit::execute(int slot_idx)
                         DPRINTF(InOrderUseDef, "[tid:%i]: [sn:%i]: Reading Misc Reg %i "
                                 " (%i) from Register File:0x%x.\n",
                                 tid, seq_num,
-                                reg_idx - Ctrl_Base_DepTag, flat_idx,
+                                reg_idx - Misc_Reg_Base, flat_idx,
                                 cpu->readMiscReg(flat_idx,
                                 inst->readTid()));
                         inst->setIntSrc(ud_idx,
@@ -315,7 +315,7 @@ UseDefUnit::execute(int slot_idx)
                             DPRINTF(InOrderUseDef, "[tid:%i]: Forwarding dest."
                                     " reg %i (%i) value 0x%x from "
                                     "[sn:%i] to [sn:%i] source #%i.\n",
-                                    tid, reg_idx - FP_Base_DepTag, flat_idx,
+                                    tid, reg_idx - FP_Reg_Base, flat_idx,
                                     forward_inst->readFloatResult(dest_reg_idx),
                                     forward_inst->seqNum, inst->seqNum, ud_idx);
                             inst->setFloatSrc(ud_idx,
@@ -329,7 +329,7 @@ UseDefUnit::execute(int slot_idx)
                             DPRINTF(InOrderUseDef, "[tid:%i]: Forwarding dest."
                                     " reg %i (%i) value 0x%x from "
                                     "[sn:%i] to [sn:%i] source #%i.\n",
-                                    tid, reg_idx - Ctrl_Base_DepTag, flat_idx,
+                                    tid, reg_idx - Misc_Reg_Base, flat_idx,
                                     forward_inst->readIntResult(dest_reg_idx),
                                     forward_inst->seqNum, 
                                     inst->seqNum, ud_idx);
@@ -412,7 +412,7 @@ UseDefUnit::execute(int slot_idx)
                                     tid, seq_num,
                                     inst->readFloatResult(ud_idx), 
                                     inst->readFloatBitsResult(ud_idx),
-                                    reg_idx - FP_Base_DepTag, flat_idx);
+                                    reg_idx - FP_Reg_Base, flat_idx);
 
                             // Check for FloatRegBits Here
                             cpu->setFloatRegBits(flat_idx,
@@ -425,7 +425,7 @@ UseDefUnit::execute(int slot_idx)
                                     "idx %i (%i).\n",
                                     tid, seq_num, inst->readFloatResult(ud_idx),
                                     inst->readIntResult(ud_idx), 
-                                    reg_idx - FP_Base_DepTag, flat_idx);
+                                    reg_idx - FP_Reg_Base, flat_idx);
 
                             cpu->setFloatReg(flat_idx,
                                              inst->readFloatResult(ud_idx),
@@ -438,7 +438,7 @@ UseDefUnit::execute(int slot_idx)
                                     tid, seq_num,
                                     inst->readFloatResult(ud_idx), 
                                     inst->readIntResult(ud_idx), 
-                                    reg_idx - FP_Base_DepTag, flat_idx);
+                                    reg_idx - FP_Reg_Base, flat_idx);
 
                             cpu->setFloatReg(flat_idx,
                                              inst->readFloatResult(ud_idx),
@@ -458,7 +458,7 @@ UseDefUnit::execute(int slot_idx)
 
                         DPRINTF(InOrderUseDef, "[tid:%i]: Writing Misc. 0x%x "
                                 "to register idx %i.\n",
-                                tid, inst->readIntResult(ud_idx), reg_idx - Ctrl_Base_DepTag);
+                                tid, inst->readIntResult(ud_idx), reg_idx - Misc_Reg_Base);
 
                         // Remove Dependencies
                         regDepMap[tid]->removeFront(reg_type, flat_idx, inst);
diff --git a/src/cpu/o3/dyn_inst.hh b/src/cpu/o3/dyn_inst.hh
index ece42b81a..15a82851b 100644
--- a/src/cpu/o3/dyn_inst.hh
+++ b/src/cpu/o3/dyn_inst.hh
@@ -175,7 +175,7 @@ class BaseO3DynInst : public BaseDynInst<Impl>
     TheISA::MiscReg readMiscRegOperand(const StaticInst *si, int idx)
     {
         return this->cpu->readMiscReg(
-                si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag,
+                si->srcRegIdx(idx) - TheISA::Misc_Reg_Base,
                 this->threadNumber);
     }
 
@@ -185,7 +185,7 @@ class BaseO3DynInst : public BaseDynInst<Impl>
     void setMiscRegOperand(const StaticInst *si, int idx,
                                      const MiscReg &val)
     {
-        int misc_reg = si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag;
+        int misc_reg = si->destRegIdx(idx) - TheISA::Misc_Reg_Base;
         setMiscReg(misc_reg, val);
     }
 
diff --git a/src/cpu/o3/rename_impl.hh b/src/cpu/o3/rename_impl.hh
index 3ab0afe11..60a929551 100644
--- a/src/cpu/o3/rename_impl.hh
+++ b/src/cpu/o3/rename_impl.hh
@@ -953,7 +953,7 @@ DefaultRename<Impl>::renameSrcRegs(DynInstPtr &inst, ThreadID tid)
             break;
 
           case FloatRegClass:
-            src_reg = src_reg - TheISA::FP_Base_DepTag;
+            src_reg = src_reg - TheISA::FP_Reg_Base;
             flat_src_reg = inst->tcBase()->flattenFloatIndex(src_reg);
             DPRINTF(Rename, "Flattening index %d to %d.\n",
                     (int)src_reg, (int)flat_src_reg);
@@ -961,7 +961,7 @@ DefaultRename<Impl>::renameSrcRegs(DynInstPtr &inst, ThreadID tid)
             break;
 
           case MiscRegClass:
-            flat_src_reg = src_reg - TheISA::Ctrl_Base_DepTag +
+            flat_src_reg = src_reg - TheISA::Misc_Reg_Base +
                            TheISA::NumFloatRegs + TheISA::NumIntRegs;
             DPRINTF(Rename, "Adjusting reg index from %d to %d.\n",
                     src_reg, flat_src_reg);
@@ -1018,7 +1018,7 @@ DefaultRename<Impl>::renameDestRegs(DynInstPtr &inst, ThreadID tid)
             break;
 
           case FloatRegClass:
-            dest_reg = dest_reg - TheISA::FP_Base_DepTag;
+            dest_reg = dest_reg - TheISA::FP_Reg_Base;
             flat_dest_reg = inst->tcBase()->flattenFloatIndex(dest_reg);
             DPRINTF(Rename, "Flattening index %d to %d.\n",
                     (int)dest_reg, (int)flat_dest_reg);
@@ -1028,7 +1028,7 @@ DefaultRename<Impl>::renameDestRegs(DynInstPtr &inst, ThreadID tid)
           case MiscRegClass:
             // Floating point and Miscellaneous registers need their indexes
             // adjusted to account for the expanded number of flattened int regs.
-            flat_dest_reg = dest_reg - TheISA::Ctrl_Base_DepTag +
+            flat_dest_reg = dest_reg - TheISA::Misc_Reg_Base +
                             TheISA::NumIntRegs + TheISA::NumFloatRegs;
             DPRINTF(Rename, "Adjusting reg index from %d to %d.\n",
                     dest_reg, flat_dest_reg);
diff --git a/src/cpu/ozone/cpu_impl.hh b/src/cpu/ozone/cpu_impl.hh
index f64f287ea..fcab901cf 100644
--- a/src/cpu/ozone/cpu_impl.hh
+++ b/src/cpu/ozone/cpu_impl.hh
@@ -458,7 +458,7 @@ OzoneCPU<Impl>::tick()
 
     _status = Running;
     thread.renameTable[ZeroReg]->setIntResult(0);
-    thread.renameTable[ZeroReg+TheISA::FP_Base_DepTag]->
+    thread.renameTable[ZeroReg+TheISA::FP_Reg_Base]->
         setDoubleResult(0.0);
 
     comm.advance();
@@ -727,7 +727,7 @@ OzoneCPU<Impl>::OzoneTC::copyArchRegs(ThreadContext *tc)
 
     // Then loop through the floating point registers.
     for (int i = 0; i < TheISA::NumFloatRegs; ++i) {
-        int fp_idx = i + TheISA::FP_Base_DepTag;
+        int fp_idx = i + TheISA::FP_Reg_Base;
         thread->renameTable[fp_idx]->setIntResult(tc->readFloatRegBits(i));
     }
 
@@ -756,7 +756,7 @@ template <class Impl>
 double
 OzoneCPU<Impl>::OzoneTC::readFloatReg(int reg_idx)
 {
-    int idx = reg_idx + TheISA::FP_Base_DepTag;
+    int idx = reg_idx + TheISA::FP_Reg_Base;
     return thread->renameTable[idx]->readFloatResult();
 }
 
@@ -764,7 +764,7 @@ template <class Impl>
 uint64_t
 OzoneCPU<Impl>::OzoneTC::readFloatRegBits(int reg_idx)
 {
-    int idx = reg_idx + TheISA::FP_Base_DepTag;
+    int idx = reg_idx + TheISA::FP_Reg_Base;
     return thread->renameTable[idx]->readIntResult();
 }
 
@@ -783,7 +783,7 @@ template <class Impl>
 void
 OzoneCPU<Impl>::OzoneTC::setFloatReg(int reg_idx, FloatReg val)
 {
-    int idx = reg_idx + TheISA::FP_Base_DepTag;
+    int idx = reg_idx + TheISA::FP_Reg_Base;
 
     thread->renameTable[idx]->setDoubleResult(val);
 
diff --git a/src/cpu/reg_class.hh b/src/cpu/reg_class.hh
index e96c94cbb..c9d4b1c4f 100644
--- a/src/cpu/reg_class.hh
+++ b/src/cpu/reg_class.hh
@@ -65,19 +65,19 @@ inline
 RegClass regIdxToClass(TheISA::RegIndex reg_idx,
                        TheISA::RegIndex *rel_reg_idx = NULL)
 {
-    assert(reg_idx < TheISA::Max_DepTag);
+    assert(reg_idx < TheISA::Max_Reg_Index);
     RegClass cl;
     int offset;
 
-    if (reg_idx < TheISA::FP_Base_DepTag) {
+    if (reg_idx < TheISA::FP_Reg_Base) {
         cl = IntRegClass;
         offset = 0;
-    } else if (reg_idx < TheISA::Ctrl_Base_DepTag) {
+    } else if (reg_idx < TheISA::Misc_Reg_Base) {
         cl = FloatRegClass;
-        offset = TheISA::FP_Base_DepTag;
+        offset = TheISA::FP_Reg_Base;
     } else {
         cl = MiscRegClass;
-        offset = TheISA::Ctrl_Base_DepTag;
+        offset = TheISA::Misc_Reg_Base;
     }
 
     if (rel_reg_idx)
diff --git a/src/cpu/simple/base.hh b/src/cpu/simple/base.hh
index 7e84dcc16..f2e1b278a 100644
--- a/src/cpu/simple/base.hh
+++ b/src/cpu/simple/base.hh
@@ -296,14 +296,14 @@ class BaseSimpleCPU : public BaseCPU
     FloatReg readFloatRegOperand(const StaticInst *si, int idx)
     {
         numFpRegReads++;
-        int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
+        int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Reg_Base;
         return thread->readFloatReg(reg_idx);
     }
 
     FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx)
     {
         numFpRegReads++;
-        int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
+        int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Reg_Base;
         return thread->readFloatRegBits(reg_idx);
     }
 
@@ -316,7 +316,7 @@ class BaseSimpleCPU : public BaseCPU
     void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val)
     {
         numFpRegWrites++;
-        int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
+        int reg_idx = si->destRegIdx(idx) - TheISA::FP_Reg_Base;
         thread->setFloatReg(reg_idx, val);
     }
 
@@ -324,7 +324,7 @@ class BaseSimpleCPU : public BaseCPU
                                 FloatRegBits val)
     {
         numFpRegWrites++;
-        int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
+        int reg_idx = si->destRegIdx(idx) - TheISA::FP_Reg_Base;
         thread->setFloatRegBits(reg_idx, val);
     }
 
@@ -362,7 +362,7 @@ class BaseSimpleCPU : public BaseCPU
     MiscReg readMiscRegOperand(const StaticInst *si, int idx)
     {
         numIntRegReads++;
-        int reg_idx = si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag;
+        int reg_idx = si->srcRegIdx(idx) - TheISA::Misc_Reg_Base;
         return thread->readMiscReg(reg_idx);
     }
 
@@ -370,7 +370,7 @@ class BaseSimpleCPU : public BaseCPU
             const StaticInst *si, int idx, const MiscReg &val)
     {
         numIntRegWrites++;
-        int reg_idx = si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag;
+        int reg_idx = si->destRegIdx(idx) - TheISA::Misc_Reg_Base;
         return thread->setMiscReg(reg_idx, val);
     }