add pseduo instruction support for sparc

util/m5/Makefile.alpha:
    Clean up to make it a bit easier to muck with
util/m5/Makefile.alpha:
    Make the makefile more reasonable
util/m5/Makefile.alpha:
    Remove authors from copyright.
util/m5/Makefile.alpha:
    Updated Authors from bk prs info
util/m5/Makefile.alpha:
    bk cp Makefile Makefile.alpha
src/arch/sparc/tlb.cc:
    Clean up the cache code a little bit and make sure the uncacbale bit is set when appropriate
src/arch/alpha/isa/decoder.isa:
src/sim/pseudo_inst.cc:
src/sim/pseudo_inst.hh:
    Rename AlphaPseudo -> PseudoInst since it's all generic
src/arch/sparc/isa/bitfields.isa:
src/arch/sparc/isa/decoder.isa:
src/arch/sparc/isa/includes.isa:
src/arch/sparc/isa/operands.isa:
    Add support for pseudo instructions in sparc
util/m5/Makefile.alpha:
util/m5/Makefile.sparc:
    split off alpha make file and sparc make file for m5 app
util/m5/m5.c:
    ivle and ivlb aren't used anymore
util/m5/m5op.h:
    stdint seems like a more generic better fit here
util/m5/m5op_alpha.S:
    move the op ids into their own header file since we can share them between sparc and alpha

--HG--
rename : util/m5/Makefile => util/m5/Makefile.sparc
rename : util/m5/m5op.S => util/m5/m5op_alpha.S
extra : convert_revision : 490ba2e8b8bc6e28bfc009cedec6b686b28e7834

15 files changed, 337 insertions, 80 deletions

diff --git a/src/arch/alpha/isa/decoder.isa b/src/arch/alpha/isa/decoder.isa
index 1da6a60f1..49c25c3c2 100644
--- a/src/arch/alpha/isa/decoder.isa
+++ b/src/arch/alpha/isa/decoder.isa
@@ -790,19 +790,19 @@ decode OPCODE default Unknown::unknown() {
         // M5 special opcodes use the reserved 0x01 opcode space
         0x01: decode M5FUNC {
             0x00: arm({{
-                AlphaPseudo::arm(xc->tcBase());
+                PseudoInst::arm(xc->tcBase());
             }}, IsNonSpeculative);
             0x01: quiesce({{
-                AlphaPseudo::quiesce(xc->tcBase());
+                PseudoInst::quiesce(xc->tcBase());
             }}, IsNonSpeculative, IsQuiesce);
             0x02: quiesceNs({{
-                AlphaPseudo::quiesceNs(xc->tcBase(), R16);
+                PseudoInst::quiesceNs(xc->tcBase(), R16);
             }}, IsNonSpeculative, IsQuiesce);
             0x03: quiesceCycles({{
-                AlphaPseudo::quiesceCycles(xc->tcBase(), R16);
+                PseudoInst::quiesceCycles(xc->tcBase(), R16);
             }}, IsNonSpeculative, IsQuiesce, IsUnverifiable);
             0x04: quiesceTime({{
-                R0 = AlphaPseudo::quiesceTime(xc->tcBase());
+                R0 = PseudoInst::quiesceTime(xc->tcBase());
             }}, IsNonSpeculative, IsUnverifiable);
             0x10: ivlb({{
                 warn_once("Obsolete M5 instruction ivlb encountered.\n");
@@ -811,47 +811,47 @@ decode OPCODE default Unknown::unknown() {
                 warn_once("Obsolete M5 instruction ivlb encountered.\n");
             }});
             0x20: m5exit_old({{
-                AlphaPseudo::m5exit_old(xc->tcBase());
+                PseudoInst::m5exit_old(xc->tcBase());
             }}, No_OpClass, IsNonSpeculative);
             0x21: m5exit({{
-                AlphaPseudo::m5exit(xc->tcBase(), R16);
+                PseudoInst::m5exit(xc->tcBase(), R16);
             }}, No_OpClass, IsNonSpeculative);
             0x31: loadsymbol({{
-                AlphaPseudo::loadsymbol(xc->tcBase());
+                PseudoInst::loadsymbol(xc->tcBase());
             }}, No_OpClass, IsNonSpeculative);
             0x30: initparam({{ Ra = xc->tcBase()->getCpuPtr()->system->init_param; }});
             0x40: resetstats({{
-                AlphaPseudo::resetstats(xc->tcBase(), R16, R17);
+                PseudoInst::resetstats(xc->tcBase(), R16, R17);
             }}, IsNonSpeculative);
             0x41: dumpstats({{
-                AlphaPseudo::dumpstats(xc->tcBase(), R16, R17);
+                PseudoInst::dumpstats(xc->tcBase(), R16, R17);
             }}, IsNonSpeculative);
             0x42: dumpresetstats({{
-                AlphaPseudo::dumpresetstats(xc->tcBase(), R16, R17);
+                PseudoInst::dumpresetstats(xc->tcBase(), R16, R17);
             }}, IsNonSpeculative);
             0x43: m5checkpoint({{
-                AlphaPseudo::m5checkpoint(xc->tcBase(), R16, R17);
+                PseudoInst::m5checkpoint(xc->tcBase(), R16, R17);
             }}, IsNonSpeculative);
             0x50: m5readfile({{
-                R0 = AlphaPseudo::readfile(xc->tcBase(), R16, R17, R18);
+                R0 = PseudoInst::readfile(xc->tcBase(), R16, R17, R18);
             }}, IsNonSpeculative);
             0x51: m5break({{
-                AlphaPseudo::debugbreak(xc->tcBase());
+                PseudoInst::debugbreak(xc->tcBase());
             }}, IsNonSpeculative);
             0x52: m5switchcpu({{
-                AlphaPseudo::switchcpu(xc->tcBase());
+                PseudoInst::switchcpu(xc->tcBase());
             }}, IsNonSpeculative);
             0x53: m5addsymbol({{
-                AlphaPseudo::addsymbol(xc->tcBase(), R16, R17);
+                PseudoInst::addsymbol(xc->tcBase(), R16, R17);
             }}, IsNonSpeculative);
             0x54: m5panic({{
                 panic("M5 panic instruction called at pc=%#x.", xc->readPC());
             }}, IsNonSpeculative);
             0x55: m5anBegin({{
-                AlphaPseudo::anBegin(xc->tcBase(), R16);
+                PseudoInst::anBegin(xc->tcBase(), R16);
             }}, IsNonSpeculative);
             0x56: m5anWait({{
-                AlphaPseudo::anWait(xc->tcBase(), R16, R17);
+                PseudoInst::anWait(xc->tcBase(), R16, R17);
             }}, IsNonSpeculative);
         }
     }
diff --git a/src/arch/sparc/isa/bitfields.isa b/src/arch/sparc/isa/bitfields.isa
index e75680d2b..afa8f88a2 100644
--- a/src/arch/sparc/isa/bitfields.isa
+++ b/src/arch/sparc/isa/bitfields.isa
@@ -54,6 +54,7 @@ def bitfield FCN	<29:25>;
 def bitfield I		<13>;
 def bitfield IMM_ASI	<12:5>;
 def bitfield IMM22	<21:0>;
+def bitfield M5FUNC     <15:7>;
 def bitfield MMASK	<3:0>;
 def bitfield OP		<31:30>;
 def bitfield OP2	<24:22>;
diff --git a/src/arch/sparc/isa/decoder.isa b/src/arch/sparc/isa/decoder.isa
index 0be7defba..e2d1707dd 100644
--- a/src/arch/sparc/isa/decoder.isa
+++ b/src/arch/sparc/isa/decoder.isa
@@ -1009,7 +1009,16 @@ decode OP default Unknown::unknown()
                 0x80: Trap::shutdown({{fault = new IllegalInstruction;}});
                 0x81: FailUnimpl::siam();
             }
-            0x37: Trap::impdep2({{fault = new IllegalInstruction;}});
+            // M5 special opcodes use the reserved IMPDEP2A opcode space
+            0x37: decode M5FUNC {
+                // we have 7 bits of space here to play with...
+                0x21: m5exit({{PseudoInst::m5exit(xc->tcBase(), O0);
+                              }}, No_OpClass, IsNonSpeculative);
+                0x54: m5panic({{
+                              panic("M5 panic instruction called at pc=%#x.", xc->readPC());
+                              }}, No_OpClass, IsNonSpeculative);
+
+            }
             0x38: Branch::jmpl({{
                 Addr target = Rs1 + Rs2_or_imm13;
                 if(target & 0x3)
@@ -1077,7 +1086,8 @@ decode OP default Unknown::unknown()
                     }
                 }}, IsSerializeAfter, IsNonSpeculative);
             }
-            0x3B: Nop::flush({{/*Instruction memory flush*/}});
+            0x3B: Nop::flush({{/*Instruction memory flush*/}}, IsWriteBarrier,
+                          MemWriteOp);
             0x3C: save({{
                 if(Cansave == 0)
                 {
diff --git a/src/arch/sparc/isa/includes.isa b/src/arch/sparc/isa/includes.isa
index b46ef011e..05e9e8731 100644
--- a/src/arch/sparc/isa/includes.isa
+++ b/src/arch/sparc/isa/includes.isa
@@ -70,6 +70,10 @@ output exec {{
 #include <ieeefp.h>
 #endif
 
+#if FULL_SYSTEM
+#include "sim/pseudo_inst.hh"
+#endif
+
 #include <limits>
 
 #include <cmath>
diff --git a/src/arch/sparc/isa/operands.isa b/src/arch/sparc/isa/operands.isa
index f624c3e2b..82e9407de 100644
--- a/src/arch/sparc/isa/operands.isa
+++ b/src/arch/sparc/isa/operands.isa
@@ -100,6 +100,12 @@ def operands {{
     'R1':  		('IntReg', 'udw', '1', None, 7),
     'R15': 		('IntReg', 'udw', '15', 'IsInteger', 8),
     'R16': 		('IntReg', 'udw', '16', None, 9),
+    'O0':               ('IntReg', 'udw', '24', 'IsInteger', 10),
+    'O1':               ('IntReg', 'udw', '25', 'IsInteger', 11),
+    'O2':               ('IntReg', 'udw', '26', 'IsInteger', 12),
+    'O3':               ('IntReg', 'udw', '27', 'IsInteger', 13),
+    'O4':               ('IntReg', 'udw', '28', 'IsInteger', 14),
+    'O5':               ('IntReg', 'udw', '29', 'IsInteger', 15),
 
     # Control registers
 #   'Y':		('ControlReg', 'udw', 'MISCREG_Y', None, 40),
diff --git a/src/arch/sparc/tlb.cc b/src/arch/sparc/tlb.cc
index 82b1ed175..3ed2a9cc6 100644
--- a/src/arch/sparc/tlb.cc
+++ b/src/arch/sparc/tlb.cc
@@ -596,21 +596,36 @@ DTB::translate(RequestPtr &req, ThreadContext *tc, bool write)
 
     // Be fast if we can!
     if (cacheValid &&  cacheState == tlbdata) {
-        if (cacheEntry[0] && cacheAsi[0] == asi && cacheEntry[0]->range.va < vaddr + size &&
-            cacheEntry[0]->range.va + cacheEntry[0]->range.size > vaddr &&
-            (!write || cacheEntry[0]->pte.writable())) {
-                req->setPaddr(cacheEntry[0]->pte.paddr() & ~(cacheEntry[0]->pte.size()-1) |
-                              vaddr & cacheEntry[0]->pte.size()-1 );
-                return NoFault;
-        }
-        if (cacheEntry[1] && cacheAsi[1] == asi && cacheEntry[1]->range.va < vaddr + size &&
-            cacheEntry[1]->range.va + cacheEntry[1]->range.size > vaddr &&
-            (!write || cacheEntry[1]->pte.writable())) {
-                req->setPaddr(cacheEntry[1]->pte.paddr() & ~(cacheEntry[1]->pte.size()-1) |
-                              vaddr & cacheEntry[1]->pte.size()-1 );
-                return NoFault;
-        }
-    }
+
+
+
+  if (cacheEntry[0]) {
+            TlbEntry *ce = cacheEntry[0];
+           Addr ce_va = ce->range.va;
+            if (cacheAsi[0] == asi &&
+                ce_va < vaddr + size && ce_va + ce->range.size > vaddr &&
+                (!write || ce->pte.writable())) {
+                    req->setPaddr(ce->pte.paddrMask() | vaddr & ce->pte.sizeMask());
+                    if (ce->pte.sideffect() || (ce->pte.paddr() >> 39) & 1)
+                        req->setFlags(req->getFlags() | UNCACHEABLE);
+                    DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr());
+                    return NoFault;
+            } // if matched
+        } // if cache entry valid
+        if (cacheEntry[1]) {
+            TlbEntry *ce = cacheEntry[1];
+            Addr ce_va = ce->range.va;
+            if (cacheAsi[1] == asi &&
+                ce_va < vaddr + size && ce_va + ce->range.size > vaddr &&
+                (!write || ce->pte.writable())) {
+                    req->setPaddr(ce->pte.paddrMask() | vaddr & ce->pte.sizeMask());
+                    if (ce->pte.sideffect() || (ce->pte.paddr() >> 39) & 1)
+                        req->setFlags(req->getFlags() | UNCACHEABLE);
+                    DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr());
+                    return NoFault;
+            } // if matched
+        } // if cache entry valid
+     }
 
     bool red = bits(tlbdata,1,1);
     bool priv = bits(tlbdata,2,2);
@@ -756,7 +771,7 @@ DTB::translate(RequestPtr &req, ThreadContext *tc, bool write)
     }
 
 
-    if (e->pte.sideffect())
+    if (e->pte.sideffect() || (e->pte.paddr() >> 39) & 1)
         req->setFlags(req->getFlags() | UNCACHEABLE);
 
     // cache translation date for next translation
diff --git a/src/sim/pseudo_inst.cc b/src/sim/pseudo_inst.cc
index 66ebc10e1..56a779674 100644
--- a/src/sim/pseudo_inst.cc
+++ b/src/sim/pseudo_inst.cc
@@ -55,7 +55,7 @@ using namespace std;
 using namespace Stats;
 using namespace TheISA;
 
-namespace AlphaPseudo
+namespace PseudoInst
 {
     void
     arm(ThreadContext *tc)
diff --git a/src/sim/pseudo_inst.hh b/src/sim/pseudo_inst.hh
index bc71a7e64..93021abad 100644
--- a/src/sim/pseudo_inst.hh
+++ b/src/sim/pseudo_inst.hh
@@ -33,7 +33,7 @@ class ThreadContext;
 //We need the "Tick" and "Addr" data types from here
 #include "sim/host.hh"
 
-namespace AlphaPseudo
+namespace PseudoInst
 {
     /**
      * @todo these externs are only here for a hack in fullCPU::takeOver...
diff --git a/util/m5/Makefile b/util/m5/Makefile.alpha
index a98092e47..e94c2901d 100644
--- a/util/m5/Makefile
+++ b/util/m5/Makefile.alpha
@@ -36,7 +36,7 @@ AS=$(CROSS_COMPILE)as
 LD=$(CROSS_COMPILE)ld
 
 CFLAGS=-O2 
-OBJS=m5.o m5op.o
+OBJS=m5.o m5op_alpha.o
 
 all: m5
 
diff --git a/util/m5/Makefile.sparc b/util/m5/Makefile.sparc
new file mode 100644
index 000000000..835ccb2a4
--- /dev/null
+++ b/util/m5/Makefile.sparc
@@ -0,0 +1,53 @@
+# Copyright (c) 2005-2006 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Nathan Binkert
+#          Ali Saidi
+
+### If we are not compiling on an alpha, we must use cross tools ###    
+ifneq ($(shell uname -m), sun4v)
+CROSS_COMPILE?=sparc64-sun-solaris2.10-
+endif
+CC=$(CROSS_COMPILE)gcc
+AS=$(CROSS_COMPILE)as
+LD=$(CROSS_COMPILE)ld
+
+CFLAGS=-O2 
+OBJS=m5.o m5op_sparc.o
+
+all: m5
+
+%.o: %.S
+	$(CC) $(CFLAGS) -o $@ -c $<
+
+%.o: %.c
+	$(CC)  $(CFLAGS) -o $@ -c $<
+
+m5: $(OBJS)
+	$(CC) -o $@ $(OBJS)
+
+clean:
+	rm -f *.o m5
diff --git a/util/m5/m5.c b/util/m5/m5.c
index ca555ed12..190289f06 100644
--- a/util/m5/m5.c
+++ b/util/m5/m5.c
@@ -70,24 +70,6 @@ main(int argc, char *argv[])
 
     command = argv[1];
 
-    if (COMPARE("ivlb")) {
-        if (argc != 3)
-            usage();
-
-        arg1 = strtoul(argv[2], NULL, 0);
-        m5_ivlb(arg1);
-        return 0;
-    }
-
-    if (COMPARE("ivle")) {
-        if (argc != 3)
-            usage();
-
-        arg1 = strtoul(argv[2], NULL, 0);
-        m5_ivle(arg1);
-        return 0;
-    }
-
     if (COMPARE("initparam")) {
         if (argc != 2)
             usage();
@@ -203,6 +185,7 @@ main(int argc, char *argv[])
     if (COMPARE("loadsymbol")) {
         m5_loadsymbol(arg1);
         return 0;
+    }
     if (COMPARE("readfile")) {
             char buf[256*1024];
             int offset = 0;
diff --git a/util/m5/m5op.h b/util/m5/m5op.h
index e8f2baaac..f4e6bb0f1 100644
--- a/util/m5/m5op.h
+++ b/util/m5/m5op.h
@@ -32,7 +32,7 @@
 #ifndef __M5OP_H__
 #define __M5OP_H__
 
-#include <asm/types.h>
+#include <stdint.h>
 
 void arm(uint64_t address);
 void quiesce(void);
diff --git a/util/m5/m5op.S b/util/m5/m5op_alpha.S
index 61e79d5d3..c5d0e65f8 100644
--- a/util/m5/m5op.S
+++ b/util/m5/m5op_alpha.S
@@ -31,28 +31,7 @@
 
 #define m5_op 0x01
 
-#define arm_func 0x00
-#define quiesce_func 0x01
-#define quiescens_func 0x02
-#define quiescecycle_func 0x03
-#define quiescetime_func 0x04
-#define ivlb 0x10 // obsolete
-#define ivle 0x11 // obsolete
-#define exit_old_func 0x20 // deprecated!
-#define exit_func 0x21
-#define initparam_func 0x30
-#define loadsymbol_func 0x31
-#define resetstats_func 0x40
-#define dumpstats_func 0x41
-#define dumprststats_func 0x42
-#define ckpt_func 0x43
-#define readfile_func 0x50
-#define debugbreak_func 0x51
-#define switchcpu_func 0x52
-#define addsymbol_func 0x53
-#define panic_func     0x54
-#define anbegin_func     0x55
-#define anwait_func     0x56
+#include "m5ops.h"
 
 #define INST(op, ra, rb, func) \
         .long (((op) << 26) | ((ra) << 21) | ((rb) << 16) | (func))
diff --git a/util/m5/m5op_sparc.S b/util/m5/m5op_sparc.S
new file mode 100644
index 000000000..b5c421bdf
--- /dev/null
+++ b/util/m5/m5op_sparc.S
@@ -0,0 +1,152 @@
+/*
+ * Copyright (c) 2003-2006 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Nathan Binkert
+ *          Ali Saidi
+ */
+
+#define m5_op 0x2
+#define m5_op3 0x37
+
+#include "m5ops.h"
+
+#define INST(func, rs1, rs2, rd) \
+        .long (m5_op) << 30 | (rd) << 25 | (m5_op3) << 19 | (func) << 7 |  \
+              (rs1) << 14 | (rs2) << 0;
+
+
+#define LEAF(func)                \
+        .section ".text";         \
+        .align   4;               \
+        .global  func;            \
+        .type    func, #function; \
+func:
+
+#define END(func)         \
+        .size    func, (.-func)
+
+#define M5EXIT INST(exit_func, 0, 0, 0)
+#define PANIC INST(panic_func, 0, 0, 0)
+
+LEAF(m5_exit)
+    retl
+    M5EXIT
+END(m5_exit)
+
+LEAF(m5_panic)
+    retl
+    PANIC
+END(m5_panic)
+
+
+/* !!!!!! All code below here just panics !!!!!! */
+LEAF(arm)
+    retl
+    PANIC
+END(arm)
+
+LEAF(quiesce)
+    retl
+    PANIC
+END(quiesce)
+
+LEAF(quiesceNs)
+    retl
+    PANIC
+END(quiesceNs)
+
+LEAF(quiesceCycle)
+    retl
+    PANIC
+END(quiesceCycle)
+
+LEAF(quiesceTime)
+    retl
+    PANIC
+END(quiesceTime)
+
+LEAF(m5_initparam)
+    retl
+    PANIC
+END(m5_initparam)
+
+LEAF(m5_loadsymbol)
+    retl
+    PANIC
+END(m5_loadsymbol)
+
+LEAF(m5_reset_stats)
+    retl
+    PANIC
+END(m5_reset_stats)
+
+LEAF(m5_dump_stats)
+    retl
+    PANIC
+END(m5_dump_stats)
+
+LEAF(m5_dumpreset_stats)
+    retl
+    PANIC
+END(m5_dumpreset_stats)
+
+LEAF(m5_checkpoint)
+    retl
+    PANIC
+END(m5_checkpoint)
+
+LEAF(m5_readfile)
+    retl
+    PANIC
+END(m5_readfile)
+
+LEAF(m5_debugbreak)
+    retl
+    PANIC
+END(m5_debugbreak)
+
+LEAF(m5_switchcpu)
+    retl
+    PANIC
+END(m5_switchcpu)
+
+LEAF(m5_addsymbol)
+    retl
+    PANIC
+END(m5_addsymbol)
+
+LEAF(m5_anbegin)
+    retl
+    PANIC
+END(m5_anbegin)
+
+LEAF(m5_anwait)
+    retl
+    PANIC
+END(m5_anwait)
+
+
diff --git a/util/m5/m5ops.h b/util/m5/m5ops.h
new file mode 100644
index 000000000..ce0b39b29
--- /dev/null
+++ b/util/m5/m5ops.h
@@ -0,0 +1,54 @@
+/*
+ * Copyright (c) 2003-2006 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Nathan Binkert
+ *          Ali Saidi
+ */
+
+#define arm_func 0x00
+#define quiesce_func 0x01
+#define quiescens_func 0x02
+#define quiescecycle_func 0x03
+#define quiescetime_func 0x04
+#define ivlb 0x10 // obsolete
+#define ivle 0x11 // obsolete
+#define exit_old_func 0x20 // deprecated!
+#define exit_func 0x21
+#define initparam_func 0x30
+#define loadsymbol_func 0x31
+#define resetstats_func 0x40
+#define dumpstats_func 0x41
+#define dumprststats_func 0x42
+#define ckpt_func 0x43
+#define readfile_func 0x50
+#define debugbreak_func 0x51
+#define switchcpu_func 0x52
+#define addsymbol_func 0x53
+#define panic_func     0x54
+#define anbegin_func     0x55
+#define anwait_func     0x56
+