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| author | Nilay Vaish <nilay@cs.wisc.edu> | 2014-03-20 08:03:09 -0500 |
|---|---|---|
| committer | Nilay Vaish <nilay@cs.wisc.edu> | 2014-03-20 08:03:09 -0500 |
| commit | 9b3418d163ea2225a9d652b923333b04733a1e0b (patch) | |
| tree | c9b00f5674522320c315eaa472475e3b75ec048f | |
| parent | a20fbdfc23f8c7cbbe2c0b884d28db99442feba9 (diff) | |
| download | gem5-9b3418d163ea2225a9d652b923333b04733a1e0b.tar.xz | |
ruby: no piobus in se mode
Piobus was recently added to se scripts for ruby so that the interrupt
controller can be connected to something (required since the interrupt
controller sends address range messages). This patch removes the piobus
and instead, the pio port of ruby port will now ignore the range change
messages in se mode.
| -rw-r--r-- | configs/example/se.py | 4 | ||||
| -rw-r--r-- | src/mem/ruby/system/RubyPort.cc | 3 | ||||
| -rw-r--r-- | tests/configs/simple-timing-ruby.py | 3 |
3 files changed, 4 insertions, 6 deletions
diff --git a/configs/example/se.py b/configs/example/se.py index d390fbad0..97ad2c7de 100644 --- a/configs/example/se.py +++ b/configs/example/se.py @@ -232,9 +232,7 @@ if options.ruby: system.physmem = MemClass(range=AddrRange(options.mem_size), null = True) options.use_map = True - - system.piobus = NoncoherentBus() - Ruby.create_system(options, system, system.piobus) + Ruby.create_system(options, system) assert(options.num_cpus == len(system.ruby._cpu_ruby_ports)) for i in xrange(np): diff --git a/src/mem/ruby/system/RubyPort.cc b/src/mem/ruby/system/RubyPort.cc index ec1266a90..110b6924d 100644 --- a/src/mem/ruby/system/RubyPort.cc +++ b/src/mem/ruby/system/RubyPort.cc @@ -46,6 +46,7 @@ #include "mem/protocol/AccessPermission.hh" #include "mem/ruby/slicc_interface/AbstractController.hh" #include "mem/ruby/system/RubyPort.hh" +#include "sim/full_system.hh" #include "sim/system.hh" RubyPort::RubyPort(const Params *p) @@ -558,7 +559,7 @@ RubyPort::PioMasterPort::recvRangeChange() { RubyPort &r = static_cast<RubyPort &>(owner); r.gotAddrRanges--; - if (r.gotAddrRanges == 0) { + if (r.gotAddrRanges == 0 && FullSystem) { r.pioSlavePort.sendRangeChange(); } } diff --git a/tests/configs/simple-timing-ruby.py b/tests/configs/simple-timing-ruby.py index d3f4ad2ae..94cb15ed4 100644 --- a/tests/configs/simple-timing-ruby.py +++ b/tests/configs/simple-timing-ruby.py @@ -79,8 +79,7 @@ system.cpu.clk_domain = SrcClockDomain(clock = '2GHz', voltage_domain = system.voltage_domain) system.mem_ranges = AddrRange('256MB') -system.piobus = NoncoherentBus() -Ruby.create_system(options, system, system.piobus) +Ruby.create_system(options, system) # Create a separate clock for Ruby system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock, |