diff options
| author | Nathan Binkert <nate@binkert.org> | 2011-04-22 10:18:51 -0700 |
|---|---|---|
| committer | Nathan Binkert <nate@binkert.org> | 2011-04-22 10:18:51 -0700 |
| commit | a7e27f9a82300f213b268264e1dede222d26bd4d (patch) | |
| tree | 905f84d6e06111d4a243c18a1899e932646bdced | |
| parent | 2342aa2ebbb9dfe232eafcd20f01a8dd95ebfcc0 (diff) | |
| download | gem5-a7e27f9a82300f213b268264e1dede222d26bd4d.tar.xz | |
tests: updates for stat name change
64 files changed, 537 insertions, 1012 deletions
diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout index 10e34acb3..a72d72f62 100755 --- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout @@ -5,8 +5,8 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 19 2011 11:52:53 -M5 started Apr 19 2011 12:05:54 +M5 compiled Apr 21 2011 12:29:56 +M5 started Apr 21 2011 13:02:50 M5 executing on maize command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt index bb82434d0..0e211038a 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 385051 # Simulator instruction rate (inst/s) -host_mem_usage 204468 # Number of bytes of host memory used -host_seconds 1468.77 # Real time elapsed on the host -host_tick_rate 110529153 # Simulator tick rate (ticks/s) +host_inst_rate 235652 # Simulator instruction rate (inst/s) +host_mem_usage 207744 # Number of bytes of host memory used +host_seconds 2399.95 # Real time elapsed on the host +host_tick_rate 67644016 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 565552443 # Number of instructions simulated sim_seconds 0.162342 # Number of seconds simulated @@ -254,16 +254,16 @@ system.cpu.iew.iewIdleCycles 0 # Nu system.cpu.iew.iewLSQFullEvents 13837 # Number of times the LSQ has become full, causing a stall system.cpu.iew.iewSquashCycles 9601978 # Number of cycles IEW is squashing system.cpu.iew.iewUnblockCycles 64907 # Number of cycles IEW is unblocking -system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 733 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 10009719 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 9957 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 24101 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 6020 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 11448147 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 3134413 # Number of stores squashed +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.cacheBlocked 733 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.forwLoads 10009719 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.ignoredResponses 9957 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.memOrderViolation 24101 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.rescheduledLoads 6020 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.squashedLoads 11448147 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedStores 3134413 # Number of stores squashed system.cpu.iew.memOrderViolationEvents 24101 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 952315 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 3653189 # Number of branches that were predicted taken incorrectly diff --git a/tests/long/00.gzip/ref/arm/linux/o3-timing/simout b/tests/long/00.gzip/ref/arm/linux/o3-timing/simout index facf2b9b0..408898e50 100755 --- a/tests/long/00.gzip/ref/arm/linux/o3-timing/simout +++ b/tests/long/00.gzip/ref/arm/linux/o3-timing/simout @@ -5,8 +5,8 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 19 2011 12:47:10 -M5 started Apr 19 2011 12:47:12 +M5 compiled Apr 21 2011 12:05:01 +M5 started Apr 21 2011 14:06:31 M5 executing on maize command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/00.gzip/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/00.gzip/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt b/tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt index 5fb65989e..cd3ca8de5 100644 --- a/tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 283332 # Simulator instruction rate (inst/s) -host_mem_usage 214996 # Number of bytes of host memory used -host_seconds 2125.99 # Real time elapsed on the host -host_tick_rate 92433779 # Simulator tick rate (ticks/s) +host_inst_rate 169360 # Simulator instruction rate (inst/s) +host_mem_usage 217476 # Number of bytes of host memory used +host_seconds 3556.69 # Real time elapsed on the host +host_tick_rate 55251704 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 602359865 # Number of instructions simulated sim_seconds 0.196513 # Number of seconds simulated @@ -265,16 +265,16 @@ system.cpu.iew.iewIdleCycles 0 # Nu system.cpu.iew.iewLSQFullEvents 3721 # Number of times the LSQ has become full, causing a stall system.cpu.iew.iewSquashCycles 12871984 # Number of cycles IEW is squashing system.cpu.iew.iewUnblockCycles 65726 # Number of cycles IEW is unblocking -system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 8982 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 25082678 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 87734 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 611520 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 15892 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 27153747 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 11966835 # Number of stores squashed +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.cacheBlocked 8982 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.forwLoads 25082678 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.ignoredResponses 87734 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.memOrderViolation 611520 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.rescheduledLoads 15892 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.squashedLoads 27153747 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedStores 11966835 # Number of stores squashed system.cpu.iew.memOrderViolationEvents 611520 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 628522 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 3676919 # Number of branches that were predicted taken incorrectly diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout b/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout index 9d435e3a3..750396309 100755 --- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout +++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout @@ -5,8 +5,8 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 19 2011 12:19:46 -M5 started Apr 19 2011 12:20:08 +M5 compiled Apr 21 2011 13:27:10 +M5 started Apr 21 2011 13:30:00 M5 executing on maize command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing -re tests/run.py build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt b/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt index 04c8a25b6..9d595253b 100644 --- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt +++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 280029 # Simulator instruction rate (inst/s) -host_mem_usage 206320 # Number of bytes of host memory used -host_seconds 5019.49 # Real time elapsed on the host -host_tick_rate 116031336 # Simulator tick rate (ticks/s) +host_inst_rate 154343 # Simulator instruction rate (inst/s) +host_mem_usage 212152 # Number of bytes of host memory used +host_seconds 9107.03 # Real time elapsed on the host +host_tick_rate 63952564 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1405604152 # Number of instructions simulated sim_seconds 0.582418 # Number of seconds simulated @@ -243,16 +243,16 @@ system.cpu.iew.iewIdleCycles 0 # Nu system.cpu.iew.iewLSQFullEvents 8462 # Number of times the LSQ has become full, causing a stall system.cpu.iew.iewSquashCycles 27885594 # Number of cycles IEW is squashing system.cpu.iew.iewUnblockCycles 128708 # Number of cycles IEW is unblocking -system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 40205 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 129748862 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 35905 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 460365 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 237 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 58644458 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 20174020 # Number of stores squashed +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.cacheBlocked 40205 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.forwLoads 129748862 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.ignoredResponses 35905 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.memOrderViolation 460365 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.rescheduledLoads 237 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.squashedLoads 58644458 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedStores 20174020 # Number of stores squashed system.cpu.iew.memOrderViolationEvents 460365 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 670427 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 5004860 # Number of branches that were predicted taken incorrectly diff --git a/tests/long/00.gzip/ref/x86/linux/o3-timing/simout b/tests/long/00.gzip/ref/x86/linux/o3-timing/simout index f0ad86715..fc45f8a25 100755 --- a/tests/long/00.gzip/ref/x86/linux/o3-timing/simout +++ b/tests/long/00.gzip/ref/x86/linux/o3-timing/simout @@ -5,8 +5,8 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 19 2011 12:22:33 -M5 started Apr 19 2011 12:31:00 +M5 compiled Apr 21 2011 13:30:37 +M5 started Apr 21 2011 13:30:43 M5 executing on maize command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/00.gzip/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/fast/long/00.gzip/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/00.gzip/ref/x86/linux/o3-timing/stats.txt b/tests/long/00.gzip/ref/x86/linux/o3-timing/stats.txt index 99a6b6318..a21571816 100644 --- a/tests/long/00.gzip/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/00.gzip/ref/x86/linux/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 229365 # Simulator instruction rate (inst/s) -host_mem_usage 211952 # Number of bytes of host memory used -host_seconds 7069.49 # Real time elapsed on the host -host_tick_rate 106242349 # Simulator tick rate (ticks/s) +host_inst_rate 131052 # Simulator instruction rate (inst/s) +host_mem_usage 215332 # Number of bytes of host memory used +host_seconds 12372.92 # Real time elapsed on the host +host_tick_rate 60703496 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1621493982 # Number of instructions simulated sim_seconds 0.751079 # Number of seconds simulated @@ -232,16 +232,16 @@ system.cpu.iew.iewIdleCycles 0 # Nu system.cpu.iew.iewLSQFullEvents 6 # Number of times the LSQ has become full, causing a stall system.cpu.iew.iewSquashCycles 99378480 # Number of cycles IEW is squashing system.cpu.iew.iewUnblockCycles 111986 # Number of cycles IEW is unblocking -system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 30239 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 119484333 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 15966 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 6399400 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 47 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 196809249 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 62612798 # Number of stores squashed +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.cacheBlocked 30239 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.forwLoads 119484333 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.ignoredResponses 15966 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.memOrderViolation 6399400 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.rescheduledLoads 47 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.squashedLoads 196809249 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedStores 62612798 # Number of stores squashed system.cpu.iew.memOrderViolationEvents 6399400 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 4677718 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 4430140 # Number of branches that were predicted taken incorrectly diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout index 9ebdcf06b..6aab5269d 100755 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout @@ -5,12 +5,13 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 19 2011 12:17:36 -M5 started Apr 19 2011 12:17:43 +M5 compiled Apr 21 2011 12:02:59 +M5 started Apr 21 2011 13:21:52 M5 executing on maize command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3-dual -re tests/run.py build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3-dual Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/m5/system/binaries/vmlinux + 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 info: Entering event queue @ 0. Starting simulation... info: Launching CPU 1 @ 109002500 Exiting @ tick 1901725056500 because m5_exit instruction encountered diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt index 31187c584..a973eefe5 100644 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 245660 # Simulator instruction rate (inst/s) -host_mem_usage 294304 # Number of bytes of host memory used -host_seconds 232.36 # Real time elapsed on the host -host_tick_rate 8184534150 # Simulator tick rate (ticks/s) +host_inst_rate 146685 # Simulator instruction rate (inst/s) +host_mem_usage 297796 # Number of bytes of host memory used +host_seconds 389.14 # Real time elapsed on the host +host_tick_rate 4887032789 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 57080594 # Number of instructions simulated sim_seconds 1.901725 # Number of seconds simulated @@ -362,16 +362,16 @@ system.cpu0.iew.iewIdleCycles 0 # Nu system.cpu0.iew.iewLSQFullEvents 5675 # Number of times the LSQ has become full, causing a stall system.cpu0.iew.iewSquashCycles 1085015 # Number of cycles IEW is squashing system.cpu0.iew.iewUnblockCycles 526785 # Number of cycles IEW is unblocking -system.cpu0.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread.0.cacheBlocked 157871 # Number of times an access to memory failed due to the cache being blocked -system.cpu0.iew.lsq.thread.0.forwLoads 427137 # Number of loads that had data forwarded from stores -system.cpu0.iew.lsq.thread.0.ignoredResponses 7542 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu0.iew.lsq.thread.0.memOrderViolation 14768 # Number of memory ordering violations -system.cpu0.iew.lsq.thread.0.rescheduledLoads 12869 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread.0.squashedLoads 1004382 # Number of loads squashed -system.cpu0.iew.lsq.thread.0.squashedStores 318301 # Number of stores squashed +system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu0.iew.lsq.thread0.cacheBlocked 157871 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.forwLoads 427137 # Number of loads that had data forwarded from stores +system.cpu0.iew.lsq.thread0.ignoredResponses 7542 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu0.iew.lsq.thread0.memOrderViolation 14768 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.rescheduledLoads 12869 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.squashedLoads 1004382 # Number of loads squashed +system.cpu0.iew.lsq.thread0.squashedStores 318301 # Number of stores squashed system.cpu0.iew.memOrderViolationEvents 14768 # Number of memory order violations system.cpu0.iew.predictedNotTakenIncorrect 331464 # Number of branches that were predicted not taken incorrectly system.cpu0.iew.predictedTakenIncorrect 323527 # Number of branches that were predicted taken incorrectly @@ -978,16 +978,16 @@ system.cpu1.iew.iewIdleCycles 0 # Nu system.cpu1.iew.iewLSQFullEvents 5665 # Number of times the LSQ has become full, causing a stall system.cpu1.iew.iewSquashCycles 401676 # Number of cycles IEW is squashing system.cpu1.iew.iewUnblockCycles 76714 # Number of cycles IEW is unblocking -system.cpu1.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread.0.cacheBlocked 25188 # Number of times an access to memory failed due to the cache being blocked -system.cpu1.iew.lsq.thread.0.forwLoads 88996 # Number of loads that had data forwarded from stores -system.cpu1.iew.lsq.thread.0.ignoredResponses 4435 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu1.iew.lsq.thread.0.memOrderViolation 4299 # Number of memory ordering violations -system.cpu1.iew.lsq.thread.0.rescheduledLoads 5923 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread.0.squashedLoads 416191 # Number of loads squashed -system.cpu1.iew.lsq.thread.0.squashedStores 148395 # Number of stores squashed +system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu1.iew.lsq.thread0.cacheBlocked 25188 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.forwLoads 88996 # Number of loads that had data forwarded from stores +system.cpu1.iew.lsq.thread0.ignoredResponses 4435 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu1.iew.lsq.thread0.memOrderViolation 4299 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.rescheduledLoads 5923 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.squashedLoads 416191 # Number of loads squashed +system.cpu1.iew.lsq.thread0.squashedStores 148395 # Number of stores squashed system.cpu1.iew.memOrderViolationEvents 4299 # Number of memory order violations system.cpu1.iew.predictedNotTakenIncorrect 105547 # Number of branches that were predicted not taken incorrectly system.cpu1.iew.predictedTakenIncorrect 123821 # Number of branches that were predicted taken incorrectly diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout index 4d6dea231..6e8d29977 100755 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout @@ -5,11 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 19 2011 12:17:36 -M5 started Apr 19 2011 12:17:43 +M5 compiled Apr 21 2011 12:02:59 +M5 started Apr 21 2011 13:21:52 M5 executing on maize command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3 -re tests/run.py build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3 Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/m5/system/binaries/vmlinux + 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 info: Entering event queue @ 0. Starting simulation... Exiting @ tick 1863702170500 because m5_exit instruction encountered diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt index 3f1d069d1..3d92c2fae 100644 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 247292 # Simulator instruction rate (inst/s) -host_mem_usage 292024 # Number of bytes of host memory used -host_seconds 214.68 # Real time elapsed on the host -host_tick_rate 8681128138 # Simulator tick rate (ticks/s) +host_inst_rate 146689 # Simulator instruction rate (inst/s) +host_mem_usage 295516 # Number of bytes of host memory used +host_seconds 361.92 # Real time elapsed on the host +host_tick_rate 5149474067 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 53089625 # Number of instructions simulated sim_seconds 1.863702 # Number of seconds simulated @@ -360,16 +360,16 @@ system.cpu.iew.iewIdleCycles 0 # Nu system.cpu.iew.iewLSQFullEvents 12252 # Number of times the LSQ has become full, causing a stall system.cpu.iew.iewSquashCycles 1435065 # Number of cycles IEW is squashing system.cpu.iew.iewUnblockCycles 608300 # Number of cycles IEW is unblocking -system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 167273 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 486953 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 6665 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 18985 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 17936 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 1381305 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 456751 # Number of stores squashed +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.cacheBlocked 167273 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.forwLoads 486953 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.ignoredResponses 6665 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.memOrderViolation 18985 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.rescheduledLoads 17936 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.squashedLoads 1381305 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedStores 456751 # Number of stores squashed system.cpu.iew.memOrderViolationEvents 18985 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 404859 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 429533 # Number of branches that were predicted taken incorrectly diff --git a/tests/long/10.linux-boot/ref/arm/linux/realview-o3/simout b/tests/long/10.linux-boot/ref/arm/linux/realview-o3/simout index 7cdd9066f..64f7ad077 100755 --- a/tests/long/10.linux-boot/ref/arm/linux/realview-o3/simout +++ b/tests/long/10.linux-boot/ref/arm/linux/realview-o3/simout @@ -5,8 +5,8 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 19 2011 13:41:05 -M5 started Apr 19 2011 13:41:08 +M5 compiled Apr 21 2011 12:05:49 +M5 started Apr 21 2011 15:19:16 M5 executing on maize command line: build/ARM_FS/m5.fast -d build/ARM_FS/tests/fast/long/10.linux-boot/arm/linux/realview-o3 -re tests/run.py build/ARM_FS/tests/fast/long/10.linux-boot/arm/linux/realview-o3 Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/10.linux-boot/ref/arm/linux/realview-o3/stats.txt b/tests/long/10.linux-boot/ref/arm/linux/realview-o3/stats.txt index 4fdec7dfb..f3579a27d 100644 --- a/tests/long/10.linux-boot/ref/arm/linux/realview-o3/stats.txt +++ b/tests/long/10.linux-boot/ref/arm/linux/realview-o3/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 182620 # Simulator instruction rate (inst/s) -host_mem_usage 341656 # Number of bytes of host memory used -host_seconds 284.63 # Real time elapsed on the host -host_tick_rate 290422658 # Simulator tick rate (ticks/s) +host_inst_rate 112653 # Simulator instruction rate (inst/s) +host_mem_usage 348660 # Number of bytes of host memory used +host_seconds 461.40 # Real time elapsed on the host +host_tick_rate 179154205 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 51978682 # Number of instructions simulated sim_seconds 0.082662 # Number of seconds simulated @@ -356,16 +356,16 @@ system.cpu.iew.iewIdleCycles 0 # Nu system.cpu.iew.iewLSQFullEvents 45641 # Number of times the LSQ has become full, causing a stall system.cpu.iew.iewSquashCycles 2568567 # Number of cycles IEW is squashing system.cpu.iew.iewUnblockCycles 263948 # Number of cycles IEW is unblocking -system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 8235 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 331109 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 7560 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 280540 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 17000484 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 3641022 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 1649637 # Number of stores squashed +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.cacheBlocked 8235 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.forwLoads 331109 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.ignoredResponses 7560 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.memOrderViolation 280540 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.rescheduledLoads 17000484 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.squashedLoads 3641022 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedStores 1649637 # Number of stores squashed system.cpu.iew.memOrderViolationEvents 280540 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 186102 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 525140 # Number of branches that were predicted taken incorrectly diff --git a/tests/long/10.mcf/ref/arm/linux/o3-timing/simout b/tests/long/10.mcf/ref/arm/linux/o3-timing/simout index 6a4d20d87..7af784c72 100755 --- a/tests/long/10.mcf/ref/arm/linux/o3-timing/simout +++ b/tests/long/10.mcf/ref/arm/linux/o3-timing/simout @@ -5,8 +5,8 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 19 2011 12:47:10 -M5 started Apr 19 2011 12:49:23 +M5 compiled Apr 21 2011 12:05:01 +M5 started Apr 21 2011 14:14:26 M5 executing on maize command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/10.mcf/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/10.mcf/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/10.mcf/ref/arm/linux/o3-timing/stats.txt b/tests/long/10.mcf/ref/arm/linux/o3-timing/stats.txt index 9f9cc3407..465862e0f 100644 --- a/tests/long/10.mcf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/10.mcf/ref/arm/linux/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 230945 # Simulator instruction rate (inst/s) -host_mem_usage 347768 # Number of bytes of host memory used -host_seconds 395.11 # Real time elapsed on the host -host_tick_rate 113371387 # Simulator tick rate (ticks/s) +host_inst_rate 137427 # Simulator instruction rate (inst/s) +host_mem_usage 350244 # Number of bytes of host memory used +host_seconds 663.99 # Real time elapsed on the host +host_tick_rate 67463360 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 91249905 # Number of instructions simulated sim_seconds 0.044795 # Number of seconds simulated @@ -266,16 +266,16 @@ system.cpu.iew.iewIdleCycles 0 # Nu system.cpu.iew.iewLSQFullEvents 187 # Number of times the LSQ has become full, causing a stall system.cpu.iew.iewSquashCycles 5457924 # Number of cycles IEW is squashing system.cpu.iew.iewUnblockCycles 196064 # Number of cycles IEW is unblocking -system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 21877 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 398676 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 24099 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 14224 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 8920401 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 1867594 # Number of stores squashed +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.cacheBlocked 21877 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.forwLoads 398676 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.ignoredResponses 24099 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.memOrderViolation 14224 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.squashedLoads 8920401 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedStores 1867594 # Number of stores squashed system.cpu.iew.memOrderViolationEvents 14224 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 282853 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 1526930 # Number of branches that were predicted taken incorrectly diff --git a/tests/long/10.mcf/ref/x86/linux/o3-timing/simout b/tests/long/10.mcf/ref/x86/linux/o3-timing/simout index c33237447..b2a54aa34 100755 --- a/tests/long/10.mcf/ref/x86/linux/o3-timing/simout +++ b/tests/long/10.mcf/ref/x86/linux/o3-timing/simout @@ -5,8 +5,8 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 19 2011 12:22:33 -M5 started Apr 19 2011 12:30:19 +M5 compiled Apr 21 2011 13:30:37 +M5 started Apr 21 2011 13:35:14 M5 executing on maize command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/10.mcf/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/fast/long/10.mcf/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/10.mcf/ref/x86/linux/o3-timing/stats.txt b/tests/long/10.mcf/ref/x86/linux/o3-timing/stats.txt index 6bc8ba293..516464ff9 100644 --- a/tests/long/10.mcf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/10.mcf/ref/x86/linux/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 265187 # Simulator instruction rate (inst/s) -host_mem_usage 346300 # Number of bytes of host memory used -host_seconds 1049.04 # Real time elapsed on the host -host_tick_rate 77591071 # Simulator tick rate (ticks/s) +host_inst_rate 154675 # Simulator instruction rate (inst/s) +host_mem_usage 349680 # Number of bytes of host memory used +host_seconds 1798.56 # Real time elapsed on the host +host_tick_rate 45256270 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 278192519 # Number of instructions simulated sim_seconds 0.081396 # Number of seconds simulated @@ -233,16 +233,16 @@ system.cpu.iew.iewIdleCycles 0 # Nu system.cpu.iew.iewLSQFullEvents 66782 # Number of times the LSQ has become full, causing a stall system.cpu.iew.iewSquashCycles 12492114 # Number of cycles IEW is squashing system.cpu.iew.iewUnblockCycles 101572 # Number of cycles IEW is unblocking -system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 14164 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 43812375 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 37185 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 237293 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 3275 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 30748500 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 8203432 # Number of stores squashed +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.cacheBlocked 14164 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.forwLoads 43812375 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.ignoredResponses 37185 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.memOrderViolation 237293 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.rescheduledLoads 3275 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.squashedLoads 30748500 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedStores 8203432 # Number of stores squashed system.cpu.iew.memOrderViolationEvents 237293 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 582972 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 2283313 # Number of branches that were predicted taken incorrectly diff --git a/tests/long/20.parser/ref/arm/linux/o3-timing/simout b/tests/long/20.parser/ref/arm/linux/o3-timing/simout index 092b47dee..b82973c4c 100755 --- a/tests/long/20.parser/ref/arm/linux/o3-timing/simout +++ b/tests/long/20.parser/ref/arm/linux/o3-timing/simout @@ -5,8 +5,8 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 19 2011 12:47:10 -M5 started Apr 19 2011 12:52:10 +M5 compiled Apr 21 2011 12:05:01 +M5 started Apr 21 2011 14:20:25 M5 executing on maize command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/20.parser/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/20.parser/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/20.parser/ref/arm/linux/o3-timing/stats.txt b/tests/long/20.parser/ref/arm/linux/o3-timing/stats.txt index 8a2f1e243..c47be9104 100644 --- a/tests/long/20.parser/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/20.parser/ref/arm/linux/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 191028 # Simulator instruction rate (inst/s) -host_mem_usage 221120 # Number of bytes of host memory used -host_seconds 3001.36 # Real time elapsed on the host -host_tick_rate 110860138 # Simulator tick rate (ticks/s) +host_inst_rate 116803 # Simulator instruction rate (inst/s) +host_mem_usage 223612 # Number of bytes of host memory used +host_seconds 4908.63 # Real time elapsed on the host +host_tick_rate 67784916 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 573342397 # Number of instructions simulated sim_seconds 0.332731 # Number of seconds simulated @@ -265,16 +265,16 @@ system.cpu.iew.iewIdleCycles 0 # Nu system.cpu.iew.iewLSQFullEvents 7156 # Number of times the LSQ has become full, causing a stall system.cpu.iew.iewSquashCycles 57332647 # Number of cycles IEW is squashing system.cpu.iew.iewUnblockCycles 209223 # Number of cycles IEW is unblocking -system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 75 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 5626597 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 13730 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 241250 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 24511 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 70118828 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 56769769 # Number of stores squashed +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.cacheBlocked 75 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.forwLoads 5626597 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.ignoredResponses 13730 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.memOrderViolation 241250 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.rescheduledLoads 24511 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.squashedLoads 70118828 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedStores 56769769 # Number of stores squashed system.cpu.iew.memOrderViolationEvents 241250 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 6965983 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 18134157 # Number of branches that were predicted taken incorrectly diff --git a/tests/long/20.parser/ref/x86/linux/o3-timing/simerr b/tests/long/20.parser/ref/x86/linux/o3-timing/simerr index 94d399eab..1dcf06ae0 100755 --- a/tests/long/20.parser/ref/x86/linux/o3-timing/simerr +++ b/tests/long/20.parser/ref/x86/linux/o3-timing/simerr @@ -4,4 +4,5 @@ warn: instruction 'fnstcw_Mw' unimplemented For more information see: http://www.m5sim.org/warn/437d5238 warn: instruction 'fldcw_Mw' unimplemented For more information see: http://www.m5sim.org/warn/437d5238 -hack: be nice to actually delete the event here +m5.fast: build/X86_SE/arch/x86/emulenv.cc:49: void X86ISA::EmulEnv::doModRM(const X86ISA::ExtMachInst&): Assertion `machInst.modRM.mod != 3' failed. +Program aborted at cycle 582313255000 diff --git a/tests/long/20.parser/ref/x86/linux/o3-timing/simout b/tests/long/20.parser/ref/x86/linux/o3-timing/simout index 22653279f..31c2daa64 100755 --- a/tests/long/20.parser/ref/x86/linux/o3-timing/simout +++ b/tests/long/20.parser/ref/x86/linux/o3-timing/simout @@ -5,8 +5,8 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 19 2011 12:22:33 -M5 started Apr 19 2011 12:32:37 +M5 compiled Apr 21 2011 13:30:37 +M5 started Apr 21 2011 13:42:45 M5 executing on maize command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/20.parser/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/fast/long/20.parser/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second @@ -71,6 +71,3 @@ info: Increasing stack size by one page. we like to eat at restaurants , usually on weekends what did John say he thought you should do about 2 million people attended - the five best costumes got prizes -No errors! -Exiting @ tick 584102039000 because target called exit() diff --git a/tests/long/20.parser/ref/x86/linux/o3-timing/stats.txt b/tests/long/20.parser/ref/x86/linux/o3-timing/stats.txt index 6f1b3f3b0..e69de29bb 100644 --- a/tests/long/20.parser/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/20.parser/ref/x86/linux/o3-timing/stats.txt @@ -1,475 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -host_inst_rate 233996 # Simulator instruction rate (inst/s) -host_mem_usage 255168 # Number of bytes of host memory used -host_seconds 6534.25 # Real time elapsed on the host -host_tick_rate 89390880 # Simulator tick rate (ticks/s) -sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 1528988756 # Number of instructions simulated -sim_seconds 0.584102 # Number of seconds simulated -sim_ticks 584102039000 # Number of ticks simulated -system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.BTBHits 218742072 # Number of BTB hits -system.cpu.BPredUnit.BTBLookups 237579384 # Number of BTB lookups -system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.BPredUnit.condIncorrect 16731555 # Number of conditional branches incorrect -system.cpu.BPredUnit.condPredicted 252612909 # Number of conditional branches predicted -system.cpu.BPredUnit.lookups 252612909 # Number of BP lookups -system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. -system.cpu.commit.branchMispredicts 16763223 # The number of times a branch was mispredicted -system.cpu.commit.branches 149758588 # Number of branches committed -system.cpu.commit.bw_lim_events 41097639 # number cycles where commit BW limit reached -system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.commitCommittedInsts 1528988756 # The number of committed instructions -system.cpu.commit.commitNonSpecStalls 553 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 795955462 # The number of squashed insts skipped by commit -system.cpu.commit.committed_per_cycle::samples 1035309655 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.476842 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.993609 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 433213212 41.84% 41.84% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 271303976 26.21% 68.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 102660477 9.92% 77.96% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 102477093 9.90% 87.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 38291141 3.70% 91.56% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 25044351 2.42% 93.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 10787246 1.04% 95.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 10434520 1.01% 96.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 41097639 3.97% 100.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1035309655 # Number of insts commited each cycle -system.cpu.commit.count 1528988756 # Number of instructions committed -system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.int_insts 1528317614 # Number of committed integer instructions. -system.cpu.commit.loads 384102160 # Number of loads committed -system.cpu.commit.membars 0 # Number of memory barriers committed -system.cpu.commit.refs 533262345 # Number of memory references committed -system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.committedInsts 1528988756 # Number of Instructions Simulated -system.cpu.committedInsts_total 1528988756 # Number of Instructions Simulated -system.cpu.cpi 0.764037 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.764037 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 323639192 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 15916.826695 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 8444.942006 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 320628262 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 47924451000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.009303 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 3010930 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 1248670 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 14882183500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.005445 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 1762260 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses 149160201 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 23726.182533 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 18050.899847 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 147539972 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 38441849000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.010862 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 1620229 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 607112 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 18287673500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.006792 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 1013117 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 185.317160 # Average number of references to valid blocks. -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 472799393 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 18648.960228 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 11951.477943 # average overall mshr miss latency -system.cpu.dcache.demand_hits 468168234 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 86366300000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.009795 # miss rate for demand accesses -system.cpu.dcache.demand_misses 4631159 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 1855782 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 33169857000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.005870 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 2775377 # number of demand (read+write) MSHR misses -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_blocks::0 4088.515779 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.998173 # Average percentage of cache occupancy -system.cpu.dcache.overall_accesses 472799393 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 18648.960228 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 11951.477943 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 468168234 # number of overall hits -system.cpu.dcache.overall_miss_latency 86366300000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.009795 # miss rate for overall accesses -system.cpu.dcache.overall_misses 4631159 # number of overall misses -system.cpu.dcache.overall_mshr_hits 1855782 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 33169857000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.005870 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 2775377 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.replacements 2529347 # number of replacements -system.cpu.dcache.sampled_refs 2533443 # Sample count of references to valid blocks. -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4088.515779 # Cycle average of tags in use -system.cpu.dcache.total_refs 469490463 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 2268948000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 2231104 # number of writebacks -system.cpu.decode.BlockedCycles 187291575 # Number of cycles decode is blocked -system.cpu.decode.DecodedInsts 2489806075 # Number of instructions handled by decode -system.cpu.decode.IdleCycles 422005844 # Number of cycles decode is idle -system.cpu.decode.RunCycles 404270583 # Number of cycles decode is running -system.cpu.decode.SquashCycles 108207267 # Number of cycles decode is squashing -system.cpu.decode.UnblockCycles 21741653 # Number of cycles decode is unblocking -system.cpu.fetch.Branches 252612909 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 188594062 # Number of cache lines fetched -system.cpu.fetch.Cycles 440470513 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 3788635 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 1360923556 # Number of instructions fetch has processed -system.cpu.fetch.MiscStallCycles 78504 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.SquashCycles 19199509 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.216240 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 188594062 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 218742072 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 1.164971 # Number of inst fetches per cycle -system.cpu.fetch.rateDist::samples 1143516922 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.221243 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.208291 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 707206433 61.84% 61.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 32665502 2.86% 64.70% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 37223305 3.26% 67.96% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 33654778 2.94% 70.90% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 21116720 1.85% 72.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 40194771 3.52% 76.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 44517058 3.89% 80.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 36097891 3.16% 83.31% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 190840464 16.69% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1143516922 # Number of instructions fetched each cycle (Total) -system.cpu.fp_regfile_reads 40 # number of floating regfile reads -system.cpu.icache.ReadReq_accesses 188594062 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 6510.591789 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 3406.338578 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 188336504 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 1676855000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.001366 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 257558 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 1428 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 872465500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.001358 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 256130 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 16890.533363 # Average number of references to valid blocks. -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 188594062 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 6510.591789 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 3406.338578 # average overall mshr miss latency -system.cpu.icache.demand_hits 188336504 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 1676855000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.001366 # miss rate for demand accesses -system.cpu.icache.demand_misses 257558 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 1428 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 872465500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.001358 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 256130 # number of demand (read+write) MSHR misses -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_blocks::0 960.715295 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.469099 # Average percentage of cache occupancy -system.cpu.icache.overall_accesses 188594062 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 6510.591789 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 3406.338578 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 188336504 # number of overall hits -system.cpu.icache.overall_miss_latency 1676855000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.001366 # miss rate for overall accesses -system.cpu.icache.overall_misses 257558 # number of overall misses -system.cpu.icache.overall_mshr_hits 1428 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 872465500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.001358 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 256130 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.replacements 9707 # number of replacements -system.cpu.icache.sampled_refs 11150 # Sample count of references to valid blocks. -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 960.715295 # Cycle average of tags in use -system.cpu.icache.total_refs 188329447 # Total number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.writebacks 6 # number of writebacks -system.cpu.idleCycles 24687157 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.branchMispredicts 18167511 # Number of branch mispredicts detected at execute -system.cpu.iew.exec_branches 173444431 # Number of branches executed -system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_rate 1.602205 # Inst execution rate -system.cpu.iew.exec_refs 612750445 # number of memory reference insts executed -system.cpu.iew.exec_stores 165978925 # Number of stores executed -system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.iewBlockCycles 9685611 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 586119276 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 9659 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 2269927 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 223085364 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 2324941378 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 446771520 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 30325762 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 1871702722 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 1004270 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 42321 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 108207267 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 1500742 # Number of cycles IEW is unblocking -system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 122021898 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 146459 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 2443893 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 1254 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 202017116 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 73925179 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 2443893 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 2771097 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 15396414 # Number of branches that were predicted taken incorrectly -system.cpu.iew.wb_consumers 2110704618 # num instructions consuming a value -system.cpu.iew.wb_count 1858331416 # cumulative count of insts written-back -system.cpu.iew.wb_fanout 0.678632 # average fanout of values written-back -system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.wb_producers 1432391344 # num instructions producing a value -system.cpu.iew.wb_rate 1.590759 # insts written-back per cycle -system.cpu.iew.wb_sent 1864643959 # cumulative count of insts sent to commit -system.cpu.int_regfile_reads 3111234049 # number of integer regfile reads -system.cpu.int_regfile_writes 1733847214 # number of integer regfile writes -system.cpu.ipc 1.308837 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.308837 # IPC: Total IPC of All Threads -system.cpu.iq.FU_type_0::No_OpClass 2348064 0.12% 0.12% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1272739342 66.91% 67.04% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 67.04% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.04% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.04% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.04% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.04% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.04% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.04% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.04% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.04% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.04% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.04% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.04% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.04% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.04% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.04% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.04% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.04% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.04% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.04% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.04% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.04% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.04% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.04% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.04% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.04% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.04% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.04% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.04% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 456676516 24.01% 91.05% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 170264562 8.95% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1902028484 # Type of FU issued -system.cpu.iq.fp_alu_accesses 77 # Number of floating point alu accesses -system.cpu.iq.fp_inst_queue_reads 156 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_wakeup_accesses 40 # Number of floating instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_writes 7351 # Number of floating instruction queue writes -system.cpu.iq.fu_busy_cnt 11137895 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.005856 # FU busy rate (busy events/executed inst) -system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 1120921 10.06% 10.06% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 10.06% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 10.06% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 10.06% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 10.06% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 10.06% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 10.06% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 10.06% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 10.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 10.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 10.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 10.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 10.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 10.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 10.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 10.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 10.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 10.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 10.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 10.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 10.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 10.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 10.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 10.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 10.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 10.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 10.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 10.06% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 7318318 65.71% 75.77% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 2698656 24.23% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.int_alu_accesses 1910818238 # Number of integer alu accesses -system.cpu.iq.int_inst_queue_reads 4959453857 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_wakeup_accesses 1858331376 # Number of integer instruction queue wakeup accesses -system.cpu.iq.int_inst_queue_writes 3120531509 # Number of integer instruction queue writes -system.cpu.iq.iqInstsAdded 2324931719 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 1902028484 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 9659 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 793159883 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 742228 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 9106 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 1353359987 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.issued_per_cycle::samples 1143516922 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.663315 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.649679 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 363234856 31.76% 31.76% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 268152711 23.45% 55.21% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 190268701 16.64% 71.85% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 150184864 13.13% 84.99% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 96042571 8.40% 93.39% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 45507451 3.98% 97.37% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 20662852 1.81% 99.17% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 8604200 0.75% 99.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 858716 0.08% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1143516922 # Number of insts issued each cycle -system.cpu.iq.rate 1.628165 # Inst issue rate -system.cpu.l2cache.ReadExReq_accesses 775816 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 34258.394889 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31002.535640 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_hits 528344 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_miss_latency 8477993500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate 0.318983 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 247472 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 7672259500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.318983 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 247472 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 1768657 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 34159.791245 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31005.301453 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 1429599 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 11582150500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.191704 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 339058 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 10512595500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.191704 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 339058 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 244851 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 42.349749 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31003.844007 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_hits 1225 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_miss_latency 10317500 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_rate 0.994997 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 243626 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 7553342500 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.994997 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 243626 # number of UpgradeReq MSHR misses -system.cpu.l2cache.Writeback_accesses 2231110 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 2231110 # number of Writeback hits -system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 5.363240 # Average number of references to valid blocks. -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 2544473 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 34201.394643 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31004.134486 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 1957943 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 20060144000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.230511 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 586530 # number of demand (read+write) misses -system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 18184855000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.230511 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 586530 # number of demand (read+write) MSHR misses -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_blocks::0 7751.549385 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 13703.522900 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.236559 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.418198 # Average percentage of cache occupancy -system.cpu.l2cache.overall_accesses 2544473 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 34201.394643 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31004.134486 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 1957943 # number of overall hits -system.cpu.l2cache.overall_miss_latency 20060144000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.230511 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 586530 # number of overall misses -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 18184855000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.230511 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 586530 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.replacements 575744 # number of replacements -system.cpu.l2cache.sampled_refs 594863 # Sample count of references to valid blocks. -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 21455.072285 # Cycle average of tags in use -system.cpu.l2cache.total_refs 3190393 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 306991433000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 412280 # number of writebacks -system.cpu.memDep0.conflictingLoads 354716110 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 139191834 # Number of conflicting stores. -system.cpu.memDep0.insertedLoads 586119276 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 223082546 # Number of stores inserted to the mem dependence unit. -system.cpu.misc_regfile_reads 1024751398 # number of misc regfile reads -system.cpu.numCycles 1168204079 # number of cpu cycles simulated -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.rename.BlockCycles 50725953 # Number of cycles rename is blocking -system.cpu.rename.CommittedMaps 1427299027 # Number of HB maps that are committed -system.cpu.rename.IQFullEvents 53866080 # Number of times rename has blocked due to IQ full -system.cpu.rename.IdleCycles 461056510 # Number of cycles rename is idle -system.cpu.rename.LSQFullEvents 71664979 # Number of times rename has blocked due to LSQ full -system.cpu.rename.ROBFullEvents 8215 # Number of times rename has blocked due to ROB full -system.cpu.rename.RenameLookups 5693696762 # Number of register rename lookups that rename has made -system.cpu.rename.RenamedInsts 2424853504 # Number of instructions processed by rename -system.cpu.rename.RenamedOperands 2263021553 # Number of destination operands rename has renamed -system.cpu.rename.RunCycles 385257729 # Number of cycles rename is running -system.cpu.rename.SquashCycles 108207267 # Number of cycles rename is squashing -system.cpu.rename.UnblockCycles 138255029 # Number of cycles rename is unblocking -system.cpu.rename.UndoneMaps 835722526 # Number of HB maps that are undone due to squashing -system.cpu.rename.fp_rename_lookups 18042 # Number of floating rename lookups -system.cpu.rename.int_rename_lookups 5693678720 # Number of integer rename lookups -system.cpu.rename.serializeStallCycles 14434 # count of cycles rename stalled for serializing inst -system.cpu.rename.serializingInsts 2322 # count of serializing insts renamed -system.cpu.rename.skidInsts 301380597 # count of insts added to the skid buffer -system.cpu.rename.tempSerializingInsts 2286 # count of temporary serializing insts renamed -system.cpu.rob.rob_reads 3319156234 # The number of ROB reads -system.cpu.rob.rob_writes 4758159890 # The number of ROB writes -system.cpu.timesIdled 639156 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.workload.num_syscalls 551 # Number of system calls - ----------- End Simulation Statistics ---------- diff --git a/tests/long/30.eon/ref/alpha/tru64/o3-timing/simout b/tests/long/30.eon/ref/alpha/tru64/o3-timing/simout index caf1c0c92..1209b95f2 100755 --- a/tests/long/30.eon/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/30.eon/ref/alpha/tru64/o3-timing/simout @@ -5,8 +5,8 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 19 2011 11:52:53 -M5 started Apr 19 2011 11:58:24 +M5 compiled Apr 21 2011 12:29:56 +M5 started Apr 21 2011 13:02:51 M5 executing on maize command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/30.eon/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/30.eon/ref/alpha/tru64/o3-timing/stats.txt index 4140bf39e..d0a61b61f 100644 --- a/tests/long/30.eon/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/30.eon/ref/alpha/tru64/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 334419 # Simulator instruction rate (inst/s) -host_mem_usage 210864 # Number of bytes of host memory used -host_seconds 1123.07 # Real time elapsed on the host -host_tick_rate 100628798 # Simulator tick rate (ticks/s) +host_inst_rate 199356 # Simulator instruction rate (inst/s) +host_mem_usage 214136 # Number of bytes of host memory used +host_seconds 1883.94 # Real time elapsed on the host +host_tick_rate 59987309 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 375574812 # Number of instructions simulated sim_seconds 0.113013 # Number of seconds simulated @@ -254,16 +254,16 @@ system.cpu.iew.iewIdleCycles 0 # Nu system.cpu.iew.iewLSQFullEvents 51 # Number of times the LSQ has become full, causing a stall system.cpu.iew.iewSquashCycles 9813191 # Number of cycles IEW is squashing system.cpu.iew.iewUnblockCycles 192371 # Number of cycles IEW is unblocking -system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 10208559 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 208520 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 5629 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 192417 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 12228157 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 12856211 # Number of stores squashed +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.forwLoads 10208559 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.ignoredResponses 208520 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.memOrderViolation 5629 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.rescheduledLoads 192417 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.squashedLoads 12228157 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedStores 12856211 # Number of stores squashed system.cpu.iew.memOrderViolationEvents 5629 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 886790 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 4738827 # Number of branches that were predicted taken incorrectly diff --git a/tests/long/30.eon/ref/arm/linux/o3-timing/simout b/tests/long/30.eon/ref/arm/linux/o3-timing/simout index 09bb8bdda..41f4f6ce7 100755 --- a/tests/long/30.eon/ref/arm/linux/o3-timing/simout +++ b/tests/long/30.eon/ref/arm/linux/o3-timing/simout @@ -5,8 +5,8 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 19 2011 12:47:10 -M5 started Apr 19 2011 12:56:09 +M5 compiled Apr 21 2011 12:05:01 +M5 started Apr 21 2011 14:25:17 M5 executing on maize command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/30.eon/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/30.eon/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/30.eon/ref/arm/linux/o3-timing/stats.txt b/tests/long/30.eon/ref/arm/linux/o3-timing/stats.txt index 22fc80d01..76b5527a0 100644 --- a/tests/long/30.eon/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/30.eon/ref/arm/linux/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 250845 # Simulator instruction rate (inst/s) -host_mem_usage 223896 # Number of bytes of host memory used -host_seconds 1391.56 # Real time elapsed on the host -host_tick_rate 109041329 # Simulator tick rate (ticks/s) +host_inst_rate 153284 # Simulator instruction rate (inst/s) +host_mem_usage 226404 # Number of bytes of host memory used +host_seconds 2277.25 # Real time elapsed on the host +host_tick_rate 66631737 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 349065985 # Number of instructions simulated sim_seconds 0.151737 # Number of seconds simulated @@ -266,16 +266,16 @@ system.cpu.iew.iewIdleCycles 0 # Nu system.cpu.iew.iewLSQFullEvents 34 # Number of times the LSQ has become full, causing a stall system.cpu.iew.iewSquashCycles 5956648 # Number of cycles IEW is squashing system.cpu.iew.iewUnblockCycles 247 # Number of cycles IEW is unblocking -system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 169 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 3624729 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 41298 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 165832 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 270 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 9469235 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 6767279 # Number of stores squashed +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.cacheBlocked 169 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.forwLoads 3624729 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.ignoredResponses 41298 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.memOrderViolation 165832 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.rescheduledLoads 270 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.squashedLoads 9469235 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedStores 6767279 # Number of stores squashed system.cpu.iew.memOrderViolationEvents 165832 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 360118 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 3215056 # Number of branches that were predicted taken incorrectly diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simout b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simout index 2316b9142..2b957fca5 100755 --- a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simout @@ -5,8 +5,8 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 19 2011 11:52:53 -M5 started Apr 19 2011 11:58:35 +M5 compiled Apr 21 2011 12:29:56 +M5 started Apr 21 2011 13:02:51 M5 executing on maize command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt index c6cbb8474..1074a9ea8 100644 --- a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 299190 # Simulator instruction rate (inst/s) -host_mem_usage 211252 # Number of bytes of host memory used -host_seconds 6093.26 # Real time elapsed on the host -host_tick_rate 113092899 # Simulator tick rate (ticks/s) +host_inst_rate 175234 # Simulator instruction rate (inst/s) +host_mem_usage 214520 # Number of bytes of host memory used +host_seconds 10403.50 # Real time elapsed on the host +host_tick_rate 66237786 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1823043370 # Number of instructions simulated sim_seconds 0.689105 # Number of seconds simulated @@ -254,16 +254,16 @@ system.cpu.iew.iewIdleCycles 0 # Nu system.cpu.iew.iewLSQFullEvents 3376 # Number of times the LSQ has become full, causing a stall system.cpu.iew.iewSquashCycles 94589845 # Number of cycles IEW is squashing system.cpu.iew.iewUnblockCycles 136604 # Number of cycles IEW is unblocking -system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 15 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 51921347 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 444 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 1647 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 4160 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 130104006 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 84105156 # Number of stores squashed +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.cacheBlocked 15 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.forwLoads 51921347 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.ignoredResponses 444 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.memOrderViolation 1647 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.rescheduledLoads 4160 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.squashedLoads 130104006 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedStores 84105156 # Number of stores squashed system.cpu.iew.memOrderViolationEvents 1647 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 787925 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 30089490 # Number of branches that were predicted taken incorrectly diff --git a/tests/long/40.perlbmk/ref/arm/linux/o3-timing/simout b/tests/long/40.perlbmk/ref/arm/linux/o3-timing/simout index ef09fb549..7274e4b93 100755 --- a/tests/long/40.perlbmk/ref/arm/linux/o3-timing/simout +++ b/tests/long/40.perlbmk/ref/arm/linux/o3-timing/simout @@ -5,8 +5,8 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 19 2011 12:47:10 -M5 started Apr 19 2011 13:00:27 +M5 compiled Apr 21 2011 12:05:01 +M5 started Apr 21 2011 14:31:07 M5 executing on maize command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/40.perlbmk/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/40.perlbmk/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/40.perlbmk/ref/arm/linux/o3-timing/stats.txt b/tests/long/40.perlbmk/ref/arm/linux/o3-timing/stats.txt index d75eda4b1..4b473ce36 100644 --- a/tests/long/40.perlbmk/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/40.perlbmk/ref/arm/linux/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 198311 # Simulator instruction rate (inst/s) -host_mem_usage 221048 # Number of bytes of host memory used -host_seconds 9507.00 # Real time elapsed on the host -host_tick_rate 91419245 # Simulator tick rate (ticks/s) +host_inst_rate 123746 # Simulator instruction rate (inst/s) +host_mem_usage 223548 # Number of bytes of host memory used +host_seconds 15235.59 # Real time elapsed on the host +host_tick_rate 57045555 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1885343131 # Number of instructions simulated sim_seconds 0.869123 # Number of seconds simulated @@ -266,16 +266,16 @@ system.cpu.iew.iewIdleCycles 0 # Nu system.cpu.iew.iewLSQFullEvents 325 # Number of times the LSQ has become full, causing a stall system.cpu.iew.iewSquashCycles 162682073 # Number of cycles IEW is squashing system.cpu.iew.iewUnblockCycles 10344235 # Number of cycles IEW is unblocking -system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 25 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 36704375 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 1640 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 2659902 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 95 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 314908964 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 201953747 # Number of stores squashed +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.cacheBlocked 25 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.forwLoads 36704375 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.ignoredResponses 1640 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.memOrderViolation 2659902 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.rescheduledLoads 95 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.squashedLoads 314908964 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedStores 201953747 # Number of stores squashed system.cpu.iew.memOrderViolationEvents 2659902 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 7823566 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 38670994 # Number of branches that were predicted taken incorrectly diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout index 0e04160b4..2d55160c7 100755 --- a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout @@ -5,8 +5,8 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 19 2011 11:52:53 -M5 started Apr 19 2011 11:58:35 +M5 compiled Apr 21 2011 12:29:56 +M5 started Apr 21 2011 13:02:51 M5 executing on maize command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt index 2aed2a2e0..713ba31b4 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 329538 # Simulator instruction rate (inst/s) -host_mem_usage 213968 # Number of bytes of host memory used -host_seconds 241.53 # Real time elapsed on the host -host_tick_rate 105857368 # Simulator tick rate (ticks/s) +host_inst_rate 200493 # Simulator instruction rate (inst/s) +host_mem_usage 217108 # Number of bytes of host memory used +host_seconds 396.98 # Real time elapsed on the host +host_tick_rate 64404396 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 79591756 # Number of instructions simulated sim_seconds 0.025567 # Number of seconds simulated @@ -254,16 +254,16 @@ system.cpu.iew.iewIdleCycles 0 # Nu system.cpu.iew.iewLSQFullEvents 1058 # Number of times the LSQ has become full, causing a stall system.cpu.iew.iewSquashCycles 1063649 # Number of cycles IEW is squashing system.cpu.iew.iewUnblockCycles 29880 # Number of cycles IEW is unblocking -system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 30 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 1016178 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 1322 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 6217 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 1472 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 2214794 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 1168217 # Number of stores squashed +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.cacheBlocked 30 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.forwLoads 1016178 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.ignoredResponses 1322 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.memOrderViolation 6217 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.rescheduledLoads 1472 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.squashedLoads 2214794 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedStores 1168217 # Number of stores squashed system.cpu.iew.memOrderViolationEvents 6217 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 133065 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 262730 # Number of branches that were predicted taken incorrectly diff --git a/tests/long/50.vortex/ref/arm/linux/o3-timing/simout b/tests/long/50.vortex/ref/arm/linux/o3-timing/simout index 8381f7581..f3dc52cc8 100755 --- a/tests/long/50.vortex/ref/arm/linux/o3-timing/simout +++ b/tests/long/50.vortex/ref/arm/linux/o3-timing/simout @@ -5,8 +5,8 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 19 2011 12:47:10 -M5 started Apr 19 2011 13:18:26 +M5 compiled Apr 21 2011 12:05:01 +M5 started Apr 21 2011 14:53:22 M5 executing on maize command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/50.vortex/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/50.vortex/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/50.vortex/ref/arm/linux/o3-timing/stats.txt b/tests/long/50.vortex/ref/arm/linux/o3-timing/stats.txt index 50e06cc2a..d0dfce1d1 100644 --- a/tests/long/50.vortex/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/50.vortex/ref/arm/linux/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 252526 # Simulator instruction rate (inst/s) -host_mem_usage 223792 # Number of bytes of host memory used -host_seconds 398.51 # Real time elapsed on the host -host_tick_rate 100102950 # Simulator tick rate (ticks/s) +host_inst_rate 153606 # Simulator instruction rate (inst/s) +host_mem_usage 226292 # Number of bytes of host memory used +host_seconds 655.14 # Real time elapsed on the host +host_tick_rate 60890397 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 100633305 # Number of instructions simulated sim_seconds 0.039892 # Number of seconds simulated @@ -270,16 +270,16 @@ system.cpu.iew.iewIdleCycles 0 # Nu system.cpu.iew.iewLSQFullEvents 6915 # Number of times the LSQ has become full, causing a stall system.cpu.iew.iewSquashCycles 2130394 # Number of cycles IEW is squashing system.cpu.iew.iewUnblockCycles 55938 # Number of cycles IEW is unblocking -system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 7 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 1108085 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 2818 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 8523 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 41 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 2436412 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 1650781 # Number of stores squashed +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.cacheBlocked 7 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.forwLoads 1108085 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.ignoredResponses 2818 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.memOrderViolation 8523 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.rescheduledLoads 41 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.squashedLoads 2436412 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedStores 1650781 # Number of stores squashed system.cpu.iew.memOrderViolationEvents 8523 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 227397 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 647345 # Number of branches that were predicted taken incorrectly diff --git a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simout b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simout index 489ef9061..4b8d5a543 100755 --- a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simout @@ -5,8 +5,8 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 19 2011 11:52:53 -M5 started Apr 19 2011 12:02:34 +M5 compiled Apr 21 2011 12:29:56 +M5 started Apr 21 2011 13:06:19 M5 executing on maize command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt index bd83aa84a..d22652a78 100644 --- a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 279473 # Simulator instruction rate (inst/s) -host_mem_usage 204448 # Number of bytes of host memory used -host_seconds 6211.84 # Real time elapsed on the host -host_tick_rate 113004567 # Simulator tick rate (ticks/s) +host_inst_rate 172416 # Simulator instruction rate (inst/s) +host_mem_usage 207720 # Number of bytes of host memory used +host_seconds 10068.91 # Real time elapsed on the host +host_tick_rate 69716202 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1736043781 # Number of instructions simulated sim_seconds 0.701966 # Number of seconds simulated @@ -262,16 +262,16 @@ system.cpu.iew.iewIdleCycles 0 # Nu system.cpu.iew.iewLSQFullEvents 16282 # Number of times the LSQ has become full, causing a stall system.cpu.iew.iewSquashCycles 83930076 # Number of cycles IEW is squashing system.cpu.iew.iewUnblockCycles 949861 # Number of cycles IEW is unblocking -system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 162061 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 39718780 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 292481 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 198174 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 20 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 165817327 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 66687540 # Number of stores squashed +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.cacheBlocked 162061 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.forwLoads 39718780 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.ignoredResponses 292481 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.memOrderViolation 198174 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.rescheduledLoads 20 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.squashedLoads 165817327 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedStores 66687540 # Number of stores squashed system.cpu.iew.memOrderViolationEvents 198174 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 3374280 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 18296998 # Number of branches that were predicted taken incorrectly diff --git a/tests/long/60.bzip2/ref/arm/linux/o3-timing/simout b/tests/long/60.bzip2/ref/arm/linux/o3-timing/simout index dc1adbfd8..274d54dad 100755 --- a/tests/long/60.bzip2/ref/arm/linux/o3-timing/simout +++ b/tests/long/60.bzip2/ref/arm/linux/o3-timing/simout @@ -5,8 +5,8 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 19 2011 12:47:10 -M5 started Apr 19 2011 13:21:07 +M5 compiled Apr 21 2011 12:05:01 +M5 started Apr 21 2011 15:04:28 M5 executing on maize command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/60.bzip2/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/60.bzip2/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/60.bzip2/ref/arm/linux/o3-timing/stats.txt b/tests/long/60.bzip2/ref/arm/linux/o3-timing/stats.txt index 5a7da6a72..599b799cb 100644 --- a/tests/long/60.bzip2/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/60.bzip2/ref/arm/linux/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 253143 # Simulator instruction rate (inst/s) -host_mem_usage 215164 # Number of bytes of host memory used -host_seconds 6806.72 # Real time elapsed on the host -host_tick_rate 94449374 # Simulator tick rate (ticks/s) +host_inst_rate 154101 # Simulator instruction rate (inst/s) +host_mem_usage 217652 # Number of bytes of host memory used +host_seconds 11181.42 # Real time elapsed on the host +host_tick_rate 57496303 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1723073854 # Number of instructions simulated sim_seconds 0.642891 # Number of seconds simulated @@ -266,16 +266,16 @@ system.cpu.iew.iewIdleCycles 0 # Nu system.cpu.iew.iewLSQFullEvents 76087 # Number of times the LSQ has become full, causing a stall system.cpu.iew.iewSquashCycles 70439042 # Number of cycles IEW is squashing system.cpu.iew.iewUnblockCycles 2509999 # Number of cycles IEW is unblocking -system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 185300 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 54506765 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 584812 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 734835 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 2 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 140151655 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 50405377 # Number of stores squashed +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.cacheBlocked 185300 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.forwLoads 54506765 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.ignoredResponses 584812 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.memOrderViolation 734835 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.rescheduledLoads 2 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.squashedLoads 140151655 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedStores 50405377 # Number of stores squashed system.cpu.iew.memOrderViolationEvents 734835 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 3232685 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 16119258 # Number of branches that were predicted taken incorrectly diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout index ec6c3f639..ac46e69ac 100755 --- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout @@ -5,8 +5,8 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 19 2011 11:52:53 -M5 started Apr 19 2011 11:58:35 +M5 compiled Apr 21 2011 12:29:56 +M5 started Apr 21 2011 13:11:19 M5 executing on maize command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing Couldn't unlink build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing/smred.sav diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt index 8dc1a35af..b64b31530 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 274016 # Simulator instruction rate (inst/s) -host_mem_usage 208580 # Number of bytes of host memory used -host_seconds 307.21 # Real time elapsed on the host -host_tick_rate 111296260 # Simulator tick rate (ticks/s) +host_inst_rate 170645 # Simulator instruction rate (inst/s) +host_mem_usage 211856 # Number of bytes of host memory used +host_seconds 493.30 # Real time elapsed on the host +host_tick_rate 69310511 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 84179709 # Number of instructions simulated sim_seconds 0.034191 # Number of seconds simulated @@ -254,16 +254,16 @@ system.cpu.iew.iewIdleCycles 0 # Nu system.cpu.iew.iewLSQFullEvents 45 # Number of times the LSQ has become full, causing a stall system.cpu.iew.iewSquashCycles 5601227 # Number of cycles IEW is squashing system.cpu.iew.iewUnblockCycles 20318 # Number of cycles IEW is unblocking -system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 1 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 1076434 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 4810 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 361752 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 9740 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 8840023 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 2710213 # Number of stores squashed +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.cacheBlocked 1 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.forwLoads 1076434 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.ignoredResponses 4810 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.memOrderViolation 361752 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.rescheduledLoads 9740 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.squashedLoads 8840023 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedStores 2710213 # Number of stores squashed system.cpu.iew.memOrderViolationEvents 361752 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 455682 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 1627472 # Number of branches that were predicted taken incorrectly diff --git a/tests/long/70.twolf/ref/arm/linux/o3-timing/simout b/tests/long/70.twolf/ref/arm/linux/o3-timing/simout index 573beb25f..e91437a5d 100755 --- a/tests/long/70.twolf/ref/arm/linux/o3-timing/simout +++ b/tests/long/70.twolf/ref/arm/linux/o3-timing/simout @@ -5,8 +5,8 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 19 2011 12:47:10 -M5 started Apr 19 2011 13:27:04 +M5 compiled Apr 21 2011 12:05:01 +M5 started Apr 21 2011 15:06:04 M5 executing on maize command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/70.twolf/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/70.twolf/arm/linux/o3-timing Couldn't unlink build/ARM_SE/tests/fast/long/70.twolf/arm/linux/o3-timing/smred.sav diff --git a/tests/long/70.twolf/ref/arm/linux/o3-timing/stats.txt b/tests/long/70.twolf/ref/arm/linux/o3-timing/stats.txt index cc9da8f96..e312dcfc6 100644 --- a/tests/long/70.twolf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/70.twolf/ref/arm/linux/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 180598 # Simulator instruction rate (inst/s) -host_mem_usage 218960 # Number of bytes of host memory used -host_seconds 1044.69 # Real time elapsed on the host -host_tick_rate 120412102 # Simulator tick rate (ticks/s) +host_inst_rate 111275 # Simulator instruction rate (inst/s) +host_mem_usage 221396 # Number of bytes of host memory used +host_seconds 1695.51 # Real time elapsed on the host +host_tick_rate 74191752 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 188669132 # Number of instructions simulated sim_seconds 0.125793 # Number of seconds simulated @@ -266,16 +266,16 @@ system.cpu.iew.iewIdleCycles 0 # Nu system.cpu.iew.iewLSQFullEvents 2590 # Number of times the LSQ has become full, causing a stall system.cpu.iew.iewSquashCycles 27129630 # Number of cycles IEW is squashing system.cpu.iew.iewUnblockCycles 7356 # Number of cycles IEW is unblocking -system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 954573 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 20572 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 222499 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 3 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 20486294 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 5462392 # Number of stores squashed +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.forwLoads 954573 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.ignoredResponses 20572 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.memOrderViolation 222499 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.rescheduledLoads 3 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.squashedLoads 20486294 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedStores 5462392 # Number of stores squashed system.cpu.iew.memOrderViolationEvents 222499 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 2295597 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 8864678 # Number of branches that were predicted taken incorrectly diff --git a/tests/long/70.twolf/ref/x86/linux/o3-timing/simout b/tests/long/70.twolf/ref/x86/linux/o3-timing/simout index 09f414a42..5be7bed53 100755 --- a/tests/long/70.twolf/ref/x86/linux/o3-timing/simout +++ b/tests/long/70.twolf/ref/x86/linux/o3-timing/simout @@ -5,8 +5,8 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 19 2011 12:22:33 -M5 started Apr 19 2011 12:39:55 +M5 compiled Apr 21 2011 13:30:37 +M5 started Apr 21 2011 13:53:57 M5 executing on maize command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/70.twolf/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/fast/long/70.twolf/x86/linux/o3-timing Couldn't unlink build/X86_SE/tests/fast/long/70.twolf/x86/linux/o3-timing/smred.sav diff --git a/tests/long/70.twolf/ref/x86/linux/o3-timing/stats.txt b/tests/long/70.twolf/ref/x86/linux/o3-timing/stats.txt index 84b97ca66..e5f49060a 100644 --- a/tests/long/70.twolf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/70.twolf/ref/x86/linux/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 200454 # Simulator instruction rate (inst/s) -host_mem_usage 220376 # Number of bytes of host memory used -host_seconds 1104.31 # Real time elapsed on the host -host_tick_rate 96698720 # Simulator tick rate (ticks/s) +host_inst_rate 120975 # Simulator instruction rate (inst/s) +host_mem_usage 223752 # Number of bytes of host memory used +host_seconds 1829.83 # Real time elapsed on the host +host_tick_rate 58358040 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 221363017 # Number of instructions simulated sim_seconds 0.106785 # Number of seconds simulated @@ -233,16 +233,16 @@ system.cpu.iew.iewIdleCycles 0 # Nu system.cpu.iew.iewLSQFullEvents 13026 # Number of times the LSQ has become full, causing a stall system.cpu.iew.iewSquashCycles 23161998 # Number of cycles IEW is squashing system.cpu.iew.iewUnblockCycles 523918 # Number of cycles IEW is unblocking -system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 16343714 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 20445 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 35659 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 45746 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 48346210 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 16601009 # Number of stores squashed +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.forwLoads 16343714 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.ignoredResponses 20445 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.memOrderViolation 35659 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.rescheduledLoads 45746 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.squashedLoads 48346210 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedStores 16601009 # Number of stores squashed system.cpu.iew.memOrderViolationEvents 35659 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 741660 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 2532614 # Number of branches that were predicted taken incorrectly diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/simout b/tests/quick/00.hello/ref/alpha/linux/o3-timing/simout index fb1ddd9ef..41814d32d 100755 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/simout +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/simout @@ -5,8 +5,8 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 19 2011 11:52:53 -M5 started Apr 19 2011 12:00:29 +M5 compiled Apr 21 2011 12:29:56 +M5 started Apr 21 2011 13:14:52 M5 executing on maize command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/o3-timing Global frequency set at 1000000000000 ticks per second diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt index 6483a471a..4a581cbe3 100644 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 150919 # Simulator instruction rate (inst/s) -host_mem_usage 203704 # Number of bytes of host memory used -host_seconds 0.04 # Real time elapsed on the host -host_tick_rate 290889761 # Simulator tick rate (ticks/s) +host_inst_rate 96993 # Simulator instruction rate (inst/s) +host_mem_usage 206980 # Number of bytes of host memory used +host_seconds 0.07 # Real time elapsed on the host +host_tick_rate 187197945 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 6386 # Number of instructions simulated sim_seconds 0.000012 # Number of seconds simulated @@ -252,16 +252,16 @@ system.cpu.iew.iewIdleCycles 0 # Nu system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu.iew.iewSquashCycles 825 # Number of cycles IEW is squashing system.cpu.iew.iewUnblockCycles 9 # Number of cycles IEW is unblocking -system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 44 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 6 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 16 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 959 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 330 # Number of stores squashed +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.forwLoads 44 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.ignoredResponses 6 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.memOrderViolation 16 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.squashedLoads 959 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedStores 330 # Number of stores squashed system.cpu.iew.memOrderViolationEvents 16 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 304 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 125 # Number of branches that were predicted taken incorrectly diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout index fc9118372..8a87312b4 100755 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout @@ -5,8 +5,8 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 19 2011 11:52:53 -M5 started Apr 19 2011 12:04:56 +M5 compiled Apr 21 2011 12:29:56 +M5 started Apr 21 2011 13:15:23 M5 executing on maize command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt index e80a12bfa..b8b5c99cd 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 106844 # Simulator instruction rate (inst/s) -host_mem_usage 202600 # Number of bytes of host memory used -host_seconds 0.02 # Real time elapsed on the host -host_tick_rate 323591910 # Simulator tick rate (ticks/s) +host_inst_rate 66320 # Simulator instruction rate (inst/s) +host_mem_usage 205872 # Number of bytes of host memory used +host_seconds 0.04 # Real time elapsed on the host +host_tick_rate 201598879 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 2387 # Number of instructions simulated sim_seconds 0.000007 # Number of seconds simulated @@ -251,16 +251,16 @@ system.cpu.iew.iewIdleCycles 0 # Nu system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu.iew.iewSquashCycles 374 # Number of cycles IEW is squashing system.cpu.iew.iewUnblockCycles 3 # Number of cycles IEW is unblocking -system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 28 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 4 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 364 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 134 # Number of stores squashed +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.forwLoads 28 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.memOrderViolation 4 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.squashedLoads 364 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedStores 134 # Number of stores squashed system.cpu.iew.memOrderViolationEvents 4 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 118 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 53 # Number of branches that were predicted taken incorrectly diff --git a/tests/quick/00.hello/ref/arm/linux/o3-timing/simout b/tests/quick/00.hello/ref/arm/linux/o3-timing/simout index ca0b775a3..f5ea06dc5 100755 --- a/tests/quick/00.hello/ref/arm/linux/o3-timing/simout +++ b/tests/quick/00.hello/ref/arm/linux/o3-timing/simout @@ -5,8 +5,8 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 19 2011 12:47:10 -M5 started Apr 19 2011 13:32:41 +M5 compiled Apr 21 2011 12:05:01 +M5 started Apr 21 2011 15:18:29 M5 executing on maize command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/quick/00.hello/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/quick/00.hello/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second diff --git a/tests/quick/00.hello/ref/arm/linux/o3-timing/stats.txt b/tests/quick/00.hello/ref/arm/linux/o3-timing/stats.txt index d620e2c6d..1ac2ece63 100644 --- a/tests/quick/00.hello/ref/arm/linux/o3-timing/stats.txt +++ b/tests/quick/00.hello/ref/arm/linux/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 117635 # Simulator instruction rate (inst/s) -host_mem_usage 212912 # Number of bytes of host memory used -host_seconds 0.05 # Real time elapsed on the host -host_tick_rate 220680920 # Simulator tick rate (ticks/s) +host_inst_rate 81044 # Simulator instruction rate (inst/s) +host_mem_usage 215360 # Number of bytes of host memory used +host_seconds 0.07 # Real time elapsed on the host +host_tick_rate 152195453 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5739 # Number of instructions simulated sim_seconds 0.000011 # Number of seconds simulated @@ -265,16 +265,16 @@ system.cpu.iew.iewIdleCycles 0 # Nu system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu.iew.iewSquashCycles 770 # Number of cycles IEW is squashing system.cpu.iew.iewUnblockCycles 26 # Number of cycles IEW is unblocking -system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 52 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 12 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 1171 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 560 # Number of stores squashed +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.forwLoads 52 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.memOrderViolation 12 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.squashedLoads 1171 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedStores 560 # Number of stores squashed system.cpu.iew.memOrderViolationEvents 12 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 246 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 119 # Number of branches that were predicted taken incorrectly diff --git a/tests/quick/00.hello/ref/mips/linux/o3-timing/simout b/tests/quick/00.hello/ref/mips/linux/o3-timing/simout index 5852e6d08..095fea48a 100755 --- a/tests/quick/00.hello/ref/mips/linux/o3-timing/simout +++ b/tests/quick/00.hello/ref/mips/linux/o3-timing/simout @@ -5,8 +5,8 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 19 2011 12:18:54 -M5 started Apr 19 2011 12:19:08 +M5 compiled Apr 21 2011 13:26:02 +M5 started Apr 21 2011 13:26:16 M5 executing on maize command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/o3-timing -re tests/run.py build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/o3-timing Global frequency set at 1000000000000 ticks per second diff --git a/tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt b/tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt index cdb83d87c..57f562650 100644 --- a/tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt +++ b/tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 109180 # Simulator instruction rate (inst/s) -host_mem_usage 204504 # Number of bytes of host memory used -host_seconds 0.05 # Real time elapsed on the host -host_tick_rate 269299917 # Simulator tick rate (ticks/s) +host_inst_rate 83007 # Simulator instruction rate (inst/s) +host_mem_usage 207744 # Number of bytes of host memory used +host_seconds 0.06 # Real time elapsed on the host +host_tick_rate 204865540 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5169 # Number of instructions simulated sim_seconds 0.000013 # Number of seconds simulated @@ -245,16 +245,16 @@ system.cpu.iew.iewIdleCycles 0 # Nu system.cpu.iew.iewLSQFullEvents 1 # Number of times the LSQ has become full, causing a stall system.cpu.iew.iewSquashCycles 636 # Number of cycles IEW is squashing system.cpu.iew.iewUnblockCycles 14 # Number of cycles IEW is unblocking -system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 59 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 5 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 945 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 202 # Number of stores squashed +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.forwLoads 59 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.memOrderViolation 5 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.squashedLoads 945 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedStores 202 # Number of stores squashed system.cpu.iew.memOrderViolationEvents 5 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 259 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 118 # Number of branches that were predicted taken incorrectly diff --git a/tests/quick/00.hello/ref/power/linux/o3-timing/simerr b/tests/quick/00.hello/ref/power/linux/o3-timing/simerr index e5517f525..7f3c6560c 100755 --- a/tests/quick/00.hello/ref/power/linux/o3-timing/simerr +++ b/tests/quick/00.hello/ref/power/linux/o3-timing/simerr @@ -1,5 +1,5 @@ warn: Sockets disabled, not accepting gdb connections For more information see: http://www.m5sim.org/warn/d946bea6 -warn: allowing mmap of file @ fd 32051064. This will break if not /dev/zero. +warn: allowing mmap of file @ fd 34160904. This will break if not /dev/zero. For more information see: http://www.m5sim.org/warn/3a2134f6 hack: be nice to actually delete the event here diff --git a/tests/quick/00.hello/ref/power/linux/o3-timing/simout b/tests/quick/00.hello/ref/power/linux/o3-timing/simout index 5a9dfcd0e..cc20667bc 100755 --- a/tests/quick/00.hello/ref/power/linux/o3-timing/simout +++ b/tests/quick/00.hello/ref/power/linux/o3-timing/simout @@ -5,8 +5,8 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 19 2011 12:19:26 -M5 started Apr 19 2011 12:19:32 +M5 compiled Apr 21 2011 13:26:57 +M5 started Apr 21 2011 13:27:10 M5 executing on maize command line: build/POWER_SE/m5.fast -d build/POWER_SE/tests/fast/quick/00.hello/power/linux/o3-timing -re tests/run.py build/POWER_SE/tests/fast/quick/00.hello/power/linux/o3-timing Global frequency set at 1000000000000 ticks per second diff --git a/tests/quick/00.hello/ref/power/linux/o3-timing/stats.txt b/tests/quick/00.hello/ref/power/linux/o3-timing/stats.txt index 7ecc0010b..082e541b8 100644 --- a/tests/quick/00.hello/ref/power/linux/o3-timing/stats.txt +++ b/tests/quick/00.hello/ref/power/linux/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 146379 # Simulator instruction rate (inst/s) -host_mem_usage 202304 # Number of bytes of host memory used -host_seconds 0.04 # Real time elapsed on the host -host_tick_rate 293581871 # Simulator tick rate (ticks/s) +host_inst_rate 98738 # Simulator instruction rate (inst/s) +host_mem_usage 204672 # Number of bytes of host memory used +host_seconds 0.06 # Real time elapsed on the host +host_tick_rate 198408181 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5800 # Number of instructions simulated sim_seconds 0.000012 # Number of seconds simulated @@ -245,16 +245,16 @@ system.cpu.iew.iewIdleCycles 0 # Nu system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu.iew.iewSquashCycles 549 # Number of cycles IEW is squashing system.cpu.iew.iewUnblockCycles 12 # Number of cycles IEW is unblocking -system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 29 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 1 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 13 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 704 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 390 # Number of stores squashed +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.forwLoads 29 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.ignoredResponses 1 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.memOrderViolation 13 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.squashedLoads 704 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedStores 390 # Number of stores squashed system.cpu.iew.memOrderViolationEvents 13 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 202 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 77 # Number of branches that were predicted taken incorrectly diff --git a/tests/quick/00.hello/ref/x86/linux/o3-timing/simout b/tests/quick/00.hello/ref/x86/linux/o3-timing/simout index 79df40ec6..f23e1efe6 100755 --- a/tests/quick/00.hello/ref/x86/linux/o3-timing/simout +++ b/tests/quick/00.hello/ref/x86/linux/o3-timing/simout @@ -5,8 +5,8 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 19 2011 12:22:33 -M5 started Apr 19 2011 12:38:12 +M5 compiled Apr 21 2011 13:30:37 +M5 started Apr 21 2011 14:05:23 M5 executing on maize command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/quick/00.hello/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/fast/quick/00.hello/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second diff --git a/tests/quick/00.hello/ref/x86/linux/o3-timing/stats.txt b/tests/quick/00.hello/ref/x86/linux/o3-timing/stats.txt index 177a37ea2..71886c36a 100644 --- a/tests/quick/00.hello/ref/x86/linux/o3-timing/stats.txt +++ b/tests/quick/00.hello/ref/x86/linux/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 147922 # Simulator instruction rate (inst/s) -host_mem_usage 208856 # Number of bytes of host memory used -host_seconds 0.07 # Real time elapsed on the host -host_tick_rate 171003814 # Simulator tick rate (ticks/s) +host_inst_rate 99680 # Simulator instruction rate (inst/s) +host_mem_usage 212240 # Number of bytes of host memory used +host_seconds 0.10 # Real time elapsed on the host +host_tick_rate 115331857 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 9809 # Number of instructions simulated sim_seconds 0.000011 # Number of seconds simulated @@ -232,16 +232,16 @@ system.cpu.iew.iewIdleCycles 0 # Nu system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu.iew.iewSquashCycles 1477 # Number of cycles IEW is squashing system.cpu.iew.iewUnblockCycles 20 # Number of cycles IEW is unblocking -system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 69 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 12 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 14 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 1026 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 683 # Number of stores squashed +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.forwLoads 69 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.ignoredResponses 12 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.memOrderViolation 14 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.squashedLoads 1026 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedStores 683 # Number of stores squashed system.cpu.iew.memOrderViolationEvents 14 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 497 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 69 # Number of branches that were predicted taken incorrectly diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout index 138b08408..5cdcc3460 100755 --- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout +++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout @@ -5,8 +5,8 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 19 2011 11:52:53 -M5 started Apr 19 2011 12:00:40 +M5 compiled Apr 21 2011 12:29:56 +M5 started Apr 21 2011 13:15:44 M5 executing on maize command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/01.hello-2T-smt/alpha/linux/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/01.hello-2T-smt/alpha/linux/o3-timing Global frequency set at 1000000000000 ticks per second diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt index 93b62df2d..fe96eb65d 100644 --- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 136040 # Simulator instruction rate (inst/s) -host_mem_usage 204288 # Number of bytes of host memory used -host_seconds 0.09 # Real time elapsed on the host -host_tick_rate 149415554 # Simulator tick rate (ticks/s) +host_inst_rate 78127 # Simulator instruction rate (inst/s) +host_mem_usage 207556 # Number of bytes of host memory used +host_seconds 0.16 # Real time elapsed on the host +host_tick_rate 85893759 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 12773 # Number of instructions simulated sim_seconds 0.000014 # Number of seconds simulated @@ -388,26 +388,26 @@ system.cpu.iew.iewIdleCycles 0 # Nu system.cpu.iew.iewLSQFullEvents 3 # Number of times the LSQ has become full, causing a stall system.cpu.iew.iewSquashCycles 1971 # Number of cycles IEW is squashing system.cpu.iew.iewUnblockCycles 59 # Number of cycles IEW is unblocking -system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 56 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 15 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 1178 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 386 # Number of stores squashed -system.cpu.iew.lsq.thread.1.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.1.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.1.forwLoads 55 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.1.ignoredResponses 10 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread.1.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread.1.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.1.memOrderViolation 13 # Number of memory ordering violations -system.cpu.iew.lsq.thread.1.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.1.squashedLoads 1143 # Number of loads squashed -system.cpu.iew.lsq.thread.1.squashedStores 334 # Number of stores squashed +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.forwLoads 56 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.memOrderViolation 15 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.squashedLoads 1178 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedStores 386 # Number of stores squashed +system.cpu.iew.lsq.thread1.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread1.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread1.forwLoads 55 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread1.ignoredResponses 10 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread1.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread1.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread1.memOrderViolation 13 # Number of memory ordering violations +system.cpu.iew.lsq.thread1.rescheduledLoads 1 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread1.squashedLoads 1143 # Number of loads squashed +system.cpu.iew.lsq.thread1.squashedStores 334 # Number of stores squashed system.cpu.iew.memOrderViolationEvents 28 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 1056 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 257 # Number of branches that were predicted taken incorrectly diff --git a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/simout b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/simout index 1dc2f9c34..67bff692e 100755 --- a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/simout +++ b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/simout @@ -5,8 +5,8 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 19 2011 12:19:46 -M5 started Apr 19 2011 12:19:52 +M5 compiled Apr 21 2011 13:27:10 +M5 started Apr 21 2011 13:28:40 M5 executing on maize command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/o3-timing -re tests/run.py build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/o3-timing Global frequency set at 1000000000000 ticks per second diff --git a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt index 89a5a939e..db37ab210 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt +++ b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 110747 # Simulator instruction rate (inst/s) -host_mem_usage 203956 # Number of bytes of host memory used -host_seconds 0.13 # Real time elapsed on the host -host_tick_rate 142631877 # Simulator tick rate (ticks/s) +host_inst_rate 79158 # Simulator instruction rate (inst/s) +host_mem_usage 209796 # Number of bytes of host memory used +host_seconds 0.18 # Real time elapsed on the host +host_tick_rate 101982426 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 14449 # Number of instructions simulated sim_seconds 0.000019 # Number of seconds simulated @@ -233,16 +233,16 @@ system.cpu.iew.iewIdleCycles 0 # Nu system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu.iew.iewSquashCycles 1159 # Number of cycles IEW is squashing system.cpu.iew.iewUnblockCycles 11 # Number of cycles IEW is unblocking -system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 30 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 30 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 818 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 446 # Number of stores squashed +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.forwLoads 30 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.memOrderViolation 30 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.squashedLoads 818 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedStores 446 # Number of stores squashed system.cpu.iew.memOrderViolationEvents 30 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 560 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 240 # Number of branches that were predicted taken incorrectly diff --git a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout index c40feed46..a126d9514 100755 --- a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout +++ b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout @@ -5,8 +5,8 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 19 2011 12:19:46 -M5 started Apr 19 2011 12:19:52 +M5 compiled Apr 21 2011 13:27:10 +M5 started Apr 21 2011 13:27:31 M5 executing on maize command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/40.m5threads-test-atomic/sparc/linux/o3-timing-mp -re tests/run.py build/SPARC_SE/tests/fast/quick/40.m5threads-test-atomic/sparc/linux/o3-timing-mp Global frequency set at 1000000000000 ticks per second diff --git a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt index 2fc95f0fc..6a03641e3 100644 --- a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt +++ b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 211769 # Simulator instruction rate (inst/s) -host_mem_usage 214500 # Number of bytes of host memory used -host_seconds 5.45 # Real time elapsed on the host -host_tick_rate 21567548 # Simulator tick rate (ticks/s) +host_inst_rate 107432 # Simulator instruction rate (inst/s) +host_mem_usage 220336 # Number of bytes of host memory used +host_seconds 10.73 # Real time elapsed on the host +host_tick_rate 10941647 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1153138 # Number of instructions simulated sim_seconds 0.000117 # Number of seconds simulated @@ -244,16 +244,16 @@ system.cpu0.iew.iewIdleCycles 0 # Nu system.cpu0.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu0.iew.iewSquashCycles 2044 # Number of cycles IEW is squashing system.cpu0.iew.iewUnblockCycles 27 # Number of cycles IEW is unblocking -system.cpu0.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread.0.cacheBlocked 18 # Number of times an access to memory failed due to the cache being blocked -system.cpu0.iew.lsq.thread.0.forwLoads 85880 # Number of loads that had data forwarded from stores -system.cpu0.iew.lsq.thread.0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu0.iew.lsq.thread.0.memOrderViolation 44 # Number of memory ordering violations -system.cpu0.iew.lsq.thread.0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread.0.squashedLoads 1671 # Number of loads squashed -system.cpu0.iew.lsq.thread.0.squashedStores 1054 # Number of stores squashed +system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu0.iew.lsq.thread0.cacheBlocked 18 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.forwLoads 85880 # Number of loads that had data forwarded from stores +system.cpu0.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu0.iew.lsq.thread0.memOrderViolation 44 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.squashedLoads 1671 # Number of loads squashed +system.cpu0.iew.lsq.thread0.squashedStores 1054 # Number of stores squashed system.cpu0.iew.memOrderViolationEvents 44 # Number of memory order violations system.cpu0.iew.predictedNotTakenIncorrect 817 # Number of branches that were predicted not taken incorrectly system.cpu0.iew.predictedTakenIncorrect 425 # Number of branches that were predicted taken incorrectly @@ -639,16 +639,16 @@ system.cpu1.iew.iewIdleCycles 0 # Nu system.cpu1.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu1.iew.iewSquashCycles 1741 # Number of cycles IEW is squashing system.cpu1.iew.iewUnblockCycles 54 # Number of cycles IEW is unblocking -system.cpu1.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu1.iew.lsq.thread.0.forwLoads 37142 # Number of loads that had data forwarded from stores -system.cpu1.iew.lsq.thread.0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu1.iew.lsq.thread.0.memOrderViolation 29 # Number of memory ordering violations -system.cpu1.iew.lsq.thread.0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread.0.squashedLoads 1440 # Number of loads squashed -system.cpu1.iew.lsq.thread.0.squashedStores 770 # Number of stores squashed +system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu1.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.forwLoads 37142 # Number of loads that had data forwarded from stores +system.cpu1.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu1.iew.lsq.thread0.memOrderViolation 29 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.squashedLoads 1440 # Number of loads squashed +system.cpu1.iew.lsq.thread0.squashedStores 770 # Number of stores squashed system.cpu1.iew.memOrderViolationEvents 29 # Number of memory order violations system.cpu1.iew.predictedNotTakenIncorrect 196 # Number of branches that were predicted not taken incorrectly system.cpu1.iew.predictedTakenIncorrect 990 # Number of branches that were predicted taken incorrectly @@ -1033,16 +1033,16 @@ system.cpu2.iew.iewIdleCycles 0 # Nu system.cpu2.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu2.iew.iewSquashCycles 1781 # Number of cycles IEW is squashing system.cpu2.iew.iewUnblockCycles 67 # Number of cycles IEW is unblocking -system.cpu2.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu2.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu2.iew.lsq.thread.0.forwLoads 40852 # Number of loads that had data forwarded from stores -system.cpu2.iew.lsq.thread.0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu2.iew.lsq.thread.0.memOrderViolation 29 # Number of memory ordering violations -system.cpu2.iew.lsq.thread.0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu2.iew.lsq.thread.0.squashedLoads 1554 # Number of loads squashed -system.cpu2.iew.lsq.thread.0.squashedStores 772 # Number of stores squashed +system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu2.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked +system.cpu2.iew.lsq.thread0.forwLoads 40852 # Number of loads that had data forwarded from stores +system.cpu2.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu2.iew.lsq.thread0.memOrderViolation 29 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled +system.cpu2.iew.lsq.thread0.squashedLoads 1554 # Number of loads squashed +system.cpu2.iew.lsq.thread0.squashedStores 772 # Number of stores squashed system.cpu2.iew.memOrderViolationEvents 29 # Number of memory order violations system.cpu2.iew.predictedNotTakenIncorrect 202 # Number of branches that were predicted not taken incorrectly system.cpu2.iew.predictedTakenIncorrect 996 # Number of branches that were predicted taken incorrectly @@ -1427,16 +1427,16 @@ system.cpu3.iew.iewIdleCycles 0 # Nu system.cpu3.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu3.iew.iewSquashCycles 1781 # Number of cycles IEW is squashing system.cpu3.iew.iewUnblockCycles 47 # Number of cycles IEW is unblocking -system.cpu3.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu3.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu3.iew.lsq.thread.0.forwLoads 24834 # Number of loads that had data forwarded from stores -system.cpu3.iew.lsq.thread.0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed -system.cpu3.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu3.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu3.iew.lsq.thread.0.memOrderViolation 29 # Number of memory ordering violations -system.cpu3.iew.lsq.thread.0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu3.iew.lsq.thread.0.squashedLoads 1517 # Number of loads squashed -system.cpu3.iew.lsq.thread.0.squashedStores 742 # Number of stores squashed +system.cpu3.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu3.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked +system.cpu3.iew.lsq.thread0.forwLoads 24834 # Number of loads that had data forwarded from stores +system.cpu3.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed +system.cpu3.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu3.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu3.iew.lsq.thread0.memOrderViolation 29 # Number of memory ordering violations +system.cpu3.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled +system.cpu3.iew.lsq.thread0.squashedLoads 1517 # Number of loads squashed +system.cpu3.iew.lsq.thread0.squashedStores 742 # Number of stores squashed system.cpu3.iew.memOrderViolationEvents 29 # Number of memory order violations system.cpu3.iew.predictedNotTakenIncorrect 182 # Number of branches that were predicted not taken incorrectly system.cpu3.iew.predictedTakenIncorrect 1011 # Number of branches that were predicted taken incorrectly |