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| author | Korey Sewell <ksewell@umich.edu> | 2011-06-19 21:43:42 -0400 |
|---|---|---|
| committer | Korey Sewell <ksewell@umich.edu> | 2011-06-19 21:43:42 -0400 |
| commit | b963b339b9d0f5a4583e62f32766f085ad95529e (patch) | |
| tree | b464533d83eb260f3d9b0c49d4a06a6cfd11f3e5 | |
| parent | eedd04e894b828489975dcc8407eaf9e400d1f15 (diff) | |
| download | gem5-b963b339b9d0f5a4583e62f32766f085ad95529e.tar.xz | |
inorder: se: squash after syscalls
| -rw-r--r-- | src/cpu/inorder/cpu.cc | 11 | ||||
| -rw-r--r-- | src/cpu/inorder/inorder_dyn_inst.hh | 2 |
2 files changed, 11 insertions, 2 deletions
diff --git a/src/cpu/inorder/cpu.cc b/src/cpu/inorder/cpu.cc index fbd4a6068..d8552d9d3 100644 --- a/src/cpu/inorder/cpu.cc +++ b/src/cpu/inorder/cpu.cc @@ -1713,7 +1713,16 @@ InOrderCPU::wakeup() void InOrderCPU::syscallContext(Fault fault, ThreadID tid, DynInstPtr inst, int delay) { - //@todo: squash behind syscall + // Syscall must be non-speculative, so squash from last stage + unsigned squash_stage = NumStages - 1; + inst->setSquashInfo(squash_stage); + + // Squash In Pipeline Stage + pipelineStage[squash_stage]->setupSquash(inst, tid); + + // Schedule Squash Through-out Resource Pool + resPool->scheduleEvent( + (InOrderCPU::CPUEventType)ResourcePool::SquashAll, inst, 0); scheduleCpuEvent(Syscall, fault, tid, inst, delay, Syscall_Pri); } diff --git a/src/cpu/inorder/inorder_dyn_inst.hh b/src/cpu/inorder/inorder_dyn_inst.hh index b655de380..c2d37d716 100644 --- a/src/cpu/inorder/inorder_dyn_inst.hh +++ b/src/cpu/inorder/inorder_dyn_inst.hh @@ -867,7 +867,7 @@ class InOrderDynInst : public FastAlloc, public RefCounted void setFloatSrc(int idx, FloatReg val); void setFloatRegBitsSrc(int idx, TheISA::FloatRegBits val); - uint64_t* getIntSrcPtr(int idx) { return &instSrc[idx].intVal; } + TheISA::IntReg* getIntSrcPtr(int idx) { return &instSrc[idx].intVal; } uint64_t readIntSrc(int idx) { return instSrc[idx].intVal; } /** These Instructions read a integer/float/misc. source register |