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authorKevin Lim <ktlim@umich.edu>2006-06-09 12:25:55 -0400
committerKevin Lim <ktlim@umich.edu>2006-06-09 12:25:55 -0400
commite6a6204b177c91aff8e0865999a8ecc3dcb49e56 (patch)
tree97a6e6bd6b031818412ed7d0836edbe6792b5825
parent068379a9ed22bc00b9544e33b382da8d9aebc13a (diff)
downloadgem5-e6a6204b177c91aff8e0865999a8ecc3dcb49e56.tar.xz
Remove obsolete stuff.
src/cpu/o3/alpha_cpu.hh: Remove functions no longer used for reading and writing. --HG-- extra : convert_revision : aa2fde86ebad06a9a3a9628016b885ff546c0189
-rw-r--r--src/cpu/o3/alpha_cpu.hh99
1 files changed, 0 insertions, 99 deletions
diff --git a/src/cpu/o3/alpha_cpu.hh b/src/cpu/o3/alpha_cpu.hh
index 974b230f3..f81837f3c 100644
--- a/src/cpu/o3/alpha_cpu.hh
+++ b/src/cpu/o3/alpha_cpu.hh
@@ -411,33 +411,6 @@ class AlphaFullCPU : public FullO3CPU<Impl>
void setSyscallReturn(SyscallReturn return_value, int tid);
#endif
- /** Read from memory function. */
- template <class T>
- Fault read(RequestPtr &req, T &data)
- {
-#if 0
-#if FULL_SYSTEM && THE_ISA == ALPHA_ISA
- if (req->flags & LOCKED) {
- req->xc->setMiscReg(TheISA::Lock_Addr_DepTag, req->paddr);
- req->xc->setMiscReg(TheISA::Lock_Flag_DepTag, true);
- }
-#endif
-#endif
- Fault error;
-
-#if FULL_SYSTEM
- // @todo: Fix this LL/SC hack.
- if (req->flags & LOCKED) {
- lockAddr = req->paddr;
- lockFlag = true;
- }
-#endif
-
- error = this->mem->read(req, data);
- data = gtoh(data);
- return error;
- }
-
/** CPU read function, forwards read to LSQ. */
template <class T>
Fault read(RequestPtr &req, T &data, int load_idx)
@@ -445,78 +418,6 @@ class AlphaFullCPU : public FullO3CPU<Impl>
return this->iew.ldstQueue.read(req, data, load_idx);
}
- /** Write to memory function. */
- template <class T>
- Fault write(RequestPtr &req, T &data)
- {
-#if 0
-#if FULL_SYSTEM && THE_ISA == ALPHA_ISA
- ExecContext *xc;
-
- // If this is a store conditional, act appropriately
- if (req->flags & LOCKED) {
- xc = req->xc;
-
- if (req->flags & UNCACHEABLE) {
- // Don't update result register (see stq_c in isa_desc)
- req->result = 2;
- xc->setStCondFailures(0);//Needed? [RGD]
- } else {
- bool lock_flag = xc->readMiscReg(TheISA::Lock_Flag_DepTag);
- Addr lock_addr = xc->readMiscReg(TheISA::Lock_Addr_DepTag);
- req->result = lock_flag;
- if (!lock_flag ||
- ((lock_addr & ~0xf) != (req->paddr & ~0xf))) {
- xc->setMiscReg(TheISA::Lock_Flag_DepTag, false);
- xc->setStCondFailures(xc->readStCondFailures() + 1);
- if (((xc->readStCondFailures()) % 100000) == 0) {
- std::cerr << "Warning: "
- << xc->readStCondFailures()
- << " consecutive store conditional failures "
- << "on cpu " << req->xc->readCpuId()
- << std::endl;
- }
- return NoFault;
- }
- else xc->setStCondFailures(0);
- }
- }
-
- // Need to clear any locked flags on other proccessors for
- // this address. Only do this for succsful Store Conditionals
- // and all other stores (WH64?). Unsuccessful Store
- // Conditionals would have returned above, and wouldn't fall
- // through.
- for (int i = 0; i < this->system->execContexts.size(); i++){
- xc = this->system->execContexts[i];
- if ((xc->readMiscReg(TheISA::Lock_Addr_DepTag) & ~0xf) ==
- (req->paddr & ~0xf)) {
- xc->setMiscReg(TheISA::Lock_Flag_DepTag, false);
- }
- }
-
-#endif
-#endif
-
-#if FULL_SYSTEM
- // @todo: Fix this LL/SC hack.
- if (req->getFlags() & LOCKED) {
- if (req->getFlags() & UNCACHEABLE) {
- req->setScResult(2);
- } else {
- if (this->lockFlag) {
- req->setScResult(1);
- } else {
- req->setScResult(0);
- return NoFault;
- }
- }
- }
-#endif
-
- return this->mem->write(req, (T)htog(data));
- }
-
/** CPU write function, forwards write to LSQ. */
template <class T>
Fault write(RequestPtr &req, T &data, int store_idx)