summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorGabe Black <gblack@eecs.umich.edu>2006-12-16 07:34:34 -0500
committerGabe Black <gblack@eecs.umich.edu>2006-12-16 07:34:34 -0500
commit244506ae12d079e012ec40fe85b68f54d3fd91c6 (patch)
treef1150bc9fe942bf85f32682e6f22acef0205c033
parent6413b74e4ff3ce879852162306dc18213f8562c5 (diff)
downloadgem5-244506ae12d079e012ec40fe85b68f54d3fd91c6.tar.xz
Make sure endian conversion is done on the memory data when it's just set to an existing buffer.
--HG-- extra : convert_revision : 5a890091b6a31b5414acbf68f19e28d7122a98d7
-rw-r--r--src/cpu/o3/lsq_unit_impl.hh15
1 files changed, 12 insertions, 3 deletions
diff --git a/src/cpu/o3/lsq_unit_impl.hh b/src/cpu/o3/lsq_unit_impl.hh
index 7ce3dc9cb..ebd9301f6 100644
--- a/src/cpu/o3/lsq_unit_impl.hh
+++ b/src/cpu/o3/lsq_unit_impl.hh
@@ -601,8 +601,17 @@ LSQUnit<Impl>::writebackStores()
TheISA::IntReg convertedData =
TheISA::htog(storeQueue[storeWBIdx].data);
- memcpy(inst->memData, (uint8_t *)&convertedData,
- req->getSize());
+ //FIXME This is a hack to get SPARC working. It, along with endianness
+ //in the memory system in general, need to be straightened out more
+ //formally. The problem is that the data's endianness is swapped when
+ //it's in the 64 bit data field in the store queue. The data that you
+ //want won't start at the beginning of the field anymore unless it was
+ //a 64 bit access.
+ memcpy(inst->memData,
+ (uint8_t *)&convertedData +
+ (TheISA::ByteOrderDiffers ?
+ (sizeof(TheISA::IntReg) - req->getSize()) : 0),
+ req->getSize());
PacketPtr data_pkt = new Packet(req, Packet::WriteReq, Packet::Broadcast);
data_pkt->dataStatic(inst->memData);
@@ -616,7 +625,7 @@ LSQUnit<Impl>::writebackStores()
DPRINTF(LSQUnit, "D-Cache: Writing back store idx:%i PC:%#x "
"to Addr:%#x, data:%#x [sn:%lli]\n",
storeWBIdx, inst->readPC(),
- req->getPaddr(), *(inst->memData),
+ req->getPaddr(), (int)*(inst->memData),
inst->seqNum);
// @todo: Remove this SC hack once the memory system handles it.