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author | Gabe Black <gblack@eecs.umich.edu> | 2006-12-04 19:55:52 -0500 |
---|---|---|
committer | Gabe Black <gblack@eecs.umich.edu> | 2006-12-04 19:55:52 -0500 |
commit | 251f4e1134731137fa9703bcb39e55be9e0db4f5 (patch) | |
tree | dc554fb7cca983f6be2e622220ecd37f997c7a15 | |
parent | 36c03001bb325a6a180bbd014036966171f354a4 (diff) | |
download | gem5-251f4e1134731137fa9703bcb39e55be9e0db4f5.tar.xz |
Add in code to pass the ASI to translation.
--HG--
extra : convert_revision : 4a985635cda7680abcddaf0bc9579fa03d5bc7c6
-rw-r--r-- | src/arch/sparc/isa/decoder.isa | 50 | ||||
-rw-r--r-- | src/arch/sparc/isa/formats/mem/basicmem.isa | 19 | ||||
-rw-r--r-- | src/arch/sparc/isa/formats/mem/blockmem.isa | 12 | ||||
-rw-r--r-- | src/arch/sparc/isa/formats/mem/util.isa | 15 |
4 files changed, 49 insertions, 47 deletions
diff --git a/src/arch/sparc/isa/decoder.isa b/src/arch/sparc/isa/decoder.isa index 4e09e2e59..a355816ac 100644 --- a/src/arch/sparc/isa/decoder.isa +++ b/src/arch/sparc/isa/decoder.isa @@ -1054,36 +1054,36 @@ decode OP default Unknown::unknown() {{uReg0 = Rd.uw; Rd.uw = Mem.uw;}}, {{Mem.uw = uReg0;}}); - format Load { - 0x10: lduwa({{Rd = Mem.uw;}}); - 0x11: lduba({{Rd = Mem.ub;}}); - 0x12: lduha({{Rd = Mem.uhw;}}); + format LoadAlt { + 0x10: lduwa({{Rd = Mem.uw;}}, {{EXT_ASI}}); + 0x11: lduba({{Rd = Mem.ub;}}, {{EXT_ASI}}); + 0x12: lduha({{Rd = Mem.uhw;}}, {{EXT_ASI}}); 0x13: ldda({{ uint64_t val = Mem.udw; RdLow = val<31:0>; RdHigh = val<63:32>; - }}); + }}, {{EXT_ASI}}); } - format Store { - 0x14: stwa({{Mem.uw = Rd;}}); - 0x15: stba({{Mem.ub = Rd;}}); - 0x16: stha({{Mem.uhw = Rd;}}); - 0x17: stda({{Mem.udw = RdLow<31:0> | RdHigh<31:0> << 32;}}); + format StoreAlt { + 0x14: stwa({{Mem.uw = Rd;}}, {{EXT_ASI}}); + 0x15: stba({{Mem.ub = Rd;}}, {{EXT_ASI}}); + 0x16: stha({{Mem.uhw = Rd;}}, {{EXT_ASI}}); + 0x17: stda({{Mem.udw = RdLow<31:0> | RdHigh<31:0> << 32;}}, {{EXT_ASI}}); } - format Load { - 0x18: ldswa({{Rd = (int32_t)Mem.sw;}}); - 0x19: ldsba({{Rd = (int8_t)Mem.sb;}}); - 0x1A: ldsha({{Rd = (int16_t)Mem.shw;}}); - 0x1B: ldxa({{Rd = (int64_t)Mem.sdw;}}); + format LoadAlt { + 0x18: ldswa({{Rd = (int32_t)Mem.sw;}}, {{EXT_ASI}}); + 0x19: ldsba({{Rd = (int8_t)Mem.sb;}}, {{EXT_ASI}}); + 0x1A: ldsha({{Rd = (int16_t)Mem.shw;}}, {{EXT_ASI}}); + 0x1B: ldxa({{Rd = (int64_t)Mem.sdw;}}, {{EXT_ASI}}); } - 0x1D: LoadStore::ldstuba( + 0x1D: LoadStoreAlt::ldstuba( {{Rd = Mem.ub;}}, - {{Mem.ub = 0xFF}}); - 0x1E: Store::stxa({{Mem.udw = Rd}}); - 0x1F: LoadStore::swapa( + {{Mem.ub = 0xFF}}, {{EXT_ASI}}); + 0x1E: StoreAlt::stxa({{Mem.udw = Rd}}, {{EXT_ASI}}); + 0x1F: LoadStoreAlt::swapa( {{uReg0 = Rd.uw; Rd.uw = Mem.uw;}}, - {{Mem.uw = uReg0;}}); + {{Mem.uw = uReg0;}}, {{EXT_ASI}}); format Trap { 0x20: Load::ldf({{Frd.uw = Mem.uw;}}); 0x21: decode X { @@ -1100,7 +1100,7 @@ decode OP default Unknown::unknown() 0x26: stqf({{fault = new FpDisabled;}}); 0x27: Store::stdf({{Mem.udw = Frd.udw;}}); 0x2D: Nop::prefetch({{ }}); - 0x30: Load::ldfa({{Frd.uw = Mem.uw;}}); + 0x30: LoadAlt::ldfa({{Frd.uw = Mem.uw;}}, {{EXT_ASI}}); 0x32: ldqfa({{fault = new FpDisabled;}}); format LoadAlt { 0x33: decode EXT_ASI { @@ -1152,7 +1152,7 @@ decode OP default Unknown::unknown() //ASI_BLOCK_AS_IF_USER_SECONDARY_LITTLE 0x1F: FailUnimpl::ldblockf_aiusl(); //ASI_BLOCK_PRIMARY - 0xF0: ldblockf_p({{Frd_N.udw = Mem.udw;}}); + 0xF0: ldblockf_p({{Frd_N.udw = Mem.udw;}}, {{EXT_ASI}}); //ASI_BLOCK_SECONDARY 0xF1: FailUnimpl::ldblockf_s(); //ASI_BLOCK_PRIMARY_LITTLE @@ -1235,7 +1235,7 @@ decode OP default Unknown::unknown() //ASI_BLOCK_AS_IF_USER_SECONDARY_LITTLE 0x1F: FailUnimpl::stblockf_aiusl(); //ASI_BLOCK_PRIMARY - 0xF0: stblockf_p({{Mem.udw = Frd_N.udw;}}); + 0xF0: stblockf_p({{Mem.udw = Frd_N.udw;}}, {{EXT_ASI}}); //ASI_BLOCK_SECONDARY 0xF1: FailUnimpl::stblockf_s(); //ASI_BLOCK_PRIMARY_LITTLE @@ -1272,7 +1272,7 @@ decode OP default Unknown::unknown() Mem.uw = Rd.uw; else storeCond = false; - Rd.uw = uReg0;}}); + Rd.uw = uReg0;}}, {{EXT_ASI}}); 0x3D: Nop::prefetcha({{ }}); 0x3E: Cas::casxa( {{uReg0 = Mem.udw;}}, @@ -1280,7 +1280,7 @@ decode OP default Unknown::unknown() Mem.udw = Rd; else storeCond = false; - Rd = uReg0;}}); + Rd = uReg0;}}, {{EXT_ASI}}); } } } diff --git a/src/arch/sparc/isa/formats/mem/basicmem.isa b/src/arch/sparc/isa/formats/mem/basicmem.isa index cb6c2f161..55e9fba45 100644 --- a/src/arch/sparc/isa/formats/mem/basicmem.isa +++ b/src/arch/sparc/isa/formats/mem/basicmem.isa @@ -52,7 +52,7 @@ def template MemDeclare {{ }}; let {{ - def doMemFormat(code, execute, faultCode, name, Name, opt_flags): + def doMemFormat(code, execute, faultCode, name, Name, asi, opt_flags): addrCalcReg = 'EA = Rs1 + Rs2;' addrCalcImm = 'EA = Rs1 + imm;' iop = InstObjParams(name, Name, 'Mem', code, @@ -62,25 +62,26 @@ let {{ header_output = MemDeclare.subst(iop) + MemDeclare.subst(iop_imm) decoder_output = BasicConstructor.subst(iop) + BasicConstructor.subst(iop_imm) decode_block = ROrImmDecode.subst(iop) - exec_output = doDualSplitExecute(code, addrCalcReg, addrCalcImm, execute, - faultCode, name, name + "Imm", Name, Name + "Imm", opt_flags) + exec_output = doDualSplitExecute(code, addrCalcReg, addrCalcImm, + execute, faultCode, name, name + "Imm", Name, Name + "Imm", + asi, opt_flags) return (header_output, decoder_output, exec_output, decode_block) }}; -def format LoadAlt(code, *opt_flags) {{ +def format LoadAlt(code, asi, *opt_flags) {{ (header_output, decoder_output, exec_output, decode_block) = doMemFormat(code, LoadExecute, - AlternateAsiPrivFaultCheck, name, Name, opt_flags) + AlternateASIPrivFaultCheck, name, Name, asi, opt_flags) }}; -def format StoreAlt(code, *opt_flags) {{ +def format StoreAlt(code, asi, *opt_flags) {{ (header_output, decoder_output, exec_output, decode_block) = doMemFormat(code, StoreExecute, - AlternateAsiPrivFaultCheck, name, Name, opt_flags) + AlternateASIPrivFaultCheck, name, Name, asi, opt_flags) }}; def format Load(code, *opt_flags) {{ @@ -88,7 +89,7 @@ def format Load(code, *opt_flags) {{ decoder_output, exec_output, decode_block) = doMemFormat(code, - LoadExecute, '', name, Name, opt_flags) + LoadExecute, '', name, Name, 0, opt_flags) }}; def format Store(code, *opt_flags) {{ @@ -96,5 +97,5 @@ def format Store(code, *opt_flags) {{ decoder_output, exec_output, decode_block) = doMemFormat(code, - StoreExecute, '', name, Name, opt_flags) + StoreExecute, '', name, Name, 0, opt_flags) }}; diff --git a/src/arch/sparc/isa/formats/mem/blockmem.isa b/src/arch/sparc/isa/formats/mem/blockmem.isa index 8b4aca473..7a1a58d13 100644 --- a/src/arch/sparc/isa/formats/mem/blockmem.isa +++ b/src/arch/sparc/isa/formats/mem/blockmem.isa @@ -273,7 +273,7 @@ def template BlockMemMicroConstructor {{ let {{ - def doBlockMemFormat(code, faultCode, execute, name, Name, opt_flags): + def doBlockMemFormat(code, faultCode, execute, name, Name, asi, opt_flags): # XXX Need to take care of pstate.hpriv as well. The lower ASIs # are split into ones that are available in priv and hpriv, and # those that are only available in hpriv @@ -309,12 +309,12 @@ let {{ makeMicroName(name + "Imm", microPc), makeMicroName(Name, microPc), makeMicroName(Name + "Imm", microPc), - opt_flags); + asi, opt_flags); faultCode = '' return (header_output, decoder_output, exec_output, decode_block) }}; -def format BlockLoad(code, *opt_flags) {{ +def format BlockLoad(code, asi, *opt_flags) {{ # We need to make sure to check the highest priority fault last. # That way, if other faults have been detected, they'll be overwritten # rather than the other way around. @@ -323,10 +323,10 @@ def format BlockLoad(code, *opt_flags) {{ decoder_output, exec_output, decode_block) = doBlockMemFormat(code, faultCode, - LoadExecute, name, Name, opt_flags) + LoadExecute, name, Name, asi, opt_flags) }}; -def format BlockStore(code, *opt_flags) {{ +def format BlockStore(code, asi, *opt_flags) {{ # We need to make sure to check the highest priority fault last. # That way, if other faults have been detected, they'll be overwritten # rather than the other way around. @@ -335,5 +335,5 @@ def format BlockStore(code, *opt_flags) {{ decoder_output, exec_output, decode_block) = doBlockMemFormat(code, faultCode, - StoreExecute, name, Name, opt_flags) + StoreExecute, name, Name, asi, opt_flags) }}; diff --git a/src/arch/sparc/isa/formats/mem/util.isa b/src/arch/sparc/isa/formats/mem/util.isa index 857f37160..3c9d33cda 100644 --- a/src/arch/sparc/isa/formats/mem/util.isa +++ b/src/arch/sparc/isa/formats/mem/util.isa @@ -202,7 +202,6 @@ def template StoreExecute {{ Trace::InstRecord *traceData) const { Fault fault = NoFault; - uint64_t write_result = 0; //This is to support the conditional store in cas instructions. //It should be optomized out in all the others bool storeCond = true; @@ -218,7 +217,8 @@ def template StoreExecute {{ } if(storeCond && fault == NoFault) { - fault = xc->write((uint%(mem_acc_size)s_t)Mem, EA, 0, &write_result); + fault = xc->write((uint%(mem_acc_size)s_t)Mem, + EA, %(asi_val)s, 0); } if(fault == NoFault) { @@ -233,7 +233,6 @@ def template StoreExecute {{ Trace::InstRecord * traceData) const { Fault fault = NoFault; - uint64_t write_result = 0; bool storeCond = true; Addr EA; %(op_decl)s; @@ -247,7 +246,8 @@ def template StoreExecute {{ } if(storeCond && fault == NoFault) { - fault = xc->write((uint%(mem_acc_size)s_t)Mem, EA, 0, &write_result); + fault = xc->write((uint%(mem_acc_size)s_t)Mem, + EA, %(asi_val)s, 0); } if(fault == NoFault) { @@ -309,7 +309,8 @@ let {{ //and in the other they're distributed across two. Also note that for //execute functions, the name of the base class doesn't matter. let {{ - def doSplitExecute(code, execute, name, Name, opt_flags, microParam): + def doSplitExecute(code, execute, name, Name, asi, opt_flags, microParam): + microParam["asi_val"] = asi; codeParam = microParam.copy() codeParam["ea_code"] = '' codeIop = InstObjParams(name, Name, '', code, opt_flags, codeParam) @@ -326,13 +327,13 @@ let {{ def doDualSplitExecute(code, eaRegCode, eaImmCode, execute, - faultCode, nameReg, nameImm, NameReg, NameImm, opt_flags): + faultCode, nameReg, nameImm, NameReg, NameImm, asi, opt_flags): executeCode = '' for (eaCode, name, Name) in ( (eaRegCode, nameReg, NameReg), (eaImmCode, nameImm, NameImm)): microParams = {"ea_code" : eaCode, "fault_check": faultCode} executeCode += doSplitExecute(code, execute, name, Name, - opt_flags, microParams) + asi, opt_flags, microParams) return executeCode }}; |