diff options
| author | Ali Saidi <saidi@eecs.umich.edu> | 2008-01-16 11:11:55 -0500 |
|---|---|---|
| committer | Ali Saidi <saidi@eecs.umich.edu> | 2008-01-16 11:11:55 -0500 |
| commit | 48295aa5147b11cdf4eebbf561b65c8d5668c019 (patch) | |
| tree | 2bd0bf851c29c64e268975a7daf9d894e838f1f8 | |
| parent | a1d5beab953b6f97c7f432a53370e68d0f192cc4 (diff) | |
| download | gem5-48295aa5147b11cdf4eebbf561b65c8d5668c019.tar.xz | |
Update long o3 regressions for o3 change in previous changeset
--HG--
extra : convert_revision : 00242105076eb4466cce21038858f2b9d20b2fe2
19 files changed, 1382 insertions, 1372 deletions
diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini index 7a9d0390d..30f3d3df9 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini @@ -371,6 +371,7 @@ euid=100 executable=/dist/m5/cpu2000/binaries/alpha/tru64/gzip gid=100 input=cin +max_stack_size=67108864 output=cout pid=100 ppid=99 diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/m5stats.txt b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/m5stats.txt index c535b6427..556d1aafa 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/m5stats.txt +++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/m5stats.txt @@ -1,40 +1,40 @@ ---------- Begin Simulation Statistics ---------- global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 65676436 # Number of BTB hits -global.BPredUnit.BTBLookups 73156986 # Number of BTB lookups +global.BPredUnit.BTBHits 65678614 # Number of BTB hits +global.BPredUnit.BTBLookups 73159194 # Number of BTB lookups global.BPredUnit.RASInCorrect 166 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 4207318 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 70088985 # Number of conditional branches predicted -global.BPredUnit.lookups 76017379 # Number of BP lookups -global.BPredUnit.usedRAS 1692882 # Number of times the RAS was used to get a target. -host_inst_rate 209676 # Simulator instruction rate (inst/s) -host_mem_usage 200632 # Number of bytes of host memory used -host_seconds 2697.27 # Real time elapsed on the host -host_tick_rate 60257939 # Simulator tick rate (ticks/s) -memdepunit.memDep.conflictingLoads 16721732 # Number of conflicting loads. -memdepunit.memDep.conflictingStores 11866335 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 126743752 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 43041597 # Number of stores inserted to the mem dependence unit. +global.BPredUnit.condIncorrect 4207497 # Number of conditional branches incorrect +global.BPredUnit.condPredicted 70088421 # Number of conditional branches predicted +global.BPredUnit.lookups 76016982 # Number of BP lookups +global.BPredUnit.usedRAS 1692931 # Number of times the RAS was used to get a target. +host_inst_rate 138315 # Simulator instruction rate (inst/s) +host_mem_usage 152792 # Number of bytes of host memory used +host_seconds 4088.86 # Real time elapsed on the host +host_tick_rate 39750263 # Simulator tick rate (ticks/s) +memdepunit.memDep.conflictingLoads 16723579 # Number of conflicting loads. +memdepunit.memDep.conflictingStores 11643802 # Number of conflicting stores. +memdepunit.memDep.insertedLoads 126745064 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 43041730 # Number of stores inserted to the mem dependence unit. sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 565552443 # Number of instructions simulated -sim_seconds 0.162532 # Number of seconds simulated -sim_ticks 162531946000 # Number of ticks simulated +sim_seconds 0.162533 # Number of seconds simulated +sim_ticks 162533215000 # Number of ticks simulated system.cpu.commit.COM:branches 62547159 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 20242536 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 20239745 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 315316083 +system.cpu.commit.COM:committed_per_cycle.samples 315318492 system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 101801168 3228.54% - 1 100686280 3193.19% - 2 36605446 1160.91% - 3 9846862 312.29% - 4 9756830 309.43% - 5 22230548 705.02% - 6 12726034 403.60% - 7 1420379 45.05% - 8 20242536 641.98% + 0 101802812 3228.57% + 1 100686151 3193.16% + 2 36607100 1160.96% + 3 9845619 312.24% + 4 9755343 309.38% + 5 22233236 705.10% + 6 12725159 403.57% + 7 1423327 45.14% + 8 20239745 641.88% system.cpu.commit.COM:committed_per_cycle.max_value 8 system.cpu.commit.COM:committed_per_cycle.end_dist @@ -43,72 +43,72 @@ system.cpu.commit.COM:loads 115049510 # Nu system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 154862033 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 4206693 # The number of times a branch was mispredicted +system.cpu.commit.branchMispredicts 4206873 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 601856963 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 60367294 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 60366337 # The number of squashed insts skipped by commit system.cpu.committedInsts 565552443 # Number of Instructions Simulated system.cpu.committedInsts_total 565552443 # Number of Instructions Simulated -system.cpu.cpi 0.574772 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.574772 # CPI: Total CPI of All Threads +system.cpu.cpi 0.574777 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.574777 # CPI: Total CPI of All Threads system.cpu.dcache.LoadLockedReq_accesses 1 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_hits 1 # number of LoadLockedReq hits -system.cpu.dcache.ReadReq_accesses 111194484 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 32074.811872 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 5025.209404 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 110978275 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 6934863000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_accesses 111194956 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 32075.834031 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 5025.008210 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 110978747 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 6935084000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.001944 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 216209 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 901354 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 1086495500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_hits 901399 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 1086452000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.001944 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 216209 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses 37821041 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 31690.076841 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 5379.514968 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 37483812 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 10686812923 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.008916 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 337229 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 1630280 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 1814128453 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.008916 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 337229 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_accesses 37821036 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 31686.400975 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 5378.935827 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 37483793 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 10686016924 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.008917 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 337243 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 1630285 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 1814008455 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.008917 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 337243 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs 500 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets 1750 # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 314.126008 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 314.127662 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 1 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 4 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 500 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 7000 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 149015525 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 31840.379452 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 5241.100093 # average overall mshr miss latency -system.cpu.dcache.demand_hits 148462087 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 17621675923 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_accesses 149015992 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 31838.535092 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 5240.672100 # average overall mshr miss latency +system.cpu.dcache.demand_hits 148462540 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 17621100924 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.003714 # miss rate for demand accesses -system.cpu.dcache.demand_misses 553438 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 2531634 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 2900623953 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_misses 553452 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 2531684 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 2900460455 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.003714 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 553438 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses 553452 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 149015525 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 31840.379452 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 5241.100093 # average overall mshr miss latency +system.cpu.dcache.overall_accesses 149015992 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 31838.535092 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 5240.672100 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 148462087 # number of overall hits -system.cpu.dcache.overall_miss_latency 17621675923 # number of overall miss cycles +system.cpu.dcache.overall_hits 148462540 # number of overall hits +system.cpu.dcache.overall_miss_latency 17621100924 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.003714 # miss rate for overall accesses -system.cpu.dcache.overall_misses 553438 # number of overall misses -system.cpu.dcache.overall_mshr_hits 2531634 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 2900623953 # number of overall MSHR miss cycles +system.cpu.dcache.overall_misses 553452 # number of overall misses +system.cpu.dcache.overall_mshr_hits 2531684 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 2900460455 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.003714 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 553438 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses 553452 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -120,104 +120,104 @@ system.cpu.dcache.prefetcher.num_hwpf_issued 0 system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.dcache.replacements 468780 # number of replacements -system.cpu.dcache.sampled_refs 472876 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 468779 # number of replacements +system.cpu.dcache.sampled_refs 472875 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4095.312024 # Cycle average of tags in use -system.cpu.dcache.total_refs 148542650 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 41060000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 334093 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 42961711 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 654 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 4159669 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 688665550 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 143212697 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 123677184 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 9747531 # Number of cycles decode is squashing +system.cpu.dcache.tagsinuse 4095.311897 # Cycle average of tags in use +system.cpu.dcache.total_refs 148543118 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 41066000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 334108 # number of writebacks +system.cpu.decode.DECODE:BlockedCycles 42961752 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 653 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 4159719 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 688664661 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 143214202 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 123678077 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 9747660 # Number of cycles decode is squashing system.cpu.decode.DECODE:SquashedInsts 1998 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 5464492 # Number of cycles decode is unblocking -system.cpu.dtb.accesses 162979892 # DTB accesses +system.cpu.decode.DECODE:UnblockCycles 5464462 # Number of cycles decode is unblocking +system.cpu.dtb.accesses 162980626 # DTB accesses system.cpu.dtb.acv 0 # DTB access violations -system.cpu.dtb.hits 162933690 # DTB hits -system.cpu.dtb.misses 46202 # DTB misses -system.cpu.dtb.read_accesses 122208199 # DTB read accesses +system.cpu.dtb.hits 162934426 # DTB hits +system.cpu.dtb.misses 46200 # DTB misses +system.cpu.dtb.read_accesses 122208799 # DTB read accesses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_hits 122186821 # DTB read hits +system.cpu.dtb.read_hits 122187421 # DTB read hits system.cpu.dtb.read_misses 21378 # DTB read misses -system.cpu.dtb.write_accesses 40771693 # DTB write accesses +system.cpu.dtb.write_accesses 40771827 # DTB write accesses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_hits 40746869 # DTB write hits -system.cpu.dtb.write_misses 24824 # DTB write misses -system.cpu.fetch.Branches 76017379 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 65923007 # Number of cache lines fetched -system.cpu.fetch.Cycles 196871509 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 1349795 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 697858274 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 4233156 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.233854 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 65923007 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 67369318 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 2.146834 # Number of inst fetches per cycle +system.cpu.dtb.write_hits 40747005 # DTB write hits +system.cpu.dtb.write_misses 24822 # DTB write misses +system.cpu.fetch.Branches 76016982 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 65923476 # Number of cache lines fetched +system.cpu.fetch.Cycles 196873041 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 1349337 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 697858040 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 4233176 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.233851 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 65923476 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 67371545 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 2.146817 # Number of inst fetches per cycle system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 325063615 +system.cpu.fetch.rateDist.samples 325066153 system.cpu.fetch.rateDist.min_value 0 - 0 194115151 5971.61% - 1 10367448 318.94% - 2 15852914 487.69% - 3 14602370 449.22% - 4 12321515 379.05% - 5 14794025 455.11% - 6 6009823 184.88% - 7 3340187 102.75% - 8 53660182 1650.76% + 0 194116627 5971.60% + 1 10367231 318.93% + 2 15852568 487.67% + 3 14603242 449.24% + 4 12321166 379.04% + 5 14797813 455.22% + 6 6009182 184.86% + 7 3339466 102.73% + 8 53658858 1650.71% system.cpu.fetch.rateDist.max_value 8 system.cpu.fetch.rateDist.end_dist -system.cpu.icache.ReadReq_accesses 65922920 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 7890.798226 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 5470.620843 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 65922018 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 7117500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_accesses 65923389 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 7895 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 5473.888889 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 65922489 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 7105500 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000014 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 902 # number of ReadReq misses +system.cpu.icache.ReadReq_misses 900 # number of ReadReq misses system.cpu.icache.ReadReq_mshr_hits 87 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 4934500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 4926500 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000014 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 902 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses 900 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_refs 73084.277162 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 73247.210000 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 65922920 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 7890.798226 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 5470.620843 # average overall mshr miss latency -system.cpu.icache.demand_hits 65922018 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 7117500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_accesses 65923389 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 7895 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 5473.888889 # average overall mshr miss latency +system.cpu.icache.demand_hits 65922489 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 7105500 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000014 # miss rate for demand accesses -system.cpu.icache.demand_misses 902 # number of demand (read+write) misses +system.cpu.icache.demand_misses 900 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 87 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 4934500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 4926500 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.000014 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 902 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses 900 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 65922920 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 7890.798226 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 5470.620843 # average overall mshr miss latency +system.cpu.icache.overall_accesses 65923389 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 7895 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 5473.888889 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 65922018 # number of overall hits -system.cpu.icache.overall_miss_latency 7117500 # number of overall miss cycles +system.cpu.icache.overall_hits 65922489 # number of overall hits +system.cpu.icache.overall_miss_latency 7105500 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000014 # miss rate for overall accesses -system.cpu.icache.overall_misses 902 # number of overall misses +system.cpu.icache.overall_misses 900 # number of overall misses system.cpu.icache.overall_mshr_hits 87 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 4934500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 4926500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.000014 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 902 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses 900 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -230,62 +230,62 @@ system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.icache.replacements 32 # number of replacements -system.cpu.icache.sampled_refs 902 # Sample count of references to valid blocks. +system.cpu.icache.sampled_refs 900 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 770.534444 # Cycle average of tags in use -system.cpu.icache.total_refs 65922018 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 770.534648 # Cycle average of tags in use +system.cpu.icache.total_refs 65922489 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idleCycles 278 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 67319692 # Number of branches executed -system.cpu.iew.EXEC:nop 42991424 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.842345 # Inst execution rate -system.cpu.iew.EXEC:refs 163918711 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 41167815 # Number of stores executed +system.cpu.iew.EXEC:branches 67319887 # Number of branches executed +system.cpu.iew.EXEC:nop 42990354 # number of nop insts executed +system.cpu.iew.EXEC:rate 1.842336 # Inst execution rate +system.cpu.iew.EXEC:refs 163919489 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 41167987 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 490977460 # num instructions consuming a value -system.cpu.iew.WB:count 595732364 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.805927 # average fanout of values written-back +system.cpu.iew.WB:consumers 490978856 # num instructions consuming a value +system.cpu.iew.WB:count 595734223 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.805928 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 395691865 # num instructions producing a value -system.cpu.iew.WB:rate 1.832662 # insts written-back per cycle -system.cpu.iew.WB:sent 596897738 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 4671822 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 211982 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 126743752 # Number of dispatched load instructions +system.cpu.iew.WB:producers 395693750 # num instructions producing a value +system.cpu.iew.WB:rate 1.832654 # insts written-back per cycle +system.cpu.iew.WB:sent 596899727 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 4672210 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 212004 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 126745064 # Number of dispatched load instructions system.cpu.iew.iewDispNonSpecInsts 22 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 3268805 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 43041597 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 662373944 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 122750896 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 6416858 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 598879902 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 1310 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewDispSquashedInsts 3267944 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 43041730 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 662372892 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 122751502 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 6416138 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 598881635 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 1312 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewLSQFullEvents 2 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 9747531 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 36871 # Number of cycles IEW is unblocking +system.cpu.iew.iewSquashCycles 9747660 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 36859 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 104 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 10085062 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 15402 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.cacheBlocked 103 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread.0.forwLoads 10085137 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 15442 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 28955 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 5897 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 11694242 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 3229074 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 28955 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 540642 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 4131180 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 1.739819 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.739819 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0 605296760 # Type of FU issued +system.cpu.iew.lsq.thread.0.memOrderViolation 28688 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.rescheduledLoads 5905 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 11695554 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 3229207 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 28688 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 540377 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 4131833 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 1.739806 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.739806 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0 605297773 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist No_OpClass 0 0.00% # Type of FU issued - IntAlu 438526639 72.45% # Type of FU issued - IntMult 6526 0.00% # Type of FU issued + IntAlu 438526975 72.45% # Type of FU issued + IntMult 6523 0.00% # Type of FU issued IntDiv 0 0.00% # Type of FU issued FloatAdd 29 0.00% # Type of FU issued FloatCmp 5 0.00% # Type of FU issued @@ -293,16 +293,16 @@ system.cpu.iq.ISSUE:FU_type_0.start_dist FloatMult 4 0.00% # Type of FU issued FloatDiv 0 0.00% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued - MemRead 124781721 20.61% # Type of FU issued - MemWrite 41981831 6.94% # Type of FU issued + MemRead 124782414 20.62% # Type of FU issued + MemWrite 41981818 6.94% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.end_dist -system.cpu.iq.ISSUE:fu_busy_cnt 6717566 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.011098 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_cnt 6685852 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.011046 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full.start_dist No_OpClass 0 0.00% # attempts to use FU when none available - IntAlu 5391256 80.26% # attempts to use FU when none available + IntAlu 5359505 80.16% # attempts to use FU when none available IntMult 67 0.00% # attempts to use FU when none available IntDiv 0 0.00% # attempts to use FU when none available FloatAdd 0 0.00% # attempts to use FU when none available @@ -311,105 +311,105 @@ system.cpu.iq.ISSUE:fu_full.start_dist FloatMult 0 0.00% # attempts to use FU when none available FloatDiv 0 0.00% # attempts to use FU when none available FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 838838 12.49% # attempts to use FU when none available - MemWrite 487405 7.26% # attempts to use FU when none available + MemRead 838830 12.55% # attempts to use FU when none available + MemWrite 487450 7.29% # attempts to use FU when none available IprAccess 0 0.00% # attempts to use FU when none available InstPrefetch 0 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full.end_dist system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 325063615 +system.cpu.iq.ISSUE:issued_per_cycle.samples 325066153 system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 85796359 2639.37% - 1 67542387 2077.82% - 2 80092036 2463.89% - 3 31532999 970.06% - 4 32045835 985.83% - 5 15660373 481.76% - 6 10783606 331.74% - 7 1095697 33.71% - 8 514323 15.82% + 0 85827750 2640.32% + 1 67513195 2076.91% + 2 80091695 2463.86% + 3 31532922 970.05% + 4 32017064 984.94% + 5 15691258 482.71% + 6 10782100 331.69% + 7 1096076 33.72% + 8 514093 15.82% system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 system.cpu.iq.ISSUE:issued_per_cycle.end_dist -system.cpu.iq.ISSUE:rate 1.862085 # Inst issue rate -system.cpu.iq.iqInstsAdded 619382498 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 605296760 # Number of instructions issued +system.cpu.iq.ISSUE:rate 1.862074 # Inst issue rate +system.cpu.iq.iqInstsAdded 619382516 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 605297773 # Number of instructions issued system.cpu.iq.iqNonSpecInstsAdded 22 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 52509739 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 11652 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 52509276 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 11692 # Number of squashed instructions issued system.cpu.iq.iqSquashedNonSpecRemoved 5 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 28327252 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.itb.accesses 65923045 # ITB accesses +system.cpu.iq.iqSquashedOperandsExamined 28325149 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.itb.accesses 65923515 # ITB accesses system.cpu.itb.acv 0 # ITB acv -system.cpu.itb.hits 65923007 # ITB hits -system.cpu.itb.misses 38 # ITB misses -system.cpu.l2cache.ReadExReq_accesses 256667 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 4174.217956 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 2174.217956 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 1071384000 # number of ReadExReq miss cycles +system.cpu.itb.hits 65923476 # ITB hits +system.cpu.itb.misses 39 # ITB misses +system.cpu.l2cache.ReadExReq_accesses 256666 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 4174.356946 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 2174.356946 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 1071415500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 256667 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 558050000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_misses 256666 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 558083500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 256667 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 217111 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 4357.993028 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2357.993028 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 30930 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 811375500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.857538 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 186181 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 439013500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.857538 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 186181 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 80592 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 4188.374777 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 2188.374777 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 337549500 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_mshr_misses 256666 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 217109 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 4357.887472 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2357.887472 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 30915 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 811412500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.857606 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 186194 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 439024500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.857606 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 186194 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_accesses 80608 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_avg_miss_latency 4188.213329 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 2188.213329 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 337603500 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 80592 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 176365500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_misses 80608 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 176387500 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 80592 # number of UpgradeReq MSHR misses -system.cpu.l2cache.Writeback_accesses 334093 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_mshr_misses 80608 # number of UpgradeReq MSHR misses +system.cpu.l2cache.Writeback_accesses 334108 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_miss_rate 1 # miss rate for Writeback accesses -system.cpu.l2cache.Writeback_misses 334093 # number of Writeback misses +system.cpu.l2cache.Writeback_misses 334108 # number of Writeback misses system.cpu.l2cache.Writeback_mshr_miss_rate 1 # mshr miss rate for Writeback accesses -system.cpu.l2cache.Writeback_mshr_misses 334093 # number of Writeback MSHR misses +system.cpu.l2cache.Writeback_mshr_misses 334108 # number of Writeback MSHR misses system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 4.206809 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 4.193877 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 473778 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 4251.480192 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 2251.480192 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 30930 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 1882759500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.934716 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 442848 # number of demand (read+write) misses +system.cpu.l2cache.demand_accesses 473775 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 4251.519668 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 2251.519668 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 30915 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 1882828000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.934748 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 442860 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 997063500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.934716 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 442848 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 997108000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.934748 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 442860 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 473778 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 4251.480192 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 2251.480192 # average overall mshr miss latency +system.cpu.l2cache.overall_accesses 473775 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 4251.519668 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 2251.519668 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 30930 # number of overall hits -system.cpu.l2cache.overall_miss_latency 1882759500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.934716 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 442848 # number of overall misses +system.cpu.l2cache.overall_hits 30915 # number of overall hits +system.cpu.l2cache.overall_miss_latency 1882828000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.934748 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 442860 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 997063500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.934716 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 442848 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 997108000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.934748 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 442860 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -421,29 +421,29 @@ system.cpu.l2cache.prefetcher.num_hwpf_issued 0 system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.l2cache.replacements 14218 # number of replacements -system.cpu.l2cache.sampled_refs 15715 # Sample count of references to valid blocks. +system.cpu.l2cache.replacements 14216 # number of replacements +system.cpu.l2cache.sampled_refs 15711 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 8150.643180 # Cycle average of tags in use -system.cpu.l2cache.total_refs 66110 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 8150.478384 # Cycle average of tags in use +system.cpu.l2cache.total_refs 65890 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.numCycles 325063893 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 11040699 # Number of cycles rename is blocking +system.cpu.numCycles 325066431 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 11040761 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 463854889 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 31586100 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 150557156 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 290380 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:RenameLookups 895272473 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 679363424 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 518606333 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 116560800 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 9747531 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 37157112 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 54751444 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 317 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:IQFullEvents 31586128 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 150557906 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 290343 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:RenameLookups 895274322 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 679363736 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 518608699 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 116562402 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 9747660 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 37157110 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 54753810 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 314 # count of cycles rename stalled for serializing inst system.cpu.rename.RENAME:serializingInsts 27 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 72001269 # count of insts added to the skid buffer +system.cpu.rename.RENAME:skidInsts 72001236 # count of insts added to the skid buffer system.cpu.rename.RENAME:tempSerializingInsts 25 # count of temporary serializing insts renamed system.cpu.timesIdled 103 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 17 # Number of system calls diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stderr b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stderr index f33d007a7..5992f7131 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stderr +++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stderr @@ -1,2 +1,3 @@ +0: system.remote_gdb.listener: listening for remote gdb on port 7000 warn: Entering event queue @ 0. Starting simulation... warn: Increasing stack size by one page. diff --git a/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini b/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini index 895539fc6..577c5ef58 100644 --- a/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini @@ -371,6 +371,7 @@ euid=100 executable=/dist/m5/cpu2000/binaries/alpha/tru64/eon gid=100 input=cin +max_stack_size=67108864 output=cout pid=100 ppid=99 diff --git a/tests/long/30.eon/ref/alpha/tru64/o3-timing/m5stats.txt b/tests/long/30.eon/ref/alpha/tru64/o3-timing/m5stats.txt index f75afa011..083930534 100644 --- a/tests/long/30.eon/ref/alpha/tru64/o3-timing/m5stats.txt +++ b/tests/long/30.eon/ref/alpha/tru64/o3-timing/m5stats.txt @@ -1,112 +1,112 @@ ---------- Begin Simulation Statistics ---------- global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 36861570 # Number of BTB hits -global.BPredUnit.BTBLookups 45954115 # Number of BTB lookups -global.BPredUnit.RASInCorrect 1137 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 5797485 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 35586107 # Number of conditional branches predicted -global.BPredUnit.lookups 62816866 # Number of BP lookups -global.BPredUnit.usedRAS 12584281 # Number of times the RAS was used to get a target. -host_inst_rate 162238 # Simulator instruction rate (inst/s) -host_mem_usage 208244 # Number of bytes of host memory used -host_seconds 2314.96 # Real time elapsed on the host -host_tick_rate 56377317 # Simulator tick rate (ticks/s) -memdepunit.memDep.conflictingLoads 72605768 # Number of conflicting loads. -memdepunit.memDep.conflictingStores 52678550 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 125601766 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 92855490 # Number of stores inserted to the mem dependence unit. +global.BPredUnit.BTBHits 37379171 # Number of BTB hits +global.BPredUnit.BTBLookups 46054369 # Number of BTB lookups +global.BPredUnit.RASInCorrect 1065 # Number of incorrect RAS predictions. +global.BPredUnit.condIncorrect 5708678 # Number of conditional branches incorrect +global.BPredUnit.condPredicted 35676925 # Number of conditional branches predicted +global.BPredUnit.lookups 62521881 # Number of BP lookups +global.BPredUnit.usedRAS 12341843 # Number of times the RAS was used to get a target. +host_inst_rate 102114 # Simulator instruction rate (inst/s) +host_mem_usage 157724 # Number of bytes of host memory used +host_seconds 3678.00 # Real time elapsed on the host +host_tick_rate 36798411 # Simulator tick rate (ticks/s) +memdepunit.memDep.conflictingLoads 72021924 # Number of conflicting loads. +memdepunit.memDep.conflictingStores 51152813 # Number of conflicting stores. +memdepunit.memDep.insertedLoads 125316087 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 92822357 # Number of stores inserted to the mem dependence unit. sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 375574833 # Number of instructions simulated -sim_seconds 0.130511 # Number of seconds simulated -sim_ticks 130511349000 # Number of ticks simulated -system.cpu.commit.COM:branches 44587535 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 13042688 # number cycles where commit BW limit reached +sim_insts 375574819 # Number of instructions simulated +sim_seconds 0.135344 # Number of seconds simulated +sim_ticks 135344388000 # Number of ticks simulated +system.cpu.commit.COM:branches 44587532 # Number of branches committed +system.cpu.commit.COM:bw_lim_events 13263433 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 245378648 +system.cpu.commit.COM:committed_per_cycle.samples 255158972 system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 113059928 4607.57% - 1 50147502 2043.68% - 2 19710557 803.27% - 3 20862995 850.24% - 4 12236933 498.70% - 5 8068065 328.80% - 6 4872414 198.57% - 7 3377566 137.65% - 8 13042688 531.53% + 0 123402584 4836.30% + 1 50437147 1976.70% + 2 19727704 773.15% + 3 19711791 772.53% + 4 11050231 433.07% + 5 9028978 353.86% + 6 5576340 218.54% + 7 2960764 116.04% + 8 13263433 519.81% system.cpu.commit.COM:committed_per_cycle.max_value 8 system.cpu.commit.COM:committed_per_cycle.end_dist -system.cpu.commit.COM:count 398664608 # Number of instructions committed -system.cpu.commit.COM:loads 100651996 # Number of loads committed +system.cpu.commit.COM:count 398664594 # Number of instructions committed +system.cpu.commit.COM:loads 100651995 # Number of loads committed system.cpu.commit.COM:membars 0 # Number of memory barriers committed -system.cpu.commit.COM:refs 174183399 # Number of memory references committed +system.cpu.commit.COM:refs 174183397 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 5793282 # The number of times a branch was mispredicted -system.cpu.commit.commitCommittedInsts 398664608 # The number of committed instructions +system.cpu.commit.branchMispredicts 5704488 # The number of times a branch was mispredicted +system.cpu.commit.commitCommittedInsts 398664594 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 215 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 97412298 # The number of squashed insts skipped by commit -system.cpu.committedInsts 375574833 # Number of Instructions Simulated -system.cpu.committedInsts_total 375574833 # Number of Instructions Simulated -system.cpu.cpi 0.694995 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.694995 # CPI: Total CPI of All Threads +system.cpu.commit.commitSquashedInsts 96992012 # The number of squashed insts skipped by commit +system.cpu.committedInsts 375574819 # Number of Instructions Simulated +system.cpu.committedInsts_total 375574819 # Number of Instructions Simulated +system.cpu.cpi 0.720732 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.720732 # CPI: Total CPI of All Threads system.cpu.dcache.LoadLockedReq_accesses 1 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_hits 1 # number of LoadLockedReq hits -system.cpu.dcache.ReadReq_accesses 96463931 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 11260.913706 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 5745.177665 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 96462946 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 11092000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_accesses 95831633 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 11329.441624 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 5804.568528 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 95830648 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 11159500 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.000010 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 985 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 503 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 5659000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_hits 501 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 5717500 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 985 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses 73513272 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 23662.839879 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 6056.042296 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 73509962 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 78324000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_accesses 73513281 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 23616.163142 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 6068.580060 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 73509971 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 78169500 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.000045 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 3310 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 7458 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 20045500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_hits 7448 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 20087000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.000045 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 3310 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 40702.353448 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 40550.943247 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 169977203 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 20818.626310 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 5984.749709 # average overall mshr miss latency -system.cpu.dcache.demand_hits 169972908 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 89416000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_accesses 169344914 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 20798.370198 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 6008.032596 # average overall mshr miss latency +system.cpu.dcache.demand_hits 169340619 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 89329000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.000025 # miss rate for demand accesses system.cpu.dcache.demand_misses 4295 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 7961 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 25704500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_hits 7949 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 25804500 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.000025 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 4295 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 169977203 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 20818.626310 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 5984.749709 # average overall mshr miss latency +system.cpu.dcache.overall_accesses 169344914 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 20798.370198 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 6008.032596 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 169972908 # number of overall hits -system.cpu.dcache.overall_miss_latency 89416000 # number of overall miss cycles +system.cpu.dcache.overall_hits 169340619 # number of overall hits +system.cpu.dcache.overall_miss_latency 89329000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.000025 # miss rate for overall accesses system.cpu.dcache.overall_misses 4295 # number of overall misses -system.cpu.dcache.overall_mshr_hits 7961 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 25704500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_hits 7949 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 25804500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.000025 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 4295 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -123,101 +123,101 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 780 # number of replacements system.cpu.dcache.sampled_refs 4176 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 3295.577155 # Cycle average of tags in use -system.cpu.dcache.total_refs 169973028 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 3296.898282 # Cycle average of tags in use +system.cpu.dcache.total_refs 169340739 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 635 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 10379369 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 4333 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 11455632 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 536109933 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 132797558 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 101446828 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 15642913 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 12797 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 754894 # Number of cycles decode is unblocking -system.cpu.dtb.accesses 185890093 # DTB accesses -system.cpu.dtb.acv 14625 # DTB access violations -system.cpu.dtb.hits 185845750 # DTB hits -system.cpu.dtb.misses 44343 # DTB misses -system.cpu.dtb.read_accesses 105156938 # DTB read accesses -system.cpu.dtb.read_acv 14625 # DTB read access violations -system.cpu.dtb.read_hits 105114144 # DTB read hits -system.cpu.dtb.read_misses 42794 # DTB read misses -system.cpu.dtb.write_accesses 80733155 # DTB write accesses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_hits 80731606 # DTB write hits +system.cpu.dcache.writebacks 636 # number of writebacks +system.cpu.decode.DECODE:BlockedCycles 19548233 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 4322 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 11389388 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 534561309 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 133040681 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 101286271 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 15528683 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 12726 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 1283788 # Number of cycles decode is unblocking +system.cpu.dtb.accesses 185382797 # DTB accesses +system.cpu.dtb.acv 11231 # DTB access violations +system.cpu.dtb.hits 185341833 # DTB hits +system.cpu.dtb.misses 40964 # DTB misses +system.cpu.dtb.read_accesses 104727621 # DTB read accesses +system.cpu.dtb.read_acv 11230 # DTB read access violations +system.cpu.dtb.read_hits 104688206 # DTB read hits +system.cpu.dtb.read_misses 39415 # DTB read misses +system.cpu.dtb.write_accesses 80655176 # DTB write accesses +system.cpu.dtb.write_acv 1 # DTB write access violations +system.cpu.dtb.write_hits 80653627 # DTB write hits system.cpu.dtb.write_misses 1549 # DTB write misses -system.cpu.fetch.Branches 62816866 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 64526365 # Number of cache lines fetched -system.cpu.fetch.Cycles 169349894 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 1380085 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 550063393 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 6176073 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.240657 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 64526365 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 49445851 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 2.107339 # Number of inst fetches per cycle +system.cpu.fetch.Branches 62521881 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 63961136 # Number of cache lines fetched +system.cpu.fetch.Cycles 169110905 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 1508800 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 548208679 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 6045566 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.230973 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 63961136 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 49721014 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 2.025236 # Number of inst fetches per cycle system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 261021562 +system.cpu.fetch.rateDist.samples 270687656 system.cpu.fetch.rateDist.min_value 0 - 0 156198329 5984.12% - 1 10474114 401.27% - 2 12009483 460.10% - 3 7031360 269.38% - 4 15051020 576.62% - 5 10018831 383.83% - 6 6809824 260.89% - 7 4109754 157.45% - 8 39318847 1506.34% + 0 165538187 6115.47% + 1 11382617 420.51% + 2 12322114 455.22% + 3 6555852 242.19% + 4 14993338 553.90% + 5 9782168 361.38% + 6 6628609 244.88% + 7 4019736 148.50% + 8 39465035 1457.95% system.cpu.fetch.rateDist.max_value 8 system.cpu.fetch.rateDist.end_dist -system.cpu.icache.ReadReq_accesses 64526174 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 7182.389131 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 4988.079979 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 64522273 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 28018500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.000060 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 3901 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 191 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 19458500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000060 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 3901 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_accesses 63960941 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 7182.726807 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 4985.135828 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 63957039 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 28027000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.000061 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 3902 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 195 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 19452000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.000061 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 3902 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_refs 16539.931556 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 16390.835213 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 64526174 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 7182.389131 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 4988.079979 # average overall mshr miss latency -system.cpu.icache.demand_hits 64522273 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 28018500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.000060 # miss rate for demand accesses -system.cpu.icache.demand_misses 3901 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 191 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 19458500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.000060 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 3901 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_accesses 63960941 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 7182.726807 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 4985.135828 # average overall mshr miss latency +system.cpu.icache.demand_hits 63957039 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 28027000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.000061 # miss rate for demand accesses +system.cpu.icache.demand_misses 3902 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 195 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 19452000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.000061 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 3902 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 64526174 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 7182.389131 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 4988.079979 # average overall mshr miss latency +system.cpu.icache.overall_accesses 63960941 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 7182.726807 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 4985.135828 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 64522273 # number of overall hits -system.cpu.icache.overall_miss_latency 28018500 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.000060 # miss rate for overall accesses -system.cpu.icache.overall_misses 3901 # number of overall misses -system.cpu.icache.overall_mshr_hits 191 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 19458500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.000060 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 3901 # number of overall MSHR misses +system.cpu.icache.overall_hits 63957039 # number of overall hits +system.cpu.icache.overall_miss_latency 28027000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.000061 # miss rate for overall accesses +system.cpu.icache.overall_misses 3902 # number of overall misses +system.cpu.icache.overall_mshr_hits 195 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 19452000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.000061 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 3902 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -229,187 +229,187 @@ system.cpu.icache.prefetcher.num_hwpf_issued 0 system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.icache.replacements 1979 # number of replacements -system.cpu.icache.sampled_refs 3901 # Sample count of references to valid blocks. +system.cpu.icache.replacements 1978 # number of replacements +system.cpu.icache.sampled_refs 3902 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1827.041992 # Cycle average of tags in use -system.cpu.icache.total_refs 64522273 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 1827.137830 # Cycle average of tags in use +system.cpu.icache.total_refs 63957039 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 1138 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 51184181 # Number of branches executed -system.cpu.iew.EXEC:nop 27521515 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.613803 # Inst execution rate -system.cpu.iew.EXEC:refs 192783461 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 80743835 # Number of stores executed +system.cpu.idleCycles 1122 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 51166859 # Number of branches executed +system.cpu.iew.EXEC:nop 27206903 # number of nop insts executed +system.cpu.iew.EXEC:rate 1.553018 # Inst execution rate +system.cpu.iew.EXEC:refs 192096320 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 80665864 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 284447545 # num instructions consuming a value -system.cpu.iew.WB:count 417188655 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.706015 # average fanout of values written-back +system.cpu.iew.WB:consumers 289920934 # num instructions consuming a value +system.cpu.iew.WB:count 416705161 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.697472 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 200824371 # num instructions producing a value -system.cpu.iew.WB:rate 1.598285 # insts written-back per cycle -system.cpu.iew.WB:sent 418096768 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 6170690 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 1426561 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 125601766 # Number of dispatched load instructions +system.cpu.iew.WB:producers 202211776 # num instructions producing a value +system.cpu.iew.WB:rate 1.539425 # insts written-back per cycle +system.cpu.iew.WB:sent 417409880 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 6331816 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 2208725 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 125316087 # Number of dispatched load instructions system.cpu.iew.iewDispNonSpecInsts 239 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 6545178 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 92855490 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 496077841 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 112039626 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 9995558 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 421239213 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 59610 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewDispSquashedInsts 6347988 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 92822357 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 495657556 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 111430456 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 9555482 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 420384523 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 154148 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 24612 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 15642913 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 326804 # Number of cycles IEW is unblocking +system.cpu.iew.iewLSQFullEvents 22202 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 15528683 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 511247 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 8473702 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 35459 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.forwLoads 8679637 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 18577 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 574238 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 176007 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 24949770 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 19324087 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 574238 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 908757 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 5261933 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 1.438859 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.438859 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0 431234771 # Type of FU issued +system.cpu.iew.lsq.thread.0.memOrderViolation 404895 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.rescheduledLoads 176434 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 24664092 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 19290955 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 404895 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 826576 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 5505240 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 1.387478 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.387478 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0 429940005 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist No_OpClass 33581 0.01% # Type of FU issued - IntAlu 167547165 38.85% # Type of FU issued - IntMult 2148252 0.50% # Type of FU issued + IntAlu 166734854 38.78% # Type of FU issued + IntMult 2150402 0.50% # Type of FU issued IntDiv 0 0.00% # Type of FU issued - FloatAdd 34932915 8.10% # Type of FU issued - FloatCmp 7864913 1.82% # Type of FU issued - FloatCvt 2933513 0.68% # Type of FU issued - FloatMult 16766961 3.89% # Type of FU issued - FloatDiv 1572145 0.36% # Type of FU issued + FloatAdd 35165170 8.18% # Type of FU issued + FloatCmp 7853884 1.83% # Type of FU issued + FloatCvt 2943482 0.68% # Type of FU issued + FloatMult 16785484 3.90% # Type of FU issued + FloatDiv 1589029 0.37% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued - MemRead 114624584 26.58% # Type of FU issued - MemWrite 82810742 19.20% # Type of FU issued + MemRead 114042343 26.53% # Type of FU issued + MemWrite 82641776 19.22% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.end_dist -system.cpu.iq.ISSUE:fu_busy_cnt 10914524 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.025310 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_cnt 9809447 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.022816 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full.start_dist No_OpClass 0 0.00% # attempts to use FU when none available - IntAlu 15305 0.14% # attempts to use FU when none available + IntAlu 43912 0.45% # attempts to use FU when none available IntMult 0 0.00% # attempts to use FU when none available IntDiv 0 0.00% # attempts to use FU when none available - FloatAdd 41564 0.38% # attempts to use FU when none available - FloatCmp 31641 0.29% # attempts to use FU when none available - FloatCvt 9732 0.09% # attempts to use FU when none available - FloatMult 2290427 20.99% # attempts to use FU when none available - FloatDiv 1536693 14.08% # attempts to use FU when none available + FloatAdd 84838 0.86% # attempts to use FU when none available + FloatCmp 1645 0.02% # attempts to use FU when none available + FloatCvt 15421 0.16% # attempts to use FU when none available + FloatMult 1864355 19.01% # attempts to use FU when none available + FloatDiv 751232 7.66% # attempts to use FU when none available FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 5500856 50.40% # attempts to use FU when none available - MemWrite 1488306 13.64% # attempts to use FU when none available + MemRead 5780067 58.92% # attempts to use FU when none available + MemWrite 1267977 12.93% # attempts to use FU when none available IprAccess 0 0.00% # attempts to use FU when none available InstPrefetch 0 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full.end_dist system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 261021562 +system.cpu.iq.ISSUE:issued_per_cycle.samples 270687656 system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 92982852 3562.27% - 1 54227475 2077.51% - 2 40411704 1548.21% - 3 29929713 1146.64% - 4 23083699 884.36% - 5 11888091 455.44% - 6 5433351 208.16% - 7 2498024 95.70% - 8 566653 21.71% + 0 99778614 3686.12% + 1 58432972 2158.69% + 2 39984102 1477.13% + 3 28980071 1070.61% + 4 24076713 889.46% + 5 11776300 435.05% + 6 4840111 178.81% + 7 2180586 80.56% + 8 638187 23.58% system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 system.cpu.iq.ISSUE:issued_per_cycle.end_dist -system.cpu.iq.ISSUE:rate 1.652097 # Inst issue rate -system.cpu.iq.iqInstsAdded 468556087 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 431234771 # Number of instructions issued +system.cpu.iq.ISSUE:rate 1.588319 # Inst issue rate +system.cpu.iq.iqInstsAdded 468450414 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 429940005 # Number of instructions issued system.cpu.iq.iqNonSpecInstsAdded 239 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 92147793 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 947116 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 91656765 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 1252688 # Number of squashed instructions issued system.cpu.iq.iqSquashedNonSpecRemoved 24 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 68967166 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.itb.accesses 64526661 # ITB accesses -system.cpu.itb.acv 0 # ITB acv -system.cpu.itb.hits 64526365 # ITB hits -system.cpu.itb.misses 296 # ITB misses +system.cpu.iq.iqSquashedOperandsExamined 70486985 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.itb.accesses 63961435 # ITB accesses +system.cpu.itb.acv 1 # ITB acv +system.cpu.itb.hits 63961136 # ITB hits +system.cpu.itb.misses 299 # ITB misses system.cpu.l2cache.ReadExReq_accesses 3195 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 4623.317684 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 2623.317684 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 14771500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_avg_miss_latency 4663.223787 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 2663.223787 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 14899000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_misses 3195 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 8381500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 8509000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_misses 3195 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 4882 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 4343.436699 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2343.436699 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 593 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 18629000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.878533 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 4289 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 10051000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.878533 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 4289 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 4883 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 4347.238406 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2347.238406 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 592 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 18654000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.878763 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 4291 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 10072000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.878763 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 4291 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_accesses 121 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 4487.603306 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 2487.603306 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 543000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_avg_miss_latency 4500 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 2500 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 544500 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_misses 121 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 301000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 302500 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_misses 121 # number of UpgradeReq MSHR misses -system.cpu.l2cache.Writeback_accesses 635 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses 636 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_miss_rate 1 # miss rate for Writeback accesses -system.cpu.l2cache.Writeback_misses 635 # number of Writeback misses +system.cpu.l2cache.Writeback_misses 636 # number of Writeback misses system.cpu.l2cache.Writeback_mshr_miss_rate 1 # mshr miss rate for Writeback accesses -system.cpu.l2cache.Writeback_mshr_misses 635 # number of Writeback MSHR misses +system.cpu.l2cache.Writeback_mshr_misses 636 # number of Writeback MSHR misses system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.137476 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 0.137170 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 8077 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 4462.920898 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 2462.920898 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 593 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 33400500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.926582 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 7484 # number of demand (read+write) misses +system.cpu.l2cache.demand_accesses 8078 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 4482.099920 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 2482.099920 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 592 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 33553000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.926715 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 7486 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 18432500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.926582 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 7484 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 18581000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.926715 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 7486 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 8077 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 4462.920898 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 2462.920898 # average overall mshr miss latency +system.cpu.l2cache.overall_accesses 8078 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 4482.099920 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 2482.099920 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 593 # number of overall hits -system.cpu.l2cache.overall_miss_latency 33400500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.926582 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 7484 # number of overall misses +system.cpu.l2cache.overall_hits 592 # number of overall hits +system.cpu.l2cache.overall_miss_latency 33553000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.926715 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 7486 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 18432500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.926582 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 7484 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 18581000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.926715 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 7486 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -422,30 +422,30 @@ system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.l2cache.replacements 6 # number of replacements -system.cpu.l2cache.sampled_refs 4168 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 4170 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 3522.085649 # Cycle average of tags in use -system.cpu.l2cache.total_refs 573 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 3521.000776 # Cycle average of tags in use +system.cpu.l2cache.total_refs 572 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.numCycles 261022700 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 4632657 # Number of cycles rename is blocking -system.cpu.rename.RENAME:CommittedMaps 259532351 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 371371 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 136793870 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 4480722 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:RenameLookups 687103591 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 521769627 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 337207883 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 98011455 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 15642913 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 5589343 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 77675532 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 351324 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 37944 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 12960882 # count of insts added to the skid buffer +system.cpu.numCycles 270688778 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 9099322 # Number of cycles rename is blocking +system.cpu.rename.RENAME:CommittedMaps 259532341 # Number of HB maps that are committed +system.cpu.rename.RENAME:IQFullEvents 1995191 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 138097938 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 7233951 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:RenameLookups 686963869 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 520820269 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 337090567 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 97114306 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 15528683 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 10493249 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 77558226 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 354158 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 37906 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 22964339 # count of insts added to the skid buffer system.cpu.rename.RENAME:tempSerializingInsts 253 # count of temporary serializing insts renamed -system.cpu.timesIdled 442 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.timesIdled 418 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 215 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/30.eon/ref/alpha/tru64/o3-timing/stderr b/tests/long/30.eon/ref/alpha/tru64/o3-timing/stderr index 4bb0d9bbe..982c0e2fd 100644 --- a/tests/long/30.eon/ref/alpha/tru64/o3-timing/stderr +++ b/tests/long/30.eon/ref/alpha/tru64/o3-timing/stderr @@ -1,3 +1,4 @@ +0: system.remote_gdb.listener: listening for remote gdb on port 7000 warn: Entering event queue @ 0. Starting simulation... warn: Increasing stack size by one page. getting pixel output filename pixels_out.cook diff --git a/tests/long/30.eon/ref/alpha/tru64/o3-timing/stdout b/tests/long/30.eon/ref/alpha/tru64/o3-timing/stdout index f2cd9657b..50ed34325 100644 --- a/tests/long/30.eon/ref/alpha/tru64/o3-timing/stdout +++ b/tests/long/30.eon/ref/alpha/tru64/o3-timing/stdout @@ -1,2 +1,2 @@ Eon, Version 1.1 -OO-style eon Time= 0.116667 +OO-style eon Time= 0.133333 diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini index dffb46ac1..74bf81749 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini @@ -371,6 +371,7 @@ euid=100 executable=/dist/m5/cpu2000/binaries/alpha/tru64/vortex gid=100 input=cin +max_stack_size=67108864 output=cout pid=100 ppid=99 diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/m5stats.txt b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/m5stats.txt index 15ee80644..74d2aee08 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/m5stats.txt +++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/m5stats.txt @@ -1,40 +1,40 @@ ---------- Begin Simulation Statistics ---------- global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 8001673 # Number of BTB hits -global.BPredUnit.BTBLookups 14256966 # Number of BTB lookups -global.BPredUnit.RASInCorrect 35545 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 455902 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 10551273 # Number of conditional branches predicted -global.BPredUnit.lookups 16246333 # Number of BP lookups -global.BPredUnit.usedRAS 1941036 # Number of times the RAS was used to get a target. -host_inst_rate 178455 # Simulator instruction rate (inst/s) -host_mem_usage 211564 # Number of bytes of host memory used -host_seconds 446.00 # Real time elapsed on the host -host_tick_rate 55789781 # Simulator tick rate (ticks/s) -memdepunit.memDep.conflictingLoads 12304370 # Number of conflicting loads. -memdepunit.memDep.conflictingStores 10964244 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 22974359 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 16298386 # Number of stores inserted to the mem dependence unit. +global.BPredUnit.BTBHits 8036279 # Number of BTB hits +global.BPredUnit.BTBLookups 14260181 # Number of BTB lookups +global.BPredUnit.RASInCorrect 35537 # Number of incorrect RAS predictions. +global.BPredUnit.condIncorrect 456495 # Number of conditional branches incorrect +global.BPredUnit.condPredicted 10555311 # Number of conditional branches predicted +global.BPredUnit.lookups 16250871 # Number of BP lookups +global.BPredUnit.usedRAS 1941181 # Number of times the RAS was used to get a target. +host_inst_rate 115474 # Simulator instruction rate (inst/s) +host_mem_usage 160356 # Number of bytes of host memory used +host_seconds 689.26 # Real time elapsed on the host +host_tick_rate 36122153 # Simulator tick rate (ticks/s) +memdepunit.memDep.conflictingLoads 12102830 # Number of conflicting loads. +memdepunit.memDep.conflictingStores 10931763 # Number of conflicting stores. +memdepunit.memDep.insertedLoads 22978723 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 16295551 # Number of stores inserted to the mem dependence unit. sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 79591756 # Number of instructions simulated -sim_seconds 0.024882 # Number of seconds simulated -sim_ticks 24882469000 # Number of ticks simulated +sim_seconds 0.024898 # Number of seconds simulated +sim_ticks 24897604000 # Number of ticks simulated system.cpu.commit.COM:branches 13754477 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 3430644 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 3356243 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 48501675 +system.cpu.commit.COM:committed_per_cycle.samples 48528188 system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 19715966 4065.01% - 1 10943165 2256.24% - 2 5093030 1050.07% - 3 3475751 716.62% - 4 2505421 516.56% - 5 1522534 313.91% - 6 1001460 206.48% - 7 813704 167.77% - 8 3430644 707.32% + 0 19702397 4059.99% + 1 10946158 2255.63% + 2 5036045 1037.76% + 3 3466785 714.39% + 4 2664416 549.05% + 5 1534889 316.29% + 6 1008769 207.87% + 7 812486 167.43% + 8 3356243 691.61% system.cpu.commit.COM:committed_per_cycle.max_value 8 system.cpu.commit.COM:committed_per_cycle.end_dist @@ -43,72 +43,72 @@ system.cpu.commit.COM:loads 20379399 # Nu system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 35224018 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 360143 # The number of times a branch was mispredicted +system.cpu.commit.branchMispredicts 360762 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 88340672 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 4583 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 8051078 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 8068812 # The number of squashed insts skipped by commit system.cpu.committedInsts 79591756 # Number of Instructions Simulated system.cpu.committedInsts_total 79591756 # Number of Instructions Simulated -system.cpu.cpi 0.625252 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.625252 # CPI: Total CPI of All Threads -system.cpu.dcache.LoadLockedReq_accesses 44 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_hits 44 # number of LoadLockedReq hits -system.cpu.dcache.ReadReq_accesses 20377695 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 15251.726884 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 4211.460009 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 20316168 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 938393000 # number of ReadReq miss cycles +system.cpu.cpi 0.625633 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.625633 # CPI: Total CPI of All Threads +system.cpu.dcache.LoadLockedReq_accesses 43 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_hits 43 # number of LoadLockedReq hits +system.cpu.dcache.ReadReq_accesses 20378393 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 15241.304772 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 4212.764920 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 20316865 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 937767000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.003019 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 61527 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 82932 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 259118500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_misses 61528 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 82787 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 259203000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.003019 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 61527 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses 13807431 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 30521.435580 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 5307.053083 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 13657610 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 4572752000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.010851 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 149821 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 805946 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 795108000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.010851 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 149821 # number of WriteReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses 61528 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_accesses 13782122 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 32047.161184 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 5374.422625 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 13632306 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 4801177500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.010870 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 149816 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 831255 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 805174500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.010870 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 149816 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 165.739033 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 165.626302 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 34185126 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 26076.163484 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 4988.107292 # average overall mshr miss latency -system.cpu.dcache.demand_hits 33973778 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 5511145000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.006182 # miss rate for demand accesses -system.cpu.dcache.demand_misses 211348 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 888878 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 1054226500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.006182 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 211348 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_accesses 34160515 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 27154.518226 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 5036.232398 # average overall mshr miss latency +system.cpu.dcache.demand_hits 33949171 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 5738944500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.006187 # miss rate for demand accesses +system.cpu.dcache.demand_misses 211344 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 914042 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 1064377500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.006187 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 211344 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 34185126 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 26076.163484 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 4988.107292 # average overall mshr miss latency +system.cpu.dcache.overall_accesses 34160515 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 27154.518226 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 5036.232398 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 33973778 # number of overall hits -system.cpu.dcache.overall_miss_latency 5511145000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.006182 # miss rate for overall accesses -system.cpu.dcache.overall_misses 211348 # number of overall misses -system.cpu.dcache.overall_mshr_hits 888878 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 1054226500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.006182 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 211348 # number of overall MSHR misses +system.cpu.dcache.overall_hits 33949171 # number of overall hits +system.cpu.dcache.overall_miss_latency 5738944500 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.006187 # miss rate for overall accesses +system.cpu.dcache.overall_misses 211344 # number of overall misses +system.cpu.dcache.overall_mshr_hits 914042 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 1064377500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.006187 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 211344 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -120,104 +120,104 @@ system.cpu.dcache.prefetcher.num_hwpf_issued 0 system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.dcache.replacements 200926 # number of replacements -system.cpu.dcache.sampled_refs 205022 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 200917 # number of replacements +system.cpu.dcache.sampled_refs 205013 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4080.923075 # Cycle average of tags in use -system.cpu.dcache.total_refs 33980148 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 120631000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 147761 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 953936 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 96699 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 3650405 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 101647473 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 27934130 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 19589260 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 1261472 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 284553 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 24350 # Number of cycles decode is unblocking -system.cpu.dtb.accesses 36627778 # DTB accesses -system.cpu.dtb.acv 37 # DTB access violations -system.cpu.dtb.hits 36455125 # DTB hits -system.cpu.dtb.misses 172653 # DTB misses -system.cpu.dtb.read_accesses 21565019 # DTB read accesses -system.cpu.dtb.read_acv 35 # DTB read access violations -system.cpu.dtb.read_hits 21407076 # DTB read hits -system.cpu.dtb.read_misses 157943 # DTB read misses -system.cpu.dtb.write_accesses 15062759 # DTB write accesses +system.cpu.dcache.tagsinuse 4080.927145 # Cycle average of tags in use +system.cpu.dcache.total_refs 33955545 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 120649000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 147757 # number of writebacks +system.cpu.decode.DECODE:BlockedCycles 943541 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 96612 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 3650840 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 101683737 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 27936407 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 19620838 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 1265214 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 284149 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 27403 # Number of cycles decode is unblocking +system.cpu.dtb.accesses 36632249 # DTB accesses +system.cpu.dtb.acv 36 # DTB access violations +system.cpu.dtb.hits 36460811 # DTB hits +system.cpu.dtb.misses 171438 # DTB misses +system.cpu.dtb.read_accesses 21568197 # DTB read accesses +system.cpu.dtb.read_acv 34 # DTB read access violations +system.cpu.dtb.read_hits 21411149 # DTB read hits +system.cpu.dtb.read_misses 157048 # DTB read misses +system.cpu.dtb.write_accesses 15064052 # DTB write accesses system.cpu.dtb.write_acv 2 # DTB write access violations -system.cpu.dtb.write_hits 15048049 # DTB write hits -system.cpu.dtb.write_misses 14710 # DTB write misses -system.cpu.fetch.Branches 16246333 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 13375683 # Number of cache lines fetched -system.cpu.fetch.Cycles 33194597 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 152184 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 103251284 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 572846 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.326461 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 13375683 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 9942709 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 2.074780 # Number of inst fetches per cycle +system.cpu.dtb.write_hits 15049662 # DTB write hits +system.cpu.dtb.write_misses 14390 # DTB write misses +system.cpu.fetch.Branches 16250871 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 13378376 # Number of cache lines fetched +system.cpu.fetch.Cycles 33230958 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 152674 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 103283004 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 574326 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.326354 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 13378376 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 9977460 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 2.074155 # Number of inst fetches per cycle system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 49763148 +system.cpu.fetch.rateDist.samples 49793403 system.cpu.fetch.rateDist.min_value 0 - 0 29969634 6022.46% - 1 1857821 373.33% - 2 1524433 306.34% - 3 1786134 358.93% - 4 3977224 799.23% - 5 1866445 375.07% - 6 698149 140.29% - 7 1110284 223.11% - 8 6973024 1401.24% + 0 29966239 6018.11% + 1 1875035 376.56% + 2 1535605 308.40% + 3 1804270 362.35% + 4 3961078 795.50% + 5 1877676 377.09% + 6 698372 140.25% + 7 1099999 220.91% + 8 6975129 1400.81% system.cpu.fetch.rateDist.max_value 8 system.cpu.fetch.rateDist.end_dist -system.cpu.icache.ReadReq_accesses 13374854 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 4582.447586 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 2544.287368 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 13289333 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 391895500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.006394 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 85521 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 829 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 217590000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.006394 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 85521 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_accesses 13377544 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 4583.036351 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 2544.804459 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 13291961 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 392230000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.006398 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 85583 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 832 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 217792000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.006398 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 85583 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_refs 155.392629 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 155.310763 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 13374854 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 4582.447586 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 2544.287368 # average overall mshr miss latency -system.cpu.icache.demand_hits 13289333 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 391895500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.006394 # miss rate for demand accesses -system.cpu.icache.demand_misses 85521 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 829 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 217590000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.006394 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 85521 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_accesses 13377544 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 4583.036351 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 2544.804459 # average overall mshr miss latency +system.cpu.icache.demand_hits 13291961 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 392230000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.006398 # miss rate for demand accesses +system.cpu.icache.demand_misses 85583 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 832 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 217792000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.006398 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 85583 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 13374854 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 4582.447586 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 2544.287368 # average overall mshr miss latency +system.cpu.icache.overall_accesses 13377544 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 4583.036351 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 2544.804459 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 13289333 # number of overall hits -system.cpu.icache.overall_miss_latency 391895500 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.006394 # miss rate for overall accesses -system.cpu.icache.overall_misses 85521 # number of overall misses -system.cpu.icache.overall_mshr_hits 829 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 217590000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.006394 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 85521 # number of overall MSHR misses +system.cpu.icache.overall_hits 13291961 # number of overall hits +system.cpu.icache.overall_miss_latency 392230000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.006398 # miss rate for overall accesses +system.cpu.icache.overall_misses 85583 # number of overall misses +system.cpu.icache.overall_mshr_hits 832 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 217792000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.006398 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 85583 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -229,80 +229,80 @@ system.cpu.icache.prefetcher.num_hwpf_issued 0 system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.icache.replacements 83473 # number of replacements -system.cpu.icache.sampled_refs 85521 # Sample count of references to valid blocks. +system.cpu.icache.replacements 83535 # number of replacements +system.cpu.icache.sampled_refs 85583 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1922.769682 # Cycle average of tags in use -system.cpu.icache.total_refs 13289333 # Total number of references to valid blocks. -system.cpu.icache.warmup_cycle 21643859000 # Cycle when the warmup percentage was hit. +system.cpu.icache.tagsinuse 1922.482733 # Cycle average of tags in use +system.cpu.icache.total_refs 13291961 # Total number of references to valid blocks. +system.cpu.icache.warmup_cycle 21658930000 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 1791 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 14739683 # Number of branches executed -system.cpu.iew.EXEC:nop 9380523 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.704389 # Inst execution rate -system.cpu.iew.EXEC:refs 36969776 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 15295559 # Number of stores executed +system.cpu.idleCycles 1806 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 14744087 # Number of branches executed +system.cpu.iew.EXEC:nop 9381144 # number of nop insts executed +system.cpu.iew.EXEC:rate 1.703621 # Inst execution rate +system.cpu.iew.EXEC:refs 36974156 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 15296705 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 42405904 # num instructions consuming a value -system.cpu.iew.WB:count 84333016 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.765386 # average fanout of values written-back +system.cpu.iew.WB:consumers 42381395 # num instructions consuming a value +system.cpu.iew.WB:count 84348023 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.765304 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 32456867 # num instructions producing a value -system.cpu.iew.WB:rate 1.694627 # insts written-back per cycle -system.cpu.iew.WB:sent 84566644 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 400717 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 20492 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 22974359 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 4987 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 359590 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 16298386 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 98827714 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 21674217 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 545926 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 84818805 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 2571 # Number of times the IQ has become full, causing a stall +system.cpu.iew.WB:producers 32434648 # num instructions producing a value +system.cpu.iew.WB:rate 1.693898 # insts written-back per cycle +system.cpu.iew.WB:sent 84580813 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 401245 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 18721 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 22978723 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 4986 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 359067 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 16295551 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 98839523 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 21677451 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 547314 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 84832143 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 2010 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 174 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 1261472 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 3172 # Number of cycles IEW is unblocking +system.cpu.iew.iewLSQFullEvents 182 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 1265214 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 2634 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 945093 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 1085 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.forwLoads 948620 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 989 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 19531 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 1312 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 2594960 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 1453767 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 19531 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 108348 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 292369 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 1.599354 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.599354 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0 85364731 # Type of FU issued +system.cpu.iew.lsq.thread.0.memOrderViolation 20664 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.rescheduledLoads 1306 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 2599324 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 1450932 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 20664 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 108416 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 292829 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 1.598382 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.598382 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0 85379457 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist No_OpClass 0 0.00% # Type of FU issued - IntAlu 47879047 56.09% # Type of FU issued - IntMult 43747 0.05% # Type of FU issued + IntAlu 47888413 56.09% # Type of FU issued + IntMult 42937 0.05% # Type of FU issued IntDiv 0 0.00% # Type of FU issued - FloatAdd 121378 0.14% # Type of FU issued + FloatAdd 121447 0.14% # Type of FU issued FloatCmp 86 0.00% # Type of FU issued - FloatCvt 121979 0.14% # Type of FU issued + FloatCvt 122009 0.14% # Type of FU issued FloatMult 50 0.00% # Type of FU issued - FloatDiv 38527 0.05% # Type of FU issued + FloatDiv 38531 0.05% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued - MemRead 21782176 25.52% # Type of FU issued - MemWrite 15377741 18.01% # Type of FU issued + MemRead 21786877 25.52% # Type of FU issued + MemWrite 15379107 18.01% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.end_dist -system.cpu.iq.ISSUE:fu_busy_cnt 969096 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.011352 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_cnt 969118 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.011351 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full.start_dist No_OpClass 0 0.00% # attempts to use FU when none available - IntAlu 95806 9.89% # attempts to use FU when none available + IntAlu 94143 9.71% # attempts to use FU when none available IntMult 0 0.00% # attempts to use FU when none available IntDiv 0 0.00% # attempts to use FU when none available FloatAdd 0 0.00% # attempts to use FU when none available @@ -311,105 +311,105 @@ system.cpu.iq.ISSUE:fu_full.start_dist FloatMult 0 0.00% # attempts to use FU when none available FloatDiv 0 0.00% # attempts to use FU when none available FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 442018 45.61% # attempts to use FU when none available - MemWrite 431272 44.50% # attempts to use FU when none available + MemRead 449697 46.40% # attempts to use FU when none available + MemWrite 425278 43.88% # attempts to use FU when none available IprAccess 0 0.00% # attempts to use FU when none available InstPrefetch 0 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full.end_dist system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 49763148 +system.cpu.iq.ISSUE:issued_per_cycle.samples 49793403 system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 14890253 2992.22% - 1 13307982 2674.26% - 2 8090593 1625.82% - 3 4789845 962.53% - 4 4747984 954.12% - 5 2061711 414.30% - 6 1164817 234.07% - 7 463069 93.05% - 8 246894 49.61% + 0 14936070 2999.61% + 1 13322790 2675.61% + 2 8095375 1625.79% + 3 4742465 952.43% + 4 4697667 943.43% + 5 2107602 423.27% + 6 1178715 236.72% + 7 464198 93.22% + 8 248521 49.91% system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 system.cpu.iq.ISSUE:issued_per_cycle.end_dist -system.cpu.iq.ISSUE:rate 1.715359 # Inst issue rate -system.cpu.iq.iqInstsAdded 89442204 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 85364731 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 4987 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 9646731 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 49535 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 404 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 6611614 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.itb.accesses 13401083 # ITB accesses +system.cpu.iq.ISSUE:rate 1.714612 # Inst issue rate +system.cpu.iq.iqInstsAdded 89453393 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 85379457 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 4986 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 9664351 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 49402 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 403 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 6605234 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.itb.accesses 13403794 # ITB accesses system.cpu.itb.acv 0 # ITB acv -system.cpu.itb.hits 13375683 # ITB hits -system.cpu.itb.misses 25400 # ITB misses -system.cpu.l2cache.ReadExReq_accesses 143495 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 4092.480574 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 2092.480574 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 587250500 # number of ReadExReq miss cycles +system.cpu.itb.hits 13378376 # ITB hits +system.cpu.itb.misses 25418 # ITB misses +system.cpu.l2cache.ReadExReq_accesses 143485 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 4092.825034 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 2092.825034 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 587259000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 143495 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 300260500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_misses 143485 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 300289000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 143495 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 147048 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 4140.515824 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2140.515824 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 98388 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 201477500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.330912 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 48660 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 104157500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.330912 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 48660 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 6344 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 4240.542245 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 2242.591425 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 26902000 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_mshr_misses 143485 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 147111 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 4141.158104 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2141.158104 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 98428 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 201604000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.330927 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 48683 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 104238000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.330927 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 48683 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_accesses 6350 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_avg_miss_latency 4242.677165 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 2244.724409 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 26941000 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 6344 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 14227000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_misses 6350 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 14254000 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 6344 # number of UpgradeReq MSHR misses -system.cpu.l2cache.Writeback_accesses 147761 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_mshr_misses 6350 # number of UpgradeReq MSHR misses +system.cpu.l2cache.Writeback_accesses 147757 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_miss_rate 1 # miss rate for Writeback accesses -system.cpu.l2cache.Writeback_misses 147761 # number of Writeback misses +system.cpu.l2cache.Writeback_misses 147757 # number of Writeback misses system.cpu.l2cache.Writeback_mshr_miss_rate 1 # mshr miss rate for Writeback accesses -system.cpu.l2cache.Writeback_mshr_misses 147761 # number of Writeback MSHR misses +system.cpu.l2cache.Writeback_mshr_misses 147757 # number of Writeback MSHR misses system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 2.449354 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 2.449601 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 290543 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 4104.644688 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 2104.644688 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 98388 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 788728000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.661365 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 192155 # number of demand (read+write) misses +system.cpu.l2cache.demand_accesses 290596 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 4105.069523 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 2105.069523 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 98428 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 788863000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.661289 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 192168 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 404418000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.661365 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 192155 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 404527000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.661289 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 192168 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 290543 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 4104.644688 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 2104.644688 # average overall mshr miss latency +system.cpu.l2cache.overall_accesses 290596 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 4105.069523 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 2105.069523 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 98388 # number of overall hits -system.cpu.l2cache.overall_miss_latency 788728000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.661365 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 192155 # number of overall misses +system.cpu.l2cache.overall_hits 98428 # number of overall hits +system.cpu.l2cache.overall_miss_latency 788863000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.661289 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 192168 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 404418000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.661365 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 192155 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 404527000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.661289 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 192168 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -421,31 +421,31 @@ system.cpu.l2cache.prefetcher.num_hwpf_issued 0 system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.l2cache.replacements 25943 # number of replacements -system.cpu.l2cache.sampled_refs 41849 # Sample count of references to valid blocks. +system.cpu.l2cache.replacements 25961 # number of replacements +system.cpu.l2cache.sampled_refs 41866 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 4581.530519 # Cycle average of tags in use -system.cpu.l2cache.total_refs 102503 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 4585.787881 # Cycle average of tags in use +system.cpu.l2cache.total_refs 102555 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.numCycles 49764939 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 263435 # Number of cycles rename is blocking +system.cpu.numCycles 49795209 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 258129 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 52546881 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 34724 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 28245765 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 545942 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:RenameLookups 121486902 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 100840274 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 60680951 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 19296581 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 1261472 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 621968 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 8134070 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 73927 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 5255 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 1395173 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 5253 # count of temporary serializing insts renamed -system.cpu.timesIdled 678 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.rename.RENAME:IQFullEvents 32247 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 28248638 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 541903 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:RenameLookups 121528434 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 100873332 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 60701342 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 19331218 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 1265214 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 614234 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 8154461 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 75970 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 5252 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 1383660 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 5250 # count of temporary serializing insts renamed +system.cpu.timesIdled 679 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 4583 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stderr b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stderr index f33d007a7..5992f7131 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stderr +++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stderr @@ -1,2 +1,3 @@ +0: system.remote_gdb.listener: listening for remote gdb on port 7000 warn: Entering event queue @ 0. Starting simulation... warn: Increasing stack size by one page. diff --git a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini index e0dba3f8d..dfd1626b7 100644 --- a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini @@ -371,6 +371,7 @@ euid=100 executable=/dist/m5/cpu2000/binaries/alpha/tru64/bzip2 gid=100 input=cin +max_stack_size=67108864 output=cout pid=100 ppid=99 diff --git a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/m5stats.txt b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/m5stats.txt index 752f725e4..bace5dece 100644 --- a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/m5stats.txt +++ b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/m5stats.txt @@ -1,40 +1,40 @@ ---------- Begin Simulation Statistics ---------- global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 295839321 # Number of BTB hits -global.BPredUnit.BTBLookups 304173613 # Number of BTB lookups +global.BPredUnit.BTBHits 295839323 # Number of BTB hits +global.BPredUnit.BTBLookups 304173612 # Number of BTB lookups global.BPredUnit.RASInCorrect 120 # Number of incorrect RAS predictions. global.BPredUnit.condIncorrect 19407214 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 254124044 # Number of conditional branches predicted -global.BPredUnit.lookups 329654644 # Number of BP lookups +global.BPredUnit.condPredicted 254124042 # Number of conditional branches predicted +global.BPredUnit.lookups 329654643 # Number of BP lookups global.BPredUnit.usedRAS 23321143 # Number of times the RAS was used to get a target. -host_inst_rate 162413 # Simulator instruction rate (inst/s) -host_mem_usage 200732 # Number of bytes of host memory used -host_seconds 10689.07 # Real time elapsed on the host -host_tick_rate 61198134 # Simulator tick rate (ticks/s) -memdepunit.memDep.conflictingLoads 71970991 # Number of conflicting loads. -memdepunit.memDep.conflictingStores 36581423 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 594992654 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 221743675 # Number of stores inserted to the mem dependence unit. +host_inst_rate 104317 # Simulator instruction rate (inst/s) +host_mem_usage 152912 # Number of bytes of host memory used +host_seconds 16642.00 # Real time elapsed on the host +host_tick_rate 39307247 # Simulator tick rate (ticks/s) +memdepunit.memDep.conflictingLoads 71970990 # Number of conflicting loads. +memdepunit.memDep.conflictingStores 36581415 # Number of conflicting stores. +memdepunit.memDep.insertedLoads 594992698 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 221743701 # Number of stores inserted to the mem dependence unit. sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1736043781 # Number of instructions simulated sim_seconds 0.654151 # Number of seconds simulated -sim_ticks 654151113500 # Number of ticks simulated +sim_ticks 654151114500 # Number of ticks simulated system.cpu.commit.COM:branches 214632552 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 63247574 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 63247563 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 1235798441 +system.cpu.commit.COM:committed_per_cycle.samples 1235798413 system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 591538606 4786.69% - 1 262725137 2125.95% - 2 125553765 1015.97% - 3 79229995 641.12% - 4 49991526 404.53% - 5 29482834 238.57% + 0 591538550 4786.69% + 1 262725182 2125.96% + 2 125553761 1015.97% + 3 79229965 641.12% + 4 49991517 404.53% + 5 29482875 238.57% 6 23306420 188.59% - 7 10722584 86.77% - 8 63247574 511.80% + 7 10722580 86.77% + 8 63247563 511.80% system.cpu.commit.COM:committed_per_cycle.max_value 8 system.cpu.commit.COM:committed_per_cycle.end_dist @@ -46,7 +46,7 @@ system.cpu.commit.COM:swp_count 0 # Nu system.cpu.commit.branchMispredicts 19406708 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 1819780126 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 29 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 476380119 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 476380348 # The number of squashed insts skipped by commit system.cpu.committedInsts 1736043781 # Number of Instructions Simulated system.cpu.committedInsts_total 1736043781 # Number of Instructions Simulated system.cpu.cpi 0.753611 # CPI: Cycles Per Instruction @@ -61,62 +61,62 @@ system.cpu.dcache.LoadLockedReq_misses 1 # nu system.cpu.dcache.LoadLockedReq_mshr_miss_latency 5500 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_rate 0.333333 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_mshr_misses 1 # number of LoadLockedReq MSHR misses -system.cpu.dcache.ReadReq_accesses 511433561 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 6211.231687 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 3240.921493 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 504159044 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 45183710500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_accesses 511433519 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 6211.244353 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 3240.935477 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 504159005 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 45183784000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.014224 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 7274517 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 1442446 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 23576138500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_misses 7274514 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 1442447 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 23576230500 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.014224 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 7274517 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses 158840549 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 13691.838043 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 7367.789283 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 156591934 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 30787672401 # number of WriteReq miss cycles +system.cpu.dcache.ReadReq_mshr_misses 7274514 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_accesses 158840548 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 13691.826036 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 7367.776387 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 156591933 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 30787645402 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.014156 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 2248615 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 1887953 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 16567321498 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_hits 1887954 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 16567292501 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.014156 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 2248615 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles_no_mshrs 1521.266534 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles_no_mshrs 1521.257137 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets 1667.900476 # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 72.179758 # Average number of references to valid blocks. -system.cpu.dcache.blocked_no_mshrs 34791 # number of cycles access was blocked +system.cpu.dcache.avg_refs 72.179769 # Average number of references to valid blocks. +system.cpu.dcache.blocked_no_mshrs 34783 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 65110 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_mshrs 52926384 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_mshrs 52913887 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 108597000 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 670274110 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 7977.562728 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 4215.363181 # average overall mshr miss latency -system.cpu.dcache.demand_hits 660750978 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 75971382901 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_accesses 670274067 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 7977.570124 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 4215.371124 # average overall mshr miss latency +system.cpu.dcache.demand_hits 660750938 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 75971429402 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.014208 # miss rate for demand accesses -system.cpu.dcache.demand_misses 9523132 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 3330399 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 40143459998 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_misses 9523129 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 3330401 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 40143523001 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.014208 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 9523132 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses 9523129 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 670274110 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 7977.562728 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 4215.363181 # average overall mshr miss latency +system.cpu.dcache.overall_accesses 670274067 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 7977.570124 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 4215.371124 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 660750978 # number of overall hits -system.cpu.dcache.overall_miss_latency 75971382901 # number of overall miss cycles +system.cpu.dcache.overall_hits 660750938 # number of overall hits +system.cpu.dcache.overall_miss_latency 75971429402 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.014208 # miss rate for overall accesses -system.cpu.dcache.overall_misses 9523132 # number of overall misses -system.cpu.dcache.overall_mshr_hits 3330399 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 40143459998 # number of overall MSHR miss cycles +system.cpu.dcache.overall_misses 9523129 # number of overall misses +system.cpu.dcache.overall_mshr_hits 3330401 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 40143523001 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.014208 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 9523132 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses 9523129 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -128,102 +128,102 @@ system.cpu.dcache.prefetcher.num_hwpf_issued 0 system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.dcache.replacements 9155187 # number of replacements -system.cpu.dcache.sampled_refs 9159283 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 9155185 # number of replacements +system.cpu.dcache.sampled_refs 9159281 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4084.725965 # Cycle average of tags in use -system.cpu.dcache.total_refs 661114830 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 6949550000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tagsinuse 4084.725934 # Cycle average of tags in use +system.cpu.dcache.total_refs 661114789 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 6949556000 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 2245528 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 23691683 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BlockedCycles 23691676 # Number of cycles decode is blocked system.cpu.decode.DECODE:BranchMispred 575 # Number of times decode detected a branch misprediction system.cpu.decode.DECODE:BranchResolved 51434078 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 2685033161 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 684622025 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 525046007 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 72503589 # Number of cycles decode is squashing +system.cpu.decode.DECODE:DecodedInsts 2685033131 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 684622012 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 525045997 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 72503618 # Number of cycles decode is squashing system.cpu.decode.DECODE:SquashedInsts 1687 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 2438727 # Number of cycles decode is unblocking -system.cpu.dtb.accesses 758263361 # DTB accesses +system.cpu.decode.DECODE:UnblockCycles 2438729 # Number of cycles decode is unblocking +system.cpu.dtb.accesses 758263324 # DTB accesses system.cpu.dtb.acv 0 # DTB access violations -system.cpu.dtb.hits 743549453 # DTB hits +system.cpu.dtb.hits 743549416 # DTB hits system.cpu.dtb.misses 14713908 # DTB misses -system.cpu.dtb.read_accesses 558500359 # DTB read accesses +system.cpu.dtb.read_accesses 558500328 # DTB read accesses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_hits 549711515 # DTB read hits +system.cpu.dtb.read_hits 549711484 # DTB read hits system.cpu.dtb.read_misses 8788844 # DTB read misses -system.cpu.dtb.write_accesses 199763002 # DTB write accesses +system.cpu.dtb.write_accesses 199762996 # DTB write accesses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_hits 193837938 # DTB write hits +system.cpu.dtb.write_hits 193837932 # DTB write hits system.cpu.dtb.write_misses 5925064 # DTB write misses -system.cpu.fetch.Branches 329654644 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 338459974 # Number of cache lines fetched -system.cpu.fetch.Cycles 875922763 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 8905677 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 2732615549 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 26330328 # Number of cycles fetch has spent squashing +system.cpu.fetch.Branches 329654643 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 338459959 # Number of cache lines fetched +system.cpu.fetch.Cycles 875922747 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 8905673 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 2732615563 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 26330323 # Number of cycles fetch has spent squashing system.cpu.fetch.branchRate 0.251971 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 338459974 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 319160464 # Number of branches that fetch has predicted taken +system.cpu.fetch.icacheStallCycles 338459959 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 319160466 # Number of branches that fetch has predicted taken system.cpu.fetch.rate 2.088673 # Number of inst fetches per cycle system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 1308302031 +system.cpu.fetch.rateDist.samples 1308302032 system.cpu.fetch.rateDist.min_value 0 - 0 770839278 5891.91% - 1 46037022 351.88% - 2 31884256 243.71% - 3 48862894 373.48% - 4 119031598 909.82% - 5 67260927 514.11% - 6 45605029 348.58% - 7 40088084 306.41% - 8 138692943 1060.10% + 0 770839280 5891.91% + 1 46037016 351.88% + 2 31884250 243.71% + 3 48862901 373.48% + 4 119031591 909.82% + 5 67260944 514.11% + 6 45605032 348.58% + 7 40088076 306.41% + 8 138692942 1060.10% system.cpu.fetch.rateDist.max_value 8 system.cpu.fetch.rateDist.end_dist -system.cpu.icache.ReadReq_accesses 338459894 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 7804.756637 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 5448.008850 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 338458990 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 7055500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_accesses 338459878 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 7805.862832 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 5445.796460 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 338458974 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 7056500 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000003 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 904 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 80 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 4925000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits 81 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 4923000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000003 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 904 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_refs 374401.537611 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 374401.519912 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 338459894 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 7804.756637 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 5448.008850 # average overall mshr miss latency -system.cpu.icache.demand_hits 338458990 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 7055500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_accesses 338459878 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 7805.862832 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 5445.796460 # average overall mshr miss latency +system.cpu.icache.demand_hits 338458974 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 7056500 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000003 # miss rate for demand accesses system.cpu.icache.demand_misses 904 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 80 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 4925000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_hits 81 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 4923000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.000003 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 904 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 338459894 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 7804.756637 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 5448.008850 # average overall mshr miss latency +system.cpu.icache.overall_accesses 338459878 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 7805.862832 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 5445.796460 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 338458990 # number of overall hits -system.cpu.icache.overall_miss_latency 7055500 # number of overall miss cycles +system.cpu.icache.overall_hits 338458974 # number of overall hits +system.cpu.icache.overall_miss_latency 7056500 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000003 # miss rate for overall accesses system.cpu.icache.overall_misses 904 # number of overall misses -system.cpu.icache.overall_mshr_hits 80 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 4925000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_hits 81 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 4923000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.000003 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 904 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -240,73 +240,73 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 1 # number of replacements system.cpu.icache.sampled_refs 904 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 710.981871 # Cycle average of tags in use -system.cpu.icache.total_refs 338458990 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 710.981866 # Cycle average of tags in use +system.cpu.icache.total_refs 338458974 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 197 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 270496646 # Number of branches executed -system.cpu.iew.EXEC:nop 123104849 # number of nop insts executed +system.cpu.idleCycles 198 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 270496625 # Number of branches executed +system.cpu.iew.EXEC:nop 123104848 # number of nop insts executed system.cpu.iew.EXEC:rate 1.690526 # Inst execution rate -system.cpu.iew.EXEC:refs 759555990 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 199980185 # Number of stores executed +system.cpu.iew.EXEC:refs 759555953 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 199980179 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 1477074275 # num instructions consuming a value -system.cpu.iew.WB:count 2172910283 # cumulative count of insts written-back +system.cpu.iew.WB:consumers 1477074261 # num instructions consuming a value +system.cpu.iew.WB:count 2172910244 # cumulative count of insts written-back system.cpu.iew.WB:fanout 0.814315 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 1202803999 # num instructions producing a value +system.cpu.iew.WB:producers 1202804007 # num instructions producing a value system.cpu.iew.WB:rate 1.660863 # insts written-back per cycle -system.cpu.iew.WB:sent 2193655848 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 21011443 # Number of branch mispredicts detected at execute +system.cpu.iew.WB:sent 2193655810 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 21011435 # Number of branch mispredicts detected at execute system.cpu.iew.iewBlockCycles 889547 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 594992654 # Number of dispatched load instructions +system.cpu.iew.iewDispLoadInsts 594992698 # Number of dispatched load instructions system.cpu.iew.iewDispNonSpecInsts 42 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 23236593 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 221743675 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 2499789620 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 559575805 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 40783059 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 2211719338 # Number of executed instructions +system.cpu.iew.iewDispSquashedInsts 23236538 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 221743701 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 2499789841 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 559575774 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 40783144 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 2211719271 # Number of executed instructions system.cpu.iew.iewIQFullEvents 12131 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewLSQFullEvents 5627 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 72503589 # Number of cycles IEW is squashing +system.cpu.iew.iewSquashCycles 72503618 # Number of cycles IEW is squashing system.cpu.iew.iewUnblockCycles 62383 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 123404 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread.0.cacheBlocked 123419 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.lsq.thread.0.forwLoads 36795200 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 338162 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.ignoredResponses 338163 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread.0.memOrderViolation 340968 # Number of memory ordering violations system.cpu.iew.lsq.thread.0.rescheduledLoads 5 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 149326293 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 60838693 # Number of stores squashed +system.cpu.iew.lsq.thread.0.squashedLoads 149326337 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 60838719 # Number of stores squashed system.cpu.iew.memOrderViolationEvents 340968 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 705259 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 20306184 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 705255 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 20306180 # Number of branches that were predicted taken incorrectly system.cpu.ipc 1.326944 # IPC: Instructions Per Cycle system.cpu.ipc_total 1.326944 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0 2252502397 # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0 2252502415 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist No_OpClass 0 0.00% # Type of FU issued - IntAlu 1478322730 65.63% # Type of FU issued - IntMult 88 0.00% # Type of FU issued + IntAlu 1478322731 65.63% # Type of FU issued + IntMult 86 0.00% # Type of FU issued IntDiv 0 0.00% # Type of FU issued - FloatAdd 219 0.00% # Type of FU issued - FloatCmp 16 0.00% # Type of FU issued + FloatAdd 218 0.00% # Type of FU issued + FloatCmp 15 0.00% # Type of FU issued FloatCvt 143 0.00% # Type of FU issued FloatMult 14 0.00% # Type of FU issued FloatDiv 24 0.00% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued - MemRead 570745758 25.34% # Type of FU issued - MemWrite 203433405 9.03% # Type of FU issued + MemRead 570745775 25.34% # Type of FU issued + MemWrite 203433409 9.03% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.end_dist -system.cpu.iq.ISSUE:fu_busy_cnt 16701897 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_cnt 16701899 # FU busy when requested system.cpu.iq.ISSUE:fu_busy_rate 0.007415 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full.start_dist No_OpClass 0 0.00% # attempts to use FU when none available @@ -320,65 +320,65 @@ system.cpu.iq.ISSUE:fu_full.start_dist FloatDiv 0 0.00% # attempts to use FU when none available FloatSqrt 0 0.00% # attempts to use FU when none available MemRead 10594349 63.43% # attempts to use FU when none available - MemWrite 3679414 22.03% # attempts to use FU when none available + MemWrite 3679416 22.03% # attempts to use FU when none available IprAccess 0 0.00% # attempts to use FU when none available InstPrefetch 0 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full.end_dist system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 1308302031 +system.cpu.iq.ISSUE:issued_per_cycle.samples 1308302032 system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 464994121 3554.18% - 1 246274545 1882.40% - 2 221057021 1689.65% - 3 136661440 1044.57% - 4 111222535 850.13% - 5 73372650 560.82% - 6 42938124 328.20% - 7 9505404 72.65% - 8 2276191 17.40% + 0 464994043 3554.18% + 1 246274613 1882.40% + 2 221057057 1689.65% + 3 136661391 1044.57% + 4 111222575 850.13% + 5 73372635 560.82% + 6 42938142 328.20% + 7 9505420 72.65% + 8 2276156 17.40% system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 system.cpu.iq.ISSUE:issued_per_cycle.end_dist system.cpu.iq.ISSUE:rate 1.721699 # Inst issue rate -system.cpu.iq.iqInstsAdded 2376684729 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 2252502397 # Number of instructions issued +system.cpu.iq.iqInstsAdded 2376684951 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 2252502415 # Number of instructions issued system.cpu.iq.iqNonSpecInstsAdded 42 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 628382514 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 968135 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 628382811 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 968171 # Number of squashed instructions issued system.cpu.iq.iqSquashedNonSpecRemoved 13 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 253289566 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.itb.accesses 338460010 # ITB accesses +system.cpu.iq.iqSquashedOperandsExamined 253289947 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.itb.accesses 338459995 # ITB accesses system.cpu.itb.acv 0 # ITB acv -system.cpu.itb.hits 338459974 # ITB hits +system.cpu.itb.hits 338459959 # ITB hits system.cpu.itb.misses 36 # ITB misses -system.cpu.l2cache.ReadExReq_accesses 1884766 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 5021.667411 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 3021.667411 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 9464668000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_accesses 1884767 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 5021.674297 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 3021.674297 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 9464686000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 1884766 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 5695136000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_misses 1884767 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 5695152000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 1884766 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 7275421 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 4312.514661 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2312.514661 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 5169531 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 9081681500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_mshr_misses 1884767 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 7275418 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 4312.531905 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2312.531905 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 5169529 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 9081713500 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 0.289453 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 2105890 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 4869901500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_misses 2105889 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 4869935500 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.289453 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 2105890 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 363856 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 4839.580768 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 2839.786894 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 1760910500 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadReq_mshr_misses 2105889 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_accesses 363855 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_avg_miss_latency 4840.345742 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 2840.551868 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 1761184000 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 363856 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 1033273500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_misses 363855 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 1033549000 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 363856 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses 363855 # number of UpgradeReq MSHR misses system.cpu.l2cache.Writeback_accesses 2245528 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_miss_rate 1 # miss rate for Writeback accesses system.cpu.l2cache.Writeback_misses 2245528 # number of Writeback misses @@ -386,36 +386,36 @@ system.cpu.l2cache.Writeback_mshr_miss_rate 1 # system.cpu.l2cache.Writeback_mshr_misses 2245528 # number of Writeback MSHR misses system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 4.195595 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 4.195593 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 9160187 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 4647.443804 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 2647.443804 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 5169531 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 18546349500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_accesses 9160185 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 4647.456333 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 2647.456333 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 5169529 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 18546399500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 0.435652 # miss rate for demand accesses system.cpu.l2cache.demand_misses 3990656 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 10565037500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 10565087500 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 0.435652 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 3990656 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 9160187 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 4647.443804 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 2647.443804 # average overall mshr miss latency +system.cpu.l2cache.overall_accesses 9160185 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 4647.456333 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 2647.456333 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 5169531 # number of overall hits -system.cpu.l2cache.overall_miss_latency 18546349500 # number of overall miss cycles +system.cpu.l2cache.overall_hits 5169529 # number of overall hits +system.cpu.l2cache.overall_miss_latency 18546399500 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.435652 # miss rate for overall accesses system.cpu.l2cache.overall_misses 3990656 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 10565037500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 10565087500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 0.435652 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 3990656 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -432,29 +432,29 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.l2cache.replacements 1375756 # number of replacements system.cpu.l2cache.sampled_refs 1398753 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 18802.772660 # Cycle average of tags in use -system.cpu.l2cache.total_refs 5868601 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 505903232000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tagsinuse 18802.772512 # Cycle average of tags in use +system.cpu.l2cache.total_refs 5868598 # Total number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 505903236000 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.numCycles 1308302228 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 9337867 # Number of cycles rename is blocking +system.cpu.numCycles 1308302230 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 9337863 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 1376202963 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 3445352 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 700444810 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 8719596 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:IQFullEvents 3445344 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 700444791 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 8719600 # Number of times rename has blocked due to LSQ full system.cpu.rename.RENAME:ROBFullEvents 7541 # Number of times rename has blocked due to ROB full -system.cpu.rename.RENAME:RenameLookups 3393542048 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 2622643652 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 1968531188 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 511623131 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 72503589 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 14392125 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 592328225 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:RenameLookups 3393542111 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 2622643654 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 1968531217 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 511623129 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 72503618 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 14392122 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 592328254 # Number of HB maps that are undone due to squashing system.cpu.rename.RENAME:serializeStallCycles 509 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 48 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 29038158 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 46 # count of temporary serializing insts renamed -system.cpu.timesIdled 379 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.rename.RENAME:serializingInsts 47 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 29038166 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 45 # count of temporary serializing insts renamed +system.cpu.timesIdled 380 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 29 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stderr b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stderr index d0a887867..256a7f3be 100644 --- a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stderr +++ b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stderr @@ -1,3 +1,4 @@ +0: system.remote_gdb.listener: listening for remote gdb on port 7000 warn: Entering event queue @ 0. Starting simulation... warn: Increasing stack size by one page. warn: Increasing stack size by one page. diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini index 10ff9c3eb..38d087a18 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini @@ -371,6 +371,7 @@ euid=100 executable=/dist/m5/cpu2000/binaries/alpha/tru64/twolf gid=100 input=cin +max_stack_size=67108864 output=cout pid=100 ppid=99 diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/m5stats.txt b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/m5stats.txt index 93bbafeb5..29f0901b4 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/m5stats.txt +++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/m5stats.txt @@ -1,40 +1,40 @@ ---------- Begin Simulation Statistics ---------- global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 13010658 # Number of BTB hits -global.BPredUnit.BTBLookups 16925459 # Number of BTB lookups -global.BPredUnit.RASInCorrect 1191 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 1944478 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 14575632 # Number of conditional branches predicted -global.BPredUnit.lookups 19422613 # Number of BP lookups -global.BPredUnit.usedRAS 1713685 # Number of times the RAS was used to get a target. -host_inst_rate 135551 # Simulator instruction rate (inst/s) -host_mem_usage 205692 # Number of bytes of host memory used -host_seconds 621.02 # Real time elapsed on the host -host_tick_rate 65380263 # Simulator tick rate (ticks/s) -memdepunit.memDep.conflictingLoads 17216912 # Number of conflicting loads. -memdepunit.memDep.conflictingStores 5017487 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 33831723 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 10556967 # Number of stores inserted to the mem dependence unit. +global.BPredUnit.BTBHits 12981460 # Number of BTB hits +global.BPredUnit.BTBLookups 16925064 # Number of BTB lookups +global.BPredUnit.RASInCorrect 1200 # Number of incorrect RAS predictions. +global.BPredUnit.condIncorrect 1943725 # Number of conditional branches incorrect +global.BPredUnit.condPredicted 14569092 # Number of conditional branches predicted +global.BPredUnit.lookups 19413931 # Number of BP lookups +global.BPredUnit.usedRAS 1712105 # Number of times the RAS was used to get a target. +host_inst_rate 84618 # Simulator instruction rate (inst/s) +host_mem_usage 156264 # Number of bytes of host memory used +host_seconds 994.82 # Real time elapsed on the host +host_tick_rate 40727067 # Simulator tick rate (ticks/s) +memdepunit.memDep.conflictingLoads 17086953 # Number of conflicting loads. +memdepunit.memDep.conflictingStores 4901863 # Number of conflicting stores. +memdepunit.memDep.insertedLoads 33850154 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 10567224 # Number of stores inserted to the mem dependence unit. sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 84179709 # Number of instructions simulated -sim_seconds 0.040602 # Number of seconds simulated -sim_ticks 40602361500 # Number of ticks simulated +sim_seconds 0.040516 # Number of seconds simulated +sim_ticks 40516250000 # Number of ticks simulated system.cpu.commit.COM:branches 10240685 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 2830089 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 2905596 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 73220545 +system.cpu.commit.COM:committed_per_cycle.samples 73004137 system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 35958705 4911.01% - 1 18165534 2480.93% - 2 7495163 1023.64% - 3 3905368 533.37% - 4 2115499 288.92% - 5 1290804 176.29% - 6 741318 101.24% - 7 718065 98.07% - 8 2830089 386.52% + 0 35920134 4920.29% + 1 18137405 2484.44% + 2 7363835 1008.69% + 3 3887057 532.44% + 4 2043329 279.89% + 5 1276462 174.85% + 6 715818 98.05% + 7 754501 103.35% + 8 2905596 398.00% system.cpu.commit.COM:committed_per_cycle.max_value 8 system.cpu.commit.COM:committed_per_cycle.end_dist @@ -43,72 +43,72 @@ system.cpu.commit.COM:loads 20034413 # Nu system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 26537108 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 1932029 # The number of times a branch was mispredicted +system.cpu.commit.branchMispredicts 1931243 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 91903055 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 389 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 55442802 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 55734183 # The number of squashed insts skipped by commit system.cpu.committedInsts 84179709 # Number of Instructions Simulated system.cpu.committedInsts_total 84179709 # Number of Instructions Simulated -system.cpu.cpi 0.964659 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.964659 # CPI: Total CPI of All Threads +system.cpu.cpi 0.962613 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.962613 # CPI: Total CPI of All Threads system.cpu.dcache.LoadLockedReq_accesses 7 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_hits 7 # number of LoadLockedReq hits -system.cpu.dcache.ReadReq_accesses 23305151 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 8854.743083 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 5500 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 23304645 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 4480500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_accesses 23342617 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 8955.533597 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 5521.739130 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 23342111 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 4531500 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.000022 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 506 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 115 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 2783000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_hits 125 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 2794000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.000022 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 506 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses 6494991 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 24985.167206 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 5885.922330 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 6493137 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 46322500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.000285 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 1854 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 6112 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 10912500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.000285 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 1854 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_accesses 6494986 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 24898.921833 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 5797.574124 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 6493131 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 46187500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.000286 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 1855 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 6117 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 10754500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.000286 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 1855 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 13302.637946 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 13319.361607 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 29800142 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 21526.694915 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 5803.177966 # average overall mshr miss latency -system.cpu.dcache.demand_hits 29797782 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 50803000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_accesses 29837603 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 21481.999153 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 5738.458280 # average overall mshr miss latency +system.cpu.dcache.demand_hits 29835242 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 50719000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.000079 # miss rate for demand accesses -system.cpu.dcache.demand_misses 2360 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 6227 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 13695500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_misses 2361 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 6242 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 13548500 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.000079 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 2360 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses 2361 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 29800142 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 21526.694915 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 5803.177966 # average overall mshr miss latency +system.cpu.dcache.overall_accesses 29837603 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 21481.999153 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 5738.458280 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 29797782 # number of overall hits -system.cpu.dcache.overall_miss_latency 50803000 # number of overall miss cycles +system.cpu.dcache.overall_hits 29835242 # number of overall hits +system.cpu.dcache.overall_miss_latency 50719000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.000079 # miss rate for overall accesses -system.cpu.dcache.overall_misses 2360 # number of overall misses -system.cpu.dcache.overall_mshr_hits 6227 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 13695500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_misses 2361 # number of overall misses +system.cpu.dcache.overall_mshr_hits 6242 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 13548500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.000079 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 2360 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses 2361 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -123,101 +123,101 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 159 # number of replacements system.cpu.dcache.sampled_refs 2240 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 1459.011880 # Cycle average of tags in use -system.cpu.dcache.total_refs 29797909 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 1459.079813 # Cycle average of tags in use +system.cpu.dcache.total_refs 29835370 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 105 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 3766232 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 12611 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 3034294 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 162205348 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 39405972 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 29900475 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 7983383 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 45169 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 147867 # Number of cycles decode is unblocking -system.cpu.dtb.accesses 31800987 # DTB accesses +system.cpu.decode.DECODE:BlockedCycles 3482319 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 12650 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 3029666 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 162321559 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 39484158 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 29812969 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 8027574 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 45360 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 224692 # Number of cycles decode is unblocking +system.cpu.dtb.accesses 31857877 # DTB accesses system.cpu.dtb.acv 0 # DTB access violations -system.cpu.dtb.hits 31340580 # DTB hits -system.cpu.dtb.misses 460407 # DTB misses -system.cpu.dtb.read_accesses 24617799 # DTB read accesses +system.cpu.dtb.hits 31398595 # DTB hits +system.cpu.dtb.misses 459282 # DTB misses +system.cpu.dtb.read_accesses 24667330 # DTB read accesses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_hits 24158583 # DTB read hits -system.cpu.dtb.read_misses 459216 # DTB read misses -system.cpu.dtb.write_accesses 7183188 # DTB write accesses +system.cpu.dtb.read_hits 24209046 # DTB read hits +system.cpu.dtb.read_misses 458284 # DTB read misses +system.cpu.dtb.write_accesses 7190547 # DTB write accesses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_hits 7181997 # DTB write hits -system.cpu.dtb.write_misses 1191 # DTB write misses -system.cpu.fetch.Branches 19422613 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 19195045 # Number of cache lines fetched -system.cpu.fetch.Cycles 50102609 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 509210 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 167066208 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 2080138 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.239181 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 19195045 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 14724343 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 2.057346 # Number of inst fetches per cycle +system.cpu.dtb.write_hits 7189549 # DTB write hits +system.cpu.dtb.write_misses 998 # DTB write misses +system.cpu.fetch.Branches 19413931 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 19196468 # Number of cache lines fetched +system.cpu.fetch.Cycles 50093769 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 510771 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 167169540 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 2080057 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.239582 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 19196468 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 14693565 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 2.062994 # Number of inst fetches per cycle system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 81203929 +system.cpu.fetch.rateDist.samples 81031712 system.cpu.fetch.rateDist.min_value 0 - 0 50296438 6193.84% - 1 3127485 385.14% - 2 2009190 247.43% - 3 3499443 430.95% - 4 4580392 564.06% - 5 1498651 184.55% - 6 2040206 251.24% - 7 1851037 227.95% - 8 12301087 1514.84% + 0 50134485 6187.02% + 1 3110350 383.84% + 2 2001832 247.04% + 3 3498087 431.69% + 4 4581661 565.42% + 5 1504587 185.68% + 6 2029421 250.45% + 7 1835152 226.47% + 8 12336137 1522.38% system.cpu.fetch.rateDist.max_value 8 system.cpu.fetch.rateDist.end_dist -system.cpu.icache.ReadReq_accesses 19194697 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 5285.401314 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 3152.011551 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 19184655 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 53076000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.000523 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 10042 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 348 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 31652500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000523 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 10042 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_accesses 19196110 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 5282.113499 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 3147.221947 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 19186013 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 53333500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.000526 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 10097 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 358 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 31777500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.000526 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 10097 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_refs 1910.441645 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 1900.169654 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 19194697 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 5285.401314 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 3152.011551 # average overall mshr miss latency -system.cpu.icache.demand_hits 19184655 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 53076000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.000523 # miss rate for demand accesses -system.cpu.icache.demand_misses 10042 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 348 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 31652500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.000523 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 10042 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_accesses 19196110 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 5282.113499 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 3147.221947 # average overall mshr miss latency +system.cpu.icache.demand_hits 19186013 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 53333500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.000526 # miss rate for demand accesses +system.cpu.icache.demand_misses 10097 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 358 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 31777500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.000526 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 10097 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 19194697 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 5285.401314 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 3152.011551 # average overall mshr miss latency +system.cpu.icache.overall_accesses 19196110 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 5282.113499 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 3147.221947 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 19184655 # number of overall hits -system.cpu.icache.overall_miss_latency 53076000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.000523 # miss rate for overall accesses -system.cpu.icache.overall_misses 10042 # number of overall misses -system.cpu.icache.overall_mshr_hits 348 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 31652500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.000523 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 10042 # number of overall MSHR misses +system.cpu.icache.overall_hits 19186013 # number of overall hits +system.cpu.icache.overall_miss_latency 53333500 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.000526 # miss rate for overall accesses +system.cpu.icache.overall_misses 10097 # number of overall misses +system.cpu.icache.overall_mshr_hits 358 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 31777500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.000526 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 10097 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -229,146 +229,146 @@ system.cpu.icache.prefetcher.num_hwpf_issued 0 system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.icache.replacements 8129 # number of replacements -system.cpu.icache.sampled_refs 10042 # Sample count of references to valid blocks. +system.cpu.icache.replacements 8184 # number of replacements +system.cpu.icache.sampled_refs 10097 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1547.586704 # Cycle average of tags in use -system.cpu.icache.total_refs 19184655 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 1548.546110 # Cycle average of tags in use +system.cpu.icache.total_refs 19186013 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 795 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 12760718 # Number of branches executed -system.cpu.iew.EXEC:nop 12520368 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.249709 # Inst execution rate -system.cpu.iew.EXEC:refs 31851627 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 7184817 # Number of stores executed +system.cpu.idleCycles 789 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 12780650 # Number of branches executed +system.cpu.iew.EXEC:nop 12539176 # number of nop insts executed +system.cpu.iew.EXEC:rate 1.254784 # Inst execution rate +system.cpu.iew.EXEC:refs 31909001 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 7192174 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 90693698 # num instructions consuming a value -system.cpu.iew.WB:count 99568419 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.723301 # average fanout of values written-back +system.cpu.iew.WB:consumers 90874521 # num instructions consuming a value +system.cpu.iew.WB:count 99789775 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.723650 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 65598879 # num instructions producing a value -system.cpu.iew.WB:rate 1.226141 # insts written-back per cycle -system.cpu.iew.WB:sent 100495413 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 2106580 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 285272 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 33831723 # Number of dispatched load instructions +system.cpu.iew.WB:producers 65761308 # num instructions producing a value +system.cpu.iew.WB:rate 1.231478 # insts written-back per cycle +system.cpu.iew.WB:sent 100700291 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 2107867 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 246686 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 33850154 # Number of dispatched load instructions system.cpu.iew.iewDispNonSpecInsts 429 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 1731846 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 10556967 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 147344437 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 24666810 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2188087 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 101482299 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 133099 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewDispSquashedInsts 1732826 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 10567224 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 147636366 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 24716827 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2166736 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 101678323 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 118341 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 12 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 7983383 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 165893 # Number of cycles IEW is unblocking +system.cpu.iew.iewLSQFullEvents 5 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 8027574 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 156748 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 843499 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 1537 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.forwLoads 856559 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 2771 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 250644 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 9811 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 13797310 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 4054272 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 250644 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 202889 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 1903691 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 1.036636 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.036636 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0 103670386 # Type of FU issued +system.cpu.iew.lsq.thread.0.memOrderViolation 251773 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.rescheduledLoads 9738 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 13815741 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 4064529 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 251773 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 201329 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 1906538 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 1.038839 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.038839 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0 103845059 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist No_OpClass 7 0.00% # Type of FU issued - IntAlu 64195239 61.92% # Type of FU issued - IntMult 473046 0.46% # Type of FU issued + IntAlu 64291165 61.91% # Type of FU issued + IntMult 474912 0.46% # Type of FU issued IntDiv 0 0.00% # Type of FU issued - FloatAdd 2788829 2.69% # Type of FU issued - FloatCmp 115617 0.11% # Type of FU issued - FloatCvt 2372095 2.29% # Type of FU issued - FloatMult 305683 0.29% # Type of FU issued - FloatDiv 755148 0.73% # Type of FU issued - FloatSqrt 322 0.00% # Type of FU issued - MemRead 25353594 24.46% # Type of FU issued - MemWrite 7310806 7.05% # Type of FU issued + FloatAdd 2784322 2.68% # Type of FU issued + FloatCmp 115616 0.11% # Type of FU issued + FloatCvt 2378756 2.29% # Type of FU issued + FloatMult 305685 0.29% # Type of FU issued + FloatDiv 755261 0.73% # Type of FU issued + FloatSqrt 321 0.00% # Type of FU issued + MemRead 25423503 24.48% # Type of FU issued + MemWrite 7315511 7.04% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.end_dist -system.cpu.iq.ISSUE:fu_busy_cnt 1973729 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.019039 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_cnt 1872956 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.018036 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full.start_dist No_OpClass 0 0.00% # attempts to use FU when none available - IntAlu 311847 15.80% # attempts to use FU when none available + IntAlu 224474 11.99% # attempts to use FU when none available IntMult 0 0.00% # attempts to use FU when none available IntDiv 0 0.00% # attempts to use FU when none available - FloatAdd 478 0.02% # attempts to use FU when none available + FloatAdd 178 0.01% # attempts to use FU when none available FloatCmp 0 0.00% # attempts to use FU when none available - FloatCvt 2917 0.15% # attempts to use FU when none available - FloatMult 2390 0.12% # attempts to use FU when none available - FloatDiv 832522 42.18% # attempts to use FU when none available + FloatCvt 3554 0.19% # attempts to use FU when none available + FloatMult 2233 0.12% # attempts to use FU when none available + FloatDiv 827912 44.20% # attempts to use FU when none available FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 750992 38.05% # attempts to use FU when none available - MemWrite 72583 3.68% # attempts to use FU when none available + MemRead 741386 39.58% # attempts to use FU when none available + MemWrite 73219 3.91% # attempts to use FU when none available IprAccess 0 0.00% # attempts to use FU when none available InstPrefetch 0 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full.end_dist system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 81203929 +system.cpu.iq.ISSUE:issued_per_cycle.samples 81031712 system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 35188418 4333.34% - 1 18662979 2298.29% - 2 11625415 1431.63% - 3 6937118 854.28% - 4 4927347 606.79% - 5 2234432 275.16% - 6 1373348 169.12% - 7 215389 26.52% - 8 39483 4.86% + 0 34941008 4312.02% + 1 18670913 2304.15% + 2 11746620 1449.63% + 3 6722224 829.58% + 4 5133188 633.48% + 5 2276216 280.90% + 6 1240275 153.06% + 7 251392 31.02% + 8 49876 6.16% system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 system.cpu.iq.ISSUE:issued_per_cycle.end_dist -system.cpu.iq.ISSUE:rate 1.276655 # Inst issue rate -system.cpu.iq.iqInstsAdded 134823640 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 103670386 # Number of instructions issued +system.cpu.iq.ISSUE:rate 1.281524 # Inst issue rate +system.cpu.iq.iqInstsAdded 135096761 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 103845059 # Number of instructions issued system.cpu.iq.iqNonSpecInstsAdded 429 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 50027749 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 225448 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 50310453 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 231145 # Number of squashed instructions issued system.cpu.iq.iqSquashedNonSpecRemoved 40 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 46827412 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.itb.accesses 19195118 # ITB accesses +system.cpu.iq.iqSquashedOperandsExamined 47100281 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.itb.accesses 19196542 # ITB accesses system.cpu.itb.acv 0 # ITB acv -system.cpu.itb.hits 19195045 # ITB hits -system.cpu.itb.misses 73 # ITB misses +system.cpu.itb.hits 19196468 # ITB hits +system.cpu.itb.misses 74 # ITB misses system.cpu.l2cache.ReadExReq_accesses 1735 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 4523.342939 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 2523.342939 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 7848000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_avg_miss_latency 4502.305476 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 2502.305476 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 7811500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_misses 1735 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 4378000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 4341500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_misses 1735 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 10547 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 4263.929619 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2263.929619 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 7137 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 14540000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.323315 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 3410 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 7720000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.323315 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 3410 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 10602 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 4264.852210 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2264.852210 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 7185 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 14573000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.322298 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 3417 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 7739000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.322298 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 3417 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_accesses 123 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 4430.894309 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 2430.894309 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 545000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_avg_miss_latency 4439.024390 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 2439.024390 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 546000 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_misses 123 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 299000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 300000 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_misses 123 # number of UpgradeReq MSHR misses system.cpu.l2cache.Writeback_accesses 105 # number of Writeback accesses(hits+misses) @@ -378,38 +378,38 @@ system.cpu.l2cache.Writeback_mshr_miss_rate 1 # system.cpu.l2cache.Writeback_mshr_misses 105 # number of Writeback MSHR misses system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 2.172603 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 2.182564 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 12282 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 4351.409135 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 2351.409135 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 7137 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 22388000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.418906 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 5145 # number of demand (read+write) misses +system.cpu.l2cache.demand_accesses 12337 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 4344.817547 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 2344.817547 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 7185 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 22384500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.417606 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 5152 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 12098000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.418906 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 5145 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 12080500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.417606 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 5152 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 12282 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 4351.409135 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 2351.409135 # average overall mshr miss latency +system.cpu.l2cache.overall_accesses 12337 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 4344.817547 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 2344.817547 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 7137 # number of overall hits -system.cpu.l2cache.overall_miss_latency 22388000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.418906 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 5145 # number of overall misses +system.cpu.l2cache.overall_hits 7185 # number of overall hits +system.cpu.l2cache.overall_miss_latency 22384500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.417606 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 5152 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 12098000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.418906 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 5145 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 12080500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.417606 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 5152 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -422,29 +422,29 @@ system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 3285 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 3292 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 2248.754865 # Cycle average of tags in use -system.cpu.l2cache.total_refs 7137 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 2249.807027 # Cycle average of tags in use +system.cpu.l2cache.total_refs 7185 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.numCycles 81204724 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 1670922 # Number of cycles rename is blocking +system.cpu.numCycles 81032501 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 1616562 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 68427361 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 1021107 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 40689840 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 938076 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:RenameLookups 202669964 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 157140698 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 115798524 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 28770212 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 7983383 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 2084846 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 47371163 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 4726 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 465 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 4645791 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 454 # count of temporary serializing insts renamed +system.cpu.rename.RENAME:IQFullEvents 794040 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 40700023 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 985256 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:RenameLookups 202768082 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 157137531 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 115831457 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 28813428 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 8027574 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 1869404 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 47404096 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 4721 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 464 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 4330553 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 453 # count of temporary serializing insts renamed system.cpu.timesIdled 325 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 389 # Number of system calls diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stderr b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stderr index f33d007a7..5992f7131 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stderr +++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stderr @@ -1,2 +1,3 @@ +0: system.remote_gdb.listener: listening for remote gdb on port 7000 warn: Entering event queue @ 0. Starting simulation... warn: Increasing stack size by one page. diff --git a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/m5stats.txt b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/m5stats.txt index 4a82ca24b..d627d0089 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/m5stats.txt +++ b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/m5stats.txt @@ -8,10 +8,10 @@ global.BPredUnit.condIncorrect 2012 # Nu global.BPredUnit.condPredicted 7659 # Number of conditional branches predicted global.BPredUnit.lookups 7659 # Number of BP lookups global.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. -host_inst_rate 2546 # Simulator instruction rate (inst/s) -host_mem_usage 181644 # Number of bytes of host memory used -host_seconds 4.09 # Real time elapsed on the host -host_tick_rate 3665441 # Simulator tick rate (ticks/s) +host_inst_rate 42769 # Simulator instruction rate (inst/s) +host_mem_usage 153188 # Number of bytes of host memory used +host_seconds 0.24 # Real time elapsed on the host +host_tick_rate 61517406 # Simulator tick rate (ticks/s) memdepunit.memDep.conflictingLoads 15 # Number of conflicting loads. memdepunit.memDep.conflictingStores 0 # Number of conflicting stores. memdepunit.memDep.insertedLoads 3077 # Number of loads inserted to the mem dependence unit. diff --git a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stderr b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stderr index 22ad4f8ac..eb1796ead 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stderr +++ b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stderr @@ -1,2 +1,2 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7005 +0: system.remote_gdb.listener: listening for remote gdb on port 7000 warn: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stdout b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stdout index a9100d9c2..38908c941 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stdout +++ b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stdout @@ -16,9 +16,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 28 2007 18:29:37 -M5 started Wed Nov 28 18:29:38 2007 -M5 executing on nacho +M5 compiled Jan 16 2008 04:32:20 +M5 started Wed Jan 16 04:31:23 2008 +M5 executing on m45-027.pool command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/o3-timing tests/run.py quick/02.insttest/sparc/linux/o3-timing Global frequency set at 1000000000000 ticks per second Exiting @ tick 14990500 because target called exit() |