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| author | Dylan Johnson <Dylan.Johnson@ARM.com> | 2016-08-02 10:38:01 +0100 |
|---|---|---|
| committer | Dylan Johnson <Dylan.Johnson@ARM.com> | 2016-08-02 10:38:01 +0100 |
| commit | 4fbf40daab480ae02b75a75e0dd5f56ce38386d2 (patch) | |
| tree | da3988cf1979f5b7b655661ede690cc0b23aa01d | |
| parent | e727a0eeaa5f2d46921c8496d77623a9704d40b6 (diff) | |
| download | gem5-4fbf40daab480ae02b75a75e0dd5f56ce38386d2.tar.xz | |
arm: invalidate TLB miscreg cache on modification of HSCTLR
Change-Id: I5212c91c56435fe008950ed99feacc6921609226
| -rw-r--r-- | src/arch/arm/isa.cc | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc index 0b753087e..c90de1337 100644 --- a/src/arch/arm/isa.cc +++ b/src/arch/arm/isa.cc @@ -1,5 +1,5 @@ /* - * Copyright (c) 2010-2015 ARM Limited + * Copyright (c) 2010-2016 ARM Limited * All rights reserved * * The license below extends only to copyright in the software and shall @@ -1629,6 +1629,7 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc) case MISCREG_TCR_EL3: case MISCREG_SCTLR_EL2: case MISCREG_SCTLR_EL3: + case MISCREG_HSCTLR: case MISCREG_TTBR0_EL1: case MISCREG_TTBR1_EL1: case MISCREG_TTBR0_EL2: |