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authorKorey Sewell <ksewell@umich.edu>2006-06-15 01:00:15 -0400
committerKorey Sewell <ksewell@umich.edu>2006-06-15 01:00:15 -0400
commit74b9868c786a8c58ef8fe65bebd2fd8e9573d0be (patch)
treeeb8c3573f51208d3ec329a450807fa15081894d3
parent1c55389578c0b17aa9a81f64887e7a6f02110ce4 (diff)
downloadgem5-74b9868c786a8c58ef8fe65bebd2fd8e9573d0be.tar.xz
Mips Code Cleanup:
Fix some author stuff and copyright dates Take out full system code src/arch/mips/isa/base.isa: src/arch/mips/isa/bitfields.isa: copyright info src/arch/mips/isa/decoder.isa: src/arch/mips/isa/formats/basic.isa: src/arch/mips/isa/formats/branch.isa: src/arch/mips/isa/formats/control.isa: src/arch/mips/isa/formats/fp.isa: src/arch/mips/isa/formats/int.isa: src/arch/mips/isa/formats/mem.isa: src/arch/mips/isa/formats/noop.isa: src/arch/mips/isa/formats/tlbop.isa: src/arch/mips/isa/formats/trap.isa: src/arch/mips/isa/formats/unimp.isa: src/arch/mips/isa/formats/unknown.isa: src/arch/mips/isa/formats/util.isa: src/arch/mips/isa/includes.isa: src/arch/mips/isa/main.isa: src/arch/mips/isa/operands.isa: src/arch/mips/process.cc: src/arch/mips/regfile/misc_regfile.hh: src/arch/mips/stacktrace.hh: copyright 2006 src/arch/mips/isa_traits.cc: src/arch/mips/isa_traits.hh: copyright 2006 take out full system src/arch/mips/regfile/float_regfile.hh: src/arch/mips/regfile/regfile.hh: copyright 2006 use FloatRegVal src/arch/mips/regfile/int_regfile.hh: copyright 2006 move HI/LO to types.hh src/arch/mips/types.hh: copyright 2006 typedef FloatRegVal --HG-- extra : convert_revision : 1d0d72cd655a4e28622745a6c6b06349da533a1d
-rw-r--r--src/arch/mips/isa/base.isa3
-rw-r--r--src/arch/mips/isa/bitfields.isa2
-rw-r--r--src/arch/mips/isa/decoder.isa2
-rw-r--r--src/arch/mips/isa/formats/basic.isa2
-rw-r--r--src/arch/mips/isa/formats/branch.isa2
-rw-r--r--src/arch/mips/isa/formats/control.isa2
-rw-r--r--src/arch/mips/isa/formats/fp.isa2
-rw-r--r--src/arch/mips/isa/formats/int.isa2
-rw-r--r--src/arch/mips/isa/formats/mem.isa2
-rw-r--r--src/arch/mips/isa/formats/noop.isa28
-rw-r--r--src/arch/mips/isa/formats/tlbop.isa2
-rw-r--r--src/arch/mips/isa/formats/trap.isa2
-rw-r--r--src/arch/mips/isa/formats/unimp.isa2
-rw-r--r--src/arch/mips/isa/formats/unknown.isa2
-rw-r--r--src/arch/mips/isa/formats/util.isa2
-rw-r--r--src/arch/mips/isa/includes.isa2
-rw-r--r--src/arch/mips/isa/main.isa2
-rw-r--r--src/arch/mips/isa/operands.isa16
-rw-r--r--src/arch/mips/isa_traits.cc71
-rw-r--r--src/arch/mips/isa_traits.hh19
-rw-r--r--src/arch/mips/process.cc1
-rw-r--r--src/arch/mips/regfile/float_regfile.hh4
-rw-r--r--src/arch/mips/regfile/int_regfile.hh7
-rw-r--r--src/arch/mips/regfile/misc_regfile.hh19
-rw-r--r--src/arch/mips/regfile/regfile.hh23
-rw-r--r--src/arch/mips/stacktrace.hh2
-rw-r--r--src/arch/mips/types.hh7
27 files changed, 68 insertions, 162 deletions
diff --git a/src/arch/mips/isa/base.isa b/src/arch/mips/isa/base.isa
index b733da7da..f07b06e03 100644
--- a/src/arch/mips/isa/base.isa
+++ b/src/arch/mips/isa/base.isa
@@ -1,6 +1,6 @@
// -*- mode:c++ -*-
-// Copyright (c) 2003-2006 The Regents of The University of Michigan
+// Copyright (c) 2006 The Regents of The University of Michigan
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
@@ -38,7 +38,6 @@ output header {{
using namespace MipsISA;
-
/**
* Base class for all MIPS static instructions.
*/
diff --git a/src/arch/mips/isa/bitfields.isa b/src/arch/mips/isa/bitfields.isa
index e8d4578c7..35815bf1f 100644
--- a/src/arch/mips/isa/bitfields.isa
+++ b/src/arch/mips/isa/bitfields.isa
@@ -1,6 +1,6 @@
// -*- mode:c++ -*-
-// Copyright (c) 2003-2006 The Regents of The University of Michigan
+// Copyright (c) 2006 The Regents of The University of Michigan
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
diff --git a/src/arch/mips/isa/decoder.isa b/src/arch/mips/isa/decoder.isa
index 8b9d8eeb1..9ac982e34 100644
--- a/src/arch/mips/isa/decoder.isa
+++ b/src/arch/mips/isa/decoder.isa
@@ -1,6 +1,6 @@
// -*- mode:c++ -*-
-// Copyright (c) 2003-2006 The Regents of The University of Michigan
+// Copyright (c) 2006 The Regents of The University of Michigan
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
diff --git a/src/arch/mips/isa/formats/basic.isa b/src/arch/mips/isa/formats/basic.isa
index 35ce09205..29dafd541 100644
--- a/src/arch/mips/isa/formats/basic.isa
+++ b/src/arch/mips/isa/formats/basic.isa
@@ -1,6 +1,6 @@
// -*- mode:c++ -*-
-// Copyright (c) 2003-2006 The Regents of The University of Michigan
+// Copyright (c) 2006 The Regents of The University of Michigan
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
diff --git a/src/arch/mips/isa/formats/branch.isa b/src/arch/mips/isa/formats/branch.isa
index 827e3ccf0..5230ce9cc 100644
--- a/src/arch/mips/isa/formats/branch.isa
+++ b/src/arch/mips/isa/formats/branch.isa
@@ -1,6 +1,6 @@
// -*- mode:c++ -*-
-// Copyright (c) 2003-2006 The Regents of The University of Michigan
+// Copyright (c) 2006 The Regents of The University of Michigan
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
diff --git a/src/arch/mips/isa/formats/control.isa b/src/arch/mips/isa/formats/control.isa
index 509ee7e87..6c7d396f3 100644
--- a/src/arch/mips/isa/formats/control.isa
+++ b/src/arch/mips/isa/formats/control.isa
@@ -1,6 +1,6 @@
// -*- mode:c++ -*-
-// Copyright (c) 2003-2006 The Regents of The University of Michigan
+// Copyright (c) 2006 The Regents of The University of Michigan
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
diff --git a/src/arch/mips/isa/formats/fp.isa b/src/arch/mips/isa/formats/fp.isa
index d05b04d0e..1e5d62626 100644
--- a/src/arch/mips/isa/formats/fp.isa
+++ b/src/arch/mips/isa/formats/fp.isa
@@ -1,6 +1,6 @@
// -*- mode:c++ -*-
-// Copyright (c) 2003-2006 The Regents of The University of Michigan
+// Copyright (c) 2006 The Regents of The University of Michigan
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
diff --git a/src/arch/mips/isa/formats/int.isa b/src/arch/mips/isa/formats/int.isa
index 8ac50b009..56a4ec204 100644
--- a/src/arch/mips/isa/formats/int.isa
+++ b/src/arch/mips/isa/formats/int.isa
@@ -1,6 +1,6 @@
// -*- mode:c++ -*-
-// Copyright (c) 2003-2006 The Regents of The University of Michigan
+// Copyright (c) 2006 The Regents of The University of Michigan
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
diff --git a/src/arch/mips/isa/formats/mem.isa b/src/arch/mips/isa/formats/mem.isa
index 5a8930a08..f03f7becd 100644
--- a/src/arch/mips/isa/formats/mem.isa
+++ b/src/arch/mips/isa/formats/mem.isa
@@ -1,6 +1,6 @@
// -*- mode:c++ -*-
-// Copyright (c) 2003-2005 The Regents of The University of Michigan
+// Copyright (c) 2006 The Regents of The University of Michigan
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
diff --git a/src/arch/mips/isa/formats/noop.isa b/src/arch/mips/isa/formats/noop.isa
index 430c32f82..7f3d313ad 100644
--- a/src/arch/mips/isa/formats/noop.isa
+++ b/src/arch/mips/isa/formats/noop.isa
@@ -1,5 +1,33 @@
// -*- mode:c++ -*-
+// Copyright (c) 2006 The Regents of The University of Michigan
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met: redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer;
+// redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution;
+// neither the name of the copyright holders nor the names of its
+// contributors may be used to endorse or promote products derived from
+// this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// Authors: Korey Sewell
+
////////////////////////////////////////////////////////////////////
//
// Nop
diff --git a/src/arch/mips/isa/formats/tlbop.isa b/src/arch/mips/isa/formats/tlbop.isa
index 75ab71c48..b974ccbed 100644
--- a/src/arch/mips/isa/formats/tlbop.isa
+++ b/src/arch/mips/isa/formats/tlbop.isa
@@ -1,6 +1,6 @@
// -*- mode:c++ -*-
-// Copyright (c) 2003-2006 The Regents of The University of Michigan
+// Copyright (c) 2006 The Regents of The University of Michigan
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
diff --git a/src/arch/mips/isa/formats/trap.isa b/src/arch/mips/isa/formats/trap.isa
index 8a9c5822a..b9066f374 100644
--- a/src/arch/mips/isa/formats/trap.isa
+++ b/src/arch/mips/isa/formats/trap.isa
@@ -1,6 +1,6 @@
// -*- mode:c++ -*-
-// Copyright (c) 2003-2006 The Regents of The University of Michigan
+// Copyright (c) 2006 The Regents of The University of Michigan
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
diff --git a/src/arch/mips/isa/formats/unimp.isa b/src/arch/mips/isa/formats/unimp.isa
index e17b5f832..03068fa74 100644
--- a/src/arch/mips/isa/formats/unimp.isa
+++ b/src/arch/mips/isa/formats/unimp.isa
@@ -1,7 +1,7 @@
// -*- mode:c++ -*-
-// Copyright (c) 2003-2005 The Regents of The University of Michigan
+// Copyright (c) 2006 The Regents of The University of Michigan
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
diff --git a/src/arch/mips/isa/formats/unknown.isa b/src/arch/mips/isa/formats/unknown.isa
index 41387adca..70b3901e9 100644
--- a/src/arch/mips/isa/formats/unknown.isa
+++ b/src/arch/mips/isa/formats/unknown.isa
@@ -1,6 +1,6 @@
// -*- mode:c++ -*-
-// Copyright (c) 2003-2006 The Regents of The University of Michigan
+// Copyright (c) 2006 The Regents of The University of Michigan
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
diff --git a/src/arch/mips/isa/formats/util.isa b/src/arch/mips/isa/formats/util.isa
index b67a02d07..0cc375af3 100644
--- a/src/arch/mips/isa/formats/util.isa
+++ b/src/arch/mips/isa/formats/util.isa
@@ -1,6 +1,6 @@
// -*- mode:c++ -*-
-// Copyright (c) 2003-2006 The Regents of The University of Michigan
+// Copyright (c) 2006 The Regents of The University of Michigan
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
diff --git a/src/arch/mips/isa/includes.isa b/src/arch/mips/isa/includes.isa
index 555cec255..6b5f3c588 100644
--- a/src/arch/mips/isa/includes.isa
+++ b/src/arch/mips/isa/includes.isa
@@ -1,6 +1,6 @@
// -*- mode:c++ -*-
-// Copyright (c) 2003-2006 The Regents of The University of Michigan
+// Copyright (c) 2006 The Regents of The University of Michigan
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
diff --git a/src/arch/mips/isa/main.isa b/src/arch/mips/isa/main.isa
index 9da3fc0db..2d7c63cd5 100644
--- a/src/arch/mips/isa/main.isa
+++ b/src/arch/mips/isa/main.isa
@@ -1,6 +1,6 @@
// -*- mode:c++ -*-
-// Copyright (c) 2003-2005 The Regents of The University of Michigan
+// Copyright (c) 2006 The Regents of The University of Michigan
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
diff --git a/src/arch/mips/isa/operands.isa b/src/arch/mips/isa/operands.isa
index 316552ef4..3843dc053 100644
--- a/src/arch/mips/isa/operands.isa
+++ b/src/arch/mips/isa/operands.isa
@@ -1,6 +1,6 @@
// -*- mode:c++ -*-
-// Copyright (c) 2003-2006 The Regents of The University of Michigan
+// Copyright (c) 2006 The Regents of The University of Michigan
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
@@ -53,8 +53,8 @@ def operands {{
'R2': ('IntReg', 'uw','2', 'IsInteger', 5),
#Special Integer Reg operands
- 'HI': ('IntReg', 'uw','32', 'IsInteger', 6),
- 'LO': ('IntReg', 'uw','33', 'IsInteger', 7),
+ 'HI': ('IntReg', 'uw','MipsISA::HI', 'IsInteger', 6),
+ 'LO': ('IntReg', 'uw','MipsISA::LO', 'IsInteger', 7),
#Immediate Value operand
'IntImm': ('IntReg', 'uw', 'INTIMM', 'IsInteger', 3),
@@ -66,11 +66,11 @@ def operands {{
'Fr': ('FloatReg', 'sf', 'FR', 'IsFloating', 3),
#Special Floating Point Control Reg Operands
- 'FIR': ('FloatReg', 'uw', '32', 'IsFloating', 1),
- 'FCCR': ('FloatReg', 'uw', '33', 'IsFloating', 2),
- 'FEXR': ('FloatReg', 'uw', '34', 'IsFloating', 3),
- 'FENR': ('FloatReg', 'uw', '35', 'IsFloating', 3),
- 'FCSR': ('FloatReg', 'uw', '36', 'IsFloating', 3),
+ 'FIR': ('FloatReg', 'uw', 'MipsISA::FIR', 'IsFloating', 1),
+ 'FCCR': ('FloatReg', 'uw', 'MipsISA::FCCR', 'IsFloating', 2),
+ 'FEXR': ('FloatReg', 'uw', 'MipsISA::FEXR', 'IsFloating', 3),
+ 'FENR': ('FloatReg', 'uw', 'MipsISA::FENR', 'IsFloating', 3),
+ 'FCSR': ('FloatReg', 'uw', 'MipsISA::FCSR', 'IsFloating', 3),
#Operands For Paired Singles FP Operations
'Fd1': ('FloatReg', 'sf', 'FD', 'IsFloating', 4),
diff --git a/src/arch/mips/isa_traits.cc b/src/arch/mips/isa_traits.cc
index 9f3817a60..85acc4e8c 100644
--- a/src/arch/mips/isa_traits.cc
+++ b/src/arch/mips/isa_traits.cc
@@ -30,7 +30,7 @@
*/
#include "arch/mips/isa_traits.hh"
-#include "config/full_system.hh"
+//#include "config/full_system.hh"
#include "cpu/static_inst.hh"
#include "sim/serialize.hh"
#include "base/bitfield.hh"
@@ -43,39 +43,14 @@ void
MipsISA::copyRegs(ThreadContext *src, ThreadContext *dest)
{
panic("Copy Regs Not Implemented Yet\n");
- /*fpcr = xc->readMiscReg(MipsISA::Fpcr_DepTag);
- uniq = xc->readMiscReg(MipsISA::Uniq_DepTag);
- lock_flag = xc->readMiscReg(MipsISA::Lock_Flag_DepTag);
- lock_addr = xc->readMiscReg(MipsISA::Lock_Addr_DepTag);
-
-#if FULL_SYSTEM
- copyIprs(xc);
- #endif*/
}
void
MipsISA::MiscRegFile::copyMiscRegs(ThreadContext *tc)
{
panic("Copy Misc. Regs Not Implemented Yet\n");
- /*fpcr = xc->readMiscReg(MipsISA::Fpcr_DepTag);
- uniq = xc->readMiscReg(MipsISA::Uniq_DepTag);
- lock_flag = xc->readMiscReg(MipsISA::Lock_Flag_DepTag);
- lock_addr = xc->readMiscReg(MipsISA::Lock_Addr_DepTag);
-
- #endif*/
}
-#if FULL_SYSTEM
-
-static inline Addr
-TruncPage(Addr addr)
-{ return addr & ~(MipsISA::PageBytes - 1); }
-
-static inline Addr
-RoundPage(Addr addr)
-{ return (addr + MipsISA::PageBytes - 1) & ~(MipsISA::PageBytes - 1); }
-#endif
-
void
IntRegFile::serialize(std::ostream &os)
{
@@ -100,12 +75,6 @@ RegFile::serialize(std::ostream &os)
SERIALIZE_SCALAR(pc);
SERIALIZE_SCALAR(npc);
SERIALIZE_SCALAR(nnpc);
-#if FULL_SYSTEM
- SERIALIZE_ARRAY(palregs, NumIntRegs);
- SERIALIZE_ARRAY(ipr, NumInternalProcRegs);
- SERIALIZE_SCALAR(intrflag);
- SERIALIZE_SCALAR(pal_shadow);
-#endif
}
@@ -121,43 +90,5 @@ RegFile::unserialize(Checkpoint *cp, const std::string &section)
UNSERIALIZE_SCALAR(pc);
UNSERIALIZE_SCALAR(npc);
UNSERIALIZE_SCALAR(nnpc);
-#if FULL_SYSTEM
- UNSERIALIZE_ARRAY(palregs, NumIntRegs);
- UNSERIALIZE_ARRAY(ipr, NumInternalProcRegs);
- UNSERIALIZE_SCALAR(intrflag);
- UNSERIALIZE_SCALAR(pal_shadow);
-#endif
-}
-
-#if FULL_SYSTEM
-void
-PTE::serialize(std::ostream &os)
-{
- SERIALIZE_SCALAR(tag);
- SERIALIZE_SCALAR(ppn);
- SERIALIZE_SCALAR(xre);
- SERIALIZE_SCALAR(xwe);
- SERIALIZE_SCALAR(asn);
- SERIALIZE_SCALAR(asma);
- SERIALIZE_SCALAR(fonr);
- SERIALIZE_SCALAR(fonw);
- SERIALIZE_SCALAR(valid);
}
-
-
-void
-PTE::unserialize(Checkpoint *cp, const std::string &section)
-{
- UNSERIALIZE_SCALAR(tag);
- UNSERIALIZE_SCALAR(ppn);
- UNSERIALIZE_SCALAR(xre);
- UNSERIALIZE_SCALAR(xwe);
- UNSERIALIZE_SCALAR(asn);
- UNSERIALIZE_SCALAR(asma);
- UNSERIALIZE_SCALAR(fonr);
- UNSERIALIZE_SCALAR(fonw);
- UNSERIALIZE_SCALAR(valid);
-}
-
-#endif //FULL_SYSTEM
diff --git a/src/arch/mips/isa_traits.hh b/src/arch/mips/isa_traits.hh
index dc8b6758a..ff994bef9 100644
--- a/src/arch/mips/isa_traits.hh
+++ b/src/arch/mips/isa_traits.hh
@@ -57,12 +57,6 @@ namespace LittleEndianGuest {};
class StaticInst;
class StaticInstPtr;
-namespace MIPS34K {
-int DTB_ASN_ASN(uint64_t reg);
-int ITB_ASN_ASN(uint64_t reg);
-};
-
-#if !FULL_SYSTEM
class SyscallReturn {
public:
template <class T>
@@ -95,7 +89,6 @@ class SyscallReturn {
uint64_t retval;
bool success;
};
-#endif
namespace MipsISA
{
@@ -140,12 +133,6 @@ namespace MipsISA
void copyRegs(ThreadContext *src, ThreadContext *dest);
- uint64_t fpConvert(double fp_val, ConvertType cvt_type);
- double roundFP(double val, int digits);
- double truncFP(double val);
- bool getFPConditionCode(uint32_t fcsr_reg, int cc);
- uint32_t makeCCVector(uint32_t fcsr, int num, bool val);
-
// Machine operations
void saveMachineReg(AnyReg &savereg, const RegFile &reg_file,
@@ -191,12 +178,6 @@ namespace MipsISA
};
-#if FULL_SYSTEM
-
-#include "arch/mips/mips34k.hh"
-
-#endif
-
using namespace MipsISA;
#endif // __ARCH_MIPS_ISA_TRAITS_HH__
diff --git a/src/arch/mips/process.cc b/src/arch/mips/process.cc
index 7762c2fa0..031c2030e 100644
--- a/src/arch/mips/process.cc
+++ b/src/arch/mips/process.cc
@@ -1,3 +1,4 @@
+
/*
* Copyright (c) 2003-2004 The Regents of The University of Michigan
* All rights reserved.
diff --git a/src/arch/mips/regfile/float_regfile.hh b/src/arch/mips/regfile/float_regfile.hh
index e260f681c..61efbb416 100644
--- a/src/arch/mips/regfile/float_regfile.hh
+++ b/src/arch/mips/regfile/float_regfile.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2003-2005 The Regents of The University of Michigan
+ * Copyright (c) 2006 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -100,7 +100,7 @@ namespace MipsISA
}
}
- Fault setReg(int floatReg, const FloatReg &val, int width)
+ Fault setReg(int floatReg, const FloatRegVal &val, int width)
{
using namespace std;
switch(width)
diff --git a/src/arch/mips/regfile/int_regfile.hh b/src/arch/mips/regfile/int_regfile.hh
index dc82a3c26..5add1b7be 100644
--- a/src/arch/mips/regfile/int_regfile.hh
+++ b/src/arch/mips/regfile/int_regfile.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2003-2005 The Regents of The University of Michigan
+ * Copyright (c) 2006 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -65,11 +65,6 @@ namespace MipsISA
};
- enum MiscIntRegNums {
- HI = NumIntArchRegs,
- LO
- };
-
} // namespace MipsISA
#endif
diff --git a/src/arch/mips/regfile/misc_regfile.hh b/src/arch/mips/regfile/misc_regfile.hh
index f8aeab8cb..87961f97e 100644
--- a/src/arch/mips/regfile/misc_regfile.hh
+++ b/src/arch/mips/regfile/misc_regfile.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2003-2005 The Regents of The University of Michigan
+ * Copyright (c) 2006 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -45,18 +45,12 @@ namespace MipsISA
protected:
uint64_t fpcr; // floating point condition codes
- uint64_t uniq; // process-unique register
bool lock_flag; // lock flag for LL/SC
Addr lock_addr; // lock address for LL/SC
MiscReg miscRegFile[NumMiscRegs];
public:
- //These functions should be removed once the simplescalar cpu model
- //has been replaced.
- int getInstAsid();
- int getDataAsid();
-
void copyMiscRegs(ThreadContext *tc);
MiscReg readReg(int misc_reg)
@@ -80,17 +74,6 @@ namespace MipsISA
miscRegFile[misc_reg] = val; return NoFault;
}
-#if FULL_SYSTEM
- void clearIprs() { }
-
- protected:
- InternalProcReg ipr[NumInternalProcRegs]; // Internal processor regs
-
- private:
- MiscReg readIpr(int idx, Fault &fault, ThreadContext *tc) { }
-
- Fault setIpr(int idx, uint64_t val, ThreadContext *tc) { }
-#endif
friend class RegFile;
};
} // namespace MipsISA
diff --git a/src/arch/mips/regfile/regfile.hh b/src/arch/mips/regfile/regfile.hh
index af61e62cd..a68120299 100644
--- a/src/arch/mips/regfile/regfile.hh
+++ b/src/arch/mips/regfile/regfile.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2003-2005 The Regents of The University of Michigan
+ * Copyright (c) 2006 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -81,12 +81,12 @@ namespace MipsISA
return miscRegFile.setRegWithEffect(miscReg, val, tc);
}
- FloatReg readFloatReg(int floatReg)
+ FloatRegVal readFloatReg(int floatReg)
{
return floatRegFile.readReg(floatReg,SingleWidth);
}
- FloatReg readFloatReg(int floatReg, int width)
+ FloatRegVal readFloatReg(int floatReg, int width)
{
return floatRegFile.readReg(floatReg,width);
}
@@ -101,12 +101,12 @@ namespace MipsISA
return floatRegFile.readRegBits(floatReg,width);
}
- Fault setFloatReg(int floatReg, const FloatReg &val)
+ Fault setFloatReg(int floatReg, const FloatRegVal &val)
{
return floatRegFile.setReg(floatReg, val, SingleWidth);
}
- Fault setFloatReg(int floatReg, const FloatReg &val, int width)
+ Fault setFloatReg(int floatReg, const FloatRegVal &val, int width)
{
return floatRegFile.setReg(floatReg, val, width);
}
@@ -168,16 +168,6 @@ namespace MipsISA
nnpc = val;
}
-
-#if FULL_SYSTEM
- IntReg palregs[NumIntRegs]; // PAL shadow registers
- InternalProcReg ipr[NumInternalProcRegs]; // internal processor regs
- int intrflag; // interrupt flag
- bool pal_shadow; // using pal_shadow registers
- inline int instAsid() { return MIPS34K::ITB_ASN_ASN(ipr[IPR_ITB_ASN]); }
- inline int dataAsid() { return MIPS34K::DTB_ASN_ASN(ipr[IPR_DTB_ASN]); }
-#endif // FULL_SYSTEM
-
void serialize(std::ostream &os);
void unserialize(Checkpoint *cp, const std::string &section);
@@ -193,9 +183,6 @@ namespace MipsISA
void copyMiscRegs(ThreadContext *src, ThreadContext *dest);
-#if FULL_SYSTEM
- void copyIprs(ThreadContext *src, ThreadContext *dest);
-#endif
} // namespace MipsISA
#endif
diff --git a/src/arch/mips/stacktrace.hh b/src/arch/mips/stacktrace.hh
index ff35aaeb0..f9e092dbd 100644
--- a/src/arch/mips/stacktrace.hh
+++ b/src/arch/mips/stacktrace.hh
@@ -25,7 +25,7 @@
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
- * Authors: Korey Sewell
+ * Authors: Ali Saidi
*/
#ifndef __ARCH_MIPS_STACKTRACE_HH__
diff --git a/src/arch/mips/types.hh b/src/arch/mips/types.hh
index 7cd2eed0c..6330044d9 100644
--- a/src/arch/mips/types.hh
+++ b/src/arch/mips/types.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2003-2005 The Regents of The University of Michigan
+ * Copyright (c) 2006 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -42,14 +42,15 @@ namespace MipsISA
typedef uint32_t IntReg;
// floating point register file entry type
- typedef double FloatReg;
typedef uint32_t FloatReg32;
typedef uint64_t FloatReg64;
typedef uint64_t FloatRegBits;
+ typedef double FloatRegVal;
+ typedef double FloatReg;
+
// cop-0/cop-1 system control register
typedef uint64_t MiscReg;
- typedef uint64_t InternalProcReg;
typedef union {
IntReg intreg;