Copy implementations

arch/alpha/isa_desc:
    Need to return fault for copy operations.
cpu/exec_context.hh:
    Add temporary storage to pass source address from copy load to copy store
cpu/simple_cpu/simple_cpu.cc:
    Implement copy functions.
cpu/simple_cpu/simple_cpu.hh:
    Return fault

--HG--
extra : convert_revision : 98e5ce563449d6057ba45c70eece9235f1649a90

4 files changed, 56 insertions, 11 deletions

diff --git a/arch/alpha/isa_desc b/arch/alpha/isa_desc
index 46fb306a4..41f7388e0 100644
--- a/arch/alpha/isa_desc
+++ b/arch/alpha/isa_desc
@@ -1855,7 +1855,7 @@ decode OPCODE default Unknown::unknown() {
 	0x2a: ldl_l({{ EA = Rb + disp; }}, {{ Ra.sl = Mem.sl; }}, LOCKED);
 	0x2b: ldq_l({{ EA = Rb + disp; }}, {{ Ra.uq = Mem.uq; }}, LOCKED);
 	0x20: copy_load({{EA = Ra;}}, 
-	                {{memAccessObj->copySrcTranslate(EA);}},
+	                {{fault = memAccessObj->copySrcTranslate(EA);}},
 			IsMemRef, IsLoad, IsCopy);
     }
 
@@ -1877,7 +1877,7 @@ decode OPCODE default Unknown::unknown() {
 	0x26: sts({{ EA = Rb + disp; }}, {{ Mem.ul = t_to_s(Fa.uq); }});
 	0x27: stt({{ EA = Rb + disp; }}, {{ Mem.df = Fa; }});
 	0x24: copy_store({{EA = Rb;}},
-	                 {{memAccessObj->copy(EA);}},
+	                 {{fault =memAccessObj->copy(EA);}},
 			 IsMemRef, IsStore, IsCopy);
     }
 
diff --git a/cpu/exec_context.hh b/cpu/exec_context.hh
index e9dc5efec..ccb01f486 100644
--- a/cpu/exec_context.hh
+++ b/cpu/exec_context.hh
@@ -153,6 +153,18 @@ class ExecContext
 
 #endif
 
+    /**
+     * Temporary storage to pass the source address from copy_load to
+     * copy_store.
+     * @todo Remove this temporary when we have a better way to do it.
+     */
+    Addr copySrcAddr;
+    /**
+     * Temp storage for the physical source address of a copy.
+     * @todo Remove this temporary when we have a better way to do it.
+     */
+    Addr copySrcPhysAddr;
+
 
     /*
      * number of executed instructions, for matching with syscall trace
diff --git a/cpu/simple_cpu/simple_cpu.cc b/cpu/simple_cpu/simple_cpu.cc
index 721861dd5..2553bd22a 100644
--- a/cpu/simple_cpu/simple_cpu.cc
+++ b/cpu/simple_cpu/simple_cpu.cc
@@ -327,6 +327,46 @@ change_thread_state(int thread_number, int activate, int priority)
 {
 }
 
+Fault
+SimpleCPU::copySrcTranslate(Addr src)
+{
+    memReq->reset(src, (dcacheInterface) ?
+                  dcacheInterface->getBlockSize()
+                  : 64);
+
+    // translate to physical address
+    Fault fault = xc->translateDataReadReq(memReq);
+
+    if (fault == No_Fault) {
+        xc->copySrcAddr = src;
+        xc->copySrcPhysAddr = memReq->paddr;
+    } else {
+        xc->copySrcAddr = 0;
+        xc->copySrcPhysAddr = 0;
+    }
+    return fault;
+}
+
+Fault
+SimpleCPU::copy(Addr dest)
+{
+    int blk_size = (dcacheInterface) ? dcacheInterface->getBlockSize() : 64;
+    uint8_t data[blk_size];
+    assert(xc->copySrcPhysAddr);
+    memReq->reset(dest, blk_size);
+    // translate to physical address
+    Fault fault = xc->translateDataWriteReq(memReq);
+    if (fault == No_Fault) {
+        Addr dest_addr = memReq->paddr;
+        // Need to read straight from memory since we have more than 8 bytes.
+        memReq->paddr = xc->copySrcPhysAddr;
+        xc->mem->read(memReq, data);
+        memReq->paddr = dest_addr;
+        xc->mem->write(memReq, data);
+    }
+    return fault;
+}
+
 // precise architected memory state accessor macros
 template <class T>
 Fault
diff --git a/cpu/simple_cpu/simple_cpu.hh b/cpu/simple_cpu/simple_cpu.hh
index 4bdc69ad1..9edd66ab4 100644
--- a/cpu/simple_cpu/simple_cpu.hh
+++ b/cpu/simple_cpu/simple_cpu.hh
@@ -247,16 +247,9 @@ class SimpleCPU : public BaseCPU
         // need to do this...
     }
 
-    void copySrcTranslate(Addr src)
-    {
-        panic("Haven't implemented Copy Src translate yet in SimpleCPU\n");
-    }
-
-    void copy(Addr dest)
-    {
-        panic("Haven't implemented Copy yet in SimpleCPU\n");
-    }
+    Fault copySrcTranslate(Addr src);
 
+    Fault copy(Addr dest);
 };
 
 #endif // __SIMPLE_CPU_HH__