Ruby: Remove the physMemPort and instead access memory directly

This patch removes the physMemPort from the RubySequencer and instead
uses the system pointer to access the physmem. The system already
keeps track of the physmem and the valid memory address ranges, and
with this patch we merely make use of that existing functionality. The
memory is modified so that it is possible to call the access functions
(atomic and functional) without going through the port, and the memory
is allowed to be unconnected, i.e. have no ports (since Ruby does not
attach it like the conventional memory system).

12 files changed, 17 insertions, 62 deletions

diff --git a/configs/ruby/MESI_CMP_directory.py b/configs/ruby/MESI_CMP_directory.py
index 4fdba3c27..28aba4a1b 100644
--- a/configs/ruby/MESI_CMP_directory.py
+++ b/configs/ruby/MESI_CMP_directory.py
@@ -96,8 +96,6 @@ def create_system(options, system, piobus, dma_devices, ruby_system):
         cpu_seq = RubySequencer(version = i,
                                 icache = l1i_cache,
                                 dcache = l1d_cache,
-                                physMemPort = system.physmem.port,
-                                physmem = system.physmem,
                                 ruby_system = ruby_system)
 
         l1_cntrl.sequencer = cpu_seq
@@ -169,8 +167,6 @@ def create_system(options, system, piobus, dma_devices, ruby_system):
         # Create the Ruby objects associated with the dma controller
         #
         dma_seq = DMASequencer(version = i,
-                               physMemPort = system.physmem.port,
-                               physmem = system.physmem,
                                ruby_system = ruby_system)
         
         dma_cntrl = DMA_Controller(version = i,
diff --git a/configs/ruby/MI_example.py b/configs/ruby/MI_example.py
index 851001b6f..29ed23b67 100644
--- a/configs/ruby/MI_example.py
+++ b/configs/ruby/MI_example.py
@@ -88,8 +88,6 @@ def create_system(options, system, piobus, dma_devices, ruby_system):
         cpu_seq = RubySequencer(version = i,
                                 icache = cache,
                                 dcache = cache,
-                                physMemPort = system.physmem.port,
-                                physmem = system.physmem,
                                 ruby_system = ruby_system)
 
         l1_cntrl.sequencer = cpu_seq
@@ -142,8 +140,6 @@ def create_system(options, system, piobus, dma_devices, ruby_system):
         # Create the Ruby objects associated with the dma controller
         #
         dma_seq = DMASequencer(version = i,
-                               physMemPort = system.physmem.port,
-                               physmem = system.physmem,
                                ruby_system = ruby_system)
         
         dma_cntrl = DMA_Controller(version = i,
diff --git a/configs/ruby/MOESI_CMP_directory.py b/configs/ruby/MOESI_CMP_directory.py
index ac582e4e6..753a3a37a 100644
--- a/configs/ruby/MOESI_CMP_directory.py
+++ b/configs/ruby/MOESI_CMP_directory.py
@@ -96,8 +96,6 @@ def create_system(options, system, piobus, dma_devices, ruby_system):
         cpu_seq = RubySequencer(version = i,
                                 icache = l1i_cache,
                                 dcache = l1d_cache,
-                                physMemPort = system.physmem.port,
-                                physmem = system.physmem,
                                 ruby_system = ruby_system)
 
         l1_cntrl.sequencer = cpu_seq
@@ -166,8 +164,6 @@ def create_system(options, system, piobus, dma_devices, ruby_system):
         # Create the Ruby objects associated with the dma controller
         #
         dma_seq = DMASequencer(version = i,
-                               physMemPort = system.physmem.port,
-                               physmem = system.physmem,
                                ruby_system = ruby_system)
         
         dma_cntrl = DMA_Controller(version = i,
diff --git a/configs/ruby/MOESI_CMP_token.py b/configs/ruby/MOESI_CMP_token.py
index 20b50e3af..064d6dd14 100644
--- a/configs/ruby/MOESI_CMP_token.py
+++ b/configs/ruby/MOESI_CMP_token.py
@@ -118,8 +118,6 @@ def create_system(options, system, piobus, dma_devices, ruby_system):
         cpu_seq = RubySequencer(version = i,
                                 icache = l1i_cache,
                                 dcache = l1d_cache,
-                                physMemPort = system.physmem.port,
-                                physmem = system.physmem,
                                 ruby_system = ruby_system)
 
         l1_cntrl.sequencer = cpu_seq
@@ -190,8 +188,6 @@ def create_system(options, system, piobus, dma_devices, ruby_system):
         # Create the Ruby objects associated with the dma controller
         #
         dma_seq = DMASequencer(version = i,
-                               physMemPort = system.physmem.port,
-                               physmem = system.physmem,
                                ruby_system = ruby_system)
         
         dma_cntrl = DMA_Controller(version = i,
diff --git a/configs/ruby/MOESI_hammer.py b/configs/ruby/MOESI_hammer.py
index 3f89a1a90..dc9aa3392 100644
--- a/configs/ruby/MOESI_hammer.py
+++ b/configs/ruby/MOESI_hammer.py
@@ -111,8 +111,6 @@ def create_system(options, system, piobus, dma_devices, ruby_system):
         cpu_seq = RubySequencer(version = i,
                                 icache = l1i_cache,
                                 dcache = l1d_cache,
-                                physMemPort = system.physmem.port,
-                                physmem = system.physmem,
                                 ruby_system = ruby_system)
 
         l1_cntrl.sequencer = cpu_seq
@@ -202,8 +200,6 @@ def create_system(options, system, piobus, dma_devices, ruby_system):
         # Create the Ruby objects associated with the dma controller
         #
         dma_seq = DMASequencer(version = i,
-                               physMemPort = system.physmem.port,
-                               physmem = system.physmem,
                                ruby_system = ruby_system)
         
         dma_cntrl = DMA_Controller(version = i,
diff --git a/configs/ruby/Network_test.py b/configs/ruby/Network_test.py
index 768b14677..5c1936b51 100644
--- a/configs/ruby/Network_test.py
+++ b/configs/ruby/Network_test.py
@@ -88,8 +88,6 @@ def create_system(options, system, piobus, dma_devices, ruby_system):
 
         cpu_seq = RubySequencer(icache = cache,
                                 dcache = cache,
-                                physMemPort = system.physmem.port,
-                                physmem = system.physmem,
                                 using_network_tester = True,
                                 ruby_system = ruby_system)
 
diff --git a/configs/ruby/Ruby.py b/configs/ruby/Ruby.py
index 1c9b65894..c9788b0a0 100644
--- a/configs/ruby/Ruby.py
+++ b/configs/ruby/Ruby.py
@@ -97,10 +97,7 @@ def create_system(options, system, piobus = None, dma_devices = []):
     # Create a port proxy for connecting the system port. This is
     # independent of the protocol and kept in the protocol-agnostic
     # part (i.e. here).
-    sys_port_proxy = RubyPortProxy(version = 0,
-                                   physMemPort = system.physmem.port,
-                                   physmem = system.physmem,
-                                   ruby_system = ruby)
+    sys_port_proxy = RubyPortProxy(ruby_system = ruby)
     # Give the system port proxy a SimObject parent without creating a
     # full-fledged controller
     system.sys_port_proxy = sys_port_proxy
diff --git a/src/mem/physical.cc b/src/mem/physical.cc
index 9c953e562..78181b7df 100644
--- a/src/mem/physical.cc
+++ b/src/mem/physical.cc
@@ -115,12 +115,12 @@ PhysicalMemory::PhysicalMemory(const Params *p)
 void
 PhysicalMemory::init()
 {
-    if (ports.empty()) {
-        fatal("PhysicalMemory object %s is unconnected!", name());
-    }
-
-    for (PortIterator pi = ports.begin(); pi != ports.end(); ++pi) {
-        (*pi)->sendRangeChange();
+    for (PortIterator p = ports.begin(); p != ports.end(); ++p) {
+        if (!(*p)->isConnected()) {
+            fatal("PhysicalMemory port %s is unconnected!\n", (*p)->name());
+        } else {
+            (*p)->sendRangeChange();
+        }
     }
 }
 
diff --git a/src/mem/physical.hh b/src/mem/physical.hh
index 452ac3fc0..23d4052fa 100644
--- a/src/mem/physical.hh
+++ b/src/mem/physical.hh
@@ -198,9 +198,11 @@ class PhysicalMemory : public MemObject
     void virtual init();
     unsigned int drain(Event *de);
 
-  protected:
     Tick doAtomicAccess(PacketPtr pkt);
     void doFunctionalAccess(PacketPtr pkt);
+
+
+  protected:
     virtual Tick calculateLatency(PacketPtr pkt);
 
   public:
diff --git a/src/mem/ruby/system/RubyPort.cc b/src/mem/ruby/system/RubyPort.cc
index 1769c51fd..8fd68be7c 100644
--- a/src/mem/ruby/system/RubyPort.cc
+++ b/src/mem/ruby/system/RubyPort.cc
@@ -45,14 +45,14 @@
 #include "mem/protocol/AccessPermission.hh"
 #include "mem/ruby/slicc_interface/AbstractController.hh"
 #include "mem/ruby/system/RubyPort.hh"
+#include "sim/system.hh"
 
 RubyPort::RubyPort(const Params *p)
     : MemObject(p), m_version(p->version), m_controller(NULL),
       m_mandatory_q_ptr(NULL),
       pio_port(csprintf("%s-pio-port", name()), this),
       m_usingRubyTester(p->using_ruby_tester), m_request_cnt(0),
-      physMemPort(csprintf("%s-physMemPort", name()), this),
-      drainEvent(NULL), physmem(p->physmem), ruby_system(p->ruby_system),
+      drainEvent(NULL), ruby_system(p->ruby_system), system(p->system),
       waitingOnSequencer(false), access_phys_mem(p->access_phys_mem)
 {
     assert(m_version != -1);
@@ -84,10 +84,6 @@ RubyPort::getMasterPort(const std::string &if_name, int idx)
         return pio_port;
     }
 
-    if (if_name == "physMemPort") {
-        return physMemPort;
-    }
-
     // used by the x86 CPUs to connect the interrupt PIO and interrupt slave
     // port
     if (if_name != "master") {
@@ -471,7 +467,7 @@ RubyPort::M5Port::recvFunctional(PacketPtr pkt)
         // The following command performs the real functional access.
         // This line should be removed once Ruby supplies the official version
         // of data.
-        ruby_port->physMemPort.sendFunctional(pkt);
+        ruby_port->system->physmem->doFunctionalAccess(pkt);
     }
 
     // turn packet around to go back to requester if response expected
@@ -568,10 +564,6 @@ RubyPort::getDrainCount(Event *de)
         count += pio_port.drain(de);
         DPRINTF(Config, "count after pio check %d\n", count);
     }
-    if (physMemPort.isConnected()) {
-        count += physMemPort.drain(de);
-        DPRINTF(Config, "count after physmem check %d\n", count);
-    }
 
     for (CpuPortIter p = slave_ports.begin(); p != slave_ports.end(); ++p) {
         count += (*p)->drain(de);
@@ -654,7 +646,7 @@ RubyPort::M5Port::hitCallback(PacketPtr pkt)
     DPRINTF(RubyPort, "Hit callback needs response %d\n", needsResponse);
 
     if (accessPhysMem) {
-        ruby_port->physMemPort.sendAtomic(pkt);
+        ruby_port->system->physmem->doAtomicAccess(pkt);
     } else if (needsResponse) {
         pkt->makeResponse();
     }
@@ -696,18 +688,7 @@ RubyPort::M5Port::getAddrRanges()
 bool
 RubyPort::M5Port::isPhysMemAddress(Addr addr)
 {
-    AddrRangeList physMemAddrList =
-        ruby_port->physMemPort.getSlavePort().getAddrRanges();
-    for (AddrRangeIter iter = physMemAddrList.begin();
-         iter != physMemAddrList.end();
-         iter++) {
-        if (addr >= iter->start && addr <= iter->end) {
-            DPRINTF(RubyPort, "Request found in %#llx - %#llx range\n",
-                    iter->start, iter->end);
-            return true;
-        }
-    }
-    return false;
+    return ruby_port->system->isMemory(addr);
 }
 
 unsigned
diff --git a/src/mem/ruby/system/RubyPort.hh b/src/mem/ruby/system/RubyPort.hh
index d97f6e69e..553614021 100644
--- a/src/mem/ruby/system/RubyPort.hh
+++ b/src/mem/ruby/system/RubyPort.hh
@@ -175,8 +175,6 @@ class RubyPort : public MemObject
     uint16_t m_port_id;
     uint64_t m_request_cnt;
 
-    PioPort physMemPort;
-
     /** Vector of M5 Ports attached to this Ruby port. */
     typedef std::vector<M5Port*>::iterator CpuPortIter;
     std::vector<M5Port*> slave_ports;
@@ -184,8 +182,8 @@ class RubyPort : public MemObject
 
     Event *drainEvent;
 
-    PhysicalMemory* physmem;
     RubySystem* ruby_system;
+    System* system;
 
     //
     // Based on similar code in the M5 bus.  Stores pointers to those ports
diff --git a/src/mem/ruby/system/Sequencer.py b/src/mem/ruby/system/Sequencer.py
index b1e17e052..02686d33f 100644
--- a/src/mem/ruby/system/Sequencer.py
+++ b/src/mem/ruby/system/Sequencer.py
@@ -38,13 +38,12 @@ class RubyPort(MemObject):
     master = VectorMasterPort("CPU master port")
     version = Param.Int(0, "")
     pio_port = MasterPort("Ruby_pio_port")
-    physmem = Param.PhysicalMemory("")
-    physMemPort = MasterPort("port to physical memory")
     using_ruby_tester = Param.Bool(False, "")
     using_network_tester = Param.Bool(False, "")
     access_phys_mem = Param.Bool(True,
         "should the rubyport atomically update phys_mem")
     ruby_system = Param.RubySystem("")
+    system = Param.System(Parent.any, "system object")
 
 class RubyPortProxy(RubyPort):
     type = 'RubyPortProxy'