diff options
| author | Min Kyu Jeong <minkyu.jeong@arm.com> | 2010-08-23 11:18:42 -0500 |
|---|---|---|
| committer | Min Kyu Jeong <minkyu.jeong@arm.com> | 2010-08-23 11:18:42 -0500 |
| commit | d8d6b869a2f34b602cdc216660d08b9acba93d43 (patch) | |
| tree | b1bef84ccf7247b0822051a8a127da9dec71e164 | |
| parent | e6a0be648e9fdb4b882cfb5f3224d097817338bc (diff) | |
| download | gem5-d8d6b869a2f34b602cdc216660d08b9acba93d43.tar.xz | |
O3: Skipping mem-order violation check for uncachable loads.
Uncachable load is not executed until it reaches the head of the ROB,
hence cannot cause one.
| -rw-r--r-- | src/cpu/o3/fetch_impl.hh | 6 | ||||
| -rw-r--r-- | src/cpu/o3/iew_impl.hh | 8 | ||||
| -rw-r--r-- | src/cpu/o3/lsq_unit_impl.hh | 18 |
3 files changed, 21 insertions, 11 deletions
diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh index 59149c8c3..3f8f84cab 100644 --- a/src/cpu/o3/fetch_impl.hh +++ b/src/cpu/o3/fetch_impl.hh @@ -1150,9 +1150,9 @@ DefaultFetch<Impl>::fetch(bool &status_change) instruction->setThreadState(cpu->thread[tid]); - DPRINTF(Fetch, "[tid:%i]: Instruction PC %#x created " - "[sn:%lli]\n", - tid, instruction->readPC(), inst_seq); + DPRINTF(Fetch, "[tid:%i]: Instruction PC %#x (%d) created " + "[sn:%lli]\n", tid, instruction->readPC(), + instruction->readMicroPC(), inst_seq); //DPRINTF(Fetch, "[tid:%i]: MachInst is %#x\n", tid, ext_inst); diff --git a/src/cpu/o3/iew_impl.hh b/src/cpu/o3/iew_impl.hh index abb941ef7..2089913ef 100644 --- a/src/cpu/o3/iew_impl.hh +++ b/src/cpu/o3/iew_impl.hh @@ -1318,10 +1318,10 @@ DefaultIEW<Impl>::executeInsts() DynInstPtr violator; violator = ldstQueue.getMemDepViolator(tid); - DPRINTF(IEW, "LDSTQ detected a violation. Violator PC: " - "%#x, inst PC: %#x. Addr is: %#x.\n", - violator->readPC(), inst->readPC(), inst->physEffAddr); - + DPRINTF(IEW, "LDSTQ detected a violation. Violator PC: %#x " + "[sn:%lli], inst PC: %#x [sn:%lli]. Addr is: %#x.\n", + violator->readPC(), violator->seqNum, + inst->readPC(), inst->seqNum, inst->physEffAddr); // Ensure the violating instruction is older than // current squash /* if (fetchRedirect[tid] && diff --git a/src/cpu/o3/lsq_unit_impl.hh b/src/cpu/o3/lsq_unit_impl.hh index 7330ba2ef..8aa7fe397 100644 --- a/src/cpu/o3/lsq_unit_impl.hh +++ b/src/cpu/o3/lsq_unit_impl.hh @@ -479,9 +479,14 @@ LSQUnit<Impl>::executeLoad(DynInstPtr &inst) // are quad word accesses. // @todo: Fix this, magic number being used here + + // @todo: Uncachable load is not executed until it reaches + // the head of the ROB. Once this if checks only the executed + // loads(as noted above), this check can be removed if (loadQueue[load_idx]->effAddrValid && - (loadQueue[load_idx]->effAddr >> 8) == - (inst->effAddr >> 8)) { + ((loadQueue[load_idx]->effAddr >> 8) + == (inst->effAddr >> 8)) && + !loadQueue[load_idx]->uncacheable()) { // A load incorrectly passed this load. Squash and refetch. // For now return a fault to show that it was unsuccessful. DynInstPtr violator = loadQueue[load_idx]; @@ -553,9 +558,14 @@ LSQUnit<Impl>::executeStore(DynInstPtr &store_inst) // are quad word accesses. // @todo: Fix this, magic number being used here + + // @todo: Uncachable load is not executed until it reaches + // the head of the ROB. Once this if checks only the executed + // loads(as noted above), this check can be removed if (loadQueue[load_idx]->effAddrValid && - (loadQueue[load_idx]->effAddr >> 8) == - (store_inst->effAddr >> 8)) { + ((loadQueue[load_idx]->effAddr >> 8) + == (store_inst->effAddr >> 8)) && + !loadQueue[load_idx]->uncacheable()) { // A load incorrectly passed this store. Squash and refetch. // For now return a fault to show that it was unsuccessful. DynInstPtr violator = loadQueue[load_idx]; |