Adjust references to reflect differences without special delay slot handling. Performance actually went up slightly.

--HG--
extra : convert_revision : 504f6185ddc89881aa41deb7fd934da8038d1ed2

3 files changed, 135 insertions, 137 deletions

diff --git a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/m5stats.txt b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/m5stats.txt
index 7c0d31494..4c5655a33 100644
--- a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/m5stats.txt
+++ b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/m5stats.txt
@@ -1,17 +1,17 @@
 
 ---------- Begin Simulation Statistics ----------
 global.BPredUnit.BTBCorrect                         0                       # Number of correct BTB predictions (this stat may not work properly.
-global.BPredUnit.BTBHits                         2990                       # Number of BTB hits
-global.BPredUnit.BTBLookups                      7055                       # Number of BTB lookups
+global.BPredUnit.BTBHits                         3021                       # Number of BTB hits
+global.BPredUnit.BTBLookups                      7086                       # Number of BTB lookups
 global.BPredUnit.RASInCorrect                       0                       # Number of incorrect RAS predictions.
 global.BPredUnit.condIncorrect                   2077                       # Number of conditional branches incorrect
-global.BPredUnit.condPredicted                   7846                       # Number of conditional branches predicted
-global.BPredUnit.lookups                         7846                       # Number of BP lookups
+global.BPredUnit.condPredicted                   7877                       # Number of conditional branches predicted
+global.BPredUnit.lookups                         7877                       # Number of BP lookups
 global.BPredUnit.usedRAS                            0                       # Number of times the RAS was used to get a target.
-host_inst_rate                                  15119                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 154868                       # Number of bytes of host memory used
-host_seconds                                     0.73                       # Real time elapsed on the host
-host_tick_rate                                1956796                       # Simulator tick rate (ticks/s)
+host_inst_rate                                   4388                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 179936                       # Number of bytes of host memory used
+host_seconds                                     2.50                       # Real time elapsed on the host
+host_tick_rate                                 568121                       # Simulator tick rate (ticks/s)
 memdepunit.memDep.conflictingLoads                 12                       # Number of conflicting loads.
 memdepunit.memDep.conflictingStores                 0                       # Number of conflicting stores.
 memdepunit.memDep.insertedLoads                  3250                       # Number of loads inserted to the mem dependence unit.
@@ -19,22 +19,22 @@ memdepunit.memDep.insertedStores                 2817                       # Nu
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                       10976                       # Number of instructions simulated
 sim_seconds                                  0.000001                       # Number of seconds simulated
-sim_ticks                                     1421211                       # Number of ticks simulated
+sim_ticks                                     1421207                       # Number of ticks simulated
 system.cpu.commit.COM:branches                   2152                       # Number of branches committed
-system.cpu.commit.COM:bw_lim_events               172                       # number cycles where commit BW limit reached
+system.cpu.commit.COM:bw_lim_events               225                       # number cycles where commit BW limit reached
 system.cpu.commit.COM:bw_limited                    0                       # number of insts not committed due to BW limits
 system.cpu.commit.COM:committed_per_cycle.start_dist                     # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle.samples       221349                      
+system.cpu.commit.COM:committed_per_cycle.samples       220766                      
 system.cpu.commit.COM:committed_per_cycle.min_value            0                      
-                               0       215844   9751.30%           
-                               1         2970    134.18%           
-                               2         1290     58.28%           
-                               3          631     28.51%           
-                               4          208      9.40%           
-                               5           90      4.07%           
-                               6          133      6.01%           
+                               0       215368   9755.49%           
+                               1         2915    132.04%           
+                               2         1196     54.18%           
+                               3          673     30.48%           
+                               4          208      9.42%           
+                               5           79      3.58%           
+                               6           91      4.12%           
                                7           11      0.50%           
-                               8          172      7.77%           
+                               8          225     10.19%           
 system.cpu.commit.COM:committed_per_cycle.max_value            8                      
 system.cpu.commit.COM:committed_per_cycle.end_dist
 
@@ -49,65 +49,65 @@ system.cpu.commit.commitNonSpecStalls             327                       # Th
 system.cpu.commit.commitSquashedInsts           14263                       # The number of squashed insts skipped by commit
 system.cpu.committedInsts                       10976                       # Number of Instructions Simulated
 system.cpu.committedInsts_total                 10976                       # Number of Instructions Simulated
-system.cpu.cpi                             129.483509                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                       129.483509                       # CPI: Total CPI of All Threads
-system.cpu.dcache.ReadReq_accesses               2737                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency  6585.044776                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency  6511.939394                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits                   2603                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency         882396                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate          0.048959                       # miss rate for ReadReq accesses
+system.cpu.cpi                             129.483145                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                       129.483145                       # CPI: Total CPI of All Threads
+system.cpu.dcache.ReadReq_accesses               2738                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency  6586.074627                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency  6513.166667                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits                   2604                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency         882534                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate          0.048941                       # miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_misses                  134                       # number of ReadReq misses
 system.cpu.dcache.ReadReq_mshr_hits                68                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_miss_latency       429788                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate     0.024114                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_latency       429869                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate     0.024105                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_misses              66                       # number of ReadReq MSHR misses
 system.cpu.dcache.SwapReq_accesses                  6                       # number of SwapReq accesses(hits+misses)
 system.cpu.dcache.SwapReq_hits                      6                       # number of SwapReq hits
 system.cpu.dcache.WriteReq_accesses              1292                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency  7960.583924                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency  7136.918605                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency  7962.583924                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency  7138.593023                       # average WriteReq mshr miss latency
 system.cpu.dcache.WriteReq_hits                   869                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency       3367327                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency       3368173                       # number of WriteReq miss cycles
 system.cpu.dcache.WriteReq_miss_rate         0.327399                       # miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_misses                 423                       # number of WriteReq misses
 system.cpu.dcache.WriteReq_mshr_hits              337                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_miss_latency       613775                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency       613919                       # number of WriteReq MSHR miss cycles
 system.cpu.dcache.WriteReq_mshr_miss_rate     0.066563                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_misses             86                       # number of WriteReq MSHR misses
 system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs                  22.881579                       # Average number of references to valid blocks.
+system.cpu.dcache.avg_refs                  22.888158                       # Average number of references to valid blocks.
 system.cpu.dcache.blocked_no_mshrs                  0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_no_targets                0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles_no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.demand_accesses                4029                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency  7629.664273                       # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency  6865.546053                       # average overall mshr miss latency
-system.cpu.dcache.demand_hits                    3472                       # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency         4249723                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate           0.138248                       # miss rate for demand accesses
+system.cpu.dcache.demand_accesses                4030                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency  7631.430880                       # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency  6867.026316                       # average overall mshr miss latency
+system.cpu.dcache.demand_hits                    3473                       # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency         4250707                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate           0.138213                       # miss rate for demand accesses
 system.cpu.dcache.demand_misses                   557                       # number of demand (read+write) misses
 system.cpu.dcache.demand_mshr_hits                405                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency      1043563                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate      0.037726                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_latency      1043788                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate      0.037717                       # mshr miss rate for demand accesses
 system.cpu.dcache.demand_mshr_misses              152                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.overall_accesses               4029                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency  7629.664273                       # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency  6865.546053                       # average overall mshr miss latency
+system.cpu.dcache.overall_accesses               4030                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency  7631.430880                       # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency  6867.026316                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits                   3472                       # number of overall hits
-system.cpu.dcache.overall_miss_latency        4249723                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate          0.138248                       # miss rate for overall accesses
+system.cpu.dcache.overall_hits                   3473                       # number of overall hits
+system.cpu.dcache.overall_miss_latency        4250707                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate          0.138213                       # miss rate for overall accesses
 system.cpu.dcache.overall_misses                  557                       # number of overall misses
 system.cpu.dcache.overall_mshr_hits               405                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency      1043563                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate     0.037726                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_latency      1043788                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate     0.037717                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_misses             152                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
@@ -123,50 +123,50 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss            0
 system.cpu.dcache.replacements                      0                       # number of replacements
 system.cpu.dcache.sampled_refs                    152                       # Sample count of references to valid blocks.
 system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse                 90.938737                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                     3478                       # Total number of references to valid blocks.
+system.cpu.dcache.tagsinuse                 90.938565                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                     3479                       # Total number of references to valid blocks.
 system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
 system.cpu.dcache.writebacks                        0                       # number of writebacks
-system.cpu.decode.DECODE:BlockedCycles         192719                       # Number of cycles decode is blocked
-system.cpu.decode.DECODE:DecodedInsts           39774                       # Number of instructions handled by decode
-system.cpu.decode.DECODE:IdleCycles             20128                       # Number of cycles decode is idle
-system.cpu.decode.DECODE:RunCycles               8238                       # Number of cycles decode is running
+system.cpu.decode.DECODE:BlockedCycles         192302                       # Number of cycles decode is blocked
+system.cpu.decode.DECODE:DecodedInsts           39763                       # Number of instructions handled by decode
+system.cpu.decode.DECODE:IdleCycles             19973                       # Number of cycles decode is idle
+system.cpu.decode.DECODE:RunCycles               8441                       # Number of cycles decode is running
 system.cpu.decode.DECODE:SquashCycles            3162                       # Number of cycles decode is squashing
-system.cpu.decode.DECODE:UnblockCycles            264                       # Number of cycles decode is unblocking
-system.cpu.fetch.Branches                        7846                       # Number of branches that fetch encountered
+system.cpu.decode.DECODE:UnblockCycles             50                       # Number of cycles decode is unblocking
+system.cpu.fetch.Branches                        7877                       # Number of branches that fetch encountered
 system.cpu.fetch.CacheLines                      5085                       # Number of cache lines fetched
-system.cpu.fetch.Cycles                         14399                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.Cycles                         14430                       # Number of cycles fetch has run and was not squashing or blocked
 system.cpu.fetch.IcacheSquashes                   745                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.Insts                          43304                       # Number of instructions fetch has processed
+system.cpu.fetch.Insts                          43366                       # Number of instructions fetch has processed
 system.cpu.fetch.SquashCycles                    2134                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.branchRate                  0.034947                       # Number of branch fetches per cycle
+system.cpu.fetch.branchRate                  0.035176                       # Number of branch fetches per cycle
 system.cpu.fetch.icacheStallCycles               5085                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.predictedBranches               2990                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.rate                        0.192881                       # Number of inst fetches per cycle
+system.cpu.fetch.predictedBranches               3021                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.rate                        0.193660                       # Number of inst fetches per cycle
 system.cpu.fetch.rateDist.start_dist                           # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist.samples              224511                      
+system.cpu.fetch.rateDist.samples              223928                      
 system.cpu.fetch.rateDist.min_value                 0                      
-                               0       215198   9585.19%           
-                               1         2258    100.57%           
-                               2          627     27.93%           
-                               3          958     42.67%           
-                               4          553     24.63%           
-                               5          816     36.35%           
-                               6          951     42.36%           
-                               7          280     12.47%           
-                               8         2870    127.83%           
+                               0       214584   9582.72%           
+                               1         2258    100.84%           
+                               2          658     29.38%           
+                               3          958     42.78%           
+                               4          553     24.70%           
+                               5          816     36.44%           
+                               6          951     42.47%           
+                               7          280     12.50%           
+                               8         2870    128.17%           
 system.cpu.fetch.rateDist.max_value                 8                      
 system.cpu.fetch.rateDist.end_dist
 
 system.cpu.icache.ReadReq_accesses               5085                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency  5148.266776                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency  4502.972752                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_miss_latency  5150.152209                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency  4503.673025                       # average ReadReq mshr miss latency
 system.cpu.icache.ReadReq_hits                   4474                       # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency        3145591                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency        3146743                       # number of ReadReq miss cycles
 system.cpu.icache.ReadReq_miss_rate          0.120157                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_misses                  611                       # number of ReadReq misses
 system.cpu.icache.ReadReq_mshr_hits               244                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_miss_latency      1652591                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency      1652848                       # number of ReadReq MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate     0.072173                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_misses             367                       # number of ReadReq MSHR misses
 system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
@@ -178,29 +178,29 @@ system.cpu.icache.blocked_cycles_no_mshrs            0                       # n
 system.cpu.icache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.demand_accesses                5085                       # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency  5148.266776                       # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency  4502.972752                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_miss_latency  5150.152209                       # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency  4503.673025                       # average overall mshr miss latency
 system.cpu.icache.demand_hits                    4474                       # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency         3145591                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency         3146743                       # number of demand (read+write) miss cycles
 system.cpu.icache.demand_miss_rate           0.120157                       # miss rate for demand accesses
 system.cpu.icache.demand_misses                   611                       # number of demand (read+write) misses
 system.cpu.icache.demand_mshr_hits                244                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency      1652591                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency      1652848                       # number of demand (read+write) MSHR miss cycles
 system.cpu.icache.demand_mshr_miss_rate      0.072173                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_misses              367                       # number of demand (read+write) MSHR misses
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.overall_accesses               5085                       # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency  5148.266776                       # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency  4502.972752                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_miss_latency  5150.152209                       # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency  4503.673025                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
 system.cpu.icache.overall_hits                   4474                       # number of overall hits
-system.cpu.icache.overall_miss_latency        3145591                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency        3146743                       # number of overall miss cycles
 system.cpu.icache.overall_miss_rate          0.120157                       # miss rate for overall accesses
 system.cpu.icache.overall_misses                  611                       # number of overall misses
 system.cpu.icache.overall_mshr_hits               244                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency      1652591                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency      1652848                       # number of overall MSHR miss cycles
 system.cpu.icache.overall_mshr_miss_rate     0.072173                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_misses             367                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
@@ -217,35 +217,35 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss            0
 system.cpu.icache.replacements                      1                       # number of replacements
 system.cpu.icache.sampled_refs                    363                       # Sample count of references to valid blocks.
 system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse                172.869174                       # Cycle average of tags in use
+system.cpu.icache.tagsinuse                172.868641                       # Cycle average of tags in use
 system.cpu.icache.total_refs                     4474                       # Total number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
 system.cpu.icache.writebacks                        0                       # number of writebacks
-system.cpu.idleCycles                         1196701                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.iew.EXEC:branches                     3576                       # Number of branches executed
+system.cpu.idleCycles                         1197280                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.iew.EXEC:branches                     3577                       # Number of branches executed
 system.cpu.iew.EXEC:nop                             0                       # number of nop insts executed
-system.cpu.iew.EXEC:rate                     0.092548                       # Inst execution rate
-system.cpu.iew.EXEC:refs                         5257                       # number of memory reference insts executed
+system.cpu.iew.EXEC:rate                     0.092802                       # Inst execution rate
+system.cpu.iew.EXEC:refs                         5258                       # number of memory reference insts executed
 system.cpu.iew.EXEC:stores                       2386                       # Number of stores executed
 system.cpu.iew.EXEC:swp                             0                       # number of swp insts executed
 system.cpu.iew.WB:consumers                      9737                       # num instructions consuming a value
-system.cpu.iew.WB:count                         19769                       # cumulative count of insts written-back
+system.cpu.iew.WB:count                         19771                       # cumulative count of insts written-back
 system.cpu.iew.WB:fanout                     0.790901                       # average fanout of values written-back
 system.cpu.iew.WB:penalized                         0                       # number of instrctions required to write to 'other' IQ
 system.cpu.iew.WB:penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
 system.cpu.iew.WB:producers                      7701                       # num instructions producing a value
-system.cpu.iew.WB:rate                       0.088054                       # insts written-back per cycle
-system.cpu.iew.WB:sent                          20061                       # cumulative count of insts sent to commit
-system.cpu.iew.branchMispredicts                 2593                       # Number of branch mispredicts detected at execute
+system.cpu.iew.WB:rate                       0.088292                       # insts written-back per cycle
+system.cpu.iew.WB:sent                          20063                       # cumulative count of insts sent to commit
+system.cpu.iew.branchMispredicts                 2594                       # Number of branch mispredicts detected at execute
 system.cpu.iew.iewBlockCycles                     476                       # Number of cycles IEW is blocking
 system.cpu.iew.iewDispLoadInsts                  3250                       # Number of dispatched load instructions
 system.cpu.iew.iewDispNonSpecInsts                617                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewDispSquashedInsts              2705                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispSquashedInsts              2694                       # Number of squashed instructions skipped by dispatch
 system.cpu.iew.iewDispStoreInsts                 2817                       # Number of dispatched store instructions
 system.cpu.iew.iewDispatchedInsts               25240                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewExecLoadInsts                  2871                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts              1780                       # Number of squashed instructions skipped in execute
-system.cpu.iew.iewExecutedInsts                 20778                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts                  2872                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts              1777                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewExecutedInsts                 20781                       # Number of executed instructions
 system.cpu.iew.iewIQFullEvents                      7                       # Number of times the IQ has become full, causing a stall
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
 system.cpu.iew.iewLSQFullEvents                     0                       # Number of times the LSQ has become full, causing a stall
@@ -262,7 +262,7 @@ system.cpu.iew.lsq.thread.0.rescheduledLoads            0
 system.cpu.iew.lsq.thread.0.squashedLoads         1788                       # Number of loads squashed
 system.cpu.iew.lsq.thread.0.squashedStores         1519                       # Number of stores squashed
 system.cpu.iew.memOrderViolationEvents             54                       # Number of memory order violations
-system.cpu.iew.predictedNotTakenIncorrect          962                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect          963                       # Number of branches that were predicted not taken incorrectly
 system.cpu.iew.predictedTakenIncorrect           1631                       # Number of branches that were predicted taken incorrectly
 system.cpu.ipc                               0.007723                       # IPC: Instructions Per Cycle
 system.cpu.ipc_total                         0.007723                       # IPC: Total IPC of All Threads
@@ -302,21 +302,21 @@ system.cpu.iq.ISSUE:fu_full.start_dist
                     InstPrefetch            0      0.00%            # attempts to use FU when none available
 system.cpu.iq.ISSUE:fu_full.end_dist
 system.cpu.iq.ISSUE:issued_per_cycle.start_dist                     # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle.samples       224511                      
+system.cpu.iq.ISSUE:issued_per_cycle.samples       223928                      
 system.cpu.iq.ISSUE:issued_per_cycle.min_value            0                      
-                               0       215315   9590.40%           
-                               1         4124    183.69%           
-                               2         1297     57.77%           
-                               3         1306     58.17%           
-                               4         1190     53.00%           
-                               5          707     31.49%           
-                               6          433     19.29%           
-                               7           83      3.70%           
-                               8           56      2.49%           
+                               0       214838   9594.07%           
+                               1         3976    177.56%           
+                               2         1244     55.55%           
+                               3         1359     60.69%           
+                               4         1316     58.77%           
+                               5          612     27.33%           
+                               6          444     19.83%           
+                               7           83      3.71%           
+                               8           56      2.50%           
 system.cpu.iq.ISSUE:issued_per_cycle.max_value            8                      
 system.cpu.iq.ISSUE:issued_per_cycle.end_dist
 
-system.cpu.iq.ISSUE:rate                     0.100476                       # Inst issue rate
+system.cpu.iq.ISSUE:rate                     0.100738                       # Inst issue rate
 system.cpu.iq.iqInstsAdded                      24623                       # Number of instructions added to the IQ (excludes non-spec)
 system.cpu.iq.iqInstsIssued                     22558                       # Number of instructions issued
 system.cpu.iq.iqNonSpecInstsAdded                 617                       # Number of non-speculative instructions added to the IQ
@@ -325,12 +325,12 @@ system.cpu.iq.iqSquashedInstsIssued               174                       # Nu
 system.cpu.iq.iqSquashedNonSpecRemoved            290                       # Number of squashed non-spec instructions that were removed
 system.cpu.iq.iqSquashedOperandsExamined         5834                       # Number of squashed operands that are examined and possibly removed from graph
 system.cpu.l2cache.ReadReq_accesses               513                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency  4754.779727                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency  2343.506823                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_miss_latency       2439202                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_avg_miss_latency  4755.715400                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency  2343.752437                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_miss_latency       2439682                       # number of ReadReq miss cycles
 system.cpu.l2cache.ReadReq_miss_rate                1                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_misses                 513                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency      1202219                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency      1202345                       # number of ReadReq MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_miss_rate            1                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_misses            513                       # number of ReadReq MSHR misses
 system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
@@ -342,29 +342,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs            0                       #
 system.cpu.l2cache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.demand_accesses                513                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency  4754.779727                       # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency  2343.506823                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_miss_latency  4755.715400                       # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency  2343.752437                       # average overall mshr miss latency
 system.cpu.l2cache.demand_hits                      0                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency        2439202                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency        2439682                       # number of demand (read+write) miss cycles
 system.cpu.l2cache.demand_miss_rate                 1                       # miss rate for demand accesses
 system.cpu.l2cache.demand_misses                  513                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency      1202219                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency      1202345                       # number of demand (read+write) MSHR miss cycles
 system.cpu.l2cache.demand_mshr_miss_rate            1                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_misses             513                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.l2cache.overall_accesses               513                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency  4754.779727                       # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency  2343.506823                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_miss_latency  4755.715400                       # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency  2343.752437                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
 system.cpu.l2cache.overall_hits                     0                       # number of overall hits
-system.cpu.l2cache.overall_miss_latency       2439202                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency       2439682                       # number of overall miss cycles
 system.cpu.l2cache.overall_miss_rate                1                       # miss rate for overall accesses
 system.cpu.l2cache.overall_misses                 513                       # number of overall misses
 system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency      1202219                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency      1202345                       # number of overall MSHR miss cycles
 system.cpu.l2cache.overall_mshr_miss_rate            1                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_misses            513                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
@@ -381,28 +381,27 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss            0
 system.cpu.l2cache.replacements                     0                       # number of replacements
 system.cpu.l2cache.sampled_refs                   512                       # Sample count of references to valid blocks.
 system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse               262.946375                       # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse               262.945674                       # Cycle average of tags in use
 system.cpu.l2cache.total_refs                       0                       # Total number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
 system.cpu.l2cache.writebacks                       0                       # number of writebacks
-system.cpu.numCycles                           224511                       # number of cpu cycles simulated
+system.cpu.numCycles                           223928                       # number of cpu cycles simulated
 system.cpu.rename.RENAME:BlockCycles              960                       # Number of cycles rename is blocking
 system.cpu.rename.RENAME:CommittedMaps           9868                       # Number of HB maps that are committed
 system.cpu.rename.RENAME:IQFullEvents               2                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.RENAME:IdleCycles             20098                       # Number of cycles rename is idle
-system.cpu.rename.RENAME:LSQFullEvents            481                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RENAME:IdleCycles             21302                       # Number of cycles rename is idle
+system.cpu.rename.RENAME:LSQFullEvents            411                       # Number of times rename has blocked due to LSQ full
 system.cpu.rename.RENAME:ROBFullEvents              4                       # Number of times rename has blocked due to ROB full
 system.cpu.rename.RENAME:RenameLookups          46931                       # Number of register rename lookups that rename has made
-system.cpu.rename.RENAME:RenamedInsts           31260                       # Number of instructions processed by rename
+system.cpu.rename.RENAME:RenamedInsts           31249                       # Number of instructions processed by rename
 system.cpu.rename.RENAME:RenamedOperands        25831                       # Number of destination operands rename has renamed
-system.cpu.rename.RENAME:RunCycles               7921                       # Number of cycles rename is running
+system.cpu.rename.RENAME:RunCycles               7136                       # Number of cycles rename is running
 system.cpu.rename.RENAME:SquashCycles            3162                       # Number of cycles rename is squashing
-system.cpu.rename.RENAME:SquashedInsts           8042                       # Number of squashed instructions processed by rename
-system.cpu.rename.RENAME:UnblockCycles           1212                       # Number of cycles rename is unblocking
+system.cpu.rename.RENAME:UnblockCycles            614                       # Number of cycles rename is unblocking
 system.cpu.rename.RENAME:UndoneMaps             15963                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.RENAME:serializeStallCycles       190573                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RENAME:serializeStallCycles       190754                       # count of cycles rename stalled for serializing inst
 system.cpu.rename.RENAME:serializingInsts          638                       # count of serializing insts renamed
-system.cpu.rename.RENAME:skidInsts               5594                       # count of insts added to the skid buffer
+system.cpu.rename.RENAME:skidInsts               5529                       # count of insts added to the skid buffer
 system.cpu.rename.RENAME:tempSerializingInsts          629                       # count of temporary serializing insts renamed
 system.cpu.timesIdled                             289                       # Number of times that the entire CPU went into an idle state and unscheduled itself
 system.cpu.workload.PROG:num_syscalls               8                       # Number of system calls
diff --git a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stderr b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stderr
index 48affb0e2..7873672f2 100644
--- a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stderr
+++ b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stderr
@@ -1,4 +1,3 @@
 warn: More than two loadable segments in ELF object.
 warn: Ignoring segment @ 0x0 length 0x0.
-0: system.remote_gdb.listener: listening for remote gdb on port 7003
 warn: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stdout b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stdout
index 6cba2ba7e..38b0c1787 100644
--- a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stdout
+++ b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stdout
@@ -16,9 +16,9 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Apr  9 2007 03:06:26
-M5 started Mon Apr  9 03:06:54 2007
-M5 executing on zizzer.eecs.umich.edu
+M5 compiled Apr 13 2007 13:56:34
+M5 started Fri Apr 13 13:56:35 2007
+M5 executing on ahchoo.blinky.homelinux.org
 command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/o3-timing tests/run.py quick/02.insttest/sparc/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
-Exiting @ tick 1421211 because target called exit()
+Exiting @ tick 1421207 because target called exit()