Switch the endianness of data that's forwarded. This is the same sort of problem that was happening when stores went all the way to memory and back.

--HG--
extra : convert_revision : 09fece7ae934f542e51046d33505df3f7ec0b919

1 files changed, 6 insertions, 0 deletions

diff --git a/src/cpu/o3/lsq_unit.hh b/src/cpu/o3/lsq_unit.hh
index a2e11173e..0318175c3 100644
--- a/src/cpu/o3/lsq_unit.hh
+++ b/src/cpu/o3/lsq_unit.hh
@@ -561,6 +561,12 @@ LSQUnit<Impl>::read(Request *req, T &data, int load_idx)
             // Cast this to type T?
             data = storeQueue[store_idx].data >> shift_amt;
 
+            // When the data comes from the store queue entry, it's in host
+            // order. When it gets sent to the load, it needs to be in guest
+            // order so when the load converts it again, it ends up back
+            // in host order like the inst expects.
+            data = TheISA::htog(data);
+
             assert(!load_inst->memData);
             load_inst->memData = new uint8_t[64];