diff options
author | Lisa Hsu <hsul@eecs.umich.edu> | 2006-10-26 16:04:09 -0400 |
---|---|---|
committer | Lisa Hsu <hsul@eecs.umich.edu> | 2006-10-26 16:04:09 -0400 |
commit | 260b3c0cf074bddb4dff8a126811ea9c4c2d6687 (patch) | |
tree | 62be265f0b57366286f6b23504276e30ee458405 | |
parent | 86bd01dfc99e4bb40b5d7266e12b843285847c7c (diff) | |
download | gem5-260b3c0cf074bddb4dff8a126811ea9c4c2d6687.tar.xz |
se.py:
make the same os.getcwd fix ali made in fs.py, make connectMemPorts occur after caches are created.
configs/example/se.py:
make the same os.getcwd fix ali made in fs.py, make connectMemPorts occur after caches are created.
--HG--
extra : convert_revision : 9760ae073d97cd62d3e44f10199d31cce79d4a1d
-rw-r--r-- | configs/example/se.py | 11 |
1 files changed, 6 insertions, 5 deletions
diff --git a/configs/example/se.py b/configs/example/se.py index 2e63e27da..c4150eed7 100644 --- a/configs/example/se.py +++ b/configs/example/se.py @@ -129,14 +129,15 @@ cpu.cpu_id = 0 system = System(cpu = cpu, physmem = PhysicalMemory(range=AddrRange("512MB")), membus = Bus()) -system.physmem.port = system.membus.port -system.cpu.connectMemPorts(system.membus) -system.cpu.mem = system.physmem -system.cpu.clock = '2GHz' + if options.caches and not options.standard_switch: system.cpu.addPrivateSplitL1Caches(MyCache(size = '32kB'), MyCache(size = '64kB')) +system.physmem.port = system.membus.port +system.cpu.connectMemPorts(system.membus) +system.cpu.mem = system.physmem +system.cpu.clock = '2GHz' root = Root(system = system) if options.timing or options.detailed: @@ -169,7 +170,7 @@ m5.instantiate(root) if options.checkpoint_dir: cptdir = options.checkpoint_dir else: - cptdir = getcwd() + cptdir = os.getcwd() if options.checkpoint_restore: from os.path import isdir |