summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorGabe Black <gblack@eecs.umich.edu>2010-06-02 12:58:08 -0500
committerGabe Black <gblack@eecs.umich.edu>2010-06-02 12:58:08 -0500
commit2c94bf7f30d3e9febe30485cf7182b650f48f4d5 (patch)
tree94bf4b64cd4788baf04566eea744d472639bae1c
parent00320a53ab67e5f7b7a22b67f6b14ade31348c50 (diff)
downloadgem5-2c94bf7f30d3e9febe30485cf7182b650f48f4d5.tar.xz
ARM: Implement the clz instruction.
-rw-r--r--src/arch/arm/isa/insts/misc.isa10
1 files changed, 10 insertions, 0 deletions
diff --git a/src/arch/arm/isa/insts/misc.isa b/src/arch/arm/isa/insts/misc.isa
index 09d27360e..c673372bb 100644
--- a/src/arch/arm/isa/insts/misc.isa
+++ b/src/arch/arm/isa/insts/misc.isa
@@ -174,6 +174,16 @@ let {{
decoder_output += RevOpConstructor.subst(rbitIop)
exec_output += PredOpExecute.subst(rbitIop)
+ clzCode = '''
+ Dest = (Op1 == 0) ? 32 : (31 - findMsbSet(Op1));
+ '''
+ clzIop = InstObjParams("clz", "ClzInst", "RevOp",
+ { "code": clzCode,
+ "predicate_test": predicateTest }, [])
+ header_output += RevOpDeclare.subst(clzIop)
+ decoder_output += RevOpConstructor.subst(clzIop)
+ exec_output += PredOpExecute.subst(clzIop)
+
ssatCode = '''
int32_t operand = shift_rm_imm(Op1, shiftAmt, shiftType, 0);
int32_t res;