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authorGabe Black <gblack@eecs.umich.edu>2007-04-15 21:51:05 +0000
committerGabe Black <gblack@eecs.umich.edu>2007-04-15 21:51:05 +0000
commit308b2f0ce3215eaaed69da937555008f9ed36835 (patch)
tree3ca305dd2307770485a9c782cb070282378d5e90
parentc3081d9c1c36e1a08c173048783d191fa19463de (diff)
downloadgem5-308b2f0ce3215eaaed69da937555008f9ed36835.tar.xz
Add extra constructors to Alpha and MIPS
--HG-- extra : convert_revision : 26ea87bfe9e5c27134eb9a15bf9e4629afae6c69
-rw-r--r--src/cpu/o3/alpha/dyn_inst.hh9
-rw-r--r--src/cpu/o3/alpha/dyn_inst_impl.hh19
-rwxr-xr-xsrc/cpu/o3/mips/dyn_inst.hh10
-rwxr-xr-xsrc/cpu/o3/mips/dyn_inst_impl.hh18
4 files changed, 47 insertions, 9 deletions
diff --git a/src/cpu/o3/alpha/dyn_inst.hh b/src/cpu/o3/alpha/dyn_inst.hh
index 20759d849..a6fb7b885 100644
--- a/src/cpu/o3/alpha/dyn_inst.hh
+++ b/src/cpu/o3/alpha/dyn_inst.hh
@@ -73,8 +73,13 @@ class AlphaDynInst : public BaseDynInst<Impl>
public:
/** BaseDynInst constructor given a binary instruction. */
- AlphaDynInst(ExtMachInst inst, Addr PC, Addr NPC,
- Addr Pred_PC, Addr Pred_NPC,
+ AlphaDynInst(StaticInstPtr staticInst, Addr PC, Addr NPC, Addr microPC,
+ Addr Pred_PC, Addr Pred_NPC, Addr Pred_MicroPC,
+ InstSeqNum seq_num, O3CPU *cpu);
+
+ /** BaseDynInst constructor given a binary instruction. */
+ AlphaDynInst(ExtMachInst inst, Addr PC, Addr NPC, Addr microPC,
+ Addr Pred_PC, Addr Pred_NPC, Addr Pred_MicroPC,
InstSeqNum seq_num, O3CPU *cpu);
/** BaseDynInst constructor given a static inst pointer. */
diff --git a/src/cpu/o3/alpha/dyn_inst_impl.hh b/src/cpu/o3/alpha/dyn_inst_impl.hh
index fdce1ade5..6dfe0ccdd 100644
--- a/src/cpu/o3/alpha/dyn_inst_impl.hh
+++ b/src/cpu/o3/alpha/dyn_inst_impl.hh
@@ -31,10 +31,25 @@
#include "cpu/o3/alpha/dyn_inst.hh"
template <class Impl>
-AlphaDynInst<Impl>::AlphaDynInst(ExtMachInst inst, Addr PC, Addr NPC,
+AlphaDynInst<Impl>::AlphaDynInst(StaticInstPtr staticInst,
+ Addr PC, Addr NPC, Addr microPC,
Addr Pred_PC, Addr Pred_NPC,
+ Addr Pred_MicroPC,
InstSeqNum seq_num, O3CPU *cpu)
- : BaseDynInst<Impl>(inst, PC, NPC, Pred_PC, Pred_NPC, seq_num, cpu)
+ : BaseDynInst<Impl>(staticInst, PC, NPC, microPC,
+ Pred_PC, Pred_NPC, Pred_MicroPC, seq_num, cpu)
+{
+ initVars();
+}
+
+template <class Impl>
+AlphaDynInst<Impl>::AlphaDynInst(ExtMachInst inst,
+ Addr PC, Addr NPC, Addr microPC,
+ Addr Pred_PC, Addr Pred_NPC,
+ Addr Pred_MicroPC,
+ InstSeqNum seq_num, O3CPU *cpu)
+ : BaseDynInst<Impl>(inst, PC, NPC, microPC,
+ Pred_PC, Pred_NPC, Pred_MicroPC, seq_num, cpu)
{
initVars();
}
diff --git a/src/cpu/o3/mips/dyn_inst.hh b/src/cpu/o3/mips/dyn_inst.hh
index 366b4bb23..cf78c0941 100755
--- a/src/cpu/o3/mips/dyn_inst.hh
+++ b/src/cpu/o3/mips/dyn_inst.hh
@@ -70,9 +70,15 @@ class MipsDynInst : public BaseDynInst<Impl>
public:
/** BaseDynInst constructor given a binary instruction. */
+ MipsDynInst(StaticInstPtr staticInst,
+ Addr PC, Addr NPC, Addr microPC,
+ Addr Pred_PC, Addr Pred_NPC, Addr Pred_MicroPC,
+ InstSeqNum seq_num, O3CPU *cpu);
+
+ /** BaseDynInst constructor given a binary instruction. */
MipsDynInst(ExtMachInst inst,
- Addr PC, Addr NPC,
- Addr Pred_PC, Addr Pred_NPC,
+ Addr PC, Addr NPC, Addr microPC,
+ Addr Pred_PC, Addr Pred_NPC, Addr Pred_MicroPC,
InstSeqNum seq_num, O3CPU *cpu);
/** BaseDynInst constructor given a static inst pointer. */
diff --git a/src/cpu/o3/mips/dyn_inst_impl.hh b/src/cpu/o3/mips/dyn_inst_impl.hh
index c0f9ae771..7e8697b32 100755
--- a/src/cpu/o3/mips/dyn_inst_impl.hh
+++ b/src/cpu/o3/mips/dyn_inst_impl.hh
@@ -31,11 +31,23 @@
#include "cpu/o3/mips/dyn_inst.hh"
template <class Impl>
+MipsDynInst<Impl>::MipsDynInst(StaticInstPtr staticInst,
+ Addr PC, Addr NPC, Addr microPC,
+ Addr Pred_PC, Addr Pred_NPC, Addr Pred_MicroPC,
+ InstSeqNum seq_num, O3CPU *cpu)
+ : BaseDynInst<Impl>(staticInst, PC, NPC, microPC,
+ Pred_PC, Pred_NPC, Pred_MicroPC, seq_num, cpu)
+{
+ initVars();
+}
+
+template <class Impl>
MipsDynInst<Impl>::MipsDynInst(ExtMachInst inst,
- Addr PC, Addr NPC,
- Addr Pred_PC, Addr Pred_NPC,
+ Addr PC, Addr NPC, Addr microPC,
+ Addr Pred_PC, Addr Pred_NPC, Addr Pred_MicroPC,
InstSeqNum seq_num, O3CPU *cpu)
- : BaseDynInst<Impl>(inst, PC, NPC, Pred_PC, Pred_NPC, seq_num, cpu)
+ : BaseDynInst<Impl>(inst, PC, NPC, microPC,
+ Pred_PC, Pred_NPC, Pred_MicroPC, seq_num, cpu)
{
initVars();
}