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authorGabe Black <gblack@eecs.umich.edu>2009-08-17 20:15:15 -0700
committerGabe Black <gblack@eecs.umich.edu>2009-08-17 20:15:15 -0700
commit3424de2861756714a85eeafa22b485f6673aaf70 (patch)
treec034a7b2c98a6ab14f5538582806e6d4e2af2522
parentc76459e5a7b5faaa8d64a3c5b461565dafd774fc (diff)
downloadgem5-3424de2861756714a85eeafa22b485f6673aaf70.tar.xz
X86: Implement a media integer multiply microop.
-rw-r--r--src/arch/x86/isa/microops/mediaop.isa39
1 files changed, 39 insertions, 0 deletions
diff --git a/src/arch/x86/isa/microops/mediaop.isa b/src/arch/x86/isa/microops/mediaop.isa
index 08ba14b00..b07b57ce9 100644
--- a/src/arch/x86/isa/microops/mediaop.isa
+++ b/src/arch/x86/isa/microops/mediaop.isa
@@ -870,6 +870,45 @@ let {{
FpDestReg.uqw = result;
'''
+ class Mmuli(MediaOp):
+ code = '''
+ int srcBits = srcSize * 8;
+ int destBits = destSize * 8;
+ assert(destBits <= 64);
+ assert(destSize >= srcSize);
+ int items = (ext & 0x1) ? 1: (sizeof(FloatRegBits) / destSize);
+ uint64_t result = FpDestReg.uqw;
+
+ for (int i = 0; i < items; i++) {
+ int srcHiIndex = (i + 1) * srcBits - 1;
+ int srcLoIndex = (i + 0) * srcBits;
+ uint64_t arg1Bits = bits(FpSrcReg1.uqw, srcHiIndex, srcLoIndex);
+ uint64_t arg2Bits = bits(FpSrcReg2.uqw, srcHiIndex, srcLoIndex);
+ uint64_t resBits;
+
+ if (ext & 0x2) {
+ int64_t arg1 = arg1Bits |
+ (0 - (arg1Bits & (1 << (srcBits - 1))));
+ int64_t arg2 = arg2Bits |
+ (0 - (arg2Bits & (1 << (srcBits - 1))));
+ resBits = (uint64_t)(arg1 * arg2);
+ } else {
+ resBits = arg1Bits * arg2Bits;
+ }
+
+ if (ext & 0x4)
+ resBits += (1 << (destBits - 1));
+
+ if (ext & 0x8)
+ resBits >>= destBits;
+
+ int destHiIndex = (i + 1) * destBits - 1;
+ int destLoIndex = (i + 0) * destBits;
+ result = insertBits(result, destHiIndex, destLoIndex, resBits);
+ }
+ FpDestReg.uqw = result;
+ '''
+
class Cvti2f(MediaOp):
def __init__(self, dest, src, \
size = None, destSize = None, srcSize = None, ext = None):