add annotation code to m5

configs/common/Benchmarks.py:
    add annotate test app
src/SConscript:
    add annotate.cc to lis
src/arch/alpha/isa/decoder.isa:
    add annotate instructions
src/base/traceflags.py:
    Add annotate trace flag
src/sim/pseudo_inst.cc:
src/sim/pseudo_inst.hh:
    add annotate pseudo ops
util/m5/m5op.S:
util/m5/m5op.h:
    add anotate ops

--HG--
extra : convert_revision : 7f965c0d84e41ce34f2ec8ec27a009276d67d8d6

11 files changed, 247 insertions, 1 deletions

diff --git a/configs/boot/bn-app.rcS b/configs/boot/bn-app.rcS
new file mode 100644
index 000000000..6fe2800f4
--- /dev/null
+++ b/configs/boot/bn-app.rcS
@@ -0,0 +1,3 @@
+cd /benchmarks/bn
+./bottleneck-app
+m5 exit
diff --git a/configs/common/Benchmarks.py b/configs/common/Benchmarks.py
index 2993efa3f..bb1ac1ab5 100644
--- a/configs/common/Benchmarks.py
+++ b/configs/common/Benchmarks.py
@@ -98,6 +98,9 @@ Benchmarks['ValStream']         = [Machine('micro_stream.rcS', '512MB')]
 Benchmarks['ValStreamScale']	= [Machine('micro_streamscale.rcS', '512MB')]
 Benchmarks['ValStreamCopy']	= [Machine('micro_streamcopy.rcS', '512MB')]
 
+
+Benchmarks['bnAn']              = [Machine('/z/saidi/work/m5.newmem.head/configs/boot/bn-app.rcS', '128MB', '/z/saidi/work/bottleneck/bnimg.img')]
+
 benchs = Benchmarks.keys()
 benchs.sort()
 DefinedBenchmarks = ", ".join(benchs)
diff --git a/src/SConscript b/src/SConscript
index 260aca25c..2722444a3 100644
--- a/src/SConscript
+++ b/src/SConscript
@@ -47,6 +47,7 @@ Import('env')
 # Base sources used by all configurations.
 
 base_sources = Split('''
+	base/annotate.cc
 	base/circlebuf.cc
 	base/cprintf.cc
 	base/fast_alloc.cc
diff --git a/src/arch/alpha/isa/decoder.isa b/src/arch/alpha/isa/decoder.isa
index f449d2d69..30959c72e 100644
--- a/src/arch/alpha/isa/decoder.isa
+++ b/src/arch/alpha/isa/decoder.isa
@@ -823,7 +823,12 @@ decode OPCODE default Unknown::unknown() {
             0x54: m5panic({{
                 panic("M5 panic instruction called at pc=%#x.", xc->readPC());
             }}, IsNonSpeculative);
-
+            0x55: m5anBegin({{
+                AlphaPseudo::anBegin(xc->tcBase(), R16);
+            }}, IsNonSpeculative);
+            0x56: m5anWait({{
+                AlphaPseudo::anWait(xc->tcBase(), R16, R17);
+            }}, IsNonSpeculative);
         }
     }
 #endif
diff --git a/src/base/annotate.cc b/src/base/annotate.cc
new file mode 100644
index 000000000..ba2fb1788
--- /dev/null
+++ b/src/base/annotate.cc
@@ -0,0 +1,122 @@
+/*
+ * Copyright (c) 2006 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Ali Saidi
+ */
+
+#include "base/annotate.hh"
+#include "base/callback.hh"
+#include "base/output.hh"
+#include "base/trace.hh"
+#include "sim/root.hh"
+#include "sim/sim_exit.hh"
+#include "sim/system.hh"
+
+
+
+class AnnotateDumpCallback : public Callback
+{
+  public:
+    virtual void process();
+};
+
+void
+AnnotateDumpCallback::process()
+{
+    Annotate::annotations.dump();
+}
+
+namespace Annotate {
+
+
+Annotate annotations;
+
+Annotate::Annotate()
+{
+    registerExitCallback(new AnnotateDumpCallback);
+}
+
+void
+Annotate::add(System *sys, Addr stack, uint32_t sm, uint32_t st,
+        uint32_t wm, uint32_t ws)
+{
+    AnnotateData *an;
+
+    an = new AnnotateData;
+    an->time = curTick;
+
+    std::map<System*, std::string>::iterator i = nameCache.find(sys);
+    if (i == nameCache.end()) {
+        nameCache[sys] = sys->name();
+    }
+
+    an->system = nameCache[sys];
+    an->stack = stack;
+    an->stateMachine = sm;
+    an->curState = st;
+    an->waitMachine = wm;
+    an->waitState = ws;
+
+    data.push_back(an);
+    if (an->waitMachine)
+        DPRINTF(Annotate, "Annotating: %s(%#llX) %d:%d waiting on %d:%d\n",
+                an->system, an->stack, an->stateMachine, an->curState,
+                an->waitMachine, an->waitState);
+    else
+        DPRINTF(Annotate, "Annotating: %s(%#llX) %d:%d beginning\n", an->system,
+                an->stack, an->stateMachine, an->curState);
+
+    DPRINTF(Annotate, "Now %d events on list\n", data.size());
+
+}
+
+void
+Annotate::dump()
+{
+
+    std::list<AnnotateData*>::iterator i;
+
+    i = data.begin();
+
+    if (i == data.end())
+        return;
+
+    std::ostream *os = simout.create("annotate.dat");
+
+    AnnotateData *an;
+
+    while (i != data.end()) {
+        DPRINTF(Annotate, "Writing\n", data.size());
+        an = *i;
+        ccprintf(*os, "%d %s(%#llX) %d %d %d %d\n", an->time, an->system,
+                an->stack, an->stateMachine, an->curState, an->waitMachine,
+                an->waitState);
+        i++;
+    }
+}
+
+} //namespace Annotate
diff --git a/src/base/annotate.hh b/src/base/annotate.hh
new file mode 100644
index 000000000..36607bf90
--- /dev/null
+++ b/src/base/annotate.hh
@@ -0,0 +1,73 @@
+/*
+ * Copyright (c) 2006 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Ali Saidi
+ */
+
+#ifndef __BASE__ANNOTATE_HH__
+#define __BASE__ANNOTATE_HH__
+
+#include "sim/host.hh"
+
+#include <string>
+#include <list>
+#include <map>
+
+
+class System;
+
+namespace Annotate {
+
+
+class Annotate {
+
+  protected:
+    struct AnnotateData {
+        Tick time;
+        std::string system;
+        Addr stack;
+        uint32_t stateMachine;
+        uint32_t curState;
+        uint32_t waitMachine;
+        uint32_t waitState;
+    };
+
+    std::list<AnnotateData*> data;
+    std::map<System*, std::string> nameCache;
+
+  public:
+   Annotate();
+   void add(System *sys, Addr stack, uint32_t sm, uint32_t st, uint32_t
+           wm, uint32_t ws);
+   void dump();
+};
+
+extern Annotate annotations;
+} //namespace Annotate
+
+#endif //__BASE__ANNOTATE_HH__
+
diff --git a/src/base/traceflags.py b/src/base/traceflags.py
index 27c24107c..8e8153b68 100644
--- a/src/base/traceflags.py
+++ b/src/base/traceflags.py
@@ -50,6 +50,7 @@ ccfilename = sys.argv[1] + '.cc'
 baseFlags = [
     'Activity',
     'AlphaConsole',
+    'Annotate',
     'BADADDR',
     'BE',
     'BPredRAS',
diff --git a/src/sim/pseudo_inst.cc b/src/sim/pseudo_inst.cc
index fcf0b957a..bd26e9dc5 100644
--- a/src/sim/pseudo_inst.cc
+++ b/src/sim/pseudo_inst.cc
@@ -36,6 +36,7 @@
 
 #include "sim/pseudo_inst.hh"
 #include "arch/vtophys.hh"
+#include "base/annotate.hh"
 #include "cpu/base.hh"
 #include "cpu/thread_context.hh"
 #include "cpu/quiesce_event.hh"
@@ -188,6 +189,21 @@ namespace AlphaPseudo
     }
 
     void
+    anBegin(ThreadContext *tc, uint64_t cur)
+    {
+        Annotate::annotations.add(tc->getSystemPtr(), 0, cur >> 32, cur &
+                0xFFFFFFFF, 0,0);
+    }
+
+    void
+    anWait(ThreadContext *tc, uint64_t cur, uint64_t wait)
+    {
+        Annotate::annotations.add(tc->getSystemPtr(), 0, cur >> 32, cur &
+                0xFFFFFFFF, wait >> 32, wait & 0xFFFFFFFF);
+    }
+
+
+    void
     dumpresetstats(ThreadContext *tc, Tick delay, Tick period)
     {
         if (!doStatisticsInsts)
diff --git a/src/sim/pseudo_inst.hh b/src/sim/pseudo_inst.hh
index 4a83b93e0..da2fb4ee3 100644
--- a/src/sim/pseudo_inst.hh
+++ b/src/sim/pseudo_inst.hh
@@ -59,4 +59,6 @@ namespace AlphaPseudo
     void debugbreak(ThreadContext *tc);
     void switchcpu(ThreadContext *tc);
     void addsymbol(ThreadContext *tc, Addr addr, Addr symbolAddr);
+    void anBegin(ThreadContext *tc, uint64_t cur);
+    void anWait(ThreadContext *tc, uint64_t cur, uint64_t wait);
 }
diff --git a/util/m5/m5op.S b/util/m5/m5op.S
index a55532c90..5c0212189 100644
--- a/util/m5/m5op.S
+++ b/util/m5/m5op.S
@@ -50,6 +50,8 @@
 #define switchcpu_func 0x52
 #define addsymbol_func 0x53
 #define panic_func     0x54
+#define anbegin_func     0x55
+#define anwait_func     0x56
 
 #define INST(op, ra, rb, func) \
         .long (((op) << 26) | ((ra) << 21) | ((rb) << 16) | (func))
@@ -84,6 +86,8 @@ func:
 #define SWITCHCPU INST(m5_op, 0, 0, switchcpu_func)
 #define ADDSYMBOL(r1,r2) INST(m5_op, r1, r2, addsymbol_func)
 #define PANIC INST(m5_op, 0, 0, panic_func)
+#define AN_BEGIN(r1) INST(m5_op, r1, 0, anbegin_func)
+#define AN_WAIT(r1,r2) INST(m5_op, r1, r2, anwait_func)
 
         .set noreorder
 
@@ -197,3 +201,17 @@ LEAF(m5_panic)
 END(m5_panic)
 
 
+        .align 4
+LEAF(m5_anbegin)
+        AN_BEGIN(16)
+        RET
+END(m5_anbegin)
+
+
+        .align 4
+LEAF(m5_anwait)
+        AN_WAIT(16,17)
+        RET
+END(m5_anwait)
+
+
diff --git a/util/m5/m5op.h b/util/m5/m5op.h
index f96c5097a..eab4e7fd5 100644
--- a/util/m5/m5op.h
+++ b/util/m5/m5op.h
@@ -53,5 +53,7 @@ void m5_debugbreak(void);
 void m5_switchcpu(void);
 void m5_addsymbol(uint64_t addr, char *symbol);
 void m5_panic(void);
+void m5_anbegin(uint64_t s);
+void m5_anwait(uint64_t s, uint64_t w);
 
 #endif // __M5OP_H__