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authorGabe Black <gblack@eecs.umich.edu>2010-06-02 12:58:06 -0500
committerGabe Black <gblack@eecs.umich.edu>2010-06-02 12:58:06 -0500
commit5495ebd68d10e9472543dcd9c95e8b5a7a58a36b (patch)
tree8a1b97d1ef79d1d52e5fbccc84d7fd262e3c7438
parentfd6e9f304e8529bf2fda6a06fe6d7524c9293433 (diff)
downloadgem5-5495ebd68d10e9472543dcd9c95e8b5a7a58a36b.tar.xz
ARM: Decode the ssub instructions.
-rw-r--r--src/arch/arm/isa/formats/data.isa10
1 files changed, 6 insertions, 4 deletions
diff --git a/src/arch/arm/isa/formats/data.isa b/src/arch/arm/isa/formats/data.isa
index 28fb50194..648e04453 100644
--- a/src/arch/arm/isa/formats/data.isa
+++ b/src/arch/arm/isa/formats/data.isa
@@ -240,11 +240,11 @@ def format ArmParallelAddSubtract() {{
case 0x2:
return new WarnUnimplemented("ssax", machInst);
case 0x3:
- return new WarnUnimplemented("ssub16", machInst);
+ return new Ssub16RegCc(machInst, rd, rn, rm, 0, LSL);
case 0x4:
return new Sadd8RegCc(machInst, rd, rn, rm, 0, LSL);
case 0x7:
- return new WarnUnimplemented("ssub8", machInst);
+ return new Ssub8RegCc(machInst, rd, rn, rm, 0, LSL);
}
break;
case 0x2:
@@ -557,12 +557,14 @@ def format Thumb32DataProcReg() {{
case 0x6:
return new WarnUnimplemented("ssax", machInst);
case 0x5:
- return new WarnUnimplemented("ssub16", machInst);
+ return new Ssub16RegCc(machInst, rd,
+ rn, rm, 0, LSL);
case 0x0:
return new Sadd8RegCc(machInst, rd,
rn, rm, 0, LSL);
case 0x4:
- return new WarnUnimplemented("ssub8", machInst);
+ return new Ssub8RegCc(machInst, rd,
+ rn, rm, 0, LSL);
}
break;
case 0x1: