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| author | Gabe Black <gblack@eecs.umich.edu> | 2007-06-21 20:35:27 +0000 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2007-06-21 20:35:27 +0000 |
| commit | 70d6044527d6e6dfaf2de6674ae412706b6e131c (patch) | |
| tree | f4fc2b74cc2267d85f84db16694107a2bbbf973d | |
| parent | ec24de8b59e174b93b7c42669d71fe61db296688 (diff) | |
| download | gem5-70d6044527d6e6dfaf2de6674ae412706b6e131c.tar.xz | |
Make symbols for regular registers.
--HG--
extra : convert_revision : 28a6df1efe4298877dc2b20179caeb25dfdc4622
| -rw-r--r-- | src/arch/x86/isa/insts/control_transfer/call.py | 4 | ||||
| -rw-r--r-- | src/arch/x86/isa/insts/data_transfer/stack_operations.py | 8 | ||||
| -rw-r--r-- | src/arch/x86/isa/microasm.isa | 3 |
3 files changed, 9 insertions, 6 deletions
diff --git a/src/arch/x86/isa/insts/control_transfer/call.py b/src/arch/x86/isa/insts/control_transfer/call.py index 1372f7dba..530162bfd 100644 --- a/src/arch/x86/isa/insts/control_transfer/call.py +++ b/src/arch/x86/isa/insts/control_transfer/call.py @@ -61,8 +61,8 @@ def macroop CALL_I limm t2, imm rdip t1 - subi "INTREG_RSP", "INTREG_RSP", dsz - st t1, ss, [0, t0, "INTREG_RSP"] + subi rsp, rsp, dsz + st t1, ss, [0, t0, rsp] wrip t1, t2 }; ''' diff --git a/src/arch/x86/isa/insts/data_transfer/stack_operations.py b/src/arch/x86/isa/insts/data_transfer/stack_operations.py index ca2443752..585437b8c 100644 --- a/src/arch/x86/isa/insts/data_transfer/stack_operations.py +++ b/src/arch/x86/isa/insts/data_transfer/stack_operations.py @@ -58,16 +58,16 @@ def macroop POP_R { # Make the default data size of pops 64 bits in 64 bit mode .adjust_env oszIn64Override - ld reg, ss, [0, t0, "INTREG_RSP"] - addi "INTREG_RSP", "INTREG_RSP", dsz + ld reg, ss, [0, t0, rsp] + addi rsp, rsp, dsz }; def macroop PUSH_R { # Make the default data size of pops 64 bits in 64 bit mode .adjust_env oszIn64Override - subi "INTREG_RSP", "INTREG_RSP", dsz - st reg, ss, [0, t0, "INTREG_RSP"] + subi rsp, rsp, dsz + st reg, ss, [0, t0, rsp] }; ''' #let {{ diff --git a/src/arch/x86/isa/microasm.isa b/src/arch/x86/isa/microasm.isa index 4e06f4391..ee2b92f53 100644 --- a/src/arch/x86/isa/microasm.isa +++ b/src/arch/x86/isa/microasm.isa @@ -91,6 +91,9 @@ let {{ "osz" : "env.operandSize", "ssz" : "env.stackSize" } + + for reg in ('ax', 'bx', 'cx', 'dx', 'sp', 'bp', 'si', 'di'): + assembler.symbols["r%s" % reg] = "INTREG_R%s" % reg.upper() assembler.symbols.update(symbols) # Code literal which forces a default 64 bit operand size in 64 bit mode. |