config: Remove redundant explicit setting of default clocks

This patch removes the explicit setting of the clock period for
certain instances of CoherentBus, NonCoherentBus and IOCache where the
specified clock is same as the default value of the system clock. As
all the values used are the defaults, there are no performance
changes. There are similar cases where the toL2Bus is set to use the
parent CPU clock which is already the default behaviour.

The main motivation for these simplifications is to ease the
introduction of clock domains.

9 files changed, 11 insertions, 16 deletions

diff --git a/configs/example/fs.py b/configs/example/fs.py
index 4fedf12db..b17266e54 100644
--- a/configs/example/fs.py
+++ b/configs/example/fs.py
@@ -134,8 +134,8 @@ if is_kvm_cpu(TestCPUClass) or is_kvm_cpu(FutureClass):
     test_sys.vm = KvmVM()
 
 if options.caches or options.l2cache:
-    test_sys.iocache = IOCache(clock = '1GHz',
-                               addr_ranges = test_sys.mem_ranges)
+    # By default the IOCache runs at the system clock
+    test_sys.iocache = IOCache(addr_ranges = test_sys.mem_ranges)
     test_sys.iocache.cpu_side = test_sys.iobus.master
     test_sys.iocache.mem_side = test_sys.membus.slave
 else:
diff --git a/src/cpu/BaseCPU.py b/src/cpu/BaseCPU.py
index f52c6b11f..e7613c5bb 100644
--- a/src/cpu/BaseCPU.py
+++ b/src/cpu/BaseCPU.py
@@ -281,10 +281,10 @@ class BaseCPU(MemObject):
 
     def addTwoLevelCacheHierarchy(self, ic, dc, l2c, iwc = None, dwc = None):
         self.addPrivateSplitL1Caches(ic, dc, iwc, dwc)
-        # Override the default bus clock of 1 GHz and uses the CPU
-        # clock for the L1-to-L2 bus, and also set a width of 32 bytes
-        # (256-bits), which is four times that of the default bus.
-        self.toL2Bus = CoherentBus(clock = Parent.clock, width = 32)
+        # Set a width of 32 bytes (256-bits), which is four times that
+        # of the default bus. The clock of the CPU is inherited by
+        # default.
+        self.toL2Bus = CoherentBus(width = 32)
         self.connectCachedPorts(self.toL2Bus)
         self.l2cache = l2c
         self.toL2Bus.master = self.l2cache.cpu_side
diff --git a/src/dev/CopyEngine.py b/src/dev/CopyEngine.py
index 68332e0a0..d56294d66 100644
--- a/src/dev/CopyEngine.py
+++ b/src/dev/CopyEngine.py
@@ -53,8 +53,6 @@ class CopyEngine(PciDevice):
     ChanCnt = Param.UInt8(4, "Number of DMA channels that exist on device")
     XferCap = Param.MemorySize('4kB', "Number of bits of transfer size that are supported")
 
-    # Override the default clock
-    clock = '500MHz'
     latBeforeBegin = Param.Latency('20ns', "Latency after a DMA command is seen before it's proccessed")
     latAfterCompletion = Param.Latency('20ns', "Latency after a DMA command is complete before it's reported as such")
 
diff --git a/src/dev/arm/RealView.py b/src/dev/arm/RealView.py
index ab994b6f0..5c2768fb9 100644
--- a/src/dev/arm/RealView.py
+++ b/src/dev/arm/RealView.py
@@ -118,8 +118,6 @@ class CpuLocalTimer(BasicPioDevice):
     gic = Param.BaseGic(Parent.any, "Gic to use for interrupting")
     int_num_timer = Param.UInt32("Interrrupt number used per-cpu to GIC")
     int_num_watchdog = Param.UInt32("Interrupt number for per-cpu watchdog to GIC")
-    # Override the default clock
-    clock = '1GHz'
 
 class PL031(AmbaIntDevice):
     type = 'PL031'
diff --git a/src/mem/ruby/system/RubySystem.py b/src/mem/ruby/system/RubySystem.py
index ba261cc36..29e395404 100644
--- a/src/mem/ruby/system/RubySystem.py
+++ b/src/mem/ruby/system/RubySystem.py
@@ -36,7 +36,6 @@ class RubySystem(ClockedObject):
     random_seed = Param.Int(1234, "random seed used by the simulation");
     randomization = Param.Bool(False,
         "insert random delays on message enqueue times");
-    clock = '1GHz'
     block_size_bytes = Param.UInt32(64,
         "default cache block size; must be a power of two");
     mem_size = Param.MemorySize("total memory size of the system");
diff --git a/tests/configs/base_config.py b/tests/configs/base_config.py
index 29aec35e7..60ba31665 100644
--- a/tests/configs/base_config.py
+++ b/tests/configs/base_config.py
@@ -161,8 +161,8 @@ class BaseFSSystem(BaseSystem):
     def init_system(self, system):
         BaseSystem.init_system(self, system)
 
-        #create the iocache
-        system.iocache = IOCache(clock='1GHz', addr_ranges=system.mem_ranges)
+        # create the iocache, which by default runs at the system clock
+        system.iocache = IOCache(addr_ranges=system.mem_ranges)
         system.iocache.cpu_side = system.iobus.master
         system.iocache.mem_side = system.membus.slave
 
diff --git a/tests/configs/memtest.py b/tests/configs/memtest.py
index 55c086d69..379b1e421 100644
--- a/tests/configs/memtest.py
+++ b/tests/configs/memtest.py
@@ -39,7 +39,7 @@ cpus = [ MemTest(clock = '2GHz') for i in xrange(nb_cores) ]
 system = System(cpu = cpus, funcmem = SimpleMemory(in_addr_map = False),
                 funcbus = NoncoherentBus(),
                 physmem = SimpleMemory(),
-                membus = CoherentBus(clock="1GHz", width=16))
+                membus = CoherentBus(width=16))
 
 # l2cache & bus
 system.toL2Bus = CoherentBus(clock="2GHz", width=16)
diff --git a/tests/configs/tgen-simple-dram.py b/tests/configs/tgen-simple-dram.py
index 407852682..b57817c95 100644
--- a/tests/configs/tgen-simple-dram.py
+++ b/tests/configs/tgen-simple-dram.py
@@ -49,7 +49,7 @@ cpu = TrafficGen(config_file = "tests/quick/se/70.tgen/tgen-simple-dram.cfg")
 
 # system simulated
 system = System(cpu = cpu, physmem = DDR3_1600_x64(),
-                membus = NoncoherentBus(clock="1GHz", width = 16))
+                membus = NoncoherentBus(width = 16))
 
 # add a communication monitor
 system.monitor = CommMonitor()
diff --git a/tests/configs/tgen-simple-mem.py b/tests/configs/tgen-simple-mem.py
index d402e557c..200834ec3 100644
--- a/tests/configs/tgen-simple-mem.py
+++ b/tests/configs/tgen-simple-mem.py
@@ -49,7 +49,7 @@ cpu = TrafficGen(config_file = "tests/quick/se/70.tgen/tgen-simple-mem.cfg")
 
 # system simulated
 system = System(cpu = cpu, physmem = SimpleMemory(),
-                membus = NoncoherentBus(clock="1GHz", width = 16))
+                membus = NoncoherentBus(width = 16))
 
 # add a communication monitor, and also trace all the packets
 system.monitor = CommMonitor(trace_file = "monitor.ptrc.gz")