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authorAli Saidi <saidi@eecs.umich.edu>2007-10-18 13:15:08 -0400
committerAli Saidi <saidi@eecs.umich.edu>2007-10-18 13:15:08 -0400
commit8351660273980196269ae14165ae7158c6ffc392 (patch)
treeb77809945e04e5a23abb3bf676eff20437345216
parent6010f350a48c9d8f049fd82d27c188ed1ebe77ed (diff)
downloadgem5-8351660273980196269ae14165ae7158c6ffc392.tar.xz
CPU: Use the ThreadContext cpu id instead of the params cpu id in all cases.
--HG-- extra : convert_revision : 6d025764682181b1f67df3b1d8d1d59099136df7
-rw-r--r--src/cpu/simple/atomic.cc8
-rw-r--r--src/cpu/simple/base.cc2
-rw-r--r--src/cpu/simple/base.hh4
-rw-r--r--src/cpu/simple/timing.cc11
-rw-r--r--src/cpu/simple/timing.hh1
5 files changed, 17 insertions, 9 deletions
diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc
index 525bcbd22..9f574e8be 100644
--- a/src/cpu/simple/atomic.cc
+++ b/src/cpu/simple/atomic.cc
@@ -159,9 +159,9 @@ AtomicSimpleCPU::AtomicSimpleCPU(Params *p)
icachePort.snoopRangeSent = false;
dcachePort.snoopRangeSent = false;
- ifetch_req.setThreadContext(p->cpu_id, 0); // Add thread ID if we add MT
- data_read_req.setThreadContext(p->cpu_id, 0); // Add thread ID here too
- data_write_req.setThreadContext(p->cpu_id, 0); // Add thread ID here too
+ ifetch_req.setThreadContext(cpuId, 0); // Add thread ID if we add MT
+ data_read_req.setThreadContext(cpuId, 0); // Add thread ID here too
+ data_write_req.setThreadContext(cpuId, 0); // Add thread ID here too
}
@@ -237,6 +237,8 @@ AtomicSimpleCPU::takeOverFrom(BaseCPU *oldCPU)
if (_status != Running) {
_status = Idle;
}
+ assert(threadContexts.size() == 1);
+ cpuId = tc->readCpuId();
}
diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc
index 68c6e12ea..1611a7275 100644
--- a/src/cpu/simple/base.cc
+++ b/src/cpu/simple/base.cc
@@ -91,6 +91,8 @@ BaseSimpleCPU::BaseSimpleCPU(Params *p)
threadContexts.push_back(tc);
+ cpuId = tc->readCpuId();
+
fetchOffset = 0;
stayAtPC = false;
}
diff --git a/src/cpu/simple/base.hh b/src/cpu/simple/base.hh
index 2bc329b68..337ef5285 100644
--- a/src/cpu/simple/base.hh
+++ b/src/cpu/simple/base.hh
@@ -117,6 +117,10 @@ class BaseSimpleCPU : public BaseCPU
* objects to modify this thread's state.
*/
ThreadContext *tc;
+ protected:
+ int cpuId;
+
+ public:
#if FULL_SYSTEM
Addr dbg_vtophys(Addr addr);
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index 30100e6c9..f1e51ac70 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -104,8 +104,7 @@ TimingSimpleCPU::CpuPort::TickEvent::schedule(PacketPtr _pkt, Tick t)
}
TimingSimpleCPU::TimingSimpleCPU(Params *p)
- : BaseSimpleCPU(p), icachePort(this, p->clock), dcachePort(this, p->clock),
- cpu_id(p->cpu_id)
+ : BaseSimpleCPU(p), icachePort(this, p->clock), dcachePort(this, p->clock)
{
_status = Idle;
@@ -207,6 +206,8 @@ TimingSimpleCPU::takeOverFrom(BaseCPU *oldCPU)
if (_status != Running) {
_status = Idle;
}
+ assert(threadContexts.size() == 1);
+ cpuId = tc->readCpuId();
previousTick = curTick;
}
@@ -249,7 +250,7 @@ TimingSimpleCPU::read(Addr addr, T &data, unsigned flags)
{
Request *req =
new Request(/* asid */ 0, addr, sizeof(T), flags, thread->readPC(),
- cpu_id, /* thread ID */ 0);
+ cpuId, /* thread ID */ 0);
if (traceData) {
traceData->setAddr(req->getVaddr());
@@ -349,7 +350,7 @@ TimingSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
{
Request *req =
new Request(/* asid */ 0, addr, sizeof(T), flags, thread->readPC(),
- cpu_id, /* thread ID */ 0);
+ cpuId, /* thread ID */ 0);
if (traceData) {
traceData->setAddr(req->getVaddr());
@@ -474,7 +475,7 @@ TimingSimpleCPU::fetch()
checkForInterrupts();
Request *ifetch_req = new Request();
- ifetch_req->setThreadContext(cpu_id, /* thread ID */ 0);
+ ifetch_req->setThreadContext(cpuId, /* thread ID */ 0);
Fault fault = setupFetchRequest(ifetch_req);
ifetch_pkt = new Packet(ifetch_req, MemCmd::ReadReq, Packet::Broadcast);
diff --git a/src/cpu/simple/timing.hh b/src/cpu/simple/timing.hh
index 4a4c276fd..668b6ddaf 100644
--- a/src/cpu/simple/timing.hh
+++ b/src/cpu/simple/timing.hh
@@ -168,7 +168,6 @@ class TimingSimpleCPU : public BaseSimpleCPU
PacketPtr ifetch_pkt;
PacketPtr dcache_pkt;
- int cpu_id;
Tick previousTick;
public: