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| author | Wade Walker <wade.walker@arm.com> | 2011-07-15 11:53:34 -0500 |
|---|---|---|
| committer | Wade Walker <wade.walker@arm.com> | 2011-07-15 11:53:34 -0500 |
| commit | 8870a5820a458ca22cbd4bec60f223a4fe4949e6 (patch) | |
| tree | d0407f485a0bd6c861dd09f86e5a494dc26ed04d | |
| parent | e6672d1f291e415c6d7e0453dabe8c8b7eb5ddc1 (diff) | |
| download | gem5-8870a5820a458ca22cbd4bec60f223a4fe4949e6.tar.xz | |
ARM: Fix SWP/SWPB undefined instruction behavior
SWP and SWPB now throw an undefined instruction exception if
SCTLR.SW == 0. This also required the MIDR to be changed
slightly so programs can correctly determine that gem5 supports
the ARM v7 behavior of SWP/SWPB (in ARM v6, SWP/SWPB were
deprecated, but not disabled at CPU startup).
| -rw-r--r-- | src/arch/arm/ArmSystem.py | 4 | ||||
| -rw-r--r-- | src/arch/arm/isa/insts/swap.isa | 14 |
2 files changed, 14 insertions, 4 deletions
diff --git a/src/arch/arm/ArmSystem.py b/src/arch/arm/ArmSystem.py index 16cb2e549..9bd11041a 100644 --- a/src/arch/arm/ArmSystem.py +++ b/src/arch/arm/ArmSystem.py @@ -49,9 +49,9 @@ class ArmSystem(System): # 0x35 Implementor is '5' from "M5" # 0x0 Variant # 0xf Architecture from CPUID scheme - # 0xf00 Primary part number + # 0xc00 Primary part number ("c" or higher implies ARM v7) # 0x0 Revision - midr_regval = Param.UInt32(0x350ff000, "MIDR value") + midr_regval = Param.UInt32(0x350fc000, "MIDR value") boot_loader = Param.String("", "File that contains the boot loader code if any") boot_loader_mem = Param.PhysicalMemory(NULL, "Memory object that boot loader is to be loaded into") diff --git a/src/arch/arm/isa/insts/swap.isa b/src/arch/arm/isa/insts/swap.isa index 6a6ac837c..3be4278fa 100644 --- a/src/arch/arm/isa/insts/swap.isa +++ b/src/arch/arm/isa/insts/swap.isa @@ -71,8 +71,18 @@ let {{ decoder_output += newDecoder exec_output += newExec + swpPreAccCode = ''' + if (!((SCTLR)Sctlr).sw) { +#if FULL_SYSTEM + return new UndefinedInstruction; +#else + return new UndefinedInstruction(false, mnemonic); +#endif + } + ''' + SwapInst('swp', 'Swp', 'EA = Base;', - 'Mem = cSwap(Op1.uw, ((CPSR)Cpsr).e);', + swpPreAccCode + 'Mem = cSwap(Op1.uw, ((CPSR)Cpsr).e);', 'Dest = cSwap((uint32_t)memData, ((CPSR)Cpsr).e);', ['Request::MEM_SWAP', 'ArmISA::TLB::AlignWord', @@ -80,7 +90,7 @@ let {{ ['IsStoreConditional']).emit() SwapInst('swpb', 'Swpb', 'EA = Base;', - 'Mem.ub = cSwap(Op1.ub, ((CPSR)Cpsr).e);', + swpPreAccCode + 'Mem.ub = cSwap(Op1.ub, ((CPSR)Cpsr).e);', 'Dest.ub = cSwap((uint8_t)memData, ((CPSR)Cpsr).e);', ['Request::MEM_SWAP', 'ArmISA::TLB::AlignByte', |