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authorGabe Black <gblack@eecs.umich.edu>2010-06-02 12:58:12 -0500
committerGabe Black <gblack@eecs.umich.edu>2010-06-02 12:58:12 -0500
commitabda50173cee3c8a9fc080e07040c042b57cb4aa (patch)
tree3224f84d261c67680179ecb885566a03bef97505
parent6365d29c21d474ddca551eb66b162e39e035f42c (diff)
downloadgem5-abda50173cee3c8a9fc080e07040c042b57cb4aa.tar.xz
ARM: Add fp operands to operands.isa.
-rw-r--r--src/arch/arm/isa/operands.isa20
1 files changed, 20 insertions, 0 deletions
diff --git a/src/arch/arm/isa/operands.isa b/src/arch/arm/isa/operands.isa
index d99211b89..53a0e78f9 100644
--- a/src/arch/arm/isa/operands.isa
+++ b/src/arch/arm/isa/operands.isa
@@ -91,10 +91,20 @@ def operands {{
#Abstracted integer reg operands
'Dest': ('IntReg', 'uw', 'dest', 'IsInteger', 2,
maybePCRead, maybePCWrite),
+ 'FpDest': ('FloatReg', 'sf', '(dest + 0)', 'IsFloating', 2),
+ 'FpDestP0': ('FloatReg', 'sf', '(dest + 0)', 'IsFloating', 2),
+ 'FpDestP1': ('FloatReg', 'sf', '(dest + 1)', 'IsFloating', 2),
+ 'FpDestP2': ('FloatReg', 'sf', '(dest + 2)', 'IsFloating', 2),
+ 'FpDestP3': ('FloatReg', 'sf', '(dest + 3)', 'IsFloating', 2),
'Result': ('IntReg', 'uw', 'result', 'IsInteger', 2,
maybePCRead, maybePCWrite),
'Dest2': ('IntReg', 'uw', 'dest2', 'IsInteger', 2,
maybePCRead, maybePCWrite),
+ 'FpDest2': ('FloatReg', 'sf', '(dest2 + 0)', 'IsFloating', 2),
+ 'FpDest2P0': ('FloatReg', 'sf', '(dest2 + 0)', 'IsFloating', 2),
+ 'FpDest2P1': ('FloatReg', 'sf', '(dest2 + 1)', 'IsFloating', 2),
+ 'FpDest2P2': ('FloatReg', 'sf', '(dest2 + 2)', 'IsFloating', 2),
+ 'FpDest2P3': ('FloatReg', 'sf', '(dest2 + 3)', 'IsFloating', 2),
'IWDest': ('IntReg', 'uw', 'dest', 'IsInteger', 2,
maybePCRead, maybeIWPCWrite),
'AIWDest': ('IntReg', 'uw', 'dest', 'IsInteger', 2,
@@ -109,9 +119,19 @@ def operands {{
maybePCRead, maybePCWrite),
'Op1': ('IntReg', 'uw', 'op1', 'IsInteger', 2,
maybePCRead, maybePCWrite),
+ 'FpOp1': ('FloatReg', 'sf', '(op1 + 0)', 'IsFloating', 2),
+ 'FpOp1P0': ('FloatReg', 'sf', '(op1 + 0)', 'IsFloating', 2),
+ 'FpOp1P1': ('FloatReg', 'sf', '(op1 + 1)', 'IsFloating', 2),
+ 'FpOp1P2': ('FloatReg', 'sf', '(op1 + 2)', 'IsFloating', 2),
+ 'FpOp1P3': ('FloatReg', 'sf', '(op1 + 3)', 'IsFloating', 2),
'MiscOp1': ('ControlReg', 'uw', 'op1', (None, None, 'IsControl'), 2),
'Op2': ('IntReg', 'uw', 'op2', 'IsInteger', 2,
maybePCRead, maybePCWrite),
+ 'FpOp2': ('FloatReg', 'sf', '(op2 + 0)', 'IsFloating', 2),
+ 'FpOp2P0': ('FloatReg', 'sf', '(op2 + 0)', 'IsFloating', 2),
+ 'FpOp2P1': ('FloatReg', 'sf', '(op2 + 1)', 'IsFloating', 2),
+ 'FpOp2P2': ('FloatReg', 'sf', '(op2 + 2)', 'IsFloating', 2),
+ 'FpOp2P3': ('FloatReg', 'sf', '(op2 + 3)', 'IsFloating', 2),
'Op3': ('IntReg', 'uw', 'op3', 'IsInteger', 2,
maybePCRead, maybePCWrite),
'Shift': ('IntReg', 'uw', 'shift', 'IsInteger', 2,