Merge ktlim@zamp:/z/ktlim2/clean/newmem-merge

into  zamp.eecs.umich.edu:/z/ktlim2/clean/newmem

--HG--
extra : convert_revision : 20e45bec8c3911a6389a89e2d193aa1de867c89e

14 files changed, 135 insertions, 107 deletions

diff --git a/AUTHORS b/AUTHORS
new file mode 100644
index 000000000..8904070d8
--- /dev/null
+++ b/AUTHORS
@@ -0,0 +1,42 @@
+Steven K. Reinhardt
+-----------------------
+
+Nathan L. Binkert
+-----------------------
+
+Erik G. Hallnor
+-----------------------
+
+Steve E. Raasch
+-----------------------
+
+Lisa R. Hsu
+-----------------------
+
+Ali G. Saidi
+-----------------------
+
+Andrew L. Schultz
+-----------------------
+
+Kevin T. Lim
+-----------------------
+
+Ronald G. Dreslinski Jr
+-----------------------
+
+Gabriel Black
+-----------------------
+
+Korey Sewell
+-----------------------
+
+David Green
+-----------------------
+
+Benjamin S. Nash
+-----------------------
+
+Miguel J. Serrano
+-----------------------
+
diff --git a/README b/README
index 62214d8c5..7bcbe9523 100644
--- a/README
+++ b/README
@@ -1,21 +1,27 @@
-This is release m5_1.1 of the M5 simulator.
+This is release 2.0 of the M5 simulator.
 
-This file contains brief "getting started" instructions.  For more
-information, see http://m5.eecs.umich.edu.  If you have questions,
-please send mail to m5sim-users@lists.sourceforge.net.
+For information about building the simulator and getting started please refer
+to: http://m5.eecs.umich.edu/
+
+Specific Pages of Interest are:
+http://m5.eecs.umich.edu/wiki/index.php/Compiling_M5
+http://m5.eecs.umich.edu/wiki/index.php/Running_M5
+
+If you have questions, please send mail to m5sim-users@lists.sourceforge.net.
 
 WHAT'S INCLUDED (AND NOT)
 -------------------------
 
 The basic source release includes these subdirectories:
- - m5: the simulator itself
- - m5-test: regression tests
- - ext: less-common external packages needed to build m5
- - alpha-system: source for Alpha console and PALcode
+ - m5: 
+   - src: source code of the m5 simulator
+   - test: regression tests
+   - ext: less-common external packages needed to build m5
+   - system/alpha: source for Alpha console and PALcode
 
 To run full-system simulations, you will need compiled console,
 PALcode, and kernel binaries and one or more disk images.  These files
-are collected in a separate archive, m5_system_1.1.tar.bz2.  This file
+are collected in a separate archive, m5_system_2.0.tar.bz2.  This file
 is included on the CD release, or you can download it separately from
 Sourceforge.
 
@@ -31,66 +37,8 @@ set of Linux source patches (linux_m5-2.6.8.1.diff), and the scons
 program needed to build M5.  If you do not have the CD, the same HTML
 documentation is available online at http://m5.eecs.umich.edu/docs,
 the Linux source patches are available at
-http://m5.eecs.umich.edu/dist/linux_m5-2.6.8.1.diff, and the scons
-program is available from http://www.scons.org.
-
-WHAT'S NEEDED
--------------
-- GCC version 3.3 or newer
-- Python 2.3 or newer
-- SCons 0.96.1 or newer (see http://www.scons.org)
-
-WHAT'S RECOMMENDED
-------------------
-- MySQL (for statistics complex statistics storage/retrieval)
-- Python-MysqlDB (for statistics analysis) 
-
-GETTING STARTED
----------------
-
-There are two different build targets and three optimizations levels:
-
-Target:
--------
-ALPHA_SE - Syscall emulation simulation
-ALPHA_FS - Full system simulation
-
-Optimization:
--------------
-m5.debug - debug version of the code with tracing and without optimization
-m5.opt   - optimized version of code with tracing
-m5.fast  - optimized version of the code without tracing and asserts
-
-Different targets are built in different subdirectories of m5/build.
-Binaries with the same target but different optimization levels share
-the same directory.  Note that you can build m5 in any directory you
-choose;p just configure the target directory using the 'mkbuilddir'
-script in m5/build.
-
-The following steps will build and test the simulator.  The variable
-"$top" refers to the top directory where you've unpacked the files,
-i.e., the one containing the m5, m5-test, and ext directories.  If you
-have a multiprocessor system, you should give scons a "-j N" argument (like
-make) to run N jobs in parallel.
-
-To build and test the syscall-emulation simulator:
-
-	cd $top/m5/build
-	scons ALPHA_SE/test/opt/quick
-
-This process takes under 10 minutes on a dual 3GHz Xeon system (using
-the '-j 4' option).
-
-To build and test the full-system simulator:
-
-1. Unpack the full-system binaries from m5_system_1.1.tar.bz2.  (See
-   above for directions on obtaining this file if you don't have it.)
-   This package includes disk images and kernel, palcode, and console
-   binaries for Linux and FreeBSD.
-2. Edit the SYSTEMDIR search path in $top/m5-test/SysPaths.py to
-   include the path to your local copy of the binaries.
-3. In $top/m5/build, run "scons ALPHA_FS/test/opt/quick".
+http://m5.eecs.umich.edu/dist/linux_m5-2.6.8.1.diff, the scons
+program is available from http://www.scons.org, and swig is available from
+http://www.swig.org.
 
-This process also takes under 10 minutes on a dual 3GHz Xeon system
-(again using the '-j 4' option).
 
diff --git a/RELEASE_NOTES b/RELEASE_NOTES
index 983c9b2e9..6eb9b1844 100644
--- a/RELEASE_NOTES
+++ b/RELEASE_NOTES
@@ -1,3 +1,11 @@
+XXX. X, 2006: m5_2.0
+--------------------
+Major update to M5 including:
+- New CPU model
+- Sew memory system
+- More extensive python integration
+- Preliminary syscall emulation support for MIPS and SPARC
+
 Oct. 8, 2005: m5_1.1
 --------------------
 Update release for IOSCA workshop mini-tutorial.  New features include:
diff --git a/configs/test/test.py b/configs/test/test.py
index 2047d65af..3095cd1d1 100644
--- a/configs/test/test.py
+++ b/configs/test/test.py
@@ -11,12 +11,19 @@ from FullO3Config import *
 # parse command-line arguments
 parser = optparse.OptionParser(option_list=m5.standardOptions)
 
-parser.add_option("-c", "--cmd", default="hello")
-parser.add_option("-o", "--options", default="")
-parser.add_option("-i", "--input", default="")
-parser.add_option("-t", "--timing", action="store_true")
-parser.add_option("-d", "--detailed", action="store_true")
-parser.add_option("-m", "--maxtick", type="int")
+parser.add_option("-c", "--cmd", default="hello",
+                  help="The binary to run in syscall emulation mode.")
+parser.add_option("-o", "--options", default="",
+        help="The options to pass to the binary, use \" \" around the entire\
+                string.")
+parser.add_option("-i", "--input", default="",
+        help="A file of input to give to the binary.")
+parser.add_option("-t", "--timing", action="store_true",
+        help="Use simple timing CPU.")
+parser.add_option("-d", "--detailed", action="store_true",
+        help="Use detailed CPU.")
+parser.add_option("-m", "--maxtick", type="int",
+        help="Set the maximum number of ticks to run  for")
 
 (options, args) = parser.parse_args()
 m5.setStandardOptions(options)
@@ -37,6 +44,10 @@ if options.input != "":
 magicbus = Bus()
 mem = PhysicalMemory()
 
+if options.timing and options.detailed:
+       print "Error: you may only specify one cpu model";
+       sys.exit(1)
+
 if options.timing:
     cpu = TimingSimpleCPU()
 elif options.detailed:
diff --git a/src/arch/alpha/faults.cc b/src/arch/alpha/faults.cc
index 06765768a..eef4361fd 100644
--- a/src/arch/alpha/faults.cc
+++ b/src/arch/alpha/faults.cc
@@ -194,11 +194,13 @@ void PageTableFault::invoke(ThreadContext *tc)
 
     // We've accessed the next page
     if (vaddr > p->stack_min - PageBytes) {
+        warn("Increasing stack %#x:%#x to %#x:%#x because of access to %#x",
+                p->stack_min, p->stack_base, p->stack_min - PageBytes,
+                p->stack_base, vaddr);
         p->stack_min -= PageBytes;
         if (p->stack_base - p->stack_min > 8*1024*1024)
             fatal("Over max stack size for one thread\n");
         p->pTable->allocate(p->stack_min, PageBytes);
-        warn("Increasing stack size by one page.");
     } else {
         FaultBase::invoke(tc);
     }
diff --git a/src/cpu/o3/alpha_cpu.hh b/src/cpu/o3/alpha_cpu.hh
index 55b975142..d7f3d5801 100644
--- a/src/cpu/o3/alpha_cpu.hh
+++ b/src/cpu/o3/alpha_cpu.hh
@@ -384,8 +384,6 @@ class AlphaO3CPU : public FullO3CPU<Impl>
     bool inPalMode(uint64_t PC)
     { return AlphaISA::PcPAL(PC); }
 
-    /** Traps to handle given fault. */
-    void trap(Fault fault, unsigned tid);
     bool simPalCheck(int palFunc, unsigned tid);
 
     /** Processes any interrupts. */
@@ -395,6 +393,8 @@ class AlphaO3CPU : public FullO3CPU<Impl>
     void halt() { panic("Halt not implemented!\n"); }
 #endif
 
+    /** Traps to handle given fault. */
+    void trap(Fault fault, unsigned tid);
 
 #if !FULL_SYSTEM
     /** Executes a syscall.
diff --git a/src/cpu/o3/alpha_cpu_impl.hh b/src/cpu/o3/alpha_cpu_impl.hh
index 532611fb6..eca6fbbcb 100644
--- a/src/cpu/o3/alpha_cpu_impl.hh
+++ b/src/cpu/o3/alpha_cpu_impl.hh
@@ -755,14 +755,6 @@ AlphaO3CPU<Impl>::simPalCheck(int palFunc, unsigned tid)
 
 template <class Impl>
 void
-AlphaO3CPU<Impl>::trap(Fault fault, unsigned tid)
-{
-    // Pass the thread's TC into the invoke method.
-    fault->invoke(this->threadContexts[tid]);
-}
-
-template <class Impl>
-void
 AlphaO3CPU<Impl>::processInterrupts()
 {
     // Check for interrupts here.  For now can copy the code that
@@ -823,6 +815,14 @@ AlphaO3CPU<Impl>::processInterrupts()
 
 #endif // FULL_SYSTEM
 
+template <class Impl>
+void
+AlphaO3CPU<Impl>::trap(Fault fault, unsigned tid)
+{
+    // Pass the thread's TC into the invoke method.
+    fault->invoke(this->threadContexts[tid]);
+}
+
 #if !FULL_SYSTEM
 
 template <class Impl>
diff --git a/src/cpu/o3/commit_impl.hh b/src/cpu/o3/commit_impl.hh
index 176f83246..cd7dd47d4 100644
--- a/src/cpu/o3/commit_impl.hh
+++ b/src/cpu/o3/commit_impl.hh
@@ -991,7 +991,6 @@ DefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num)
 
     if (inst_fault != NoFault) {
         head_inst->setCompleted();
-#if FULL_SYSTEM
         DPRINTF(Commit, "Inst [sn:%lli] PC %#x has a fault\n",
                 head_inst->seqNum, head_inst->readPC());
 
@@ -1035,10 +1034,6 @@ DefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num)
         generateTrapEvent(tid);
 
         return false;
-#else // !FULL_SYSTEM
-        panic("fault (%d) detected @ PC %08p", inst_fault,
-              head_inst->PC);
-#endif // FULL_SYSTEM
     }
 
     updateComInstStats(head_inst);
diff --git a/src/cpu/o3/fetch.hh b/src/cpu/o3/fetch.hh
index 790c28f09..7fcd21b7d 100644
--- a/src/cpu/o3/fetch.hh
+++ b/src/cpu/o3/fetch.hh
@@ -36,7 +36,7 @@
 #include "base/statistics.hh"
 #include "base/timebuf.hh"
 #include "cpu/pc_event.hh"
-#include "mem/packet.hh"
+#include "mem/packet_impl.hh"
 #include "mem/port.hh"
 #include "sim/eventq.hh"
 
diff --git a/src/cpu/o3/lsq_unit.hh b/src/cpu/o3/lsq_unit.hh
index 9b67e61f2..74b8fe5bb 100644
--- a/src/cpu/o3/lsq_unit.hh
+++ b/src/cpu/o3/lsq_unit.hh
@@ -40,7 +40,7 @@
 #include "config/full_system.hh"
 #include "base/hashmap.hh"
 #include "cpu/inst_seq.hh"
-#include "mem/packet.hh"
+#include "mem/packet_impl.hh"
 #include "mem/port.hh"
 
 /**
diff --git a/src/mem/page_table.cc b/src/mem/page_table.cc
index 7daf31900..a34a0393a 100644
--- a/src/mem/page_table.cc
+++ b/src/mem/page_table.cc
@@ -54,6 +54,9 @@ PageTable::PageTable(System *_system, Addr _pageSize)
       system(_system)
 {
     assert(isPowerOf2(pageSize));
+    pTableCache[0].vaddr = 0;
+    pTableCache[1].vaddr = 0;
+    pTableCache[2].vaddr = 0;
 }
 
 PageTable::~PageTable()
@@ -95,7 +98,7 @@ PageTable::allocate(Addr vaddr, int size)
     assert(pageOffset(vaddr) == 0);
 
     for (; size > 0; size -= pageSize, vaddr += pageSize) {
-        std::map<Addr,Addr>::iterator iter = pTable.find(vaddr);
+        m5::hash_map<Addr,Addr>::iterator iter = pTable.find(vaddr);
 
         if (iter != pTable.end()) {
             // already mapped
@@ -103,6 +106,12 @@ PageTable::allocate(Addr vaddr, int size)
         }
 
         pTable[vaddr] = system->new_page();
+        pTableCache[2].paddr = pTableCache[1].paddr;
+        pTableCache[2].vaddr = pTableCache[1].vaddr;
+        pTableCache[1].paddr = pTableCache[0].paddr;
+        pTableCache[1].vaddr = pTableCache[0].vaddr;
+        pTableCache[0].paddr = pTable[vaddr];
+        pTableCache[0].vaddr = vaddr;
     }
 }
 
@@ -112,7 +121,22 @@ bool
 PageTable::translate(Addr vaddr, Addr &paddr)
 {
     Addr page_addr = pageAlign(vaddr);
-    std::map<Addr,Addr>::iterator iter = pTable.find(page_addr);
+    paddr = 0;
+
+    if (pTableCache[0].vaddr == vaddr) {
+        paddr = pTableCache[0].paddr;
+        return true;
+    }
+    if (pTableCache[1].vaddr == vaddr) {
+        paddr = pTableCache[1].paddr;
+        return true;
+    }
+    if (pTableCache[2].vaddr == vaddr) {
+        paddr = pTableCache[2].paddr;
+        return true;
+    }
+
+    m5::hash_map<Addr,Addr>::iterator iter = pTable.find(page_addr);
 
     if (iter == pTable.end()) {
         return false;
diff --git a/src/mem/page_table.hh b/src/mem/page_table.hh
index f7212d423..494c0ce9a 100644
--- a/src/mem/page_table.hh
+++ b/src/mem/page_table.hh
@@ -37,9 +37,9 @@
 #define __PAGE_TABLE__
 
 #include <string>
-#include <map>
 
 #include "arch/isa_traits.hh"
+#include "base/hashmap.hh"
 #include "base/trace.hh"
 #include "mem/request.hh"
 #include "mem/packet.hh"
@@ -53,7 +53,14 @@ class System;
 class PageTable
 {
   protected:
-    std::map<Addr,Addr> pTable;
+    m5::hash_map<Addr,Addr> pTable;
+
+    struct cacheElement {
+        Addr paddr;
+        Addr vaddr;
+    } ;
+
+    struct cacheElement pTableCache[3];
 
     const Addr pageSize;
     const Addr offsetMask;
diff --git a/src/sim/pseudo_inst.cc b/src/sim/pseudo_inst.cc
index ae52cdd41..b2854e491 100644
--- a/src/sim/pseudo_inst.cc
+++ b/src/sim/pseudo_inst.cc
@@ -209,12 +209,6 @@ namespace AlphaPseudo
     {
         if (!doCheckpointInsts)
             return;
-
-
-        Tick when = curTick + delay * Clock::Int::ns;
-        Tick repeat = period * Clock::Int::ns;
-
-        Checkpoint::setup(when, repeat);
     }
 
     uint64_t
diff --git a/src/sim/serialize.hh b/src/sim/serialize.hh
index 5a820b27e..a80dc99e4 100644
--- a/src/sim/serialize.hh
+++ b/src/sim/serialize.hh
@@ -241,9 +241,6 @@ class Checkpoint
 
     // Filename for base checkpoint file within directory.
     static const char *baseFilename;
-
-    // Set up a checkpoint creation event or series of events.
-    static void setup(Tick when, Tick period = 0);
 };
 
 #endif // __SERIALIZE_HH__