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authorGabe Black <gblack@eecs.umich.edu>2010-06-02 12:58:13 -0500
committerGabe Black <gblack@eecs.umich.edu>2010-06-02 12:58:13 -0500
commitcd86e34187942b955366986add435dc1c9d9018b (patch)
tree511a44499a4ae246566e45a37f652cb210b00eb7
parentc5a8a1d673b0bdd1258aa2de1706f1e9b9bab759 (diff)
downloadgem5-cd86e34187942b955366986add435dc1c9d9018b.tar.xz
ARM: Add in some missing SCTLR fields.
-rw-r--r--src/arch/arm/miscregs.hh4
1 files changed, 3 insertions, 1 deletions
diff --git a/src/arch/arm/miscregs.hh b/src/arch/arm/miscregs.hh
index 4fd52fd1e..badad6c31 100644
--- a/src/arch/arm/miscregs.hh
+++ b/src/arch/arm/miscregs.hh
@@ -241,6 +241,7 @@ namespace ArmISA
static const uint32_t CondCodesMask = 0xF80F0000;
BitUnion32(SCTLR)
+ Bitfield<31> ie; // Instruction endianness
Bitfield<30> te; // Thumb Exception Enable
Bitfield<29> afe; // Access flag enable
Bitfield<28> tre; // TEX Remap bit
@@ -250,8 +251,9 @@ namespace ArmISA
Bitfield<23> rao1;// Read as one
Bitfield<22> u; // Alignment (now unused)
Bitfield<21> fi; // Fast interrupts configuration enable
+ Bitfield<19> dz; // Divide by Zero fault enable bit
Bitfield<18> rao2;// Read as one
- Bitfield<17> ha; // Hardware access flag enable
+ Bitfield<17> br; // Background region bit
Bitfield<16> rao3;// Read as one
Bitfield<14> rr; // Round robin cache replacement
Bitfield<13> v; // Base address for exception vectors