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| author | Gabe Black <gblack@eecs.umich.edu> | 2010-06-02 12:58:09 -0500 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2010-06-02 12:58:09 -0500 |
| commit | e658b6fed46afb0b587dba037bd4558e82c05b0d (patch) | |
| tree | 7d5096febe4f2b3af4d0d24e9d1a12bb904d9e2a | |
| parent | 896c7617c47cd83b0e119b62baa133307d05cecd (diff) | |
| download | gem5-e658b6fed46afb0b587dba037bd4558e82c05b0d.tar.xz | |
ARM: Add support for the clidr register.
This register will always report 0 caches as implemented. It's not clear how
to find out how many there really are when dealing with an arbitrary
hierarchy.
| -rw-r--r-- | src/arch/arm/isa.hh | 5 | ||||
| -rw-r--r-- | src/arch/arm/miscregs.hh | 6 |
2 files changed, 8 insertions, 3 deletions
diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh index dd80976bb..1d8f14cab 100644 --- a/src/arch/arm/isa.hh +++ b/src/arch/arm/isa.hh @@ -164,6 +164,11 @@ namespace ArmISA panic("Unimplemented CP15 register %s read.\n", miscRegName[misc_reg]); } + switch (misc_reg) { + case MISCREG_CLIDR: + warn("The clidr register always reports 0 caches.\n"); + break; + } return readMiscRegNoEffect(misc_reg); } diff --git a/src/arch/arm/miscregs.hh b/src/arch/arm/miscregs.hh index fa4c27bd9..f6b8c2df9 100644 --- a/src/arch/arm/miscregs.hh +++ b/src/arch/arm/miscregs.hh @@ -92,6 +92,7 @@ namespace ArmISA MISCREG_CP15DSB, MISCREG_CP15DMB, MISCREG_CPACR, + MISCREG_CLIDR, MISCREG_CP15_UNIMP_START, MISCREG_CTR = MISCREG_CP15_UNIMP_START, MISCREG_TCMTR, @@ -113,7 +114,6 @@ namespace ArmISA MISCREG_ID_ISAR4, MISCREG_ID_ISAR5, MISCREG_CCSIDR, - MISCREG_CLIDR, MISCREG_AIDR, MISCREG_CSSELR, MISCREG_ACTLR, @@ -160,12 +160,12 @@ namespace ArmISA "fpsr", "fpsid", "fpscr", "fpexc", "sctlr", "dccisw", "dccimvac", "contextidr", "tpidrurw", "tpidruro", "tpidrprw", - "cp15isb", "cp15dsb", "cp15dmb", "cpacr", + "cp15isb", "cp15dsb", "cp15dmb", "cpacr", "clidr", "ctr", "tcmtr", "mpuir", "mpidr", "midr", "id_pfr0", "id_pfr1", "id_dfr0", "id_afr0", "id_mmfr0", "id_mmfr1", "id_mmfr2", "id_mmfr3", "id_isar0", "id_isar1", "id_isar2", "id_isar3", "id_isar4", "id_isar5", - "ccsidr", "clidr", "aidr", "csselr", "actlr", + "ccsidr", "aidr", "csselr", "actlr", "dfsr", "ifsr", "adfsr", "aifsr", "dfar", "ifar", "drbar", "irbar", "drsr", "irsr", "dracr", "iracr", "rgnr", "icialluis", "bpiallis", "iciallu", "icimvau", |