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authorGabe Black <gblack@eecs.umich.edu>2010-06-02 12:58:09 -0500
committerGabe Black <gblack@eecs.umich.edu>2010-06-02 12:58:09 -0500
commiteb0823c4f2666e6b3de441fa661e9e17ef908d8f (patch)
tree4fe0a87da67a488b6c01397de47f11c1a84f6a48
parentbb0d390105073f3fe827026d36cd950005a15e46 (diff)
downloadgem5-eb0823c4f2666e6b3de441fa661e9e17ef908d8f.tar.xz
ARM: Fix the implementation of BX to work in thumbEE mode.
-rw-r--r--src/arch/arm/insts/static_inst.hh4
-rw-r--r--src/arch/arm/isa/insts/branch.isa24
2 files changed, 13 insertions, 15 deletions
diff --git a/src/arch/arm/insts/static_inst.hh b/src/arch/arm/insts/static_inst.hh
index 2c83ee79c..23c04306d 100644
--- a/src/arch/arm/insts/static_inst.hh
+++ b/src/arch/arm/insts/static_inst.hh
@@ -238,9 +238,9 @@ class ArmStaticInst : public StaticInst
Addr newPc = (val & ~PcModeMask);
if (thumbEE) {
if (bits(newPc, 0)) {
- warn("Bad thumbEE interworking branch address %#x.\n", newPc);
- } else {
newPc = newPc & ~mask(1);
+ } else {
+ panic("Bad thumbEE interworking branch address %#x.\n", newPc);
}
} else {
if (bits(newPc, 0)) {
diff --git a/src/arch/arm/isa/insts/branch.isa b/src/arch/arm/isa/insts/branch.isa
index 71a98053e..b79f610b6 100644
--- a/src/arch/arm/isa/insts/branch.isa
+++ b/src/arch/arm/isa/insts/branch.isa
@@ -69,15 +69,8 @@ let {{
blxCode = '''
Addr PC = readPC(xc);
Addr tBit = PC & (ULL(1) << PcTBitShift);
- // Other than the assert below, jBit isn't used.
-#if !defined(NDEBUG)
- Addr jBit = PC & (ULL(1) << PcJBitShift);
-#endif
- // X isn't permitted in ThumbEE mode. We shouldn't be in jazzelle mode?
- assert(!jBit);
bool arm = !tBit;
arm = arm; // In case it's not used otherwise.
- Addr tempPc = ((%(newPC)s) & mask(32)) | (PC & ~mask(32));
%(link)s
// Switch modes
%(branch)s
@@ -89,11 +82,6 @@ let {{
for (mnem, imm, link) in blxList:
Name = mnem.capitalize()
- if imm and link: #blx with imm
- branchStr = "FNPC = tempPc ^ (ULL(1) << PcTBitShift);"
- else:
- branchStr = "IWNPC = tempPc ^ (ULL(1) << PcTBitShift);"
-
if imm:
Name += "Imm"
# Since we're switching ISAs, the target ISA will be the opposite
@@ -104,7 +92,7 @@ let {{
constructor = BranchImmConstructor
else:
Name += "Reg"
- newPC = '(PC & PcModeMask) | Op1'
+ newPC = 'Op1'
base = "BranchRegCond"
declare = BranchRegCondDeclare
constructor = BranchRegCondConstructor
@@ -127,6 +115,16 @@ let {{
'''
else:
linkStr = ""
+
+ if imm and link: #blx with imm
+ branchStr = '''
+ Addr tempPc = ((%(newPC)s) & mask(32)) | (PC & ~mask(32));
+ FNPC = tempPc ^ (ULL(1) << PcTBitShift);
+ '''
+ else:
+ branchStr = "IWNPC = %(newPC)s;"
+ branchStr = branchStr % { "newPC" : newPC }
+
code = blxCode % {"link": linkStr,
"newPC": newPC,
"branch": branchStr}