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| author | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2018-04-17 11:08:29 +0100 |
|---|---|---|
| committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2018-04-19 11:59:25 +0000 |
| commit | 1de574fcbdf009eacda9eae1b239e7c367e2cb79 (patch) | |
| tree | a968701ca53eb7c987fd41ae53a2cc9fe125c9f2 | |
| parent | c21a2a54ca366c2e699571b1dddd083a77601831 (diff) | |
| download | gem5-1de574fcbdf009eacda9eae1b239e7c367e2cb79.tar.xz | |
arch-arm: Add ARMv8.1 TTBR1_EL2 register
This patch adds ARMv8.1 TTBR1_EL2 register into the decodeAArch64SysReg
table, but stil leaving it unimplemented (Accessing it through MSR/MRS
causes an exception)
Change-Id: I463b86cc544233aa1ee5b2fcba689d6b9f2a874b
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/10063
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
| -rw-r--r-- | src/arch/arm/isa.cc | 1 | ||||
| -rw-r--r-- | src/arch/arm/miscregs.cc | 4 | ||||
| -rw-r--r-- | src/arch/arm/miscregs.hh | 16 |
3 files changed, 14 insertions, 7 deletions
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc index 7f0e0f42b..42d1b920b 100644 --- a/src/arch/arm/isa.cc +++ b/src/arch/arm/isa.cc @@ -1713,6 +1713,7 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc) case MISCREG_TTBR0_EL1: case MISCREG_TTBR1_EL1: case MISCREG_TTBR0_EL2: + case MISCREG_TTBR1_EL2: case MISCREG_TTBR0_EL3: getITBPtr(tc)->invalidateMiscReg(); getDTBPtr(tc)->invalidateMiscReg(); diff --git a/src/arch/arm/miscregs.cc b/src/arch/arm/miscregs.cc index b5ae4ced2..66159132d 100644 --- a/src/arch/arm/miscregs.cc +++ b/src/arch/arm/miscregs.cc @@ -1689,6 +1689,8 @@ decodeAArch64SysReg(unsigned op0, unsigned op1, switch (op2) { case 0: return MISCREG_TTBR0_EL2; + case 1: + return MISCREG_TTBR1_EL2; case 2: return MISCREG_TCR_EL2; } @@ -3519,6 +3521,8 @@ ISA::initializeMiscRegMetadata() InitReg(MISCREG_TTBR0_EL2) .hyp().mon() .mapsTo(MISCREG_HTTBR); + InitReg(MISCREG_TTBR1_EL2) + .unimplemented(); InitReg(MISCREG_TCR_EL2) .hyp().mon() .mapsTo(MISCREG_HTCR); diff --git a/src/arch/arm/miscregs.hh b/src/arch/arm/miscregs.hh index 9bca3d116..06d1a0d79 100644 --- a/src/arch/arm/miscregs.hh +++ b/src/arch/arm/miscregs.hh @@ -666,14 +666,16 @@ namespace ArmISA MISCREG_CBAR_EL1, // 598 MISCREG_CONTEXTIDR_EL2, // 599 + // Introduced in ARMv8.1 + MISCREG_TTBR1_EL2, // 600 + // These MISCREG_FREESLOT are available Misc Register // slots for future registers to be implemented. - MISCREG_FREESLOT_1, // 600 - MISCREG_FREESLOT_2, // 601 - MISCREG_FREESLOT_3, // 602 - MISCREG_FREESLOT_4, // 603 - MISCREG_FREESLOT_5, // 604 - MISCREG_FREESLOT_6, // 605 + MISCREG_FREESLOT_1, // 601 + MISCREG_FREESLOT_2, // 602 + MISCREG_FREESLOT_3, // 603 + MISCREG_FREESLOT_4, // 604 + MISCREG_FREESLOT_5, // 605 // NUM_PHYS_MISCREGS specifies the number of actual physical // registers, not considering the following pseudo-registers @@ -1370,12 +1372,12 @@ namespace ArmISA "cbar_el1", "contextidr_el2", + "ttbr1_el2", "freeslot1", "freeslot2", "freeslot3", "freeslot4", "freeslot5", - "freeslot6", "num_phys_regs", |