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| author | Korey Sewell <ksewell@umich.edu> | 2007-11-14 15:33:43 -0500 |
|---|---|---|
| committer | Korey Sewell <ksewell@umich.edu> | 2007-11-14 15:33:43 -0500 |
| commit | 2820a448e2bcb861d099b1256087004462b78895 (patch) | |
| tree | 2b58cfc1191aeaf2bb732e9401dae67204c675ac | |
| parent | 5f7879a9352985775abef9515e216591a2e3e39d (diff) | |
| download | gem5-2820a448e2bcb861d099b1256087004462b78895.tar.xz | |
comment and spacing
--HG--
extra : convert_revision : b3acde37bc11919700c257eae58ea9e0f66c9786
| -rw-r--r-- | src/arch/mips/tlb.hh | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/src/arch/mips/tlb.hh b/src/arch/mips/tlb.hh index 5240eb2a9..0dfe3ecf1 100644 --- a/src/arch/mips/tlb.hh +++ b/src/arch/mips/tlb.hh @@ -53,7 +53,6 @@ class ThreadContext; namespace MipsISA { // WARN: This particular TLB entry is not necessarily conformed to MIPS ISA -// We just need this to make compiler happy. Use "PTE" type for real entry. struct TlbEntry { Addr _pageStart; |