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authorGabe Black <gblack@eecs.umich.edu>2010-06-02 12:58:04 -0500
committerGabe Black <gblack@eecs.umich.edu>2010-06-02 12:58:04 -0500
commit28227440a7645d2f486c0c1f79ef22514aeaa4c8 (patch)
tree6fd6c842bfd6332f2019376e909abdc96c8223b2
parentd63f748b5361df3fb84ba5274ab89a642cec2dfb (diff)
downloadgem5-28227440a7645d2f486c0c1f79ef22514aeaa4c8.tar.xz
ARM: Align the PC when using it as the base for a load.
-rw-r--r--src/arch/arm/isa/operands.isa6
1 files changed, 5 insertions, 1 deletions
diff --git a/src/arch/arm/isa/operands.isa b/src/arch/arm/isa/operands.isa
index 6e792f725..c507864b6 100644
--- a/src/arch/arm/isa/operands.isa
+++ b/src/arch/arm/isa/operands.isa
@@ -56,6 +56,10 @@ let {{
((%(reg_idx)s == PCReg) ? (readPC(xc) & ~PcModeMask) :
xc->%(func)s(this, %(op_idx)s))
'''
+ maybeAlignedPCRead = '''
+ ((%(reg_idx)s == PCReg) ? (roundDown(readPC(xc) & ~PcModeMask, 4)) :
+ xc->%(func)s(this, %(op_idx)s))
+ '''
maybePCWrite = '''
((%(reg_idx)s == PCReg) ? setNextPC(xc, %(final_val)s) :
xc->%(func)s(this, %(op_idx)s, %(final_val)s))
@@ -91,7 +95,7 @@ def operands {{
'AIWDest': ('IntReg', 'uw', 'dest', 'IsInteger', 0,
maybePCRead, maybeAIWPCWrite),
'Base': ('IntReg', 'uw', 'base', 'IsInteger', 1,
- maybePCRead, maybePCWrite),
+ maybeAlignedPCRead, maybePCWrite),
'Index': ('IntReg', 'uw', 'index', 'IsInteger', 2,
maybePCRead, maybePCWrite),
'Op1': ('IntReg', 'uw', 'op1', 'IsInteger', 3,