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| author | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2018-04-18 10:31:44 +0100 |
|---|---|---|
| committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2018-04-19 11:59:10 +0000 |
| commit | 291c2798103999b66f9ad5b9a885a67f3ef2160e (patch) | |
| tree | a30d447029aa72a47a215eee24df642faa146d36 | |
| parent | ce9d9c9a4c119131bdcfd774f1c2a2cf28e42db9 (diff) | |
| download | gem5-291c2798103999b66f9ad5b9a885a67f3ef2160e.tar.xz | |
arch-arm: Change disassemble when MSR to UNKNOWN register
This patch changes the fault being thrown when MSR/MRS to an unknown
Misc register in AArch64. While previously the instruction was decoded
as an Unknown instruction (hence not printing any information), it is
now decoded as a FailUnimplemented and the unrecognized System register
numbers (CRn, op0...) are printed.
Change-Id: I205ff7adcde5934231c77e8d2250db69a34581fc
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/10061
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
| -rw-r--r-- | src/arch/arm/isa/formats/aarch64.isa | 9 |
1 files changed, 8 insertions, 1 deletions
diff --git a/src/arch/arm/isa/formats/aarch64.isa b/src/arch/arm/isa/formats/aarch64.isa index 7752ba08f..00bd0770f 100644 --- a/src/arch/arm/isa/formats/aarch64.isa +++ b/src/arch/arm/isa/formats/aarch64.isa @@ -369,7 +369,14 @@ namespace Aarch64 } // Check for invalid registers if (miscReg == MISCREG_UNKNOWN) { - return new Unknown64(machInst); + auto full_mnemonic = + csprintf("%s op0:%d op1:%d crn:%d crm:%d op2:%d", + read ? "mrs" : "msr", + op0, op1, crn, crm, op2); + + return new FailUnimplemented(read ? "mrs" : "msr", + machInst, full_mnemonic); + } else if (miscRegInfo[miscReg][MISCREG_IMPLEMENTED]) { if (miscReg == MISCREG_NZCV) { if (read) |