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authorGabe Black <gblack@eecs.umich.edu>2010-06-02 12:58:13 -0500
committerGabe Black <gblack@eecs.umich.edu>2010-06-02 12:58:13 -0500
commit4491170df6e7a130c43d38d4220e5dff3c1dd214 (patch)
tree644fdbf13a53ab53dc8d5c85bcea0eeb6767ce24
parentcd86e34187942b955366986add435dc1c9d9018b (diff)
downloadgem5-4491170df6e7a130c43d38d4220e5dff3c1dd214.tar.xz
ARM: Make integer division by zero return a fault.
-rw-r--r--src/arch/arm/isa/insts/div.isa14
-rw-r--r--src/arch/arm/isa/operands.isa1
2 files changed, 15 insertions, 0 deletions
diff --git a/src/arch/arm/isa/insts/div.isa b/src/arch/arm/isa/insts/div.isa
index b240e2967..302beb6b3 100644
--- a/src/arch/arm/isa/insts/div.isa
+++ b/src/arch/arm/isa/insts/div.isa
@@ -40,6 +40,13 @@
let {{
sdivCode = '''
if (Op2.sw == 0) {
+ if (((SCTLR)Sctlr).dz) {
+#if FULL_SYSTEM
+ return new UndefinedInstruction;
+#else
+ return new UndefinedInstruction(false, mnemonic);
+#endif
+ }
Dest.sw = 0;
} else if (Op1.sw == INT_MIN && Op2.sw == -1) {
Dest.sw = INT_MIN;
@@ -56,6 +63,13 @@ let {{
udivCode = '''
if (Op2.uw == 0) {
+ if (((SCTLR)Sctlr).dz) {
+#if FULL_SYSTEM
+ return new UndefinedInstruction;
+#else
+ return new UndefinedInstruction(false, mnemonic);
+#endif
+ }
Dest.uw = 0;
} else {
Dest.uw = Op1.uw / Op2.uw;
diff --git a/src/arch/arm/isa/operands.isa b/src/arch/arm/isa/operands.isa
index 9f4a0ca2f..4c269276a 100644
--- a/src/arch/arm/isa/operands.isa
+++ b/src/arch/arm/isa/operands.isa
@@ -176,6 +176,7 @@ def operands {{
'Fpsid': ('ControlReg', 'uw', 'MISCREG_FPSID', None, 2),
'Fpscr': ('ControlReg', 'uw', 'MISCREG_FPSCR', None, 2),
'Fpexc': ('ControlReg', 'uw', 'MISCREG_FPEXC', None, 2),
+ 'Sctlr': ('ControlReg', 'uw', 'MISCREG_SCTLR', None, 2),
'SevMailbox': ('ControlReg', 'uw', 'MISCREG_SEV_MAILBOX', None, 2),
'NPC': ('NPC', 'ud', None, (None, None, 'IsControl'), 2,
readNPC, writeNPC),