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authorSteve Reinhardt <stever@eecs.umich.edu>2007-07-02 13:57:45 -0700
committerSteve Reinhardt <stever@eecs.umich.edu>2007-07-02 13:57:45 -0700
commit4b68652c87f61fe0a2fd4040b79130de0846df85 (patch)
treee2c557a61e20560536043037c26585c556b7b3c1
parente9c04dad60f7a382fe94ca587fa505926dbd925c (diff)
downloadgem5-4b68652c87f61fe0a2fd4040b79130de0846df85.tar.xz
Couple more minor bug fixes for FS timing mode.
src/cpu/simple/timing.cc: Fix another SC problem. src/mem/cache/cache_impl.hh: Forgot to call makeTimingResponse() on uncached timing responses. --HG-- extra : convert_revision : 5a5a58ca2053e4e8de2133205bfd37de15eb4209
-rw-r--r--src/cpu/simple/timing.cc13
-rw-r--r--src/mem/cache/cache_impl.hh1
2 files changed, 8 insertions, 6 deletions
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index 492a669b8..0c03815b5 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -356,8 +356,6 @@ TimingSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
MemCmd cmd = MemCmd::WriteReq; // default
bool do_access = true; // flag to suppress cache access
- assert(dcache_pkt == NULL);
-
if (req->isLocked()) {
cmd = MemCmd::StoreCondReq;
do_access = TheISA::handleLockedWrite(thread, req);
@@ -369,11 +367,14 @@ TimingSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
}
}
- if (do_access) {
- dcache_pkt = new Packet(req, cmd, Packet::Broadcast);
- dcache_pkt->allocate();
- dcache_pkt->set(data);
+ // Note: need to allocate dcache_pkt even if do_access is
+ // false, as it's used unconditionally to call completeAcc().
+ assert(dcache_pkt == NULL);
+ dcache_pkt = new Packet(req, cmd, Packet::Broadcast);
+ dcache_pkt->allocate();
+ dcache_pkt->set(data);
+ if (do_access) {
if (!dcachePort.sendTiming(dcache_pkt)) {
_status = DcacheRetry;
} else {
diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh
index b4c3c6359..0d76b6bec 100644
--- a/src/mem/cache/cache_impl.hh
+++ b/src/mem/cache/cache_impl.hh
@@ -698,6 +698,7 @@ Cache<TagStore>::handleResponse(PacketPtr pkt)
if (pkt->isRead()) {
target->pkt->setData(pkt->getPtr<uint8_t>());
}
+ target->pkt->makeTimingResponse();
cpuSidePort->respond(target->pkt, time);
}
assert(!mshr->hasTargets());