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authorGabe Black <gblack@eecs.umich.edu>2009-01-25 20:35:00 -0800
committerGabe Black <gblack@eecs.umich.edu>2009-01-25 20:35:00 -0800
commit56e182a6a9e58b951712582c4c63cf303847156e (patch)
tree0431ff1519392b7febc83bf4e94e41c6cb1ca7df
parent151bc018dd621b62b60ee5eca10c7531de6eb441 (diff)
downloadgem5-56e182a6a9e58b951712582c4c63cf303847156e.tar.xz
X86: Add a dummy minimal DMA controller that doesn't do anything.
-rw-r--r--src/dev/x86/I8237.py36
-rw-r--r--src/dev/x86/SConscript4
-rw-r--r--src/dev/x86/SouthBridge.py4
-rw-r--r--src/dev/x86/i8237.cc130
-rw-r--r--src/dev/x86/i8237.hh66
5 files changed, 240 insertions, 0 deletions
diff --git a/src/dev/x86/I8237.py b/src/dev/x86/I8237.py
new file mode 100644
index 000000000..20788a164
--- /dev/null
+++ b/src/dev/x86/I8237.py
@@ -0,0 +1,36 @@
+# Copyright (c) 2008 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Gabe Black
+
+from m5.params import *
+from m5.proxy import *
+from Device import BasicPioDevice
+
+class I8237(BasicPioDevice):
+ type = 'I8237'
+ cxx_class = 'X86ISA::I8237'
+ pio_latency = Param.Latency('1ns', "Programmed IO latency in simticks")
diff --git a/src/dev/x86/SConscript b/src/dev/x86/SConscript
index 3481235c6..167b14a84 100644
--- a/src/dev/x86/SConscript
+++ b/src/dev/x86/SConscript
@@ -49,6 +49,10 @@ if env['FULL_SYSTEM'] and env['TARGET_ISA'] == 'x86':
Source('i8254.cc')
TraceFlag('I8254', 'Interrupts from the I8254 timer');
+ SimObject('I8237.py')
+ Source('i8237.cc')
+ TraceFlag('I8237', 'The I8237 dma controller');
+
SimObject('PcSpeaker.py')
Source('speaker.cc')
TraceFlag('PcSpeaker')
diff --git a/src/dev/x86/SouthBridge.py b/src/dev/x86/SouthBridge.py
index 8a9bea01b..bbe3ad102 100644
--- a/src/dev/x86/SouthBridge.py
+++ b/src/dev/x86/SouthBridge.py
@@ -30,6 +30,7 @@ from m5.params import *
from m5.proxy import *
from Cmos import Cmos
from I82094AA import I82094AA
+from I8237 import I8237
from I8254 import I8254
from I8259 import I8259
from PcSpeaker import PcSpeaker
@@ -47,6 +48,7 @@ class SouthBridge(SimObject):
_pic1 = I8259(pio_addr=x86IOAddress(0x20), mode='I8259Master')
_pic2 = I8259(pio_addr=x86IOAddress(0xA0), mode='I8259Slave')
_cmos = Cmos(pio_addr=x86IOAddress(0x70))
+ _dma1 = I8237(pio_addr=x86IOAddress(0x0))
_pit = I8254(pio_addr=x86IOAddress(0x40))
_speaker = PcSpeaker(pio_addr=x86IOAddress(0x61))
_io_apic = I82094AA(pio_addr=0xFEC00000)
@@ -54,6 +56,7 @@ class SouthBridge(SimObject):
pic1 = Param.I8259(_pic1, "Master PIC")
pic2 = Param.I8259(_pic2, "Slave PIC")
cmos = Param.Cmos(_cmos, "CMOS memory and real time clock device")
+ dma1 = Param.I8237(_dma1, "The first dma controller")
pit = Param.I8254(_pit, "Programmable interval timer")
speaker = Param.PcSpeaker(_speaker, "PC speaker")
io_apic = Param.I82094AA(_io_apic, "I/O APIC")
@@ -67,6 +70,7 @@ class SouthBridge(SimObject):
self.speaker.i8254 = self.pit
# Connect to the bus
self.cmos.pio = bus.port
+ self.dma1.pio = bus.port
self.pic1.pio = bus.port
self.pic2.pio = bus.port
self.pit.pio = bus.port
diff --git a/src/dev/x86/i8237.cc b/src/dev/x86/i8237.cc
new file mode 100644
index 000000000..5afe6b91a
--- /dev/null
+++ b/src/dev/x86/i8237.cc
@@ -0,0 +1,130 @@
+/*
+ * Copyright (c) 2008 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+#include "dev/x86/i8237.hh"
+#include "mem/packet.hh"
+#include "mem/packet_access.hh"
+
+Tick
+X86ISA::I8237::read(PacketPtr pkt)
+{
+ assert(pkt->getSize() == 1);
+ Addr offset = pkt->getAddr() - pioAddr;
+ switch (offset) {
+ case 0x0:
+ panic("Read from i8237 channel 0 current address unimplemented.\n");
+ case 0x1:
+ panic("Read from i8237 channel 0 remaining "
+ "word count unimplemented.\n");
+ case 0x2:
+ panic("Read from i8237 channel 1 current address unimplemented.\n");
+ case 0x3:
+ panic("Read from i8237 channel 1 remaining "
+ "word count unimplemented.\n");
+ case 0x4:
+ panic("Read from i8237 channel 2 current address unimplemented.\n");
+ case 0x5:
+ panic("Read from i8237 channel 2 remaining "
+ "word count unimplemented.\n");
+ case 0x6:
+ panic("Read from i8237 channel 3 current address unimplemented.\n");
+ case 0x7:
+ panic("Read from i8237 channel 3 remaining "
+ "word count unimplemented.\n");
+ case 0x8:
+ panic("Read from i8237 status register unimplemented.\n");
+ default:
+ panic("Read from undefined i8237 register %d.\n", offset);
+ }
+ return latency;
+}
+
+Tick
+X86ISA::I8237::write(PacketPtr pkt)
+{
+ assert(pkt->getSize() == 1);
+ Addr offset = pkt->getAddr() - pioAddr;
+ switch (offset) {
+ case 0x0:
+ panic("Write to i8237 channel 0 starting address unimplemented.\n");
+ case 0x1:
+ panic("Write to i8237 channel 0 starting "
+ "word count unimplemented.\n");
+ case 0x2:
+ panic("Write to i8237 channel 1 starting address unimplemented.\n");
+ case 0x3:
+ panic("Write to i8237 channel 1 starting "
+ "word count unimplemented.\n");
+ case 0x4:
+ panic("Write to i8237 channel 2 starting address unimplemented.\n");
+ case 0x5:
+ panic("Write to i8237 channel 2 starting "
+ "word count unimplemented.\n");
+ case 0x6:
+ panic("Write to i8237 channel 3 starting address unimplemented.\n");
+ case 0x7:
+ panic("Write to i8237 channel 3 starting "
+ "word count unimplemented.\n");
+ case 0x8:
+ panic("Write to i8237 command register unimplemented.\n");
+ case 0x9:
+ panic("Write to i8237 request register unimplemented.\n");
+ case 0xa:
+ {
+ uint8_t command = pkt->get<uint8_t>();
+ uint8_t select = bits(command, 1, 0);
+ uint8_t bitVal = bits(command, 2);
+ if (!bitVal)
+ panic("Turning on i8237 channels unimplemented.\n");
+ replaceBits(maskReg, select, bitVal);
+ }
+ break;
+ case 0xb:
+ panic("Write to i8237 mode register unimplemented.\n");
+ case 0xc:
+ panic("Write to i8237 clear LSB/MSB flip-flop "
+ "register unimplemented.\n");
+ case 0xd:
+ panic("Write to i8237 master clear/reset register unimplemented.\n");
+ case 0xe:
+ panic("Write to i8237 clear mask register unimplemented.\n");
+ case 0xf:
+ panic("Write to i8237 write all mask register bits unimplemented.\n");
+ default:
+ panic("Write to undefined i8254 register.\n");
+ }
+ return latency;
+}
+
+X86ISA::I8237 *
+I8237Params::create()
+{
+ return new X86ISA::I8237(this);
+}
diff --git a/src/dev/x86/i8237.hh b/src/dev/x86/i8237.hh
new file mode 100644
index 000000000..2d73b8ab5
--- /dev/null
+++ b/src/dev/x86/i8237.hh
@@ -0,0 +1,66 @@
+/*
+ * Copyright (c) 2008 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+#ifndef __DEV_X86_I8237_HH__
+#define __DEV_X86_I8237_HH__
+
+#include "dev/io_device.hh"
+#include "params/I8237.hh"
+
+namespace X86ISA
+{
+
+class I8237 : public BasicPioDevice
+{
+ protected:
+ Tick latency;
+ uint8_t maskReg;
+
+ public:
+ typedef I8237Params Params;
+
+ const Params *
+ params() const
+ {
+ return dynamic_cast<const Params *>(_params);
+ }
+
+ I8237(Params *p) : BasicPioDevice(p), latency(p->pio_latency), maskReg(0)
+ {
+ pioSize = 16;
+ }
+ Tick read(PacketPtr pkt);
+
+ Tick write(PacketPtr pkt);
+};
+
+}; // namespace X86ISA
+
+#endif //__DEV_X86_I8237_HH__