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authorSteve Reinhardt <stever@eecs.umich.edu>2007-06-28 08:28:58 -0700
committerSteve Reinhardt <stever@eecs.umich.edu>2007-06-28 08:28:58 -0700
commit7f3dfa7c09e0b708e1c873997f191d640751541d (patch)
tree2304f8219644b8a20db789fd3da70f50d9616867
parent9117c94f9c74f0674d75731385a106d17a1dee09 (diff)
parente28cbc98a0c1cc516f8086697f69db702bbe47de (diff)
downloadgem5-7f3dfa7c09e0b708e1c873997f191d640751541d.tar.xz
Merge vm1.(none):/home/stever/bk/newmem-head
into vm1.(none):/home/stever/bk/newmem-cache2 --HG-- extra : convert_revision : b1c954c187e3b3172a194396ba63808253121195
-rw-r--r--src/arch/mips/isa/formats/mem.isa4
-rwxr-xr-xsrc/cpu/o3/mips/dyn_inst.hh54
2 files changed, 54 insertions, 4 deletions
diff --git a/src/arch/mips/isa/formats/mem.isa b/src/arch/mips/isa/formats/mem.isa
index c8e85a754..81e231810 100644
--- a/src/arch/mips/isa/formats/mem.isa
+++ b/src/arch/mips/isa/formats/mem.isa
@@ -117,7 +117,7 @@ output exec {{
/** return data in cases where there the size of data is only
known in the packet
*/
- uint64_t getStoreData(Packet *packet) {
+ uint64_t getStoreData(%(CPU_exec_context)s *xc, Packet *packet) {
switch (packet->getSize())
{
case 8:
@@ -542,7 +542,7 @@ def template StoreCompleteAcc {{
if (fault == NoFault) {
%(op_wb)s;
- if (traceData) { traceData->setData(getStoreData(pkt)); }
+ if (traceData) { traceData->setData(getStoreData(xc, pkt)); }
}
return fault;
diff --git a/src/cpu/o3/mips/dyn_inst.hh b/src/cpu/o3/mips/dyn_inst.hh
index cf78c0941..7cd53413b 100755
--- a/src/cpu/o3/mips/dyn_inst.hh
+++ b/src/cpu/o3/mips/dyn_inst.hh
@@ -107,7 +107,7 @@ class MipsDynInst : public BaseDynInst<Impl>
/** Reads a misc. register, including any side-effects the read
* might have as defined by the architecture.
*/
- MiscReg readMiscReg(int misc_reg)
+ MiscReg readMiscReg(int misc_reg, unsigned tid = 0)
{
return this->cpu->readMiscReg(misc_reg, this->threadNumber);
}
@@ -122,12 +122,13 @@ class MipsDynInst : public BaseDynInst<Impl>
/** Sets a misc. register, including any side-effects the write
* might have as defined by the architecture.
*/
- void setMiscReg(int misc_reg, const MiscReg &val)
+ void setMiscReg(int misc_reg, const MiscReg &val, unsigned tid = 0)
{
return this->cpu->setMiscReg(misc_reg, val,
this->threadNumber);
}
+
/** Calls a syscall. */
void syscall(int64_t callnum);
@@ -206,6 +207,55 @@ class MipsDynInst : public BaseDynInst<Impl>
BaseDynInst<Impl>::setFloatRegOperandBits(si, idx, val);
}
+ /** Reads a miscellaneous register. */
+ TheISA::MiscReg readMiscRegOperandNoEffect(const StaticInst *si, int idx)
+ {
+ return this->cpu->readMiscRegNoEffect(
+ si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag,
+ this->threadNumber);
+ }
+
+ /** Reads a misc. register, including any side-effects the read
+ * might have as defined by the architecture.
+ */
+ TheISA::MiscReg readMiscRegOperand(const StaticInst *si, int idx)
+ {
+ return this->cpu->readMiscReg(
+ si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag,
+ this->threadNumber);
+ }
+
+ /** Sets a misc. register. */
+ void setMiscRegOperandNoEffect(const StaticInst * si, int idx, const MiscReg &val)
+ {
+ this->instResult.integer = val;
+ return this->cpu->setMiscRegNoEffect(
+ si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag,
+ val, this->threadNumber);
+ }
+
+ /** Sets a misc. register, including any side-effects the write
+ * might have as defined by the architecture.
+ */
+ void setMiscRegOperand(const StaticInst *si, int idx,
+ const MiscReg &val)
+ {
+ return this->cpu->setMiscReg(
+ si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag,
+ val, this->threadNumber);
+ }
+
+ uint64_t readRegOtherThread(int misc_reg)
+ {
+ panic("MIPS MT not defined for O3 CPU.\n");
+ return 0;
+ }
+
+ void setRegOtherThread(int misc_reg, const TheISA::MiscReg &val)
+ {
+ panic("MIPS MT not defined for O3 CPU.\n");
+ }
+
public:
/** Calculates EA part of a memory instruction. Currently unused,
* though it may be useful in the future if we want to split