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authorGiacomo Travaglini <giacomo.travaglini@arm.com>2018-03-27 16:22:31 +0100
committerGiacomo Travaglini <giacomo.travaglini@arm.com>2018-04-06 09:58:41 +0000
commit96bba0c50cda359b23365e3cb3a3f295796b06e4 (patch)
treeaf2a15f7121cfe9848b1c8d11b44668d111959cc
parent0fa5ed40c471429318c967833592aee0bd361dea (diff)
downloadgem5-96bba0c50cda359b23365e3cb3a3f295796b06e4.tar.xz
arch-arm: Fix secure write of SCTLR when EL3 is AArch64
MiscRegisters are not banked between secure and non-secure mode if EL3 is not implemented or if EL3 is using AArch64 (highestELIs64). In this scenario a unique register is used and it is mapped to the NS version (see snsBankedIndex implementation), so that a secure world read/write should access the non secure storage. Change-Id: Ica4182e3cdf4021d2bd1db23e477ce2bbf055926 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/9502 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
-rw-r--r--src/arch/arm/isa.cc10
1 files changed, 8 insertions, 2 deletions
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index d0dccdd3e..899cda9b5 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -952,8 +952,14 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
{
DPRINTF(MiscRegs, "Writing SCTLR: %#x\n", newVal);
scr = readMiscRegNoEffect(MISCREG_SCR);
- MiscRegIndex sctlr_idx = (haveSecurity && !scr.ns)
- ? MISCREG_SCTLR_S : MISCREG_SCTLR_NS;
+
+ MiscRegIndex sctlr_idx;
+ if (haveSecurity && !highestELIs64 && !scr.ns) {
+ sctlr_idx = MISCREG_SCTLR_S;
+ } else {
+ sctlr_idx = MISCREG_SCTLR_NS;
+ }
+
SCTLR sctlr = miscRegs[sctlr_idx];
SCTLR new_sctlr = newVal;
new_sctlr.nmfi = ((bool)sctlr.nmfi) && !haveVirtualization;