Merged with Gabe's recent changes.

41 files changed, 895 insertions, 1282 deletions

diff --git a/src/arch/alpha/isa/main.isa b/src/arch/alpha/isa/main.isa
index 4b5678e81..c03a99970 100644
--- a/src/arch/alpha/isa/main.isa
+++ b/src/arch/alpha/isa/main.isa
@@ -73,6 +73,7 @@ output exec {{
 
 #include "arch/alpha/registers.hh"
 #include "arch/alpha/regredir.hh"
+#include "arch/generic/memhelpers.hh"
 #include "base/cp_annotate.hh"
 #include "base/fenv.hh"
 #include "config/ss_compatible_fp.hh"
diff --git a/src/arch/alpha/isa/mem.isa b/src/arch/alpha/isa/mem.isa
index fe72e049e..ed5128204 100644
--- a/src/arch/alpha/isa/mem.isa
+++ b/src/arch/alpha/isa/mem.isa
@@ -197,7 +197,7 @@ def template LoadExecute {{
         %(ea_code)s;
 
         if (fault == NoFault) {
-            fault = xc->read(EA, (uint%(mem_acc_size)d_t&)Mem, memAccessFlags);
+            fault = readMemAtomic(xc, traceData, EA, Mem, memAccessFlags);
             %(memacc_code)s;
         }
 
@@ -223,7 +223,7 @@ def template LoadInitiateAcc {{
         %(ea_code)s;
 
         if (fault == NoFault) {
-            fault = xc->read(EA, (uint%(mem_acc_size)d_t &)Mem, memAccessFlags);
+            fault = readMemTiming(xc, traceData, EA, Mem, memAccessFlags);
         }
 
         return fault;
@@ -241,7 +241,7 @@ def template LoadCompleteAcc {{
         %(fp_enable_check)s;
         %(op_decl)s;
 
-        Mem = pkt->get<typeof(Mem)>();
+        getMem(pkt, Mem, traceData);
 
         if (fault == NoFault) {
             %(memacc_code)s;
@@ -273,8 +273,8 @@ def template StoreExecute {{
         }
 
         if (fault == NoFault) {
-            fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
-                              memAccessFlags, NULL);
+            fault = writeMemAtomic(xc, traceData, Mem, EA,
+                    memAccessFlags, NULL);
         }
 
         if (fault == NoFault) {
@@ -307,8 +307,8 @@ def template StoreCondExecute {{
         }
 
         if (fault == NoFault) {
-            fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
-                              memAccessFlags, &write_result);
+            fault = writeMemAtomic(xc, traceData, Mem, EA,
+                    memAccessFlags, &write_result);
         }
 
         if (fault == NoFault) {
@@ -340,8 +340,8 @@ def template StoreInitiateAcc {{
         }
 
         if (fault == NoFault) {
-            fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
-                              memAccessFlags, NULL);
+            fault = writeMemTiming(xc, traceData, Mem, EA,
+                    memAccessFlags, NULL);
         }
 
         return fault;
diff --git a/src/arch/arm/isa/includes.isa b/src/arch/arm/isa/includes.isa
index b54545e10..bfd6fedd4 100644
--- a/src/arch/arm/isa/includes.isa
+++ b/src/arch/arm/isa/includes.isa
@@ -80,6 +80,7 @@ output exec {{
 #include "arch/arm/faults.hh"
 #include "arch/arm/isa_traits.hh"
 #include "arch/arm/utility.hh"
+#include "arch/generic/memhelpers.hh"
 #include "base/condcodes.hh"
 #include "sim/pseudo_inst.hh"
 #if defined(linux)
diff --git a/src/arch/arm/isa/templates/mem.isa b/src/arch/arm/isa/templates/mem.isa
index cb255feda..a00114409 100644
--- a/src/arch/arm/isa/templates/mem.isa
+++ b/src/arch/arm/isa/templates/mem.isa
@@ -87,8 +87,8 @@ def template SwapExecute {{
             %(preacc_code)s;
 
             if (fault == NoFault) {
-                fault = xc->write((uint%(mem_acc_size)d_t&)Mem,
-                        EA, memAccessFlags, &memData);
+                fault = writeMemAtomic(xc, traceData, Mem, EA, memAccessFlags,
+                        &memData);
             }
 
             if (fault == NoFault) {
@@ -123,8 +123,8 @@ def template SwapInitiateAcc {{
             %(preacc_code)s;
 
             if (fault == NoFault) {
-                fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
-                                  memAccessFlags, &memData);
+                fault = writeMemTiming(xc, traceData, Mem, EA, memAccessFlags,
+                        &memData);
             }
         } else {
             xc->setPredicate(false);
@@ -147,7 +147,8 @@ def template SwapCompleteAcc {{
         if (%(predicate_test)s)
         {
             // ARM instructions will not have a pkt if the predicate is false
-            uint64_t memData = pkt->get<typeof(Mem)>();
+            getMem(pkt, Mem, traceData);
+            uint64_t memData = Mem;
 
             %(postacc_code)s;
 
@@ -174,7 +175,7 @@ def template LoadExecute {{
         if (%(predicate_test)s)
         {
             if (fault == NoFault) {
-                fault = xc->read(EA, (uint%(mem_acc_size)d_t&)Mem, memAccessFlags);
+                fault = readMemAtomic(xc, traceData, EA, Mem, memAccessFlags);
                 %(memacc_code)s;
             }
 
@@ -208,7 +209,7 @@ def template NeonLoadExecute {{
         if (%(predicate_test)s)
         {
             if (fault == NoFault) {
-                fault = xc->readBytes(EA, dataPtr, %(size)d, memAccessFlags);
+                fault = xc->readMem(EA, dataPtr, %(size)d, memAccessFlags);
                 %(memacc_code)s;
             }
 
@@ -241,8 +242,8 @@ def template StoreExecute {{
             }
 
             if (fault == NoFault) {
-                fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
-                                  memAccessFlags, NULL);
+                fault = writeMemAtomic(xc, traceData, Mem, EA,
+                        memAccessFlags, NULL);
             }
 
             if (fault == NoFault) {
@@ -279,8 +280,8 @@ def template NeonStoreExecute {{
             }
 
             if (fault == NoFault) {
-                fault = xc->writeBytes(dataPtr, %(size)d, EA,
-                                       memAccessFlags, NULL);
+                fault = xc->writeMem(dataPtr, %(size)d, EA,
+                                     memAccessFlags, NULL);
             }
 
             if (fault == NoFault) {
@@ -314,8 +315,8 @@ def template StoreExExecute {{
             uint64_t writeResult;
 
             if (fault == NoFault) {
-                fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
-                                  memAccessFlags, &writeResult);
+                fault = writeMemAtomic(xc, traceData, Mem, EA, memAccessFlags,
+                        &writeResult);
             }
 
             if (fault == NoFault) {
@@ -351,8 +352,8 @@ def template StoreExInitiateAcc {{
             }
 
             if (fault == NoFault) {
-                fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
-                                  memAccessFlags, NULL);
+                fault = writeMemTiming(xc, traceData, Mem, EA, memAccessFlags,
+                        NULL);
             }
         } else {
             xc->setPredicate(false);
@@ -380,8 +381,8 @@ def template StoreInitiateAcc {{
             }
 
             if (fault == NoFault) {
-                fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
-                                  memAccessFlags, NULL);
+                fault = writeMemTiming(xc, traceData, Mem, EA, memAccessFlags,
+                        NULL);
             }
         } else {
             xc->setPredicate(false);
@@ -412,8 +413,8 @@ def template NeonStoreInitiateAcc {{
             }
 
             if (fault == NoFault) {
-                fault = xc->writeBytes(memUnion.bytes, %(size)d, EA,
-                                       memAccessFlags, NULL);
+                fault = xc->writeMem(memUnion.bytes, %(size)d, EA,
+                                     memAccessFlags, NULL);
             }
         } else {
             xc->setPredicate(false);
@@ -437,7 +438,7 @@ def template LoadInitiateAcc {{
         if (%(predicate_test)s)
         {
             if (fault == NoFault) {
-                fault = xc->read(EA, (uint%(mem_acc_size)d_t &)Mem, memAccessFlags);
+                fault = readMemTiming(xc, traceData, EA, Mem, memAccessFlags);
             }
         } else {
             xc->setPredicate(false);
@@ -466,7 +467,7 @@ def template NeonLoadInitiateAcc {{
         if (%(predicate_test)s)
         {
             if (fault == NoFault) {
-                fault = xc->readBytes(EA, dataPtr, %(size)d, memAccessFlags);
+                fault = xc->readMem(EA, dataPtr, %(size)d, memAccessFlags);
             }
         } else {
             xc->setPredicate(false);
@@ -489,7 +490,7 @@ def template LoadCompleteAcc {{
         if (%(predicate_test)s)
         {
             // ARM instructions will not have a pkt if the predicate is false
-            Mem = pkt->get<typeof(Mem)>();
+            getMem(pkt, Mem, traceData);
 
             if (fault == NoFault) {
                 %(memacc_code)s;
diff --git a/src/arch/generic/memhelpers.hh b/src/arch/generic/memhelpers.hh
new file mode 100644
index 000000000..c753aaf2a
--- /dev/null
+++ b/src/arch/generic/memhelpers.hh
@@ -0,0 +1,100 @@
+/*
+ * Copyright (c) 2011 Google
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+#ifndef __ARCH_GENERIC_MEMHELPERS_HH__
+#define __ARCH_GENERIC_MEMHELPERS_HH__
+
+#include "base/types.hh"
+#include "sim/byteswap.hh"
+#include "sim/fault_fwd.hh"
+#include "sim/insttracer.hh"
+
+/// Read from memory in timing mode.
+template <class XC, class MemT>
+Fault
+readMemTiming(XC *xc, Trace::InstRecord *traceData, Addr addr,
+        MemT &mem, unsigned flags)
+{
+    return xc->readMem(addr, (uint8_t *)&mem, sizeof(MemT), flags);
+}
+
+/// Extract the data returned from a timing mode read.
+template <class MemT>
+void
+getMem(PacketPtr pkt, MemT &mem, Trace::InstRecord *traceData)
+{
+    mem = pkt->get<MemT>();
+    if (traceData)
+        traceData->setData(mem);
+}
+
+/// Read from memory in atomic mode.
+template <class XC, class MemT>
+Fault
+readMemAtomic(XC *xc, Trace::InstRecord *traceData, Addr addr, MemT &mem,
+        unsigned flags)
+{
+    memset(&mem, 0, sizeof(mem));
+    Fault fault = readMemTiming(xc, traceData, addr, mem, flags);
+    if (fault == NoFault) {
+        mem = gtoh(mem);
+        if (traceData)
+            traceData->setData(mem);
+    }
+    return fault;
+}
+
+/// Write to memory in timing mode.
+template <class XC, class MemT>
+Fault
+writeMemTiming(XC *xc, Trace::InstRecord *traceData, MemT mem, Addr addr,
+        unsigned flags, uint64_t *res)
+{
+    if (traceData) {
+        traceData->setData(mem);
+    }
+    mem = TheISA::htog(mem);
+    return xc->writeMem((uint8_t *)&mem, sizeof(MemT), addr, flags, res);
+}
+
+/// Write to memory in atomic mode.
+template <class XC, class MemT>
+Fault
+writeMemAtomic(XC *xc, Trace::InstRecord *traceData, const MemT &mem,
+        Addr addr, unsigned flags, uint64_t *res)
+{
+    Fault fault = writeMemTiming(xc, traceData, mem, addr, flags, res);
+    if (fault == NoFault && res != NULL) {
+        *res = gtoh((MemT)*res);
+    }
+    return fault;
+}
+
+#endif
diff --git a/src/arch/mips/isa/formats/mem.isa b/src/arch/mips/isa/formats/mem.isa
index c4666e4ab..bc3a2b3ce 100644
--- a/src/arch/mips/isa/formats/mem.isa
+++ b/src/arch/mips/isa/formats/mem.isa
@@ -216,7 +216,7 @@ def template LoadExecute {{
         %(ea_code)s;
 
         if (fault == NoFault) {
-            fault = xc->read(EA, (uint%(mem_acc_size)d_t&)Mem, memAccessFlags);
+            fault = readMemAtomic(xc, traceData, EA, Mem, memAccessFlags);
             %(memacc_code)s;
         }
 
@@ -248,7 +248,7 @@ def template LoadInitiateAcc {{
         %(ea_code)s;
 
         if (fault == NoFault) {
-            fault = xc->read(EA, (uint%(mem_acc_size)d_t &)Mem, memAccessFlags);
+            fault = readMemTiming(xc, traceData, EA, Mem, memAccessFlags);
         }
 
         return fault;
@@ -272,7 +272,7 @@ def template LoadCompleteAcc {{
         %(op_decl)s;
         %(op_rd)s;
 
-        Mem = pkt->get<typeof(Mem)>();
+        getMem(pkt, Mem, traceData);
 
         if (fault == NoFault) {
             %(memacc_code)s;
@@ -303,8 +303,8 @@ def template StoreExecute {{
         }
 
         if (fault == NoFault) {
-            fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
-                              memAccessFlags, NULL);
+            fault = writeMemAtomic(xc, traceData, Mem, EA, memAccessFlags,
+                    NULL);
         }
 
         if (fault == NoFault) {
@@ -339,8 +339,8 @@ def template StoreFPExecute {{
         }
 
         if (fault == NoFault) {
-            fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
-                              memAccessFlags, NULL);
+            fault = writeMemAtomic(xc, traceData, Mem, EA, memAccessFlags,
+                    NULL);
         }
 
         if (fault == NoFault) {
@@ -373,8 +373,8 @@ def template StoreCondExecute {{
         }
 
         if (fault == NoFault) {
-            fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
-                              memAccessFlags, &write_result);
+            fault = writeMemAtomic(xc, traceData, Mem, EA, memAccessFlags,
+                    &write_result);
         }
 
         if (fault == NoFault) {
@@ -406,8 +406,8 @@ def template StoreInitiateAcc {{
         }
 
         if (fault == NoFault) {
-            fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
-                              memAccessFlags, NULL);
+            fault = writeMemTiming(xc, traceData, Mem, EA, memAccessFlags,
+                    NULL);
         }
 
         return fault;
@@ -559,14 +559,15 @@ def format LoadUnalignedMemory(memacc_code, ea_code = {{ EA = (Rs + disp) & ~3;
 
 def format StoreUnalignedMemory(memacc_code, ea_code = {{ EA = (Rs + disp) & ~3; }},
                      mem_flags = [], inst_flags = []) {{
-    decl_code = 'uint32_t mem_word = 0;\n'
-    decl_code += 'uint32_t unaligned_addr = Rs + disp;\n'
-    decl_code += 'uint32_t byte_offset = unaligned_addr & 3;\n'
-    decl_code += '#if BYTE_ORDER == BIG_ENDIAN\n'
-    decl_code += '\tbyte_offset ^= 3;\n'
-    decl_code += '#endif\n'
-    decl_code += 'fault = xc->read(EA, (uint32_t&)mem_word, memAccessFlags);\n'
-    #decl_code += 'xc->readFunctional(EA,(uint32_t&)mem_word);'
+    decl_code = '''
+        uint32_t mem_word = 0;
+        uint32_t unaligned_addr = Rs + disp;
+        uint32_t byte_offset = unaligned_addr & 3;
+        #if BYTE_ORDER == BIG_ENDIAN
+            byte_offset ^= 3;
+        #endif
+        fault = readMemAtomic(xc, traceData, EA, mem_word, memAccessFlags);
+    '''
     memacc_code = decl_code + memacc_code + '\nMem = mem_word;\n'
 
     (header_output, decoder_output, decode_block, exec_output) = \
diff --git a/src/arch/mips/isa/includes.isa b/src/arch/mips/isa/includes.isa
index 73d751f6e..9c1183839 100644
--- a/src/arch/mips/isa/includes.isa
+++ b/src/arch/mips/isa/includes.isa
@@ -68,6 +68,7 @@ using namespace MipsISA;
 output exec {{
 #include <math.h>
 
+#include "arch/generic/memhelpers.hh"
 #include "arch/mips/dsp.hh"
 #include "arch/mips/dt_constants.hh"
 #include "arch/mips/faults.hh"
diff --git a/src/arch/power/isa/formats/mem.isa b/src/arch/power/isa/formats/mem.isa
index 014e4ff5a..519275a16 100644
--- a/src/arch/power/isa/formats/mem.isa
+++ b/src/arch/power/isa/formats/mem.isa
@@ -84,7 +84,7 @@ def template LoadExecute {{
         %(ea_code)s;
 
         if (fault == NoFault) {
-            fault = xc->read(EA, (uint%(mem_acc_size)d_t&)Mem, memAccessFlags);
+            fault = readMemAtomic(xc, traceData, EA, Mem, memAccessFlags);
             %(memacc_code)s;
         }
 
@@ -109,7 +109,7 @@ def template LoadInitiateAcc {{
         %(ea_code)s;
 
         if (fault == NoFault) {
-            fault = xc->read(EA, (uint%(mem_acc_size)d_t &)Mem, memAccessFlags);
+            fault = readMemTiming(xc, traceData, EA, Mem, memAccessFlags);
             xc->setEA(EA);
         }
 
@@ -132,7 +132,7 @@ def template LoadCompleteAcc {{
 
         EA = xc->getEA();
 
-        val = pkt->get<uint%(mem_acc_size)d_t>();
+        getMem(pkt, val, traceData);
         *((uint%(mem_acc_size)d_t*)&Mem) = val;
 
         if (fault == NoFault) {
@@ -164,8 +164,8 @@ def template StoreExecute {{
         }
 
         if (fault == NoFault) {
-            fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
-                              memAccessFlags, NULL);
+            fault = writeMemAtomic(xc, traceData, Mem, EA, memAccessFlags,
+                    NULL);
         }
 
         if (fault == NoFault) {
@@ -193,8 +193,8 @@ def template StoreInitiateAcc {{
         }
 
         if (fault == NoFault) {
-            fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
-                              memAccessFlags, NULL);
+            fault = writeMemTiming(xc, traceData, Mem, EA, memAccessFlags,
+                    NULL);
         }
 
         // Need to write back any potential address register update
diff --git a/src/arch/power/isa/includes.isa b/src/arch/power/isa/includes.isa
index 5c2b74141..f6292eaab 100644
--- a/src/arch/power/isa/includes.isa
+++ b/src/arch/power/isa/includes.isa
@@ -75,6 +75,7 @@ output exec {{
 #include <fenv.h>
 #endif
 
+#include "arch/generic/memhelpers.hh"
 #include "arch/power/faults.hh"
 #include "arch/power/isa_traits.hh"
 #include "arch/power/utility.hh"
diff --git a/src/arch/sparc/isa/formats/mem/swap.isa b/src/arch/sparc/isa/formats/mem/swap.isa
index 99bbf3a68..17a490c4b 100644
--- a/src/arch/sparc/isa/formats/mem/swap.isa
+++ b/src/arch/sparc/isa/formats/mem/swap.isa
@@ -50,8 +50,8 @@ def template SwapExecute {{
             }
             if (storeCond && fault == NoFault) {
                 %(EA_trunc)s
-                fault = xc->write((uint%(mem_acc_size)s_t)Mem,
-                        EA, %(asi_val)s, &mem_data);
+                fault = writeMemAtomic(xc, traceData, Mem, EA,
+                        %(asi_val)s, &mem_data);
             }
             if (fault == NoFault) {
                 // Handle the swapping
@@ -87,8 +87,8 @@ def template SwapInitiateAcc {{
             }
             if (fault == NoFault) {
                 %(EA_trunc)s
-                fault = xc->write((uint%(mem_acc_size)s_t)Mem,
-                        EA, %(asi_val)s, &mem_data);
+                fault = writeMemTiming(xc, traceData, Mem, EA, %(asi_val)s,
+                        &mem_data);
             }
             return fault;
         }
@@ -103,7 +103,8 @@ def template SwapCompleteAcc {{
             Fault fault = NoFault;
             %(op_decl)s;
 
-            uint64_t mem_data = pkt->get<uint%(mem_acc_size)s_t>();
+            getMem(pkt, Mem, traceData);
+            uint64_t mem_data = Mem;
 
             if (fault == NoFault) {
                 // Handle the swapping
diff --git a/src/arch/sparc/isa/formats/mem/util.isa b/src/arch/sparc/isa/formats/mem/util.isa
index aaa04b4bf..06206c02b 100644
--- a/src/arch/sparc/isa/formats/mem/util.isa
+++ b/src/arch/sparc/isa/formats/mem/util.isa
@@ -143,7 +143,7 @@ def template LoadExecute {{
             %(fault_check)s;
             if (fault == NoFault) {
                 %(EA_trunc)s
-                fault = xc->read(EA, (%(mem_acc_type)s%(mem_acc_size)s_t&)Mem, %(asi_val)s);
+                fault = readMemAtomic(xc, traceData, EA, Mem, %(asi_val)s);
             }
             if (fault == NoFault) {
                 %(code)s;
@@ -171,7 +171,7 @@ def template LoadInitiateAcc {{
             %(fault_check)s;
             if (fault == NoFault) {
                 %(EA_trunc)s
-                fault = xc->read(EA, (%(mem_acc_type)s%(mem_acc_size)s_t&)Mem, %(asi_val)s);
+                fault = readMemTiming(xc, traceData, EA, Mem, %(asi_val)s);
             }
             return fault;
         }
@@ -184,7 +184,7 @@ def template LoadCompleteAcc {{
             Fault fault = NoFault;
             %(op_decl)s;
             %(op_rd)s;
-            Mem = pkt->get<typeof(Mem)>();
+            getMem(pkt, Mem, traceData);
             %(code)s;
             if (fault == NoFault) {
                 %(op_wb)s;
@@ -214,8 +214,7 @@ def template StoreExecute {{
             }
             if (storeCond && fault == NoFault) {
                 %(EA_trunc)s
-                fault = xc->write((%(mem_acc_type)s%(mem_acc_size)s_t)Mem,
-                        EA, %(asi_val)s, 0);
+                fault = writeMemAtomic(xc, traceData, Mem, EA, %(asi_val)s, 0);
             }
             if (fault == NoFault) {
                 // Write the resulting state to the execution context
@@ -245,8 +244,7 @@ def template StoreInitiateAcc {{
             }
             if (storeCond && fault == NoFault) {
                 %(EA_trunc)s
-                fault = xc->write((%(mem_acc_type)s%(mem_acc_size)s_t)Mem,
-                        EA, %(asi_val)s, 0);
+                fault = writeMemTiming(xc, traceData, Mem, EA, %(asi_val)s, 0);
             }
             return fault;
         }
diff --git a/src/arch/sparc/isa/includes.isa b/src/arch/sparc/isa/includes.isa
index 885cd9cc2..db3677752 100644
--- a/src/arch/sparc/isa/includes.isa
+++ b/src/arch/sparc/isa/includes.isa
@@ -70,6 +70,7 @@ output exec {{
 #include <cmath>
 #include <limits>
 
+#include "arch/generic/memhelpers.hh"
 #include "arch/sparc/asi.hh"
 #include "base/bigint.hh"
 #include "cpu/base.hh"
diff --git a/src/arch/x86/insts/microldstop.hh b/src/arch/x86/insts/microldstop.hh
index 5487655e2..c618bc128 100644
--- a/src/arch/x86/insts/microldstop.hh
+++ b/src/arch/x86/insts/microldstop.hh
@@ -97,73 +97,6 @@ namespace X86ISA
 
         std::string generateDisassembly(Addr pc,
             const SymbolTable *symtab) const;
-
-        template<class Context, class MemType>
-        Fault read(Context *xc, Addr EA, MemType & Mem, unsigned flags) const
-        {
-            Fault fault = NoFault;
-            switch(dataSize)
-            {
-              case 1:
-                fault = xc->read(EA, (uint8_t&)Mem, flags);
-                break;
-              case 2:
-                fault = xc->read(EA, (uint16_t&)Mem, flags);
-                break;
-              case 4:
-                fault = xc->read(EA, (uint32_t&)Mem, flags);
-                break;
-              case 8:
-                fault = xc->read(EA, (uint64_t&)Mem, flags);
-                break;
-              default:
-                panic("Bad operand size %d for read at %#x.\n", dataSize, EA);
-            }
-            return fault;
-        }
-
-        template<class Context, class MemType>
-        Fault write(Context *xc, MemType & Mem, Addr EA, unsigned flags) const
-        {
-            Fault fault = NoFault;
-            switch(dataSize)
-            {
-              case 1:
-                fault = xc->write((uint8_t&)Mem, EA, flags, 0);
-                break;
-              case 2:
-                fault = xc->write((uint16_t&)Mem, EA, flags, 0);
-                break;
-              case 4:
-                fault = xc->write((uint32_t&)Mem, EA, flags, 0);
-                break;
-              case 8:
-                fault = xc->write((uint64_t&)Mem, EA, flags, 0);
-                break;
-              default:
-                panic("Bad operand size %d for write at %#x.\n", dataSize, EA);
-            }
-            return fault;
-        }
-
-        uint64_t
-        get(PacketPtr pkt) const
-        {
-            switch(dataSize)
-            {
-              case 1:
-                return pkt->get<uint8_t>();
-              case 2:
-                return pkt->get<uint16_t>();
-              case 4:
-                return pkt->get<uint32_t>();
-              case 8:
-                return pkt->get<uint64_t>();
-              default:
-                panic("Bad operand size %d for read at %#x.\n",
-                        dataSize, pkt->getAddr());
-            }
-        }
     };
 }
 
diff --git a/src/arch/x86/isa/includes.isa b/src/arch/x86/isa/includes.isa
index 8d4af6829..dc8abbc66 100644
--- a/src/arch/x86/isa/includes.isa
+++ b/src/arch/x86/isa/includes.isa
@@ -112,6 +112,7 @@ output exec {{
 #include "arch/x86/regs/misc.hh"
 #include "arch/x86/cpuid.hh"
 #include "arch/x86/faults.hh"
+#include "arch/x86/memhelpers.hh"
 #include "arch/x86/tlb.hh"
 #include "base/bigint.hh"
 #include "base/compiler.hh"
diff --git a/src/arch/x86/isa/microops/ldstop.isa b/src/arch/x86/isa/microops/ldstop.isa
index 811b35c8a..c88161f34 100644
--- a/src/arch/x86/isa/microops/ldstop.isa
+++ b/src/arch/x86/isa/microops/ldstop.isa
@@ -98,7 +98,7 @@ def template MicroLoadExecute {{
         %(ea_code)s;
         DPRINTF(X86, "%s : %s: The address is %#x\n", instMnem, mnemonic, EA);
 
-        fault = read(xc, EA, Mem, memFlags);
+        fault = readMemAtomic(xc, traceData, EA, Mem, dataSize, memFlags);
 
         if (fault == NoFault) {
             %(code)s;
@@ -127,7 +127,7 @@ def template MicroLoadInitiateAcc {{
         %(ea_code)s;
         DPRINTF(X86, "%s : %s: The address is %#x\n", instMnem, mnemonic, EA);
 
-        fault = read(xc, EA, Mem, memFlags);
+        fault = readMemTiming(xc, traceData, EA, Mem, dataSize, memFlags);
 
         return fault;
     }
@@ -143,7 +143,7 @@ def template MicroLoadCompleteAcc {{
         %(op_decl)s;
         %(op_rd)s;
 
-        Mem = get(pkt);
+        Mem = getMem(pkt, dataSize, traceData);
 
         %(code)s;
 
@@ -174,7 +174,8 @@ def template MicroStoreExecute {{
 
         if(fault == NoFault)
         {
-            fault = write(xc, Mem, EA, memFlags);
+            fault = writeMemAtomic(xc, traceData, Mem, dataSize, EA,
+                    memFlags, NULL);
             if(fault == NoFault)
             {
                 %(op_wb)s;
@@ -201,7 +202,8 @@ def template MicroStoreInitiateAcc {{
 
         if(fault == NoFault)
         {
-            write(xc, Mem, EA, memFlags);
+            fault = writeMemTiming(xc, traceData, Mem, dataSize, EA,
+                    memFlags, NULL);
         }
         return fault;
     }
diff --git a/src/arch/x86/memhelpers.hh b/src/arch/x86/memhelpers.hh
new file mode 100644
index 000000000..43612c9be
--- /dev/null
+++ b/src/arch/x86/memhelpers.hh
@@ -0,0 +1,120 @@
+/*
+ * Copyright (c) 2011 Google
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+#ifndef __ARCH_X86_MEMHELPERS_HH__
+#define __ARCH_X86_MEMHELPERS_HH__
+
+#include "base/types.hh"
+#include "sim/byteswap.hh"
+#include "sim/fault_fwd.hh"
+#include "sim/insttracer.hh"
+
+namespace X86ISA
+{
+
+template <class XC>
+Fault
+readMemTiming(XC *xc, Trace::InstRecord *traceData, Addr addr,
+        uint64_t &mem, unsigned dataSize, unsigned flags)
+{
+    return xc->readMem(addr, (uint8_t *)&mem, dataSize, flags);
+}
+
+static inline uint64_t
+getMem(PacketPtr pkt, unsigned dataSize, Trace::InstRecord *traceData)
+{
+    uint64_t mem;
+    switch (dataSize) {
+      case 1:
+        mem = pkt->get<uint8_t>();
+        break;
+      case 2:
+        mem = pkt->get<uint16_t>();
+        break;
+      case 4:
+        mem = pkt->get<uint32_t>();
+        break;
+      case 8:
+        mem = pkt->get<uint64_t>();
+        break;
+      default:
+        panic("Unhandled size in getMem.\n");
+    }
+    if (traceData)
+        traceData->setData(mem);
+    return mem;
+}
+
+template <class XC>
+Fault
+readMemAtomic(XC *xc, Trace::InstRecord *traceData, Addr addr, uint64_t &mem,
+        unsigned dataSize, unsigned flags)
+{
+    memset(&mem, 0, sizeof(mem));
+    Fault fault = readMemTiming(xc, traceData, addr, mem, dataSize, flags);
+    if (fault == NoFault) {
+        // If LE to LE, this is a nop, if LE to BE, the actual data ends up
+        // in the right place because the LSBs where at the low addresses on
+        // access. This doesn't work for BE guests.
+        mem = gtoh(mem);
+        if (traceData)
+            traceData->setData(mem);
+    }
+    return fault;
+}
+
+template <class XC>
+Fault
+writeMemTiming(XC *xc, Trace::InstRecord *traceData, uint64_t mem,
+        unsigned dataSize, Addr addr, unsigned flags, uint64_t *res)
+{
+    if (traceData) {
+        traceData->setData(mem);
+    }
+    mem = TheISA::htog(mem);
+    return xc->writeMem((uint8_t *)&mem, dataSize, addr, flags, res);
+}
+
+template <class XC>
+Fault
+writeMemAtomic(XC *xc, Trace::InstRecord *traceData, uint64_t mem,
+        unsigned dataSize, Addr addr, unsigned flags, uint64_t *res)
+{
+    Fault fault = writeMemTiming(xc, traceData, mem, dataSize, addr, flags,
+            res);
+    if (fault == NoFault && res != NULL) {
+        *res = gtoh(*res);
+    }
+    return fault;
+}
+
+}
+
+#endif
diff --git a/src/cpu/base_dyn_inst.hh b/src/cpu/base_dyn_inst.hh
index 4c7abe376..f0d36cc83 100644
--- a/src/cpu/base_dyn_inst.hh
+++ b/src/cpu/base_dyn_inst.hh
@@ -124,31 +124,10 @@ class BaseDynInst : public FastAlloc, public RefCounted
         cpu->demapPage(vaddr, asn);
     }
 
-    /**
-     * Does a read to a given address.
-     * @param addr The address to read.
-     * @param data The read's data is written into this parameter.
-     * @param flags The request's flags.
-     * @return Returns any fault due to the read.
-     */
-    template <class T>
-    Fault read(Addr addr, T &data, unsigned flags);
-
-    Fault readBytes(Addr addr, uint8_t *data, unsigned size, unsigned flags);
-
-    /**
-     * Does a write to a given address.
-     * @param data The data to be written.
-     * @param addr The address to write to.
-     * @param flags The request's flags.
-     * @param res The result of the write (for load locked/store conditionals).
-     * @return Returns any fault due to the write.
-     */
-    template <class T>
-    Fault write(T data, Addr addr, unsigned flags, uint64_t *res);
+    Fault readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags);
 
-    Fault writeBytes(uint8_t *data, unsigned size,
-                     Addr addr, unsigned flags, uint64_t *res);
+    Fault writeMem(uint8_t *data, unsigned size,
+                   Addr addr, unsigned flags, uint64_t *res);
 
     /** Splits a request in two if it crosses a dcache block. */
     void splitRequest(RequestPtr req, RequestPtr &sreqLow,
@@ -862,8 +841,8 @@ class BaseDynInst : public FastAlloc, public RefCounted
 
 template<class Impl>
 Fault
-BaseDynInst<Impl>::readBytes(Addr addr, uint8_t *data,
-                             unsigned size, unsigned flags)
+BaseDynInst<Impl>::readMem(Addr addr, uint8_t *data,
+                           unsigned size, unsigned flags)
 {
     reqMade = true;
     Request *req = NULL;
@@ -913,25 +892,9 @@ BaseDynInst<Impl>::readBytes(Addr addr, uint8_t *data,
 }
 
 template<class Impl>
-template<class T>
-inline Fault
-BaseDynInst<Impl>::read(Addr addr, T &data, unsigned flags)
-{
-    Fault fault = readBytes(addr, (uint8_t *)&data, sizeof(T), flags);
-
-    data = TheISA::gtoh(data);
-
-    if (traceData) {
-        traceData->setData(data);
-    }
-
-    return fault;
-}
-
-template<class Impl>
 Fault
-BaseDynInst<Impl>::writeBytes(uint8_t *data, unsigned size,
-                              Addr addr, unsigned flags, uint64_t *res)
+BaseDynInst<Impl>::writeMem(uint8_t *data, unsigned size,
+                            Addr addr, unsigned flags, uint64_t *res)
 {
     if (traceData) {
         traceData->setAddr(addr);
@@ -968,18 +931,6 @@ BaseDynInst<Impl>::writeBytes(uint8_t *data, unsigned size,
 }
 
 template<class Impl>
-template<class T>
-inline Fault
-BaseDynInst<Impl>::write(T data, Addr addr, unsigned flags, uint64_t *res)
-{
-    if (traceData) {
-        traceData->setData(data);
-    }
-    data = TheISA::htog(data);
-    return writeBytes((uint8_t *)&data, sizeof(T), addr, flags, res);
-}
-
-template<class Impl>
 inline void
 BaseDynInst<Impl>::splitRequest(RequestPtr req, RequestPtr &sreqLow,
                                 RequestPtr &sreqHigh)
diff --git a/src/cpu/exec_context.hh b/src/cpu/exec_context.hh
index a8704851f..61c9b24a9 100644
--- a/src/cpu/exec_context.hh
+++ b/src/cpu/exec_context.hh
@@ -106,21 +106,10 @@ class ExecContext {
     /** Returns a pointer to the ThreadContext. */
     ThreadContext *tcBase();
 
-    /** Reads an address, creating a memory request with the given
-     * flags.  Stores result of read in data. */
-    template <class T>
-    Fault read(Addr addr, T &data, unsigned flags);
+    Fault readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags);
 
-    Fault readBytes(Addr addr, uint8_t *data, unsigned size, unsigned flags);
-
-    /** Writes to an address, creating a memory request with the given
-     * flags.  Writes data to memory.  For store conditionals, returns
-     * the result of the store in res. */
-    template <class T>
-    Fault write(T data, Addr addr, unsigned flags, uint64_t *res);
-
-    Fault writeBytes(uint8_t *data, unsigned size,
-                     Addr addr, unsigned flags, uint64_t *res);
+    Fault writeMem(uint8_t *data, unsigned size,
+                   Addr addr, unsigned flags, uint64_t *res);
 
 #if FULL_SYSTEM
     /** Somewhat Alpha-specific function that handles returning from
diff --git a/src/cpu/inorder/inorder_dyn_inst.cc b/src/cpu/inorder/inorder_dyn_inst.cc
index a90c2cdb4..5343206c1 100644
--- a/src/cpu/inorder/inorder_dyn_inst.cc
+++ b/src/cpu/inorder/inorder_dyn_inst.cc
@@ -559,155 +559,19 @@ InOrderDynInst::deallocateContext(int thread_num)
 }
 
 Fault
-InOrderDynInst::readBytes(Addr addr, uint8_t *data,
-                          unsigned size, unsigned flags)
+InOrderDynInst::readMem(Addr addr, uint8_t *data,
+                        unsigned size, unsigned flags)
 {
     return cpu->read(this, addr, data, size, flags);
 }
 
-template<class T>
-inline Fault
-InOrderDynInst::read(Addr addr, T &data, unsigned flags)
-{
-    if (traceData) {
-        traceData->setAddr(addr);
-        traceData->setData(data);
-    }
-    Fault fault = readBytes(addr, (uint8_t *)&data, sizeof(T), flags);
-    //@todo: the below lines should be unnecessary, timing access
-    // wont have valid data right here
-    DPRINTF(InOrderDynInst, "[sn:%i] (1) Received Bytes %x\n", seqNum, data);
-    data = TheISA::gtoh(data);
-    DPRINTF(InOrderDynInst, "[sn%:i] (2) Received Bytes %x\n", seqNum, data);
-
-    if (traceData)
-        traceData->setData(data);
-    return fault;
-}
-
-#ifndef DOXYGEN_SHOULD_SKIP_THIS
-
-template
-Fault
-InOrderDynInst::read(Addr addr, Twin32_t &data, unsigned flags);
-
-template
-Fault
-InOrderDynInst::read(Addr addr, Twin64_t &data, unsigned flags);
-
-template
-Fault
-InOrderDynInst::read(Addr addr, uint64_t &data, unsigned flags);
-
-template
-Fault
-InOrderDynInst::read(Addr addr, uint32_t &data, unsigned flags);
-
-template
-Fault
-InOrderDynInst::read(Addr addr, uint16_t &data, unsigned flags);
-
-template
-Fault
-InOrderDynInst::read(Addr addr, uint8_t &data, unsigned flags);
-
-#endif //DOXYGEN_SHOULD_SKIP_THIS
-
-template<>
-Fault
-InOrderDynInst::read(Addr addr, double &data, unsigned flags)
-{
-    return read(addr, *(uint64_t*)&data, flags);
-}
-
-template<>
-Fault
-InOrderDynInst::read(Addr addr, float &data, unsigned flags)
-{
-    return read(addr, *(uint32_t*)&data, flags);
-}
-
-template<>
-Fault
-InOrderDynInst::read(Addr addr, int32_t &data, unsigned flags)
-{
-    return read(addr, (uint32_t&)data, flags);
-}
-
 Fault
-InOrderDynInst::writeBytes(uint8_t *data, unsigned size,
-                           Addr addr, unsigned flags, uint64_t *res)
+InOrderDynInst::writeMem(uint8_t *data, unsigned size,
+                         Addr addr, unsigned flags, uint64_t *res)
 {
     return cpu->write(this, data, size, addr, flags, res);
 }
 
-template<class T>
-inline Fault
-InOrderDynInst::write(T data, Addr addr, unsigned flags, uint64_t *res)
-{
-    if (traceData) {
-        traceData->setAddr(addr);
-        traceData->setData(data);
-    }
-    data = TheISA::htog(data);
-    return writeBytes((uint8_t*)&data, sizeof(T), addr, flags, res);
-}
-
-#ifndef DOXYGEN_SHOULD_SKIP_THIS
-
-template
-Fault
-InOrderDynInst::write(Twin32_t data, Addr addr,
-                      unsigned flags, uint64_t *res);
-
-template
-Fault
-InOrderDynInst::write(Twin64_t data, Addr addr,
-                      unsigned flags, uint64_t *res);
-template
-Fault
-InOrderDynInst::write(uint64_t data, Addr addr,
-                       unsigned flags, uint64_t *res);
-
-template
-Fault
-InOrderDynInst::write(uint32_t data, Addr addr,
-                       unsigned flags, uint64_t *res);
-
-template
-Fault
-InOrderDynInst::write(uint16_t data, Addr addr,
-                       unsigned flags, uint64_t *res);
-
-template
-Fault
-InOrderDynInst::write(uint8_t data, Addr addr,
-                       unsigned flags, uint64_t *res);
-
-#endif //DOXYGEN_SHOULD_SKIP_THIS
-
-template<>
-Fault
-InOrderDynInst::write(double data, Addr addr, unsigned flags, uint64_t *res)
-{
-    return write(*(uint64_t*)&data, addr, flags, res);
-}
-
-template<>
-Fault
-InOrderDynInst::write(float data, Addr addr, unsigned flags, uint64_t *res)
-{
-    return write(*(uint32_t*)&data, addr, flags, res);
-}
-
-
-template<>
-Fault
-InOrderDynInst::write(int32_t data, Addr addr, unsigned flags, uint64_t *res)
-{
-    return write((uint32_t)data, addr, flags, res);
-}
-
 
 void
 InOrderDynInst::dump()
diff --git a/src/cpu/inorder/inorder_dyn_inst.hh b/src/cpu/inorder/inorder_dyn_inst.hh
index 205bb0f82..ecaf23aab 100644
--- a/src/cpu/inorder/inorder_dyn_inst.hh
+++ b/src/cpu/inorder/inorder_dyn_inst.hh
@@ -612,32 +612,11 @@ class InOrderDynInst : public FastAlloc, public RefCounted
     // MEMORY ACCESS
     //
     ////////////////////////////////////////////
-    /**
-     * Does a read to a given address.
-     * @param addr The address to read.
-     * @param data The read's data is written into this parameter.
-     * @param flags The request's flags.
-     * @return Returns any fault due to the read.
-     */
-    template <class T>
-    Fault read(Addr addr, T &data, unsigned flags);
-
-    Fault readBytes(Addr addr, uint8_t *data, unsigned size, unsigned flags);
-
-    /**
-     * Does a write to a given address.
-     * @param data The data to be written.
-     * @param addr The address to write to.
-     * @param flags The request's flags.
-     * @param res The result of the write (for load locked/store conditionals).
-     * @return Returns any fault due to the write.
-     */
-    template <class T>
-    Fault write(T data, Addr addr, unsigned flags,
-                        uint64_t *res);
 
-    Fault writeBytes(uint8_t *data, unsigned size,
-                     Addr addr, unsigned flags, uint64_t *res);
+    Fault readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags);
+
+    Fault writeMem(uint8_t *data, unsigned size,
+                   Addr addr, unsigned flags, uint64_t *res);
 
     /** Initiates a memory access - Calculate Eff. Addr & Initiate Memory
      *  Access Only valid for memory operations.
diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc
index f3d79dd2b..5376519d4 100644
--- a/src/cpu/simple/atomic.cc
+++ b/src/cpu/simple/atomic.cc
@@ -299,8 +299,8 @@ AtomicSimpleCPU::suspendContext(int thread_num)
 
 
 Fault
-AtomicSimpleCPU::readBytes(Addr addr, uint8_t * data,
-                           unsigned size, unsigned flags)
+AtomicSimpleCPU::readMem(Addr addr, uint8_t * data,
+                         unsigned size, unsigned flags)
 {
     // use the CPU's statically allocated read request and packet objects
     Request *req = &data_read_req;
@@ -386,75 +386,9 @@ AtomicSimpleCPU::readBytes(Addr addr, uint8_t * data,
 }
 
 
-template <class T>
 Fault
-AtomicSimpleCPU::read(Addr addr, T &data, unsigned flags)
-{
-    uint8_t *dataPtr = (uint8_t *)&data;
-    memset(dataPtr, 0, sizeof(data));
-    Fault fault = readBytes(addr, dataPtr, sizeof(data), flags);
-    if (fault == NoFault) {
-        data = gtoh(data);
-        if (traceData)
-            traceData->setData(data);
-    }
-    return fault;
-}
-
-#ifndef DOXYGEN_SHOULD_SKIP_THIS
-
-template
-Fault
-AtomicSimpleCPU::read(Addr addr, Twin32_t &data, unsigned flags);
-
-template
-Fault
-AtomicSimpleCPU::read(Addr addr, Twin64_t &data, unsigned flags);
-
-template
-Fault
-AtomicSimpleCPU::read(Addr addr, uint64_t &data, unsigned flags);
-
-template
-Fault
-AtomicSimpleCPU::read(Addr addr, uint32_t &data, unsigned flags);
-
-template
-Fault
-AtomicSimpleCPU::read(Addr addr, uint16_t &data, unsigned flags);
-
-template
-Fault
-AtomicSimpleCPU::read(Addr addr, uint8_t &data, unsigned flags);
-
-#endif //DOXYGEN_SHOULD_SKIP_THIS
-
-template<>
-Fault
-AtomicSimpleCPU::read(Addr addr, double &data, unsigned flags)
-{
-    return read(addr, *(uint64_t*)&data, flags);
-}
-
-template<>
-Fault
-AtomicSimpleCPU::read(Addr addr, float &data, unsigned flags)
-{
-    return read(addr, *(uint32_t*)&data, flags);
-}
-
-
-template<>
-Fault
-AtomicSimpleCPU::read(Addr addr, int32_t &data, unsigned flags)
-{
-    return read(addr, (uint32_t&)data, flags);
-}
-
-
-Fault
-AtomicSimpleCPU::writeBytes(uint8_t *data, unsigned size,
-                            Addr addr, unsigned flags, uint64_t *res)
+AtomicSimpleCPU::writeMem(uint8_t *data, unsigned size,
+                          Addr addr, unsigned flags, uint64_t *res)
 {
     // use the CPU's statically allocated write request and packet objects
     Request *req = &data_write_req;
@@ -555,80 +489,6 @@ AtomicSimpleCPU::writeBytes(uint8_t *data, unsigned size,
 }
 
 
-template <class T>
-Fault
-AtomicSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
-{
-    uint8_t *dataPtr = (uint8_t *)&data;
-    if (traceData)
-        traceData->setData(data);
-    data = htog(data);
-
-    Fault fault = writeBytes(dataPtr, sizeof(data), addr, flags, res);
-    if (fault == NoFault && data_write_req.isSwap()) {
-        *res = gtoh((T)*res);
-    }
-    return fault;
-}
-
-
-#ifndef DOXYGEN_SHOULD_SKIP_THIS
-
-template
-Fault
-AtomicSimpleCPU::write(Twin32_t data, Addr addr,
-                       unsigned flags, uint64_t *res);
-
-template
-Fault
-AtomicSimpleCPU::write(Twin64_t data, Addr addr,
-                       unsigned flags, uint64_t *res);
-
-template
-Fault
-AtomicSimpleCPU::write(uint64_t data, Addr addr,
-                       unsigned flags, uint64_t *res);
-
-template
-Fault
-AtomicSimpleCPU::write(uint32_t data, Addr addr,
-                       unsigned flags, uint64_t *res);
-
-template
-Fault
-AtomicSimpleCPU::write(uint16_t data, Addr addr,
-                       unsigned flags, uint64_t *res);
-
-template
-Fault
-AtomicSimpleCPU::write(uint8_t data, Addr addr,
-                       unsigned flags, uint64_t *res);
-
-#endif //DOXYGEN_SHOULD_SKIP_THIS
-
-template<>
-Fault
-AtomicSimpleCPU::write(double data, Addr addr, unsigned flags, uint64_t *res)
-{
-    return write(*(uint64_t*)&data, addr, flags, res);
-}
-
-template<>
-Fault
-AtomicSimpleCPU::write(float data, Addr addr, unsigned flags, uint64_t *res)
-{
-    return write(*(uint32_t*)&data, addr, flags, res);
-}
-
-
-template<>
-Fault
-AtomicSimpleCPU::write(int32_t data, Addr addr, unsigned flags, uint64_t *res)
-{
-    return write((uint32_t)data, addr, flags, res);
-}
-
-
 void
 AtomicSimpleCPU::tick()
 {
diff --git a/src/cpu/simple/atomic.hh b/src/cpu/simple/atomic.hh
index 5ec1970e7..246afa0b2 100644
--- a/src/cpu/simple/atomic.hh
+++ b/src/cpu/simple/atomic.hh
@@ -131,16 +131,10 @@ class AtomicSimpleCPU : public BaseSimpleCPU
     virtual void activateContext(int thread_num, int delay);
     virtual void suspendContext(int thread_num);
 
-    template <class T>
-    Fault read(Addr addr, T &data, unsigned flags);
+    Fault readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags);
 
-    Fault readBytes(Addr addr, uint8_t *data, unsigned size, unsigned flags);
-
-    template <class T>
-    Fault write(T data, Addr addr, unsigned flags, uint64_t *res);
-
-    Fault writeBytes(uint8_t *data, unsigned size,
-                     Addr addr, unsigned flags, uint64_t *res);
+    Fault writeMem(uint8_t *data, unsigned size,
+                   Addr addr, unsigned flags, uint64_t *res);
 
     /**
      * Print state of address in memory system via PrintReq (for
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index 187b38b85..1c726ba57 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -432,8 +432,8 @@ TimingSimpleCPU::buildSplitPacket(PacketPtr &pkt1, PacketPtr &pkt2,
 }
 
 Fault
-TimingSimpleCPU::readBytes(Addr addr, uint8_t *data,
-                           unsigned size, unsigned flags)
+TimingSimpleCPU::readMem(Addr addr, uint8_t *data,
+                         unsigned size, unsigned flags)
 {
     Fault fault;
     const int asid = 0;
@@ -479,62 +479,6 @@ TimingSimpleCPU::readBytes(Addr addr, uint8_t *data,
     return NoFault;
 }
 
-template <class T>
-Fault
-TimingSimpleCPU::read(Addr addr, T &data, unsigned flags)
-{
-    return readBytes(addr, (uint8_t *)&data, sizeof(T), flags);
-}
-
-#ifndef DOXYGEN_SHOULD_SKIP_THIS
-
-template
-Fault
-TimingSimpleCPU::read(Addr addr, Twin64_t &data, unsigned flags);
-
-template
-Fault
-TimingSimpleCPU::read(Addr addr, Twin32_t &data, unsigned flags);
-
-template
-Fault
-TimingSimpleCPU::read(Addr addr, uint64_t &data, unsigned flags);
-
-template
-Fault
-TimingSimpleCPU::read(Addr addr, uint32_t &data, unsigned flags);
-
-template
-Fault
-TimingSimpleCPU::read(Addr addr, uint16_t &data, unsigned flags);
-
-template
-Fault
-TimingSimpleCPU::read(Addr addr, uint8_t &data, unsigned flags);
-
-#endif //DOXYGEN_SHOULD_SKIP_THIS
-
-template<>
-Fault
-TimingSimpleCPU::read(Addr addr, double &data, unsigned flags)
-{
-    return read(addr, *(uint64_t*)&data, flags);
-}
-
-template<>
-Fault
-TimingSimpleCPU::read(Addr addr, float &data, unsigned flags)
-{
-    return read(addr, *(uint32_t*)&data, flags);
-}
-
-template<>
-Fault
-TimingSimpleCPU::read(Addr addr, int32_t &data, unsigned flags)
-{
-    return read(addr, (uint32_t&)data, flags);
-}
-
 bool
 TimingSimpleCPU::handleWritePacket()
 {
@@ -556,9 +500,12 @@ TimingSimpleCPU::handleWritePacket()
 }
 
 Fault
-TimingSimpleCPU::writeTheseBytes(uint8_t *data, unsigned size,
-                                 Addr addr, unsigned flags, uint64_t *res)
+TimingSimpleCPU::writeMem(uint8_t *data, unsigned size,
+                          Addr addr, unsigned flags, uint64_t *res)
 {
+    uint8_t *newData = new uint8_t[size];
+    memcpy(newData, data, size);
+
     const int asid = 0;
     const ThreadID tid = 0;
     const Addr pc = thread->instAddr();
@@ -582,7 +529,7 @@ TimingSimpleCPU::writeTheseBytes(uint8_t *data, unsigned size,
         req->splitOnVaddr(split_addr, req1, req2);
 
         WholeTranslationState *state =
-            new WholeTranslationState(req, req1, req2, data, res, mode);
+            new WholeTranslationState(req, req1, req2, newData, res, mode);
         DataTranslation<TimingSimpleCPU> *trans1 =
             new DataTranslation<TimingSimpleCPU>(this, state, 0);
         DataTranslation<TimingSimpleCPU> *trans2 =
@@ -592,7 +539,7 @@ TimingSimpleCPU::writeTheseBytes(uint8_t *data, unsigned size,
         thread->dtb->translateTiming(req2, tc, trans2, mode);
     } else {
         WholeTranslationState *state =
-            new WholeTranslationState(req, data, res, mode);
+            new WholeTranslationState(req, newData, res, mode);
         DataTranslation<TimingSimpleCPU> *translation =
             new DataTranslation<TimingSimpleCPU>(this, state);
         thread->dtb->translateTiming(req, tc, translation, mode);
@@ -602,84 +549,6 @@ TimingSimpleCPU::writeTheseBytes(uint8_t *data, unsigned size,
     return NoFault;
 }
 
-Fault
-TimingSimpleCPU::writeBytes(uint8_t *data, unsigned size,
-                            Addr addr, unsigned flags, uint64_t *res)
-{
-    uint8_t *newData = new uint8_t[size];
-    memcpy(newData, data, size);
-    return writeTheseBytes(newData, size, addr, flags, res);
-}
-
-template <class T>
-Fault
-TimingSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
-{
-    if (traceData) {
-        traceData->setData(data);
-    }
-    T *dataP = (T*) new uint8_t[sizeof(T)];
-    *dataP = TheISA::htog(data);
-
-    return writeTheseBytes((uint8_t *)dataP, sizeof(T), addr, flags, res);
-}
-
-
-#ifndef DOXYGEN_SHOULD_SKIP_THIS
-template
-Fault
-TimingSimpleCPU::write(Twin32_t data, Addr addr,
-                       unsigned flags, uint64_t *res);
-
-template
-Fault
-TimingSimpleCPU::write(Twin64_t data, Addr addr,
-                       unsigned flags, uint64_t *res);
-
-template
-Fault
-TimingSimpleCPU::write(uint64_t data, Addr addr,
-                       unsigned flags, uint64_t *res);
-
-template
-Fault
-TimingSimpleCPU::write(uint32_t data, Addr addr,
-                       unsigned flags, uint64_t *res);
-
-template
-Fault
-TimingSimpleCPU::write(uint16_t data, Addr addr,
-                       unsigned flags, uint64_t *res);
-
-template
-Fault
-TimingSimpleCPU::write(uint8_t data, Addr addr,
-                       unsigned flags, uint64_t *res);
-
-#endif //DOXYGEN_SHOULD_SKIP_THIS
-
-template<>
-Fault
-TimingSimpleCPU::write(double data, Addr addr, unsigned flags, uint64_t *res)
-{
-    return write(*(uint64_t*)&data, addr, flags, res);
-}
-
-template<>
-Fault
-TimingSimpleCPU::write(float data, Addr addr, unsigned flags, uint64_t *res)
-{
-    return write(*(uint32_t*)&data, addr, flags, res);
-}
-
-
-template<>
-Fault
-TimingSimpleCPU::write(int32_t data, Addr addr, unsigned flags, uint64_t *res)
-{
-    return write((uint32_t)data, addr, flags, res);
-}
-
 
 void
 TimingSimpleCPU::finishTranslation(WholeTranslationState *state)
diff --git a/src/cpu/simple/timing.hh b/src/cpu/simple/timing.hh
index 778506703..4301dfca7 100644
--- a/src/cpu/simple/timing.hh
+++ b/src/cpu/simple/timing.hh
@@ -256,16 +256,10 @@ class TimingSimpleCPU : public BaseSimpleCPU
     virtual void activateContext(int thread_num, int delay);
     virtual void suspendContext(int thread_num);
 
-    template <class T>
-    Fault read(Addr addr, T &data, unsigned flags);
+    Fault readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags);
 
-    Fault readBytes(Addr addr, uint8_t *data, unsigned size, unsigned flags);
-
-    template <class T>
-    Fault write(T data, Addr addr, unsigned flags, uint64_t *res);
-
-    Fault writeBytes(uint8_t *data, unsigned size,
-                     Addr addr, unsigned flags, uint64_t *res);
+    Fault writeMem(uint8_t *data, unsigned size,
+                   Addr addr, unsigned flags, uint64_t *res);
 
     void fetch();
     void sendFetch(Fault fault, RequestPtr req, ThreadContext *tc);
@@ -287,11 +281,6 @@ class TimingSimpleCPU : public BaseSimpleCPU
 
   private:
 
-    // The backend for writeBytes and write. It's the same as writeBytes, but
-    // doesn't make a copy of data.
-    Fault writeTheseBytes(uint8_t *data, unsigned size,
-                          Addr addr, unsigned flags, uint64_t *res);
-
     typedef EventWrapper<TimingSimpleCPU, &TimingSimpleCPU::fetch> FetchEvent;
     FetchEvent fetchEvent;
 
diff --git a/tests/long/00.gzip/ref/x86/linux/o3-timing/simerr b/tests/long/00.gzip/ref/x86/linux/o3-timing/simerr
index 94d399eab..ac4ad20a5 100755
--- a/tests/long/00.gzip/ref/x86/linux/o3-timing/simerr
+++ b/tests/long/00.gzip/ref/x86/linux/o3-timing/simerr
@@ -1,7 +1,4 @@
 warn: Sockets disabled, not accepting gdb connections
-For more information see: http://www.m5sim.org/warn/d946bea6
 warn: instruction 'fnstcw_Mw' unimplemented
-For more information see: http://www.m5sim.org/warn/437d5238
 warn: instruction 'fldcw_Mw' unimplemented
-For more information see: http://www.m5sim.org/warn/437d5238
 hack: be nice to actually delete the event here
diff --git a/tests/long/00.gzip/ref/x86/linux/o3-timing/simout b/tests/long/00.gzip/ref/x86/linux/o3-timing/simout
index a5d2218be..f693063ef 100755
--- a/tests/long/00.gzip/ref/x86/linux/o3-timing/simout
+++ b/tests/long/00.gzip/ref/x86/linux/o3-timing/simout
@@ -1,16 +1,10 @@
-Redirecting stdout to build/X86_SE/tests/fast/long/00.gzip/x86/linux/o3-timing/simout
-Redirecting stderr to build/X86_SE/tests/fast/long/00.gzip/x86/linux/o3-timing/simerr
-M5 Simulator System
+gem5 Simulator System.  http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
 
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled May 17 2011 12:22:59
-M5 started May 18 2011 08:01:14
-M5 executing on nadc-0105
-command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/00.gzip/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/fast/long/00.gzip/x86/linux/o3-timing
+gem5 compiled Jun 27 2011 02:06:34
+gem5 started Jun 27 2011 02:06:35
+gem5 executing on burrito
+command line: build/X86_SE/gem5.fast -d build/X86_SE/tests/fast/long/00.gzip/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/fast/long/00.gzip/x86/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 spec_init
diff --git a/tests/long/00.gzip/ref/x86/linux/o3-timing/stats.txt b/tests/long/00.gzip/ref/x86/linux/o3-timing/stats.txt
index 64628a88b..8f8873cca 100644
--- a/tests/long/00.gzip/ref/x86/linux/o3-timing/stats.txt
+++ b/tests/long/00.gzip/ref/x86/linux/o3-timing/stats.txt
@@ -3,10 +3,10 @@
 sim_seconds                                  0.750278                       # Number of seconds simulated
 sim_ticks                                750278436000                       # Number of ticks simulated
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 180615                       # Simulator instruction rate (inst/s)
-host_tick_rate                               83571906                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 250232                       # Number of bytes of host memory used
-host_seconds                                  8977.64                       # Real time elapsed on the host
+host_inst_rate                                 214715                       # Simulator instruction rate (inst/s)
+host_tick_rate                               99350353                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 230596                       # Number of bytes of host memory used
+host_seconds                                  7551.84                       # Real time elapsed on the host
 sim_insts                                  1621493982                       # Number of instructions simulated
 system.cpu.workload.num_syscalls                   48                       # Number of system calls
 system.cpu.numCycles                       1500556873                       # number of cpu cycles simulated
@@ -81,8 +81,8 @@ system.cpu.iq.iqInstsAdded                 2337617045                       # Nu
 system.cpu.iq.iqNonSpecInstsAdded                  78                       # Number of non-speculative instructions added to the IQ
 system.cpu.iq.iqInstsIssued                1854722734                       # Number of instructions issued
 system.cpu.iq.iqSquashedInstsIssued            196953                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined       715983422                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined   1505792788                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedInstsExamined       715983429                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined   1505792864                       # Number of squashed operands that are examined and possibly removed from graph
 system.cpu.iq.iqSquashedNonSpecRemoved             28                       # Number of squashed non-spec instructions that were removed
 system.cpu.iq.issued_per_cycle::samples    1500265844                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::mean         1.236263                       # Number of insts issued each cycle
@@ -174,8 +174,8 @@ system.cpu.iq.rate                           1.236023                       # In
 system.cpu.iq.fu_busy_cnt                     4256956                       # FU busy when requested
 system.cpu.iq.fu_busy_rate                   0.002295                       # FU busy rate (busy events/executed inst)
 system.cpu.iq.int_inst_queue_reads         5214165186                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes        3059990828                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses   1837811582                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.int_inst_queue_writes        3059990835                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses   1837811563                       # Number of integer instruction queue wakeup accesses
 system.cpu.iq.fp_inst_queue_reads                  35                       # Number of floating instruction queue reads
 system.cpu.iq.fp_inst_queue_writes                 32                       # Number of floating instruction queue writes
 system.cpu.iq.fp_inst_queue_wakeup_accesses           12                       # Number of floating instruction queue wakeup accesses
@@ -216,7 +216,7 @@ system.cpu.iew.exec_branches                111427506                       # Nu
 system.cpu.iew.exec_stores                  191699652                       # Number of stores executed
 system.cpu.iew.exec_rate                     1.227669                       # Inst execution rate
 system.cpu.iew.wb_sent                     1840965230                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                    1837811594                       # cumulative count of insts written-back
+system.cpu.iew.wb_count                    1837811575                       # cumulative count of insts written-back
 system.cpu.iew.wb_producers                1424401809                       # num instructions producing a value
 system.cpu.iew.wb_consumers                2083960582                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
diff --git a/tests/long/10.mcf/ref/x86/linux/o3-timing/simerr b/tests/long/10.mcf/ref/x86/linux/o3-timing/simerr
index 94d399eab..ac4ad20a5 100755
--- a/tests/long/10.mcf/ref/x86/linux/o3-timing/simerr
+++ b/tests/long/10.mcf/ref/x86/linux/o3-timing/simerr
@@ -1,7 +1,4 @@
 warn: Sockets disabled, not accepting gdb connections
-For more information see: http://www.m5sim.org/warn/d946bea6
 warn: instruction 'fnstcw_Mw' unimplemented
-For more information see: http://www.m5sim.org/warn/437d5238
 warn: instruction 'fldcw_Mw' unimplemented
-For more information see: http://www.m5sim.org/warn/437d5238
 hack: be nice to actually delete the event here
diff --git a/tests/long/10.mcf/ref/x86/linux/o3-timing/simout b/tests/long/10.mcf/ref/x86/linux/o3-timing/simout
index e9e668346..730df25c3 100755
--- a/tests/long/10.mcf/ref/x86/linux/o3-timing/simout
+++ b/tests/long/10.mcf/ref/x86/linux/o3-timing/simout
@@ -1,16 +1,10 @@
-Redirecting stdout to build/X86_SE/tests/fast/long/10.mcf/x86/linux/o3-timing/simout
-Redirecting stderr to build/X86_SE/tests/fast/long/10.mcf/x86/linux/o3-timing/simerr
-M5 Simulator System
+gem5 Simulator System.  http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
 
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled May 17 2011 12:22:59
-M5 started May 17 2011 13:00:50
-M5 executing on nadc-0309
-command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/10.mcf/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/fast/long/10.mcf/x86/linux/o3-timing
+gem5 compiled Jun 27 2011 02:06:34
+gem5 started Jun 27 2011 02:06:35
+gem5 executing on burrito
+command line: build/X86_SE/gem5.fast -d build/X86_SE/tests/fast/long/10.mcf/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/fast/long/10.mcf/x86/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 
diff --git a/tests/long/10.mcf/ref/x86/linux/o3-timing/stats.txt b/tests/long/10.mcf/ref/x86/linux/o3-timing/stats.txt
index f27bf7825..a8865befa 100644
--- a/tests/long/10.mcf/ref/x86/linux/o3-timing/stats.txt
+++ b/tests/long/10.mcf/ref/x86/linux/o3-timing/stats.txt
@@ -3,10 +3,10 @@
 sim_seconds                                  0.081353                       # Number of seconds simulated
 sim_ticks                                 81353358500                       # Number of ticks simulated
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 230671                       # Simulator instruction rate (inst/s)
-host_tick_rate                               67456393                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 384688                       # Number of bytes of host memory used
-host_seconds                                  1206.01                       # Real time elapsed on the host
+host_inst_rate                                 205113                       # Simulator instruction rate (inst/s)
+host_tick_rate                               59982451                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 365084                       # Number of bytes of host memory used
+host_seconds                                  1356.29                       # Real time elapsed on the host
 sim_insts                                   278192519                       # Number of instructions simulated
 system.cpu.workload.num_syscalls                  444                       # Number of system calls
 system.cpu.numCycles                        162706718                       # number of cpu cycles simulated
@@ -21,10 +21,10 @@ system.cpu.BPredUnit.BTBCorrect                     0                       # Nu
 system.cpu.BPredUnit.usedRAS                        0                       # Number of times the RAS was used to get a target.
 system.cpu.BPredUnit.RASInCorrect                   0                       # Number of incorrect RAS predictions.
 system.cpu.fetch.icacheStallCycles           30836194                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                      225319865                       # Number of instructions fetch has processed
+system.cpu.fetch.Insts                      225319864                       # Number of instructions fetch has processed
 system.cpu.fetch.Branches                    43478033                       # Number of branches that fetch encountered
 system.cpu.fetch.predictedBranches           38222212                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                      71185004                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.Cycles                      71185003                       # Number of cycles fetch has run and was not squashing or blocked
 system.cpu.fetch.SquashCycles                 2631314                       # Number of cycles fetch has spent squashing
 system.cpu.fetch.MiscStallCycles                   21                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
 system.cpu.fetch.CacheLines                  30836194                       # Number of cache lines fetched
@@ -33,11 +33,11 @@ system.cpu.fetch.rateDist::samples          161537602                       # Nu
 system.cpu.fetch.rateDist::mean              2.462501                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::stdev             3.241161                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                 92871454     57.49%     57.49% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                 92871455     57.49%     57.49% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::1                  4826864      2.99%     60.48% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::2                  3003358      1.86%     62.34% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::3                  6248204      3.87%     66.21% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                  7317457      4.53%     70.74% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                  7317456      4.53%     70.74% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::5                  5554189      3.44%     74.18% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::6                  8050336      4.98%     79.16% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::7                  6460332      4.00%     83.16% # Number of instructions fetched each cycle (Total)
@@ -48,22 +48,22 @@ system.cpu.fetch.rateDist::max_value                8                       # Nu
 system.cpu.fetch.rateDist::total            161537602                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.branchRate                  0.267217                       # Number of branch fetches per cycle
 system.cpu.fetch.rate                        1.384822                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 68100522                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles              13645785                       # Number of cycles decode is blocked
+system.cpu.decode.IdleCycles                 68100520                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles              13645788                       # Number of cycles decode is blocked
 system.cpu.decode.RunCycles                  66107585                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles               1213656                       # Number of cycles decode is unblocking
+system.cpu.decode.UnblockCycles               1213655                       # Number of cycles decode is unblocking
 system.cpu.decode.SquashCycles               12470054                       # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts              390299110                       # Number of instructions handled by decode
+system.cpu.decode.DecodedInsts              390299102                       # Number of instructions handled by decode
 system.cpu.rename.SquashCycles               12470054                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 72027635                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                 3012057                       # Number of cycles rename is blocking
+system.cpu.rename.IdleCycles                 72027632                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                 3012062                       # Number of cycles rename is blocking
 system.cpu.rename.serializeStallCycles           6445                       # count of cycles rename stalled for serializing inst
 system.cpu.rename.RunCycles                  63003531                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles              11017880                       # Number of cycles rename is unblocking
+system.cpu.rename.UnblockCycles              11017878                       # Number of cycles rename is unblocking
 system.cpu.rename.RenamedInsts              382954672                       # Number of instructions processed by rename
 system.cpu.rename.ROBFullEvents                    14                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                 129804                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents               9724945                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.IQFullEvents                 129805                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents               9724942                       # Number of times rename has blocked due to LSQ full
 system.cpu.rename.RenamedOperands           343637650                       # Number of destination operands rename has renamed
 system.cpu.rename.RenameLookups             940851472                       # Number of register rename lookups that rename has made
 system.cpu.rename.int_rename_lookups        940850893                       # Number of integer rename lookups
@@ -72,28 +72,28 @@ system.cpu.rename.CommittedMaps             248344192                       # Nu
 system.cpu.rename.UndoneMaps                 95293458                       # Number of HB maps that are undone due to squashing
 system.cpu.rename.serializingInsts                468                       # count of serializing insts renamed
 system.cpu.rename.tempSerializingInsts            462                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                  25876088                       # count of insts added to the skid buffer
+system.cpu.rename.skidInsts                  25876087                       # count of insts added to the skid buffer
 system.cpu.memDep0.insertedLoads            121481389                       # Number of loads inserted to the mem dependence unit.
 system.cpu.memDep0.insertedStores            39633547                       # Number of stores inserted to the mem dependence unit.
 system.cpu.memDep0.conflictingLoads          49140895                       # Number of conflicting loads.
 system.cpu.memDep0.conflictingStores         10609784                       # Number of conflicting stores.
 system.cpu.iq.iqInstsAdded                  366915906                       # Number of instructions added to the IQ (excludes non-spec)
 system.cpu.iq.iqNonSpecInstsAdded                 465                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                 331723490                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued            173771                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined        88480197                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined    124853434                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqInstsIssued                 331721300                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued            173691                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined        88480232                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined    124860059                       # Number of squashed operands that are examined and possibly removed from graph
 system.cpu.iq.iqSquashedNonSpecRemoved             19                       # Number of squashed non-spec instructions that were removed
 system.cpu.iq.issued_per_cycle::samples     161537602                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         2.053537                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         2.053524                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::stdev        1.792236                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0            44403783     27.49%     27.49% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1            26523335     16.42%     43.91% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2            27554043     17.06%     60.96% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3            26723041     16.54%     77.51% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4            19519323     12.08%     89.59% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5            11121820      6.88%     96.48% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0            44404154     27.49%     27.49% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            26523670     16.42%     43.91% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2            27554042     17.06%     60.97% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3            26722697     16.54%     77.51% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4            19519009     12.08%     89.59% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5            11121773      6.88%     96.48% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::6             3849891      2.38%     98.86% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::7             1601720      0.99%     99.85% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::8              240646      0.15%    100.00% # Number of insts issued each cycle
@@ -131,12 +131,12 @@ system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      1.17% # at
 system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      1.17% # attempts to use FU when none available
 system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      1.17% # attempts to use FU when none available
 system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      1.17% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                1580289     90.40%     91.57% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                1580184     90.40%     91.57% # attempts to use FU when none available
 system.cpu.iq.fu_full::MemWrite                147351      8.43%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass             16703      0.01%      0.01% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu             188283718     56.76%     56.76% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu             188283743     56.76%     56.76% # Type of FU issued
 system.cpu.iq.FU_type_0::IntMult                    0      0.00%     56.76% # Type of FU issued
 system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     56.76% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatAdd                  16      0.00%     56.76% # Type of FU issued
@@ -165,21 +165,21 @@ system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     56.76% # Ty
 system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     56.76% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     56.76% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     56.76% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead            108609030     32.74%     89.51% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead            108606815     32.74%     89.51% # Type of FU issued
 system.cpu.iq.FU_type_0::MemWrite            34814023     10.49%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total              331723490                       # Type of FU issued
-system.cpu.iq.rate                           2.038782                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                     1748173                       # FU busy when requested
+system.cpu.iq.FU_type_0::total              331721300                       # Type of FU issued
+system.cpu.iq.rate                           2.038768                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                     1748068                       # FU busy when requested
 system.cpu.iq.fu_busy_rate                   0.005270                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads          826906318                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes         455618768                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses    324136676                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.int_inst_queue_reads          826901753                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         455618803                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses    324135014                       # Number of integer instruction queue wakeup accesses
 system.cpu.iq.fp_inst_queue_reads                 208                       # Number of floating instruction queue reads
 system.cpu.iq.fp_inst_queue_writes                234                       # Number of floating instruction queue writes
 system.cpu.iq.fp_inst_queue_wakeup_accesses           80                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses              333454859                       # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses              333452564                       # Number of integer alu accesses
 system.cpu.iq.fp_alu_accesses                     101                       # Number of floating point alu accesses
 system.cpu.iew.lsq.thread0.forwLoads         43811715                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
@@ -193,34 +193,34 @@ system.cpu.iew.lsq.thread0.rescheduledLoads         3292                       #
 system.cpu.iew.lsq.thread0.cacheBlocked         14215                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
 system.cpu.iew.iewSquashCycles               12470054                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                  739461                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                101351                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewBlockCycles                  739464                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                101352                       # Number of cycles IEW is unblocking
 system.cpu.iew.iewDispatchedInsts           366916371                       # Number of instructions dispatched to IQ
 system.cpu.iew.iewDispSquashedInsts            440258                       # Number of squashed instructions skipped by dispatch
 system.cpu.iew.iewDispLoadInsts             121481389                       # Number of dispatched load instructions
 system.cpu.iew.iewDispStoreInsts             39633547                       # Number of dispatched store instructions
 system.cpu.iew.iewDispNonSpecInsts                465                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                   4278                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewIQFullEvents                   4279                       # Number of times the IQ has become full, causing a stall
 system.cpu.iew.iewLSQFullEvents                 66728                       # Number of times the LSQ has become full, causing a stall
 system.cpu.iew.memOrderViolationEvents         238201                       # Number of memory order violations
 system.cpu.iew.predictedTakenIncorrect        2276962                       # Number of branches that were predicted taken incorrectly
 system.cpu.iew.predictedNotTakenIncorrect       580211                       # Number of branches that were predicted not taken incorrectly
 system.cpu.iew.branchMispredicts              2857173                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts             327058428                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts             107336037                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts           4665062                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewExecutedInsts             327057192                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts             107334804                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts           4664108                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
 system.cpu.iew.exec_nop                             0                       # number of nop insts executed
-system.cpu.iew.exec_refs                    141682074                       # number of memory reference insts executed
+system.cpu.iew.exec_refs                    141680841                       # number of memory reference insts executed
 system.cpu.iew.exec_branches                 32801587                       # Number of branches executed
 system.cpu.iew.exec_stores                   34346037                       # Number of stores executed
-system.cpu.iew.exec_rate                     2.010110                       # Inst execution rate
-system.cpu.iew.wb_sent                      325338572                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                     324136756                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                 242967422                       # num instructions producing a value
-system.cpu.iew.wb_consumers                 330454967                       # num instructions consuming a value
+system.cpu.iew.exec_rate                     2.010103                       # Inst execution rate
+system.cpu.iew.wb_sent                      325338225                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                     324135094                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                 242967410                       # num instructions producing a value
+system.cpu.iew.wb_consumers                 330454956                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       1.992153                       # insts written-back per cycle
+system.cpu.iew.wb_rate                       1.992143                       # insts written-back per cycle
 system.cpu.iew.wb_fanout                     0.735251                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
 system.cpu.commit.commitCommittedInsts      278192519                       # The number of committed instructions
@@ -265,11 +265,11 @@ system.cpu.cpi                               0.584871                       # CP
 system.cpu.cpi_total                         0.584871                       # CPI: Total CPI of All Threads
 system.cpu.ipc                               1.709779                       # IPC: Instructions Per Cycle
 system.cpu.ipc_total                         1.709779                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                572578713                       # number of integer regfile reads
-system.cpu.int_regfile_writes               291474353                       # number of integer regfile writes
+system.cpu.int_regfile_reads                572576247                       # number of integer regfile reads
+system.cpu.int_regfile_writes               291474006                       # number of integer regfile writes
 system.cpu.fp_regfile_reads                        75                       # number of floating regfile reads
 system.cpu.fp_regfile_writes                       41                       # number of floating regfile writes
-system.cpu.misc_regfile_reads               211120280                       # number of misc regfile reads
+system.cpu.misc_regfile_reads               211119046                       # number of misc regfile reads
 system.cpu.icache.replacements                     60                       # number of replacements
 system.cpu.icache.tagsinuse                811.599985                       # Cycle average of tags in use
 system.cpu.icache.total_refs                 30834919                       # Total number of references to valid blocks.
@@ -328,16 +328,16 @@ system.cpu.icache.soft_prefetch_mshr_full            0                       # n
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                2073960                       # number of replacements
 system.cpu.dcache.tagsinuse               4075.298640                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                 92303486                       # Total number of references to valid blocks.
+system.cpu.dcache.total_refs                 92302253                       # Total number of references to valid blocks.
 system.cpu.dcache.sampled_refs                2078056                       # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs                  44.418190                       # Average number of references to valid blocks.
+system.cpu.dcache.avg_refs                  44.417597                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle            30307591000                       # Cycle when the warmup percentage was hit.
 system.cpu.dcache.occ_blocks::0           4075.298640                       # Average occupied blocks per context
 system.cpu.dcache.occ_percent::0             0.994946                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits               61101027                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits               61099794                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits              31202450                       # number of WriteReq hits
-system.cpu.dcache.demand_hits                92303477                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits               92303477                       # number of overall hits
+system.cpu.dcache.demand_hits                92302244                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits               92302244                       # number of overall hits
 system.cpu.dcache.ReadReq_misses              2219212                       # number of ReadReq misses
 system.cpu.dcache.WriteReq_misses              237301                       # number of WriteReq misses
 system.cpu.dcache.demand_misses               2456513                       # number of demand (read+write) misses
@@ -346,11 +346,11 @@ system.cpu.dcache.ReadReq_miss_latency    14180205500                       # nu
 system.cpu.dcache.WriteReq_miss_latency    4209484208                       # number of WriteReq miss cycles
 system.cpu.dcache.demand_miss_latency     18389689708                       # number of demand (read+write) miss cycles
 system.cpu.dcache.overall_miss_latency    18389689708                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses           63320239                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses           63319006                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses          31439751                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses            94759990                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses           94759990                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate          0.035047                       # miss rate for ReadReq accesses
+system.cpu.dcache.demand_accesses            94758757                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses           94758757                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate          0.035048                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate         0.007548                       # miss rate for WriteReq accesses
 system.cpu.dcache.demand_miss_rate           0.025924                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate          0.025924                       # miss rate for overall accesses
@@ -381,7 +381,7 @@ system.cpu.dcache.WriteReq_mshr_miss_latency   1870145708
 system.cpu.dcache.demand_mshr_miss_latency   7402756208                       # number of demand (read+write) MSHR miss cycles
 system.cpu.dcache.overall_mshr_miss_latency   7402756208                       # number of overall MSHR miss cycles
 system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate     0.031144                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate     0.031145                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate     0.003372                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.demand_mshr_miss_rate      0.021930                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate     0.021930                       # mshr miss rate for overall accesses
diff --git a/tests/long/20.parser/ref/x86/linux/o3-timing/simerr b/tests/long/20.parser/ref/x86/linux/o3-timing/simerr
index 94d399eab..ac4ad20a5 100755
--- a/tests/long/20.parser/ref/x86/linux/o3-timing/simerr
+++ b/tests/long/20.parser/ref/x86/linux/o3-timing/simerr
@@ -1,7 +1,4 @@
 warn: Sockets disabled, not accepting gdb connections
-For more information see: http://www.m5sim.org/warn/d946bea6
 warn: instruction 'fnstcw_Mw' unimplemented
-For more information see: http://www.m5sim.org/warn/437d5238
 warn: instruction 'fldcw_Mw' unimplemented
-For more information see: http://www.m5sim.org/warn/437d5238
 hack: be nice to actually delete the event here
diff --git a/tests/long/20.parser/ref/x86/linux/o3-timing/simout b/tests/long/20.parser/ref/x86/linux/o3-timing/simout
index 4df0253e7..c4825a4e7 100755
--- a/tests/long/20.parser/ref/x86/linux/o3-timing/simout
+++ b/tests/long/20.parser/ref/x86/linux/o3-timing/simout
@@ -1,16 +1,10 @@
-Redirecting stdout to build/X86_SE/tests/fast/long/20.parser/x86/linux/o3-timing/simout
-Redirecting stderr to build/X86_SE/tests/fast/long/20.parser/x86/linux/o3-timing/simerr
-M5 Simulator System
+gem5 Simulator System.  http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
 
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled May 17 2011 12:22:59
-M5 started May 17 2011 13:21:24
-M5 executing on nadc-0309
-command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/20.parser/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/fast/long/20.parser/x86/linux/o3-timing
+gem5 compiled Jun 27 2011 02:06:34
+gem5 started Jun 27 2011 02:06:35
+gem5 executing on burrito
+command line: build/X86_SE/gem5.fast -d build/X86_SE/tests/fast/long/20.parser/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/fast/long/20.parser/x86/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 
@@ -83,4 +77,4 @@ info: Increasing stack size by one page.
   about 2 million people attended 
   the five best costumes got prizes 
 No errors!
-Exiting @ tick 584023415000 because target called exit()
+Exiting @ tick 584042944000 because target called exit()
diff --git a/tests/long/20.parser/ref/x86/linux/o3-timing/stats.txt b/tests/long/20.parser/ref/x86/linux/o3-timing/stats.txt
index 59fe69eba..a6db3838d 100644
--- a/tests/long/20.parser/ref/x86/linux/o3-timing/stats.txt
+++ b/tests/long/20.parser/ref/x86/linux/o3-timing/stats.txt
@@ -1,108 +1,108 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.584023                       # Number of seconds simulated
-sim_ticks                                584023415000                       # Number of ticks simulated
+sim_seconds                                  0.584043                       # Number of seconds simulated
+sim_ticks                                584042944000                       # Number of ticks simulated
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 204231                       # Simulator instruction rate (inst/s)
-host_tick_rate                               78009509                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 293660                       # Number of bytes of host memory used
-host_seconds                                  7486.57                       # Real time elapsed on the host
+host_inst_rate                                 221280                       # Simulator instruction rate (inst/s)
+host_tick_rate                               84524523                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 274300                       # Number of bytes of host memory used
+host_seconds                                  6909.75                       # Real time elapsed on the host
 sim_insts                                  1528988756                       # Number of instructions simulated
 system.cpu.workload.num_syscalls                  551                       # Number of system calls
-system.cpu.numCycles                       1168046831                       # number of cpu cycles simulated
+system.cpu.numCycles                       1168085889                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.BPredUnit.lookups                253390632                       # Number of BP lookups
-system.cpu.BPredUnit.condPredicted          253390632                       # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect           16658352                       # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups             238513057                       # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits                219596279                       # Number of BTB hits
+system.cpu.BPredUnit.lookups                253398223                       # Number of BP lookups
+system.cpu.BPredUnit.condPredicted          253398223                       # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect           16660589                       # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups             238496117                       # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits                219579135                       # Number of BTB hits
 system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
 system.cpu.BPredUnit.usedRAS                        0                       # Number of times the RAS was used to get a target.
 system.cpu.BPredUnit.RASInCorrect                   0                       # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles          188480819                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                     1362450524                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                   253390632                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches          219596279                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                     442052723                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                19279680                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.MiscStallCycles                77230                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.CacheLines                 188480819                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes               3788271                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples         1143904596                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              2.224031                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             3.207932                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles          188493207                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                     1362528555                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                   253398223                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches          219579135                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     442066407                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                19282041                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.MiscStallCycles                77357                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.CacheLines                 188493207                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes               3791136                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples         1143941897                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              2.224075                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.207990                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                706004786     61.72%     61.72% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                 32751719      2.86%     64.58% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                 38229862      3.34%     67.92% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                 34570255      3.02%     70.95% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                 20874859      1.82%     72.77% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                 39604957      3.46%     76.23% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                 44518737      3.89%     80.13% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                 36275151      3.17%     83.30% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                191074270     16.70%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                706029092     61.72%     61.72% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                 32745689      2.86%     64.58% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                 38225778      3.34%     67.92% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                 34592742      3.02%     70.95% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                 20873132      1.82%     72.77% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                 39592075      3.46%     76.23% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                 44500061      3.89%     80.12% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                 36282476      3.17%     83.29% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                191100852     16.71%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total           1143904596                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::total           1143941897                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.branchRate                  0.216935                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        1.166435                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                421330270                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles             186446419                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                 405934175                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles              21628969                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles              108564763                       # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts             2493904791                       # Number of instructions handled by decode
-system.cpu.rename.SquashCycles              108564763                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                460258453                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                50662056                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles          15556                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                 387000173                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles             137403595                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts             2428714828                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                  8220                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents               53929654                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents              70829494                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands          2267135297                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups            5702873531                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups       5702857140                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups             16391                       # Number of floating rename lookups
+system.cpu.fetch.rate                        1.166463                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                421359771                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles             186435003                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                 405946069                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles              21628019                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles              108573035                       # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts             2494021022                       # Number of instructions handled by decode
+system.cpu.rename.SquashCycles              108573035                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                460289272                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                50662445                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles          15855                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                 387005567                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles             137395723                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts             2428811074                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                  8205                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents               53921903                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents              70830357                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenamedOperands          2267152647                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups            5703018907                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups       5703000611                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups             18296                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps            1427299027                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                839836270                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts               2552                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts           2513                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                 298757683                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads            586893998                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores           222778511                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads         352697963                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores        138822292                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                 2327078199                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded                9768                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                1903699453                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued            749156                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined       795322101                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined   1354689551                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved           9215                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples    1143904596                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         1.664212                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.649949                       # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps                839853620                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts               2555                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts           2515                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                 298765601                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads            586920489                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores           222789217                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads         352764399                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores        138805015                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                 2327145816                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded                9782                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                1903699652                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued            745209                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined       795395556                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined   1355118976                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved           9229                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples    1143941897                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         1.664158                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.649963                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0           364118171     31.83%     31.83% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1           266012583     23.25%     55.09% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2           191391841     16.73%     71.82% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3           151042401     13.20%     85.02% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4            94875410      8.29%     93.32% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5            46737983      4.09%     97.40% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6            20365340      1.78%     99.18% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7             8494546      0.74%     99.92% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8              866321      0.08%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0           364171044     31.83%     31.83% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1           265972258     23.25%     55.09% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2           191418370     16.73%     71.82% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3           151056709     13.20%     85.02% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4            94863070      8.29%     93.32% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5            46725885      4.08%     97.40% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6            20369113      1.78%     99.18% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7             8499440      0.74%     99.92% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8              866008      0.08%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total      1143904596                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total      1143941897                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                 1290623     11.43%     11.43% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                 1290505     11.43%     11.43% # attempts to use FU when none available
 system.cpu.iq.fu_full::IntMult                      0      0.00%     11.43% # attempts to use FU when none available
 system.cpu.iq.fu_full::IntDiv                       0      0.00%     11.43% # attempts to use FU when none available
 system.cpu.iq.fu_full::FloatAdd                     0      0.00%     11.43% # attempts to use FU when none available
@@ -131,119 +131,119 @@ system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     11.43% # at
 system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     11.43% # attempts to use FU when none available
 system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     11.43% # attempts to use FU when none available
 system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     11.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                7282650     64.51%     75.94% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite               2716745     24.06%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                7282962     64.50%     75.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite               2717631     24.07%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass           2276794      0.12%      0.12% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu            1273262556     66.88%     67.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                    0      0.00%     67.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     67.00% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     67.00% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     67.00% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     67.00% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     67.00% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     67.00% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     67.00% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     67.00% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     67.00% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     67.00% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     67.00% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     67.00% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     67.00% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     67.00% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     67.00% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     67.00% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     67.00% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     67.00% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     67.00% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     67.00% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     67.00% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     67.00% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     67.00% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     67.00% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     67.00% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     67.00% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     67.00% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead            457990895     24.06%     91.06% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite           170169208      8.94%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::No_OpClass           2277009      0.12%      0.12% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu            1273302138     66.89%     67.01% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                    0      0.00%     67.01% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     67.01% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     67.01% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     67.01% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     67.01% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     67.01% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     67.01% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     67.01% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     67.01% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     67.01% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     67.01% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     67.01% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     67.01% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     67.01% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     67.01% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     67.01% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     67.01% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     67.01% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     67.01% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     67.01% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     67.01% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     67.01% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     67.01% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     67.01% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     67.01% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     67.01% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     67.01% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     67.01% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead            457949055     24.06%     91.06% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite           170171450      8.94%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total             1903699453                       # Type of FU issued
-system.cpu.iq.rate                           1.629814                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                    11290018                       # FU busy when requested
+system.cpu.iq.FU_type_0::total             1903699652                       # Type of FU issued
+system.cpu.iq.rate                           1.629760                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                    11291098                       # FU busy when requested
 system.cpu.iq.fu_busy_rate                   0.005931                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads         4963342528                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes        3124994935                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses   1860002555                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads                 148                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes               6470                       # Number of floating instruction queue writes
+system.cpu.iq.int_inst_queue_reads         4963377358                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes        3125135181                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses   1859937909                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads                 150                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes               7364                       # Number of floating instruction queue writes
 system.cpu.iq.fp_inst_queue_wakeup_accesses           35                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses             1912712604                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                      73                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads        121974892                       # Number of loads that had data forwarded from stores
+system.cpu.iq.int_alu_accesses             1912713667                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                      74                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads        121955986                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads    202791838                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses       144755                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation      2595349                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores     73620402                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads    202818329                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses       145118                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation      2595412                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores     73631154                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads         1258                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.rescheduledLoads         1267                       # Number of loads that were rescheduled
 system.cpu.iew.lsq.thread0.cacheBlocked             0                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles              108564763                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                 9612649                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles               1584002                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts          2327087967                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts           2265532                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts             586893998                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts            222780587                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts               9768                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                1061349                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                 44764                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents        2595349                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect       15395124                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect      2700605                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts             18095729                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts            1873365131                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts             447946174                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts          30334322                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles              108573035                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                 9607775                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles               1579187                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts          2327155598                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts           2263253                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts             586920489                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts            222791339                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts               9782                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                1056355                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                 44992                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents        2595412                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect       15396927                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect      2702189                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts             18099116                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts            1873386406                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts             447925301                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts          30313246                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
 system.cpu.iew.exec_nop                             0                       # number of nop insts executed
-system.cpu.iew.exec_refs                    613940816                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                173514694                       # Number of branches executed
-system.cpu.iew.exec_stores                  165994642                       # Number of stores executed
-system.cpu.iew.exec_rate                     1.603844                       # Inst execution rate
-system.cpu.iew.wb_sent                     1866291041                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                    1860002590                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                1434917653                       # num instructions producing a value
-system.cpu.iew.wb_consumers                2113204026                       # num instructions consuming a value
+system.cpu.iew.exec_refs                    613922207                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                173516320                       # Number of branches executed
+system.cpu.iew.exec_stores                  165996906                       # Number of stores executed
+system.cpu.iew.exec_rate                     1.603809                       # Inst execution rate
+system.cpu.iew.wb_sent                     1866315288                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                    1859937944                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                1434930162                       # num instructions producing a value
+system.cpu.iew.wb_consumers                2113232937                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       1.592404                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.679025                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       1.592296                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.679021                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
 system.cpu.commit.commitCommittedInsts     1528988756                       # The number of committed instructions
-system.cpu.commit.commitSquashedInsts       798102573                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts       798170363                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls             553                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts          16689612                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples   1035339833                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     1.476799                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.996303                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts          16691926                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples   1035368862                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     1.476758                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.996244                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0    433023044     41.82%     41.82% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1    272005097     26.27%     68.10% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2    102852786      9.93%     78.03% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3    102343925      9.89%     87.92% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4     37875553      3.66%     91.57% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5     24412247      2.36%     93.93% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6     10662009      1.03%     94.96% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7     10610565      1.02%     95.99% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8     41554607      4.01%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0    433054636     41.83%     41.83% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1    271974415     26.27%     68.09% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2    102879563      9.94%     78.03% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3    102354239      9.89%     87.92% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4     37870792      3.66%     91.57% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5     24412946      2.36%     93.93% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6     10660961      1.03%     94.96% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7     10611646      1.02%     95.99% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8     41549664      4.01%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total   1035339833                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total   1035368862                       # Number of insts commited each cycle
 system.cpu.commit.count                    1528988756                       # Number of instructions committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
 system.cpu.commit.refs                      533262345                       # Number of memory references committed
@@ -253,48 +253,48 @@ system.cpu.commit.branches                  149758588                       # Nu
 system.cpu.commit.fp_insts                          0                       # Number of committed floating point instructions.
 system.cpu.commit.int_insts                1528317614                       # Number of committed integer instructions.
 system.cpu.commit.function_calls                    0                       # Number of function calls committed.
-system.cpu.commit.bw_lim_events              41554607                       # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events              41549664                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                   3320876555                       # The number of ROB reads
-system.cpu.rob.rob_writes                  4762809697                       # The number of ROB writes
-system.cpu.timesIdled                          612261                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                        24142235                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads                   3320978317                       # The number of ROB reads
+system.cpu.rob.rob_writes                  4762953278                       # The number of ROB writes
+system.cpu.timesIdled                          612203                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                        24143992                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                  1528988756                       # Number of Instructions Simulated
 system.cpu.committedInsts_total            1528988756                       # Number of Instructions Simulated
-system.cpu.cpi                               0.763934                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.763934                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               1.309013                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         1.309013                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads               3113980511                       # number of integer regfile reads
-system.cpu.int_regfile_writes              1735312737                       # number of integer regfile writes
+system.cpu.cpi                               0.763960                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.763960                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.308969                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.308969                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads               3113988878                       # number of integer regfile reads
+system.cpu.int_regfile_writes              1735338379                       # number of integer regfile writes
 system.cpu.fp_regfile_reads                        35                       # number of floating regfile reads
-system.cpu.misc_regfile_reads              1026187894                       # number of misc regfile reads
-system.cpu.icache.replacements                   9719                       # number of replacements
-system.cpu.icache.tagsinuse                962.212052                       # Cycle average of tags in use
-system.cpu.icache.total_refs                188218304                       # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs                  11170                       # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs               16850.340555                       # Average number of references to valid blocks.
+system.cpu.misc_regfile_reads              1026178630                       # number of misc regfile reads
+system.cpu.icache.replacements                   9690                       # number of replacements
+system.cpu.icache.tagsinuse                963.166837                       # Cycle average of tags in use
+system.cpu.icache.total_refs                188230465                       # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs                  11136                       # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs               16902.879400                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0            962.212052                       # Average occupied blocks per context
-system.cpu.icache.occ_percent::0             0.469830                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits              188225426                       # number of ReadReq hits
-system.cpu.icache.demand_hits               188225426                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits              188225426                       # number of overall hits
-system.cpu.icache.ReadReq_misses               255393                       # number of ReadReq misses
-system.cpu.icache.demand_misses                255393                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses               255393                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency     1672074500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency      1672074500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency     1672074500                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses          188480819                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses           188480819                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses          188480819                       # number of overall (read+write) accesses
+system.cpu.icache.occ_blocks::0            963.166837                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.470296                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits              188237743                       # number of ReadReq hits
+system.cpu.icache.demand_hits               188237743                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits              188237743                       # number of overall hits
+system.cpu.icache.ReadReq_misses               255464                       # number of ReadReq misses
+system.cpu.icache.demand_misses                255464                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses               255464                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency     1671443500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency      1671443500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency     1671443500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses          188493207                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses           188493207                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses          188493207                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate          0.001355                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate           0.001355                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate          0.001355                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency  6547.064720                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency  6547.064720                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency  6547.064720                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency  6542.775107                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency  6542.775107                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency  6542.775107                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -303,60 +303,60 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.writebacks                        6                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits              1431                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits               1431                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits              1431                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses          253962                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses           253962                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses          253962                       # number of overall MSHR misses
+system.cpu.icache.writebacks                        7                       # number of writebacks
+system.cpu.icache.ReadReq_mshr_hits              1428                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits               1428                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits              1428                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses          254036                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses           254036                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses          254036                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency    874487000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency    874487000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency    874487000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency    873542000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency    873542000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency    873542000                       # number of overall MSHR miss cycles
 system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate     0.001347                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate      0.001347                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate     0.001347                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency  3443.377356                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency  3443.377356                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency  3443.377356                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_miss_rate     0.001348                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate      0.001348                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate     0.001348                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency  3438.654364                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency  3438.654364                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency  3438.654364                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.replacements                2526689                       # number of replacements
-system.cpu.dcache.tagsinuse               4088.695138                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                470723878                       # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs                2530785                       # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs                 185.999158                       # Average number of references to valid blocks.
+system.cpu.dcache.replacements                2526737                       # number of replacements
+system.cpu.dcache.tagsinuse               4088.695382                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                470726270                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                2530833                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs                 185.996575                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle             2167120000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::0           4088.695138                       # Average occupied blocks per context
+system.cpu.dcache.occ_blocks::0           4088.695382                       # Average occupied blocks per context
 system.cpu.dcache.occ_percent::0             0.998217                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits              321863634                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits             147543808                       # number of WriteReq hits
-system.cpu.dcache.demand_hits               469407442                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits              469407442                       # number of overall hits
-system.cpu.dcache.ReadReq_misses              3006802                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses             1616393                       # number of WriteReq misses
-system.cpu.dcache.demand_misses               4623195                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses              4623195                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency    47968938500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency   38293464500                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency     86262403000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency    86262403000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses          324870436                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_hits              321866059                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits             147543837                       # number of WriteReq hits
+system.cpu.dcache.demand_hits               469409896                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits              469409896                       # number of overall hits
+system.cpu.dcache.ReadReq_misses              3006715                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses             1616364                       # number of WriteReq misses
+system.cpu.dcache.demand_misses               4623079                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses              4623079                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency    47957140000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency   38289086000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency     86246226000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency    86246226000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses          324872774                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses         149160201                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses           474030637                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses          474030637                       # number of overall (read+write) accesses
+system.cpu.dcache.demand_accesses           474032975                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses          474032975                       # number of overall (read+write) accesses
 system.cpu.dcache.ReadReq_miss_rate          0.009255                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate         0.010837                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate         0.010836                       # miss rate for WriteReq accesses
 system.cpu.dcache.demand_miss_rate           0.009753                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate          0.009753                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency 15953.474323                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency 23690.689393                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency 18658.612280                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency 18658.612280                       # average overall miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency 15950.011890                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency 23688.405582                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency 18655.581270                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency 18655.581270                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -365,75 +365,75 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks                  2229828                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits           1247246                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits           605486                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits            1852732                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits           1852732                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses         1759556                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses        1010907                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses          2770463                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses         2770463                       # number of overall MSHR misses
+system.cpu.dcache.writebacks                  2229867                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits           1247117                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits           605322                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits            1852439                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits           1852439                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses         1759598                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses        1011042                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses          2770640                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses         2770640                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency  14841103500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency  18213023500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency  33054127000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency  33054127000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency  14841801000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency  18214921000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency  33056722000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency  33056722000                       # number of overall MSHR miss cycles
 system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate     0.005416                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate     0.006777                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate      0.005844                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate     0.005844                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency  8434.572983                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 18016.517345                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 11930.903607                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 11930.903607                       # average overall mshr miss latency
+system.cpu.dcache.WriteReq_mshr_miss_rate     0.006778                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate      0.005845                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate     0.005845                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency  8434.768055                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 18015.988455                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 11931.078018                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 11931.078018                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.replacements                574908                       # number of replacements
-system.cpu.l2cache.tagsinuse             21475.483997                       # Cycle average of tags in use
-system.cpu.l2cache.total_refs                 3187378                       # Total number of references to valid blocks.
-system.cpu.l2cache.sampled_refs                594034                       # Sample count of references to valid blocks.
-system.cpu.l2cache.avg_refs                  5.365649                       # Average number of references to valid blocks.
+system.cpu.l2cache.replacements                574893                       # number of replacements
+system.cpu.l2cache.tagsinuse             21475.591540                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                 3187531                       # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs                594020                       # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs                  5.366033                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle          306954721000                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::0          7759.424179                       # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1         13716.059817                       # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0            0.236799                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::1            0.418581                       # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits               1427745                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits             2229834                       # number of Writeback hits
-system.cpu.l2cache.UpgradeReq_hits               1220                       # number of UpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits              528395                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits                1956140                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits               1956140                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses              338148                       # number of ReadReq misses
-system.cpu.l2cache.UpgradeReq_misses           241457                       # number of UpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses            247534                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses               585682                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses              585682                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency   11551208500                       # number of ReadReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency     10591500                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency   8481401000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency    20032609500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency   20032609500                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses           1765893                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses         2229834                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses         242677                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses          775929                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses            2541822                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses           2541822                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate         0.191488                       # miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate      0.994973                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate       0.319016                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate          0.230418                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate         0.230418                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency 34160.215349                       # average ReadReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency    43.864953                       # average UpgradeReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency 34263.579953                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency 34203.901605                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency 34203.901605                       # average overall miss latency
+system.cpu.l2cache.occ_blocks::0          7759.826991                       # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1         13715.764549                       # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0            0.236811                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::1            0.418572                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits               1427752                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits             2229874                       # number of Writeback hits
+system.cpu.l2cache.UpgradeReq_hits               1226                       # number of UpgradeReq hits
+system.cpu.l2cache.ReadExReq_hits              528421                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits                1956173                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits               1956173                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses              338145                       # number of ReadReq misses
+system.cpu.l2cache.UpgradeReq_misses           241551                       # number of UpgradeReq misses
+system.cpu.l2cache.ReadExReq_misses            247520                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses               585665                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses              585665                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency   11551149000                       # number of ReadReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency     10207000                       # number of UpgradeReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency   8480925000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency    20032074000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency   20032074000                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses           1765897                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses         2229874                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses         242777                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses          775941                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses            2541838                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses           2541838                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate         0.191486                       # miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate      0.994950                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate       0.318993                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate          0.230410                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate         0.230410                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency 34160.342457                       # average ReadReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency    42.256087                       # average UpgradeReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency 34263.594861                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency 34203.980091                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency 34203.980091                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -442,31 +442,32 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks                  412029                       # number of writebacks
-system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses         338148                       # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses       241457                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses       247534                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses          585682                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses         585682                       # number of overall MSHR misses
+system.cpu.l2cache.writebacks                  412030                       # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_hits                1                       # number of ReadReq MSHR hits
+system.cpu.l2cache.demand_mshr_hits                 1                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits                1                       # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses         338144                       # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses       241551                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses       247520                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses          585664                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses         585664                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency  10484352000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency   7486160000                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency   7674186000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency  18158538000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency  18158538000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency  10484231000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency   7489077000                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency   7673754000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency  18157985000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency  18157985000                       # number of overall MSHR miss cycles
 system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate     0.191488                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate     0.994973                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.319016                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate     0.230418                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate     0.230418                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31005.216651                       # average ReadReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31004.112533                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31002.553185                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 31004.090957                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 31004.090957                       # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_mshr_miss_rate     0.191486                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate     0.994950                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.318993                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate     0.230410                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate     0.230410                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31005.225584                       # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31004.123353                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31002.561409                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 31004.099620                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 31004.099620                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
diff --git a/tests/long/70.twolf/ref/x86/linux/o3-timing/config.ini b/tests/long/70.twolf/ref/x86/linux/o3-timing/config.ini
index 98cead180..15faea73a 100644
--- a/tests/long/70.twolf/ref/x86/linux/o3-timing/config.ini
+++ b/tests/long/70.twolf/ref/x86/linux/o3-timing/config.ini
@@ -498,7 +498,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/chips/pd/randd/dist/cpu2000/binaries/x86/linux/twolf
+executable=/dist/m5/cpu2000/binaries/x86/linux/twolf
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/long/70.twolf/ref/x86/linux/o3-timing/simerr b/tests/long/70.twolf/ref/x86/linux/o3-timing/simerr
index 94d399eab..ac4ad20a5 100755
--- a/tests/long/70.twolf/ref/x86/linux/o3-timing/simerr
+++ b/tests/long/70.twolf/ref/x86/linux/o3-timing/simerr
@@ -1,7 +1,4 @@
 warn: Sockets disabled, not accepting gdb connections
-For more information see: http://www.m5sim.org/warn/d946bea6
 warn: instruction 'fnstcw_Mw' unimplemented
-For more information see: http://www.m5sim.org/warn/437d5238
 warn: instruction 'fldcw_Mw' unimplemented
-For more information see: http://www.m5sim.org/warn/437d5238
 hack: be nice to actually delete the event here
diff --git a/tests/long/70.twolf/ref/x86/linux/o3-timing/simout b/tests/long/70.twolf/ref/x86/linux/o3-timing/simout
index 4239fb14e..46cb2af0c 100755
--- a/tests/long/70.twolf/ref/x86/linux/o3-timing/simout
+++ b/tests/long/70.twolf/ref/x86/linux/o3-timing/simout
@@ -1,16 +1,10 @@
-Redirecting stdout to build/X86_SE/tests/fast/long/70.twolf/x86/linux/o3-timing/simout
-Redirecting stderr to build/X86_SE/tests/fast/long/70.twolf/x86/linux/o3-timing/simerr
-M5 Simulator System
+gem5 Simulator System.  http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
 
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled May 17 2011 12:22:59
-M5 started May 17 2011 12:44:44
-M5 executing on nadc-0309
-command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/70.twolf/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/fast/long/70.twolf/x86/linux/o3-timing
+gem5 compiled Jun 27 2011 02:06:34
+gem5 started Jun 27 2011 02:06:35
+gem5 executing on burrito
+command line: build/X86_SE/gem5.fast -d build/X86_SE/tests/fast/long/70.twolf/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/fast/long/70.twolf/x86/linux/o3-timing
 Couldn't unlink  build/X86_SE/tests/fast/long/70.twolf/x86/linux/o3-timing/smred.sav
 Couldn't unlink  build/X86_SE/tests/fast/long/70.twolf/x86/linux/o3-timing/smred.sv2
 Global frequency set at 1000000000000 ticks per second
diff --git a/tests/long/70.twolf/ref/x86/linux/o3-timing/stats.txt b/tests/long/70.twolf/ref/x86/linux/o3-timing/stats.txt
index 3cac44fa8..934f22237 100644
--- a/tests/long/70.twolf/ref/x86/linux/o3-timing/stats.txt
+++ b/tests/long/70.twolf/ref/x86/linux/o3-timing/stats.txt
@@ -3,10 +3,10 @@
 sim_seconds                                  0.106734                       # Number of seconds simulated
 sim_ticks                                106734154000                       # Number of ticks simulated
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 173636                       # Simulator instruction rate (inst/s)
-host_tick_rate                               83720146                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 258788                       # Number of bytes of host memory used
-host_seconds                                  1274.89                       # Real time elapsed on the host
+host_inst_rate                                 152335                       # Simulator instruction rate (inst/s)
+host_tick_rate                               73451239                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 239116                       # Number of bytes of host memory used
+host_seconds                                  1453.13                       # Real time elapsed on the host
 sim_insts                                   221363017                       # Number of instructions simulated
 system.cpu.workload.num_syscalls                  400                       # Number of system calls
 system.cpu.numCycles                        213468309                       # number of cpu cycles simulated
@@ -60,82 +60,82 @@ system.cpu.rename.BlockCycles                18068346                       # Nu
 system.cpu.rename.serializeStallCycles          22426                       # count of cycles rename stalled for serializing inst
 system.cpu.rename.RunCycles                  57435303                       # Number of cycles rename is running
 system.cpu.rename.UnblockCycles              39871804                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts              409779934                       # Number of instructions processed by rename
+system.cpu.rename.RenamedInsts              409779933                       # Number of instructions processed by rename
 system.cpu.rename.IQFullEvents               21501033                       # Number of times rename has blocked due to IQ full
 system.cpu.rename.LSQFullEvents              16352489                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands           430797249                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups            1054244251                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups       1043122686                       # Number of integer rename lookups
+system.cpu.rename.RenamedOperands           430797248                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups            1054244247                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups       1043122682                       # Number of integer rename lookups
 system.cpu.rename.fp_rename_lookups          11121565                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps             234363409                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                196433840                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.UndoneMaps                196433839                       # Number of HB maps that are undone due to squashing
 system.cpu.rename.serializingInsts               1440                       # count of serializing insts renamed
 system.cpu.rename.tempSerializingInsts           1310                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                  83098345                       # count of insts added to the skid buffer
+system.cpu.rename.skidInsts                  83098346                       # count of insts added to the skid buffer
 system.cpu.memDep0.insertedLoads            104980766                       # Number of loads inserted to the mem dependence unit.
 system.cpu.memDep0.insertedStores            37095594                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads          90430171                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores         30425406                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                  395507958                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.memDep0.conflictingLoads          90430174                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores         30425407                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                  395507957                       # Number of instructions added to the IQ (excludes non-spec)
 system.cpu.iq.iqNonSpecInstsAdded                1424                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                 281831488                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued             66022                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined       173816816                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined    357685429                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqInstsIssued                 281825994                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued             65208                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined       173816854                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined    357698242                       # Number of squashed operands that are examined and possibly removed from graph
 system.cpu.iq.iqSquashedNonSpecRemoved            178                       # Number of squashed non-spec instructions that were removed
 system.cpu.iq.issued_per_cycle::samples     213378820                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         1.320803                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.372846                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         1.320778                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.372811                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0            72508340     33.98%     33.98% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1            65572290     30.73%     64.71% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2            36644917     17.17%     81.89% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3            20570479      9.64%     91.53% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4            12013956      5.63%     97.16% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5             3959522      1.86%     99.01% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6             1478424      0.69%     99.70% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7              513187      0.24%     99.94% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8              117705      0.06%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0            72508898     33.98%     33.98% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            65573468     30.73%     64.71% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2            36643591     17.17%     81.89% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3            20570957      9.64%     91.53% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4            12013670      5.63%     97.16% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5             3959812      1.86%     99.01% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6             1477782      0.69%     99.70% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7              513095      0.24%     99.94% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8              117547      0.06%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::total       213378820                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                   68507      2.43%      2.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%      2.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%      2.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%      2.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%      2.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%      2.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%      2.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%      2.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      2.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%      2.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      2.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%      2.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%      2.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%      2.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%      2.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%      2.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      2.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%      2.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      2.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      2.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      2.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      2.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      2.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      2.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      2.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      2.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      2.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      2.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      2.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                2380396     84.55%     86.98% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                   68694      2.44%      2.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%      2.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%      2.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%      2.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%      2.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%      2.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%      2.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%      2.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      2.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%      2.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      2.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%      2.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%      2.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%      2.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%      2.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%      2.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      2.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%      2.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      2.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      2.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      2.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      2.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      2.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      2.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      2.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      2.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      2.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      2.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      2.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                2379905     84.54%     86.98% # attempts to use FU when none available
 system.cpu.iq.fu_full::MemWrite                366520     13.02%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass           1200241      0.43%      0.43% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu             187039498     66.37%     66.79% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu             187039988     66.37%     66.79% # Type of FU issued
 system.cpu.iq.FU_type_0::IntMult                    0      0.00%     66.79% # Type of FU issued
 system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     66.79% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatAdd             1589434      0.56%     67.36% # Type of FU issued
@@ -164,27 +164,27 @@ system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     67.36% # Ty
 system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     67.36% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     67.36% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     67.36% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead             68498295     24.30%     91.66% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite            23504020      8.34%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead             68492447     24.30%     91.66% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite            23503884      8.34%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total              281831488                       # Type of FU issued
-system.cpu.iq.rate                           1.320250                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                     2815423                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.009990                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads          774688380                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes         563666165                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses    273461056                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.FU_type_0::total              281825994                       # Type of FU issued
+system.cpu.iq.rate                           1.320224                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                     2815119                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.009989                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads          774676274                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         563666202                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses    273457668                       # Number of integer instruction queue wakeup accesses
 system.cpu.iq.fp_inst_queue_reads             5234861                       # Number of floating instruction queue reads
 system.cpu.iq.fp_inst_queue_writes            5690969                       # Number of floating instruction queue writes
 system.cpu.iq.fp_inst_queue_wakeup_accesses      2532279                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses              280809032                       # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses              280803234                       # Number of integer alu accesses
 system.cpu.iq.fp_alu_accesses                 2637638                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads         16340043                       # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.forwLoads         16340040                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
 system.cpu.iew.lsq.thread0.squashedLoads     48331176                       # Number of loads squashed
 system.cpu.iew.lsq.thread0.ignoredResponses        20419                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation        34133                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.memOrderViolation        34128                       # Number of memory ordering violations
 system.cpu.iew.lsq.thread0.squashedStores     16579878                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
@@ -194,36 +194,36 @@ system.cpu.iew.iewIdleCycles                        0                       # Nu
 system.cpu.iew.iewSquashCycles               23148585                       # Number of cycles IEW is squashing
 system.cpu.iew.iewBlockCycles                  533368                       # Number of cycles IEW is blocking
 system.cpu.iew.iewUnblockCycles                548562                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts           395509382                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispatchedInsts           395509381                       # Number of instructions dispatched to IQ
 system.cpu.iew.iewDispSquashedInsts            255580                       # Number of squashed instructions skipped by dispatch
 system.cpu.iew.iewDispLoadInsts             104980766                       # Number of dispatched load instructions
 system.cpu.iew.iewDispStoreInsts             37095594                       # Number of dispatched store instructions
 system.cpu.iew.iewDispNonSpecInsts               1424                       # Number of dispatched non-speculative instructions
 system.cpu.iew.iewIQFullEvents                 479390                       # Number of times the IQ has become full, causing a stall
 system.cpu.iew.iewLSQFullEvents                 13059                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents          34133                       # Number of memory order violations
+system.cpu.iew.memOrderViolationEvents          34128                       # Number of memory order violations
 system.cpu.iew.predictedTakenIncorrect        2541200                       # Number of branches that were predicted taken incorrectly
 system.cpu.iew.predictedNotTakenIncorrect       744980                       # Number of branches that were predicted not taken incorrectly
 system.cpu.iew.branchMispredicts              3286180                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts             278314164                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts              67081099                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts           3517324                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewExecutedInsts             278309942                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts              67077031                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts           3516052                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
 system.cpu.iew.exec_nop                             0                       # number of nop insts executed
-system.cpu.iew.exec_refs                     90254153                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                 15873858                       # Number of branches executed
-system.cpu.iew.exec_stores                   23173054                       # Number of stores executed
-system.cpu.iew.exec_rate                     1.303773                       # Inst execution rate
-system.cpu.iew.wb_sent                      277023863                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                     275993335                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                 222941305                       # num instructions producing a value
-system.cpu.iew.wb_consumers                 371922764                       # num instructions consuming a value
+system.cpu.iew.exec_refs                     90250007                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 15873940                       # Number of branches executed
+system.cpu.iew.exec_stores                   23172976                       # Number of stores executed
+system.cpu.iew.exec_rate                     1.303753                       # Inst execution rate
+system.cpu.iew.wb_sent                      277022685                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                     275989947                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                 222941067                       # num instructions producing a value
+system.cpu.iew.wb_consumers                 371922286                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       1.292901                       # insts written-back per cycle
+system.cpu.iew.wb_rate                       1.292885                       # insts written-back per cycle
 system.cpu.iew.wb_fanout                     0.599429                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
 system.cpu.commit.commitCommittedInsts      221363017                       # The number of committed instructions
-system.cpu.commit.commitSquashedInsts       174164321                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts       174164320                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls            1246                       # The number of times commit has been forced to stall to communicate backwards
 system.cpu.commit.branchMispredicts           3072754                       # The number of times a branch was mispredicted
 system.cpu.commit.committed_per_cycle::samples    190230235                       # Number of insts commited each cycle
@@ -254,8 +254,8 @@ system.cpu.commit.int_insts                 220339606                       # Nu
 system.cpu.commit.function_calls                    0                       # Number of function calls committed.
 system.cpu.commit.bw_lim_events               2359489                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                    583398084                       # The number of ROB reads
-system.cpu.rob.rob_writes                   814214437                       # The number of ROB writes
+system.cpu.rob.rob_reads                    583398083                       # The number of ROB reads
+system.cpu.rob.rob_writes                   814214435                       # The number of ROB writes
 system.cpu.timesIdled                            1914                       # Number of times that the entire CPU went into an idle state and unscheduled itself
 system.cpu.idleCycles                           89489                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                   221363017                       # Number of Instructions Simulated
@@ -264,11 +264,11 @@ system.cpu.cpi                               0.964336                       # CP
 system.cpu.cpi_total                         0.964336                       # CPI: Total CPI of All Threads
 system.cpu.ipc                               1.036983                       # IPC: Instructions Per Cycle
 system.cpu.ipc_total                         1.036983                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                516528082                       # number of integer regfile reads
-system.cpu.int_regfile_writes               284024941                       # number of integer regfile writes
+system.cpu.int_regfile_reads                516519288                       # number of integer regfile reads
+system.cpu.int_regfile_writes               284023651                       # number of integer regfile writes
 system.cpu.fp_regfile_reads                   3512884                       # number of floating regfile reads
 system.cpu.fp_regfile_writes                  2186553                       # number of floating regfile writes
-system.cpu.misc_regfile_reads               145160346                       # number of misc regfile reads
+system.cpu.misc_regfile_reads               145156303                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                    844                       # number of misc regfile writes
 system.cpu.icache.replacements                   3419                       # number of replacements
 system.cpu.icache.tagsinuse               1603.937064                       # Cycle average of tags in use
@@ -328,16 +328,16 @@ system.cpu.icache.soft_prefetch_mshr_full            0                       # n
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                     48                       # number of replacements
 system.cpu.dcache.tagsinuse               1400.553684                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                 71038551                       # Total number of references to valid blocks.
+system.cpu.dcache.total_refs                 71034499                       # Total number of references to valid blocks.
 system.cpu.dcache.sampled_refs                   1955                       # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs               36336.854731                       # Average number of references to valid blocks.
+system.cpu.dcache.avg_refs               36334.782097                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
 system.cpu.dcache.occ_blocks::0           1400.553684                       # Average occupied blocks per context
 system.cpu.dcache.occ_percent::0             0.341932                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits               50529918                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits               50525866                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits              20508631                       # number of WriteReq hits
-system.cpu.dcache.demand_hits                71038549                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits               71038549                       # number of overall hits
+system.cpu.dcache.demand_hits                71034497                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits               71034497                       # number of overall hits
 system.cpu.dcache.ReadReq_misses                  700                       # number of ReadReq misses
 system.cpu.dcache.WriteReq_misses                7099                       # number of WriteReq misses
 system.cpu.dcache.demand_misses                  7799                       # number of demand (read+write) misses
@@ -346,10 +346,10 @@ system.cpu.dcache.ReadReq_miss_latency       23034500                       # nu
 system.cpu.dcache.WriteReq_miss_latency     187834000                       # number of WriteReq miss cycles
 system.cpu.dcache.demand_miss_latency       210868500                       # number of demand (read+write) miss cycles
 system.cpu.dcache.overall_miss_latency      210868500                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses           50530618                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses           50526566                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses          20515730                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses            71046348                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses           71046348                       # number of overall (read+write) accesses
+system.cpu.dcache.demand_accesses            71042296                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses           71042296                       # number of overall (read+write) accesses
 system.cpu.dcache.ReadReq_miss_rate          0.000014                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate         0.000346                       # miss rate for WriteReq accesses
 system.cpu.dcache.demand_miss_rate           0.000110                       # miss rate for demand accesses
diff --git a/tests/quick/00.hello/ref/x86/linux/o3-timing/simerr b/tests/quick/00.hello/ref/x86/linux/o3-timing/simerr
index 94d399eab..ac4ad20a5 100755
--- a/tests/quick/00.hello/ref/x86/linux/o3-timing/simerr
+++ b/tests/quick/00.hello/ref/x86/linux/o3-timing/simerr
@@ -1,7 +1,4 @@
 warn: Sockets disabled, not accepting gdb connections
-For more information see: http://www.m5sim.org/warn/d946bea6
 warn: instruction 'fnstcw_Mw' unimplemented
-For more information see: http://www.m5sim.org/warn/437d5238
 warn: instruction 'fldcw_Mw' unimplemented
-For more information see: http://www.m5sim.org/warn/437d5238
 hack: be nice to actually delete the event here
diff --git a/tests/quick/00.hello/ref/x86/linux/o3-timing/simout b/tests/quick/00.hello/ref/x86/linux/o3-timing/simout
index a4e55b227..5486afb8d 100755
--- a/tests/quick/00.hello/ref/x86/linux/o3-timing/simout
+++ b/tests/quick/00.hello/ref/x86/linux/o3-timing/simout
@@ -1,16 +1,10 @@
-Redirecting stdout to build/X86_SE/tests/fast/quick/00.hello/x86/linux/o3-timing/simout
-Redirecting stderr to build/X86_SE/tests/fast/quick/00.hello/x86/linux/o3-timing/simerr
-M5 Simulator System
+gem5 Simulator System.  http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
 
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled May 17 2011 12:22:59
-M5 started May 17 2011 13:06:27
-M5 executing on nadc-0309
-command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/quick/00.hello/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/fast/quick/00.hello/x86/linux/o3-timing
+gem5 compiled Jun 27 2011 02:06:34
+gem5 started Jun 27 2011 02:06:35
+gem5 executing on burrito
+command line: build/X86_SE/gem5.fast -d build/X86_SE/tests/fast/quick/00.hello/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/fast/quick/00.hello/x86/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
diff --git a/tests/quick/00.hello/ref/x86/linux/o3-timing/stats.txt b/tests/quick/00.hello/ref/x86/linux/o3-timing/stats.txt
index fb3f0ce4d..aabbd6e7a 100644
--- a/tests/quick/00.hello/ref/x86/linux/o3-timing/stats.txt
+++ b/tests/quick/00.hello/ref/x86/linux/o3-timing/stats.txt
@@ -3,10 +3,10 @@
 sim_seconds                                  0.000011                       # Number of seconds simulated
 sim_ticks                                    11369000                       # Number of ticks simulated
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 133340                       # Simulator instruction rate (inst/s)
-host_tick_rate                              154514196                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 245132                       # Number of bytes of host memory used
-host_seconds                                     0.07                       # Real time elapsed on the host
+host_inst_rate                                  90859                       # Simulator instruction rate (inst/s)
+host_tick_rate                              105280911                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 225572                       # Number of bytes of host memory used
+host_seconds                                     0.11                       # Real time elapsed on the host
 sim_insts                                        9809                       # Number of instructions simulated
 system.cpu.workload.num_syscalls                   11                       # Number of system calls
 system.cpu.numCycles                            22739                       # number of cpu cycles simulated
@@ -81,8 +81,8 @@ system.cpu.iq.iqInstsAdded                      18991                       # Nu
 system.cpu.iq.iqNonSpecInstsAdded                  33                       # Number of non-speculative instructions added to the IQ
 system.cpu.iq.iqInstsIssued                     16049                       # Number of instructions issued
 system.cpu.iq.iqSquashedInstsIssued                54                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined            8597                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined        10847                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedInstsExamined            8636                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined        10887                       # Number of squashed operands that are examined and possibly removed from graph
 system.cpu.iq.iqSquashedNonSpecRemoved             20                       # Number of squashed non-spec instructions that were removed
 system.cpu.iq.issued_per_cycle::samples         13282                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::mean         1.208327                       # Number of insts issued each cycle
@@ -174,8 +174,8 @@ system.cpu.iq.rate                           0.705792                       # In
 system.cpu.iq.fu_busy_cnt                         147                       # FU busy when requested
 system.cpu.iq.fu_busy_rate                   0.009159                       # FU busy rate (busy events/executed inst)
 system.cpu.iq.int_inst_queue_reads              45572                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes             27629                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses        15050                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.int_inst_queue_writes             27668                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses        15040                       # Number of integer instruction queue wakeup accesses
 system.cpu.iq.fp_inst_queue_reads                   9                       # Number of floating instruction queue reads
 system.cpu.iq.fp_inst_queue_writes                  4                       # Number of floating instruction queue writes
 system.cpu.iq.fp_inst_queue_wakeup_accesses            4                       # Number of floating instruction queue wakeup accesses
@@ -216,11 +216,11 @@ system.cpu.iew.exec_branches                     1546                       # Nu
 system.cpu.iew.exec_stores                       1295                       # Number of stores executed
 system.cpu.iew.exec_rate                     0.675491                       # Inst execution rate
 system.cpu.iew.wb_sent                          15177                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                         15054                       # cumulative count of insts written-back
+system.cpu.iew.wb_count                         15044                       # cumulative count of insts written-back
 system.cpu.iew.wb_producers                      9950                       # num instructions producing a value
 system.cpu.iew.wb_consumers                     14675                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       0.662034                       # insts written-back per cycle
+system.cpu.iew.wb_rate                       0.661595                       # insts written-back per cycle
 system.cpu.iew.wb_fanout                     0.678024                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
 system.cpu.commit.commitCommittedInsts           9809                       # The number of committed instructions
diff --git a/util/tracediff b/util/tracediff
index 5349c303d..5c77d9caf 100755
--- a/util/tracediff
+++ b/util/tracediff
@@ -124,11 +124,11 @@ $sim2 = shift @cmd2;
 $args1 = join(' ', @cmd1);
 $args2 = join(' ', @cmd2);
 
-# Common mistake: if you don't set any traceflags this often isn't
+# Common mistake: if you don't set any debugflags this often isn't
 # doing what you want.
-if ($args1 !~ /--trace-flags/) {
+if ($args1 !~ /--debug-flags/) {
     print "****\n";
-    print "**** WARNING: no trace flags set... you may not be diffing much!\n";
+    print "**** WARNING: no debug flags set... you may not be diffing much!\n";
     print "****\n";
 }